direct-io.hg

changeset 11937:f6007621cc0c

[IA64] VTi TLB miss fix

When present bit is 0, inject page not present fault to guest.

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author awilliam@xenbuild.aw
date Sun Oct 01 11:05:24 2006 -0600 (2006-10-01)
parents 3470d9cd27e5
children 92bd25c46f27
files xen/arch/ia64/vmx/vmmu.c xen/arch/ia64/vmx/vmx_interrupt.c xen/arch/ia64/vmx/vmx_process.c xen/include/asm-ia64/vmx_vcpu.h
line diff
     1.1 --- a/xen/arch/ia64/vmx/vmmu.c	Sun Oct 01 10:48:40 2006 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vmmu.c	Sun Oct 01 11:05:24 2006 -0600
     1.3 @@ -645,37 +645,30 @@ IA64FAULT vmx_vcpu_tpa(VCPU *vcpu, UINT6
     1.4      visr.ei=pt_isr.ei;
     1.5      visr.ir=pt_isr.ir;
     1.6      vpsr.val = VCPU(vcpu, vpsr);
     1.7 -    if(vpsr.ic==0){
     1.8 -        visr.ni=1;
     1.9 -    }
    1.10      visr.na=1;
    1.11      data = vtlb_lookup(vcpu, vadr, DSIDE_TLB);
    1.12      if(data){
    1.13          if(data->p==0){
    1.14 -            visr.na=1;
    1.15              vcpu_set_isr(vcpu,visr.val);
    1.16 -            page_not_present(vcpu, vadr);
    1.17 +            data_page_not_present(vcpu, vadr);
    1.18              return IA64_FAULT;
    1.19          }else if(data->ma == VA_MATTR_NATPAGE){
    1.20 -            visr.na = 1;
    1.21              vcpu_set_isr(vcpu, visr.val);
    1.22              dnat_page_consumption(vcpu, vadr);
    1.23              return IA64_FAULT;
    1.24          }else{
    1.25              *padr = ((data->ppn >> (data->ps - 12)) << data->ps) |
    1.26 -                                                (vadr & (PSIZE(data->ps) - 1));
    1.27 +                    (vadr & (PSIZE(data->ps) - 1));
    1.28              return IA64_NO_FAULT;
    1.29          }
    1.30      }
    1.31      data = vhpt_lookup(vadr);
    1.32      if(data){
    1.33          if(data->p==0){
    1.34 -            visr.na=1;
    1.35              vcpu_set_isr(vcpu,visr.val);
    1.36 -            page_not_present(vcpu, vadr);
    1.37 +            data_page_not_present(vcpu, vadr);
    1.38              return IA64_FAULT;
    1.39          }else if(data->ma == VA_MATTR_NATPAGE){
    1.40 -            visr.na = 1;
    1.41              vcpu_set_isr(vcpu, visr.val);
    1.42              dnat_page_consumption(vcpu, vadr);
    1.43              return IA64_FAULT;
     2.1 --- a/xen/arch/ia64/vmx/vmx_interrupt.c	Sun Oct 01 10:48:40 2006 -0600
     2.2 +++ b/xen/arch/ia64/vmx/vmx_interrupt.c	Sun Oct 01 11:05:24 2006 -0600
     2.3 @@ -383,14 +383,29 @@ dnat_page_consumption (VCPU *vcpu, uint6
     2.4  /* Deal with
     2.5   *  Page not present vector
     2.6   */
     2.7 -void
     2.8 -page_not_present(VCPU *vcpu, u64 vadr)
     2.9 +static void
    2.10 +__page_not_present(VCPU *vcpu, u64 vadr)
    2.11  {
    2.12      /* If vPSR.ic, IFA, ITIR */
    2.13      set_ifa_itir_iha (vcpu, vadr, 1, 1, 0);
    2.14      inject_guest_interruption(vcpu, IA64_PAGE_NOT_PRESENT_VECTOR);
    2.15  }
    2.16  
    2.17 +
    2.18 +void
    2.19 +data_page_not_present(VCPU *vcpu, u64 vadr)
    2.20 +{
    2.21 +    __page_not_present(vcpu, vadr);
    2.22 +}
    2.23 +
    2.24 +
    2.25 +void
    2.26 +inst_page_not_present(VCPU *vcpu, u64 vadr)
    2.27 +{
    2.28 +    __page_not_present(vcpu, vadr);
    2.29 +}
    2.30 +
    2.31 +
    2.32  /* Deal with
    2.33   *  Data access rights vector
    2.34   */
     3.1 --- a/xen/arch/ia64/vmx/vmx_process.c	Sun Oct 01 10:48:40 2006 -0600
     3.2 +++ b/xen/arch/ia64/vmx/vmx_process.c	Sun Oct 01 11:05:24 2006 -0600
     3.3 @@ -263,18 +263,20 @@ IA64FAULT
     3.4  vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs)
     3.5  {
     3.6      IA64_PSR vpsr;
     3.7 -    int type=ISIDE_TLB;
     3.8 +    int type;
     3.9      u64 vhpt_adr, gppa, pteval, rr, itir;
    3.10      ISR misr;
    3.11 -//    REGS *regs;
    3.12      thash_data_t *data;
    3.13      VCPU *v = current;
    3.14 -#ifdef  VTLB_DEBUG
    3.15 -    check_vtlb_sanity(vtlb);
    3.16 -    dump_vtlb(vtlb);
    3.17 -#endif
    3.18      vpsr.val = VCPU(v, vpsr);
    3.19      misr.val=VMX(v,cr_isr);
    3.20 +    
    3.21 +    if (vec == 1)
    3.22 +        type = ISIDE_TLB;
    3.23 +    else if (vec == 2)
    3.24 +        type = DSIDE_TLB;
    3.25 +    else
    3.26 +        panic_domain(regs, "wrong vec:%lx\n", vec);
    3.27  
    3.28      if(is_physical_mode(v)&&(!(vadr<<1>>62))){
    3.29          if(vec==2){
    3.30 @@ -286,11 +288,6 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
    3.31          physical_tlb_miss(v, vadr);
    3.32          return IA64_FAULT;
    3.33      }
    3.34 -    if(vec == 1) type = ISIDE_TLB;
    3.35 -    else if(vec == 2) type = DSIDE_TLB;
    3.36 -    else panic_domain(regs,"wrong vec:%lx\n",vec);
    3.37 -
    3.38 -//    prepare_if_physical_mode(v);
    3.39  
    3.40      if((data=vtlb_lookup(v, vadr,type))!=0){
    3.41          if (v->domain != dom0 && type == DSIDE_TLB) {
    3.42 @@ -309,46 +306,44 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
    3.43          thash_vhpt_insert(v,data->page_flags, data->itir ,vadr);
    3.44  
    3.45      }else if(type == DSIDE_TLB){
    3.46 +    
    3.47          if (misr.sp)
    3.48              return vmx_handle_lds(regs);
    3.49 +
    3.50          if(!vhpt_enabled(v, vadr, misr.rs?RSE_REF:DATA_REF)){
    3.51              if(vpsr.ic){
    3.52                  vcpu_set_isr(v, misr.val);
    3.53                  alt_dtlb(v, vadr);
    3.54                  return IA64_FAULT;
    3.55              } else{
    3.56 -                if(misr.sp){
    3.57 -                    //TODO  lds emulation
    3.58 -                    //panic("Don't support speculation load");
    3.59 -                    return vmx_handle_lds(regs);
    3.60 -                }else{
    3.61 -                    nested_dtlb(v);
    3.62 -                    return IA64_FAULT;
    3.63 -                }
    3.64 +                nested_dtlb(v);
    3.65 +                return IA64_FAULT;
    3.66              }
    3.67          } else{
    3.68              vmx_vcpu_thash(v, vadr, &vhpt_adr);
    3.69              if(!guest_vhpt_lookup(vhpt_adr, &pteval)){
    3.70 -                if ((pteval & _PAGE_P) &&
    3.71 -                    ((pteval & _PAGE_MA_MASK) != _PAGE_MA_ST)) {
    3.72 +                if (!(pteval & _PAGE_P)) {
    3.73 +                    if (vpsr.ic) {
    3.74 +                        vcpu_set_isr(v, misr.val);
    3.75 +                        data_page_not_present(v, vadr);
    3.76 +                        return IA64_FAULT;
    3.77 +                    } else {
    3.78 +                        nested_dtlb(v);
    3.79 +                        return IA64_FAULT;
    3.80 +                    }
    3.81 +                }                     
    3.82 +                else if ((pteval & _PAGE_MA_MASK) != _PAGE_MA_ST) {
    3.83                      vcpu_get_rr(v, vadr, &rr);
    3.84                      itir = rr&(RR_RID_MASK | RR_PS_MASK);
    3.85                      thash_purge_and_insert(v, pteval, itir, vadr, DSIDE_TLB);
    3.86                      return IA64_NO_FAULT;
    3.87 -                }
    3.88 -                if(vpsr.ic){
    3.89 +                } else if (vpsr.ic) {
    3.90                      vcpu_set_isr(v, misr.val);
    3.91                      dtlb_fault(v, vadr);
    3.92                      return IA64_FAULT;
    3.93                  }else{
    3.94 -                    if(misr.sp){
    3.95 -                    //TODO  lds emulation
    3.96 -                    //panic("Don't support speculation load");
    3.97 -                    return vmx_handle_lds(regs);
    3.98 -                    }else{
    3.99 -                        nested_dtlb(v);
   3.100 -                        return IA64_FAULT;
   3.101 -                    }
   3.102 +                    nested_dtlb(v);
   3.103 +                    return IA64_FAULT;
   3.104                  }
   3.105              }else{
   3.106                  if(vpsr.ic){
   3.107 @@ -356,22 +351,16 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
   3.108                      dvhpt_fault(v, vadr);
   3.109                      return IA64_FAULT;
   3.110                  }else{
   3.111 -                    if(misr.sp){
   3.112 -                    //TODO  lds emulation
   3.113 -                    //panic("Don't support speculation load");
   3.114 -                    return vmx_handle_lds(regs);
   3.115 -                    }else{
   3.116 -                        nested_dtlb(v);
   3.117 -                        return IA64_FAULT;
   3.118 -                    }
   3.119 +                    nested_dtlb(v);
   3.120 +                    return IA64_FAULT;
   3.121                  }
   3.122              }
   3.123          }
   3.124      }else if(type == ISIDE_TLB){
   3.125 +    
   3.126 +        if (!vpsr.ic)
   3.127 +            misr.ni = 1;
   3.128          if(!vhpt_enabled(v, vadr, misr.rs?RSE_REF:DATA_REF)){
   3.129 -            if(!vpsr.ic){
   3.130 -                misr.ni=1;
   3.131 -            }
   3.132              vcpu_set_isr(v, misr.val);
   3.133              alt_itlb(v, vadr);
   3.134              return IA64_FAULT;
   3.135 @@ -383,17 +372,12 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
   3.136                      itir = rr&(RR_RID_MASK | RR_PS_MASK);
   3.137                      thash_purge_and_insert(v, pteval, itir, vadr, ISIDE_TLB);
   3.138                      return IA64_NO_FAULT;
   3.139 -                }
   3.140 -                if(!vpsr.ic){
   3.141 -                    misr.ni=1;
   3.142 +                } else {
   3.143 +                    vcpu_set_isr(v, misr.val);
   3.144 +                    inst_page_not_present(v, vadr);
   3.145 +                    return IA64_FAULT;
   3.146                  }
   3.147 -                vcpu_set_isr(v, misr.val);
   3.148 -                itlb_fault(v, vadr);
   3.149 -                return IA64_FAULT;
   3.150              }else{
   3.151 -                if(!vpsr.ic){
   3.152 -                    misr.ni=1;
   3.153 -                }
   3.154                  vcpu_set_isr(v, misr.val);
   3.155                  ivhpt_fault(v, vadr);
   3.156                  return IA64_FAULT;
     4.1 --- a/xen/include/asm-ia64/vmx_vcpu.h	Sun Oct 01 10:48:40 2006 -0600
     4.2 +++ b/xen/include/asm-ia64/vmx_vcpu.h	Sun Oct 01 11:05:24 2006 -0600
     4.3 @@ -122,7 +122,8 @@ extern void nested_dtlb (VCPU *vcpu);
     4.4  extern void alt_dtlb (VCPU *vcpu, u64 vadr);
     4.5  extern void dvhpt_fault (VCPU *vcpu, u64 vadr);
     4.6  extern void dnat_page_consumption (VCPU *vcpu, uint64_t vadr);
     4.7 -extern void page_not_present(VCPU *vcpu, u64 vadr);
     4.8 +extern void data_page_not_present(VCPU *vcpu, u64 vadr);
     4.9 +extern void inst_page_not_present(VCPU *vcpu, u64 vadr);
    4.10  extern void data_access_rights(VCPU *vcpu, u64 vadr);
    4.11  
    4.12  /**************************************************************************