direct-io.hg

changeset 15094:e60051ca408f

[IA64] Add iommu drivers to sparse tree

These will be paravirtualized in upcoming commits. We're copying
lib/swiotlb.c into arch/ia64/xen/swiotlb.c simply for convenience.
Changes should be merged back into lib/swiotlb.c once Xen support
merges into Linux.

Signed-off-by: Alex Williamson <alex.williamson@hp.com>
author Alex Williamson <alex.williamson@hp.com>
date Sun May 06 20:29:45 2007 -0600 (2007-05-06)
parents 63263d715d43
children 642a9bcaf19c
files linux-2.6-xen-sparse/arch/ia64/hp/common/sba_iommu.c linux-2.6-xen-sparse/arch/ia64/xen/swiotlb.c
line diff
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/linux-2.6-xen-sparse/arch/ia64/hp/common/sba_iommu.c	Sun May 06 20:29:45 2007 -0600
     1.3 @@ -0,0 +1,2133 @@
     1.4 +/*
     1.5 +**  IA64 System Bus Adapter (SBA) I/O MMU manager
     1.6 +**
     1.7 +**	(c) Copyright 2002-2005 Alex Williamson
     1.8 +**	(c) Copyright 2002-2003 Grant Grundler
     1.9 +**	(c) Copyright 2002-2005 Hewlett-Packard Company
    1.10 +**
    1.11 +**	Portions (c) 2000 Grant Grundler (from parisc I/O MMU code)
    1.12 +**	Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
    1.13 +**
    1.14 +**	This program is free software; you can redistribute it and/or modify
    1.15 +**	it under the terms of the GNU General Public License as published by
    1.16 +**      the Free Software Foundation; either version 2 of the License, or
    1.17 +**      (at your option) any later version.
    1.18 +**
    1.19 +**
    1.20 +** This module initializes the IOC (I/O Controller) found on HP
    1.21 +** McKinley machines and their successors.
    1.22 +**
    1.23 +*/
    1.24 +
    1.25 +#include <linux/types.h>
    1.26 +#include <linux/kernel.h>
    1.27 +#include <linux/module.h>
    1.28 +#include <linux/spinlock.h>
    1.29 +#include <linux/slab.h>
    1.30 +#include <linux/init.h>
    1.31 +#include <linux/mm.h>
    1.32 +#include <linux/string.h>
    1.33 +#include <linux/pci.h>
    1.34 +#include <linux/proc_fs.h>
    1.35 +#include <linux/seq_file.h>
    1.36 +#include <linux/acpi.h>
    1.37 +#include <linux/efi.h>
    1.38 +#include <linux/nodemask.h>
    1.39 +#include <linux/bitops.h>         /* hweight64() */
    1.40 +
    1.41 +#include <asm/delay.h>		/* ia64_get_itc() */
    1.42 +#include <asm/io.h>
    1.43 +#include <asm/page.h>		/* PAGE_OFFSET */
    1.44 +#include <asm/dma.h>
    1.45 +#include <asm/system.h>		/* wmb() */
    1.46 +
    1.47 +#include <asm/acpi-ext.h>
    1.48 +
    1.49 +#define PFX "IOC: "
    1.50 +
    1.51 +/*
    1.52 +** Enabling timing search of the pdir resource map.  Output in /proc.
    1.53 +** Disabled by default to optimize performance.
    1.54 +*/
    1.55 +#undef PDIR_SEARCH_TIMING
    1.56 +
    1.57 +/*
    1.58 +** This option allows cards capable of 64bit DMA to bypass the IOMMU.  If
    1.59 +** not defined, all DMA will be 32bit and go through the TLB.
    1.60 +** There's potentially a conflict in the bio merge code with us
    1.61 +** advertising an iommu, but then bypassing it.  Since I/O MMU bypassing
    1.62 +** appears to give more performance than bio-level virtual merging, we'll
    1.63 +** do the former for now.  NOTE: BYPASS_SG also needs to be undef'd to
    1.64 +** completely restrict DMA to the IOMMU.
    1.65 +*/
    1.66 +#define ALLOW_IOV_BYPASS
    1.67 +
    1.68 +/*
    1.69 +** This option specifically allows/disallows bypassing scatterlists with
    1.70 +** multiple entries.  Coalescing these entries can allow better DMA streaming
    1.71 +** and in some cases shows better performance than entirely bypassing the
    1.72 +** IOMMU.  Performance increase on the order of 1-2% sequential output/input
    1.73 +** using bonnie++ on a RAID0 MD device (sym2 & mpt).
    1.74 +*/
    1.75 +#undef ALLOW_IOV_BYPASS_SG
    1.76 +
    1.77 +/*
    1.78 +** If a device prefetches beyond the end of a valid pdir entry, it will cause
    1.79 +** a hard failure, ie. MCA.  Version 3.0 and later of the zx1 LBA should
    1.80 +** disconnect on 4k boundaries and prevent such issues.  If the device is
    1.81 +** particularly agressive, this option will keep the entire pdir valid such
    1.82 +** that prefetching will hit a valid address.  This could severely impact
    1.83 +** error containment, and is therefore off by default.  The page that is
    1.84 +** used for spill-over is poisoned, so that should help debugging somewhat.
    1.85 +*/
    1.86 +#undef FULL_VALID_PDIR
    1.87 +
    1.88 +#define ENABLE_MARK_CLEAN
    1.89 +
    1.90 +/*
    1.91 +** The number of debug flags is a clue - this code is fragile.  NOTE: since
    1.92 +** tightening the use of res_lock the resource bitmap and actual pdir are no
    1.93 +** longer guaranteed to stay in sync.  The sanity checking code isn't going to
    1.94 +** like that.
    1.95 +*/
    1.96 +#undef DEBUG_SBA_INIT
    1.97 +#undef DEBUG_SBA_RUN
    1.98 +#undef DEBUG_SBA_RUN_SG
    1.99 +#undef DEBUG_SBA_RESOURCE
   1.100 +#undef ASSERT_PDIR_SANITY
   1.101 +#undef DEBUG_LARGE_SG_ENTRIES
   1.102 +#undef DEBUG_BYPASS
   1.103 +
   1.104 +#if defined(FULL_VALID_PDIR) && defined(ASSERT_PDIR_SANITY)
   1.105 +#error FULL_VALID_PDIR and ASSERT_PDIR_SANITY are mutually exclusive
   1.106 +#endif
   1.107 +
   1.108 +#define SBA_INLINE	__inline__
   1.109 +/* #define SBA_INLINE */
   1.110 +
   1.111 +#ifdef DEBUG_SBA_INIT
   1.112 +#define DBG_INIT(x...)	printk(x)
   1.113 +#else
   1.114 +#define DBG_INIT(x...)
   1.115 +#endif
   1.116 +
   1.117 +#ifdef DEBUG_SBA_RUN
   1.118 +#define DBG_RUN(x...)	printk(x)
   1.119 +#else
   1.120 +#define DBG_RUN(x...)
   1.121 +#endif
   1.122 +
   1.123 +#ifdef DEBUG_SBA_RUN_SG
   1.124 +#define DBG_RUN_SG(x...)	printk(x)
   1.125 +#else
   1.126 +#define DBG_RUN_SG(x...)
   1.127 +#endif
   1.128 +
   1.129 +
   1.130 +#ifdef DEBUG_SBA_RESOURCE
   1.131 +#define DBG_RES(x...)	printk(x)
   1.132 +#else
   1.133 +#define DBG_RES(x...)
   1.134 +#endif
   1.135 +
   1.136 +#ifdef DEBUG_BYPASS
   1.137 +#define DBG_BYPASS(x...)	printk(x)
   1.138 +#else
   1.139 +#define DBG_BYPASS(x...)
   1.140 +#endif
   1.141 +
   1.142 +#ifdef ASSERT_PDIR_SANITY
   1.143 +#define ASSERT(expr) \
   1.144 +        if(!(expr)) { \
   1.145 +                printk( "\n" __FILE__ ":%d: Assertion " #expr " failed!\n",__LINE__); \
   1.146 +                panic(#expr); \
   1.147 +        }
   1.148 +#else
   1.149 +#define ASSERT(expr)
   1.150 +#endif
   1.151 +
   1.152 +/*
   1.153 +** The number of pdir entries to "free" before issuing
   1.154 +** a read to PCOM register to flush out PCOM writes.
   1.155 +** Interacts with allocation granularity (ie 4 or 8 entries
   1.156 +** allocated and free'd/purged at a time might make this
   1.157 +** less interesting).
   1.158 +*/
   1.159 +#define DELAYED_RESOURCE_CNT	64
   1.160 +
   1.161 +#define PCI_DEVICE_ID_HP_SX2000_IOC	0x12ec
   1.162 +
   1.163 +#define ZX1_IOC_ID	((PCI_DEVICE_ID_HP_ZX1_IOC << 16) | PCI_VENDOR_ID_HP)
   1.164 +#define ZX2_IOC_ID	((PCI_DEVICE_ID_HP_ZX2_IOC << 16) | PCI_VENDOR_ID_HP)
   1.165 +#define REO_IOC_ID	((PCI_DEVICE_ID_HP_REO_IOC << 16) | PCI_VENDOR_ID_HP)
   1.166 +#define SX1000_IOC_ID	((PCI_DEVICE_ID_HP_SX1000_IOC << 16) | PCI_VENDOR_ID_HP)
   1.167 +#define SX2000_IOC_ID	((PCI_DEVICE_ID_HP_SX2000_IOC << 16) | PCI_VENDOR_ID_HP)
   1.168 +
   1.169 +#define ZX1_IOC_OFFSET	0x1000	/* ACPI reports SBA, we want IOC */
   1.170 +
   1.171 +#define IOC_FUNC_ID	0x000
   1.172 +#define IOC_FCLASS	0x008	/* function class, bist, header, rev... */
   1.173 +#define IOC_IBASE	0x300	/* IO TLB */
   1.174 +#define IOC_IMASK	0x308
   1.175 +#define IOC_PCOM	0x310
   1.176 +#define IOC_TCNFG	0x318
   1.177 +#define IOC_PDIR_BASE	0x320
   1.178 +
   1.179 +#define IOC_ROPE0_CFG	0x500
   1.180 +#define   IOC_ROPE_AO	  0x10	/* Allow "Relaxed Ordering" */
   1.181 +
   1.182 +
   1.183 +/* AGP GART driver looks for this */
   1.184 +#define ZX1_SBA_IOMMU_COOKIE	0x0000badbadc0ffeeUL
   1.185 +
   1.186 +/*
   1.187 +** The zx1 IOC supports 4/8/16/64KB page sizes (see TCNFG register)
   1.188 +**
   1.189 +** Some IOCs (sx1000) can run at the above pages sizes, but are
   1.190 +** really only supported using the IOC at a 4k page size.
   1.191 +**
   1.192 +** iovp_size could only be greater than PAGE_SIZE if we are
   1.193 +** confident the drivers really only touch the next physical
   1.194 +** page iff that driver instance owns it.
   1.195 +*/
   1.196 +static unsigned long iovp_size;
   1.197 +static unsigned long iovp_shift;
   1.198 +static unsigned long iovp_mask;
   1.199 +
   1.200 +struct ioc {
   1.201 +	void __iomem	*ioc_hpa;	/* I/O MMU base address */
   1.202 +	char		*res_map;	/* resource map, bit == pdir entry */
   1.203 +	u64		*pdir_base;	/* physical base address */
   1.204 +	unsigned long	ibase;		/* pdir IOV Space base */
   1.205 +	unsigned long	imask;		/* pdir IOV Space mask */
   1.206 +
   1.207 +	unsigned long	*res_hint;	/* next avail IOVP - circular search */
   1.208 +	unsigned long	dma_mask;
   1.209 +	spinlock_t	res_lock;	/* protects the resource bitmap, but must be held when */
   1.210 +					/* clearing pdir to prevent races with allocations. */
   1.211 +	unsigned int	res_bitshift;	/* from the RIGHT! */
   1.212 +	unsigned int	res_size;	/* size of resource map in bytes */
   1.213 +#ifdef CONFIG_NUMA
   1.214 +	unsigned int	node;		/* node where this IOC lives */
   1.215 +#endif
   1.216 +#if DELAYED_RESOURCE_CNT > 0
   1.217 +	spinlock_t	saved_lock;	/* may want to try to get this on a separate cacheline */
   1.218 +					/* than res_lock for bigger systems. */
   1.219 +	int		saved_cnt;
   1.220 +	struct sba_dma_pair {
   1.221 +		dma_addr_t	iova;
   1.222 +		size_t		size;
   1.223 +	} saved[DELAYED_RESOURCE_CNT];
   1.224 +#endif
   1.225 +
   1.226 +#ifdef PDIR_SEARCH_TIMING
   1.227 +#define SBA_SEARCH_SAMPLE	0x100
   1.228 +	unsigned long avg_search[SBA_SEARCH_SAMPLE];
   1.229 +	unsigned long avg_idx;	/* current index into avg_search */
   1.230 +#endif
   1.231 +
   1.232 +	/* Stuff we don't need in performance path */
   1.233 +	struct ioc	*next;		/* list of IOC's in system */
   1.234 +	acpi_handle	handle;		/* for multiple IOC's */
   1.235 +	const char 	*name;
   1.236 +	unsigned int	func_id;
   1.237 +	unsigned int	rev;		/* HW revision of chip */
   1.238 +	u32		iov_size;
   1.239 +	unsigned int	pdir_size;	/* in bytes, determined by IOV Space size */
   1.240 +	struct pci_dev	*sac_only_dev;
   1.241 +};
   1.242 +
   1.243 +static struct ioc *ioc_list;
   1.244 +static int reserve_sba_gart = 1;
   1.245 +
   1.246 +static SBA_INLINE void sba_mark_invalid(struct ioc *, dma_addr_t, size_t);
   1.247 +static SBA_INLINE void sba_free_range(struct ioc *, dma_addr_t, size_t);
   1.248 +
   1.249 +#define sba_sg_address(sg)	(page_address((sg)->page) + (sg)->offset)
   1.250 +
   1.251 +#ifdef FULL_VALID_PDIR
   1.252 +static u64 prefetch_spill_page;
   1.253 +#endif
   1.254 +
   1.255 +#ifdef CONFIG_PCI
   1.256 +# define GET_IOC(dev)	(((dev)->bus == &pci_bus_type)						\
   1.257 +			 ? ((struct ioc *) PCI_CONTROLLER(to_pci_dev(dev))->iommu) : NULL)
   1.258 +#else
   1.259 +# define GET_IOC(dev)	NULL
   1.260 +#endif
   1.261 +
   1.262 +/*
   1.263 +** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up
   1.264 +** (or rather not merge) DMA's into managable chunks.
   1.265 +** On parisc, this is more of the software/tuning constraint
   1.266 +** rather than the HW. I/O MMU allocation alogorithms can be
   1.267 +** faster with smaller size is (to some degree).
   1.268 +*/
   1.269 +#define DMA_CHUNK_SIZE  (BITS_PER_LONG*iovp_size)
   1.270 +
   1.271 +#define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1))
   1.272 +
   1.273 +/************************************
   1.274 +** SBA register read and write support
   1.275 +**
   1.276 +** BE WARNED: register writes are posted.
   1.277 +**  (ie follow writes which must reach HW with a read)
   1.278 +**
   1.279 +*/
   1.280 +#define READ_REG(addr)       __raw_readq(addr)
   1.281 +#define WRITE_REG(val, addr) __raw_writeq(val, addr)
   1.282 +
   1.283 +#ifdef DEBUG_SBA_INIT
   1.284 +
   1.285 +/**
   1.286 + * sba_dump_tlb - debugging only - print IOMMU operating parameters
   1.287 + * @hpa: base address of the IOMMU
   1.288 + *
   1.289 + * Print the size/location of the IO MMU PDIR.
   1.290 + */
   1.291 +static void
   1.292 +sba_dump_tlb(char *hpa)
   1.293 +{
   1.294 +	DBG_INIT("IO TLB at 0x%p\n", (void *)hpa);
   1.295 +	DBG_INIT("IOC_IBASE    : %016lx\n", READ_REG(hpa+IOC_IBASE));
   1.296 +	DBG_INIT("IOC_IMASK    : %016lx\n", READ_REG(hpa+IOC_IMASK));
   1.297 +	DBG_INIT("IOC_TCNFG    : %016lx\n", READ_REG(hpa+IOC_TCNFG));
   1.298 +	DBG_INIT("IOC_PDIR_BASE: %016lx\n", READ_REG(hpa+IOC_PDIR_BASE));
   1.299 +	DBG_INIT("\n");
   1.300 +}
   1.301 +#endif
   1.302 +
   1.303 +
   1.304 +#ifdef ASSERT_PDIR_SANITY
   1.305 +
   1.306 +/**
   1.307 + * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
   1.308 + * @ioc: IO MMU structure which owns the pdir we are interested in.
   1.309 + * @msg: text to print ont the output line.
   1.310 + * @pide: pdir index.
   1.311 + *
   1.312 + * Print one entry of the IO MMU PDIR in human readable form.
   1.313 + */
   1.314 +static void
   1.315 +sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
   1.316 +{
   1.317 +	/* start printing from lowest pde in rval */
   1.318 +	u64 *ptr = &ioc->pdir_base[pide  & ~(BITS_PER_LONG - 1)];
   1.319 +	unsigned long *rptr = (unsigned long *) &ioc->res_map[(pide >>3) & -sizeof(unsigned long)];
   1.320 +	uint rcnt;
   1.321 +
   1.322 +	printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
   1.323 +		 msg, rptr, pide & (BITS_PER_LONG - 1), *rptr);
   1.324 +
   1.325 +	rcnt = 0;
   1.326 +	while (rcnt < BITS_PER_LONG) {
   1.327 +		printk(KERN_DEBUG "%s %2d %p %016Lx\n",
   1.328 +		       (rcnt == (pide & (BITS_PER_LONG - 1)))
   1.329 +		       ? "    -->" : "       ",
   1.330 +		       rcnt, ptr, (unsigned long long) *ptr );
   1.331 +		rcnt++;
   1.332 +		ptr++;
   1.333 +	}
   1.334 +	printk(KERN_DEBUG "%s", msg);
   1.335 +}
   1.336 +
   1.337 +
   1.338 +/**
   1.339 + * sba_check_pdir - debugging only - consistency checker
   1.340 + * @ioc: IO MMU structure which owns the pdir we are interested in.
   1.341 + * @msg: text to print ont the output line.
   1.342 + *
   1.343 + * Verify the resource map and pdir state is consistent
   1.344 + */
   1.345 +static int
   1.346 +sba_check_pdir(struct ioc *ioc, char *msg)
   1.347 +{
   1.348 +	u64 *rptr_end = (u64 *) &(ioc->res_map[ioc->res_size]);
   1.349 +	u64 *rptr = (u64 *) ioc->res_map;	/* resource map ptr */
   1.350 +	u64 *pptr = ioc->pdir_base;	/* pdir ptr */
   1.351 +	uint pide = 0;
   1.352 +
   1.353 +	while (rptr < rptr_end) {
   1.354 +		u64 rval;
   1.355 +		int rcnt; /* number of bits we might check */
   1.356 +
   1.357 +		rval = *rptr;
   1.358 +		rcnt = 64;
   1.359 +
   1.360 +		while (rcnt) {
   1.361 +			/* Get last byte and highest bit from that */
   1.362 +			u32 pde = ((u32)((*pptr >> (63)) & 0x1));
   1.363 +			if ((rval & 0x1) ^ pde)
   1.364 +			{
   1.365 +				/*
   1.366 +				** BUMMER!  -- res_map != pdir --
   1.367 +				** Dump rval and matching pdir entries
   1.368 +				*/
   1.369 +				sba_dump_pdir_entry(ioc, msg, pide);
   1.370 +				return(1);
   1.371 +			}
   1.372 +			rcnt--;
   1.373 +			rval >>= 1;	/* try the next bit */
   1.374 +			pptr++;
   1.375 +			pide++;
   1.376 +		}
   1.377 +		rptr++;	/* look at next word of res_map */
   1.378 +	}
   1.379 +	/* It'd be nice if we always got here :^) */
   1.380 +	return 0;
   1.381 +}
   1.382 +
   1.383 +
   1.384 +/**
   1.385 + * sba_dump_sg - debugging only - print Scatter-Gather list
   1.386 + * @ioc: IO MMU structure which owns the pdir we are interested in.
   1.387 + * @startsg: head of the SG list
   1.388 + * @nents: number of entries in SG list
   1.389 + *
   1.390 + * print the SG list so we can verify it's correct by hand.
   1.391 + */
   1.392 +static void
   1.393 +sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
   1.394 +{
   1.395 +	while (nents-- > 0) {
   1.396 +		printk(KERN_DEBUG " %d : DMA %08lx/%05x CPU %p\n", nents,
   1.397 +		       startsg->dma_address, startsg->dma_length,
   1.398 +		       sba_sg_address(startsg));
   1.399 +		startsg++;
   1.400 +	}
   1.401 +}
   1.402 +
   1.403 +static void
   1.404 +sba_check_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
   1.405 +{
   1.406 +	struct scatterlist *the_sg = startsg;
   1.407 +	int the_nents = nents;
   1.408 +
   1.409 +	while (the_nents-- > 0) {
   1.410 +		if (sba_sg_address(the_sg) == 0x0UL)
   1.411 +			sba_dump_sg(NULL, startsg, nents);
   1.412 +		the_sg++;
   1.413 +	}
   1.414 +}
   1.415 +
   1.416 +#endif /* ASSERT_PDIR_SANITY */
   1.417 +
   1.418 +
   1.419 +
   1.420 +
   1.421 +/**************************************************************
   1.422 +*
   1.423 +*   I/O Pdir Resource Management
   1.424 +*
   1.425 +*   Bits set in the resource map are in use.
   1.426 +*   Each bit can represent a number of pages.
   1.427 +*   LSbs represent lower addresses (IOVA's).
   1.428 +*
   1.429 +***************************************************************/
   1.430 +#define PAGES_PER_RANGE 1	/* could increase this to 4 or 8 if needed */
   1.431 +
   1.432 +/* Convert from IOVP to IOVA and vice versa. */
   1.433 +#define SBA_IOVA(ioc,iovp,offset) ((ioc->ibase) | (iovp) | (offset))
   1.434 +#define SBA_IOVP(ioc,iova) ((iova) & ~(ioc->ibase))
   1.435 +
   1.436 +#define PDIR_ENTRY_SIZE	sizeof(u64)
   1.437 +
   1.438 +#define PDIR_INDEX(iovp)   ((iovp)>>iovp_shift)
   1.439 +
   1.440 +#define RESMAP_MASK(n)    ~(~0UL << (n))
   1.441 +#define RESMAP_IDX_MASK   (sizeof(unsigned long) - 1)
   1.442 +
   1.443 +
   1.444 +/**
   1.445 + * For most cases the normal get_order is sufficient, however it limits us
   1.446 + * to PAGE_SIZE being the minimum mapping alignment and TC flush granularity.
   1.447 + * It only incurs about 1 clock cycle to use this one with the static variable
   1.448 + * and makes the code more intuitive.
   1.449 + */
   1.450 +static SBA_INLINE int
   1.451 +get_iovp_order (unsigned long size)
   1.452 +{
   1.453 +	long double d = size - 1;
   1.454 +	long order;
   1.455 +
   1.456 +	order = ia64_getf_exp(d);
   1.457 +	order = order - iovp_shift - 0xffff + 1;
   1.458 +	if (order < 0)
   1.459 +		order = 0;
   1.460 +	return order;
   1.461 +}
   1.462 +
   1.463 +/**
   1.464 + * sba_search_bitmap - find free space in IO PDIR resource bitmap
   1.465 + * @ioc: IO MMU structure which owns the pdir we are interested in.
   1.466 + * @bits_wanted: number of entries we need.
   1.467 + * @use_hint: use res_hint to indicate where to start looking
   1.468 + *
   1.469 + * Find consecutive free bits in resource bitmap.
   1.470 + * Each bit represents one entry in the IO Pdir.
   1.471 + * Cool perf optimization: search for log2(size) bits at a time.
   1.472 + */
   1.473 +static SBA_INLINE unsigned long
   1.474 +sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted, int use_hint)
   1.475 +{
   1.476 +	unsigned long *res_ptr;
   1.477 +	unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
   1.478 +	unsigned long flags, pide = ~0UL;
   1.479 +
   1.480 +	ASSERT(((unsigned long) ioc->res_hint & (sizeof(unsigned long) - 1UL)) == 0);
   1.481 +	ASSERT(res_ptr < res_end);
   1.482 +
   1.483 +	spin_lock_irqsave(&ioc->res_lock, flags);
   1.484 +
   1.485 +	/* Allow caller to force a search through the entire resource space */
   1.486 +	if (likely(use_hint)) {
   1.487 +		res_ptr = ioc->res_hint;
   1.488 +	} else {
   1.489 +		res_ptr = (ulong *)ioc->res_map;
   1.490 +		ioc->res_bitshift = 0;
   1.491 +	}
   1.492 +
   1.493 +	/*
   1.494 +	 * N.B.  REO/Grande defect AR2305 can cause TLB fetch timeouts
   1.495 +	 * if a TLB entry is purged while in use.  sba_mark_invalid()
   1.496 +	 * purges IOTLB entries in power-of-two sizes, so we also
   1.497 +	 * allocate IOVA space in power-of-two sizes.
   1.498 +	 */
   1.499 +	bits_wanted = 1UL << get_iovp_order(bits_wanted << iovp_shift);
   1.500 +
   1.501 +	if (likely(bits_wanted == 1)) {
   1.502 +		unsigned int bitshiftcnt;
   1.503 +		for(; res_ptr < res_end ; res_ptr++) {
   1.504 +			if (likely(*res_ptr != ~0UL)) {
   1.505 +				bitshiftcnt = ffz(*res_ptr);
   1.506 +				*res_ptr |= (1UL << bitshiftcnt);
   1.507 +				pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
   1.508 +				pide <<= 3;	/* convert to bit address */
   1.509 +				pide += bitshiftcnt;
   1.510 +				ioc->res_bitshift = bitshiftcnt + bits_wanted;
   1.511 +				goto found_it;
   1.512 +			}
   1.513 +		}
   1.514 +		goto not_found;
   1.515 +
   1.516 +	}
   1.517 +	
   1.518 +	if (likely(bits_wanted <= BITS_PER_LONG/2)) {
   1.519 +		/*
   1.520 +		** Search the resource bit map on well-aligned values.
   1.521 +		** "o" is the alignment.
   1.522 +		** We need the alignment to invalidate I/O TLB using
   1.523 +		** SBA HW features in the unmap path.
   1.524 +		*/
   1.525 +		unsigned long o = 1 << get_iovp_order(bits_wanted << iovp_shift);
   1.526 +		uint bitshiftcnt = ROUNDUP(ioc->res_bitshift, o);
   1.527 +		unsigned long mask, base_mask;
   1.528 +
   1.529 +		base_mask = RESMAP_MASK(bits_wanted);
   1.530 +		mask = base_mask << bitshiftcnt;
   1.531 +
   1.532 +		DBG_RES("%s() o %ld %p", __FUNCTION__, o, res_ptr);
   1.533 +		for(; res_ptr < res_end ; res_ptr++)
   1.534 +		{ 
   1.535 +			DBG_RES("    %p %lx %lx\n", res_ptr, mask, *res_ptr);
   1.536 +			ASSERT(0 != mask);
   1.537 +			for (; mask ; mask <<= o, bitshiftcnt += o) {
   1.538 +				if(0 == ((*res_ptr) & mask)) {
   1.539 +					*res_ptr |= mask;     /* mark resources busy! */
   1.540 +					pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
   1.541 +					pide <<= 3;	/* convert to bit address */
   1.542 +					pide += bitshiftcnt;
   1.543 +					ioc->res_bitshift = bitshiftcnt + bits_wanted;
   1.544 +					goto found_it;
   1.545 +				}
   1.546 +			}
   1.547 +
   1.548 +			bitshiftcnt = 0;
   1.549 +			mask = base_mask;
   1.550 +
   1.551 +		}
   1.552 +
   1.553 +	} else {
   1.554 +		int qwords, bits, i;
   1.555 +		unsigned long *end;
   1.556 +
   1.557 +		qwords = bits_wanted >> 6; /* /64 */
   1.558 +		bits = bits_wanted - (qwords * BITS_PER_LONG);
   1.559 +
   1.560 +		end = res_end - qwords;
   1.561 +
   1.562 +		for (; res_ptr < end; res_ptr++) {
   1.563 +			for (i = 0 ; i < qwords ; i++) {
   1.564 +				if (res_ptr[i] != 0)
   1.565 +					goto next_ptr;
   1.566 +			}
   1.567 +			if (bits && res_ptr[i] && (__ffs(res_ptr[i]) < bits))
   1.568 +				continue;
   1.569 +
   1.570 +			/* Found it, mark it */
   1.571 +			for (i = 0 ; i < qwords ; i++)
   1.572 +				res_ptr[i] = ~0UL;
   1.573 +			res_ptr[i] |= RESMAP_MASK(bits);
   1.574 +
   1.575 +			pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
   1.576 +			pide <<= 3;	/* convert to bit address */
   1.577 +			res_ptr += qwords;
   1.578 +			ioc->res_bitshift = bits;
   1.579 +			goto found_it;
   1.580 +next_ptr:
   1.581 +			;
   1.582 +		}
   1.583 +	}
   1.584 +
   1.585 +not_found:
   1.586 +	prefetch(ioc->res_map);
   1.587 +	ioc->res_hint = (unsigned long *) ioc->res_map;
   1.588 +	ioc->res_bitshift = 0;
   1.589 +	spin_unlock_irqrestore(&ioc->res_lock, flags);
   1.590 +	return (pide);
   1.591 +
   1.592 +found_it:
   1.593 +	ioc->res_hint = res_ptr;
   1.594 +	spin_unlock_irqrestore(&ioc->res_lock, flags);
   1.595 +	return (pide);
   1.596 +}
   1.597 +
   1.598 +
   1.599 +/**
   1.600 + * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
   1.601 + * @ioc: IO MMU structure which owns the pdir we are interested in.
   1.602 + * @size: number of bytes to create a mapping for
   1.603 + *
   1.604 + * Given a size, find consecutive unmarked and then mark those bits in the
   1.605 + * resource bit map.
   1.606 + */
   1.607 +static int
   1.608 +sba_alloc_range(struct ioc *ioc, size_t size)
   1.609 +{
   1.610 +	unsigned int pages_needed = size >> iovp_shift;
   1.611 +#ifdef PDIR_SEARCH_TIMING
   1.612 +	unsigned long itc_start;
   1.613 +#endif
   1.614 +	unsigned long pide;
   1.615 +
   1.616 +	ASSERT(pages_needed);
   1.617 +	ASSERT(0 == (size & ~iovp_mask));
   1.618 +
   1.619 +#ifdef PDIR_SEARCH_TIMING
   1.620 +	itc_start = ia64_get_itc();
   1.621 +#endif
   1.622 +	/*
   1.623 +	** "seek and ye shall find"...praying never hurts either...
   1.624 +	*/
   1.625 +	pide = sba_search_bitmap(ioc, pages_needed, 1);
   1.626 +	if (unlikely(pide >= (ioc->res_size << 3))) {
   1.627 +		pide = sba_search_bitmap(ioc, pages_needed, 0);
   1.628 +		if (unlikely(pide >= (ioc->res_size << 3))) {
   1.629 +#if DELAYED_RESOURCE_CNT > 0
   1.630 +			unsigned long flags;
   1.631 +
   1.632 +			/*
   1.633 +			** With delayed resource freeing, we can give this one more shot.  We're
   1.634 +			** getting close to being in trouble here, so do what we can to make this
   1.635 +			** one count.
   1.636 +			*/
   1.637 +			spin_lock_irqsave(&ioc->saved_lock, flags);
   1.638 +			if (ioc->saved_cnt > 0) {
   1.639 +				struct sba_dma_pair *d;
   1.640 +				int cnt = ioc->saved_cnt;
   1.641 +
   1.642 +				d = &(ioc->saved[ioc->saved_cnt - 1]);
   1.643 +
   1.644 +				spin_lock(&ioc->res_lock);
   1.645 +				while (cnt--) {
   1.646 +					sba_mark_invalid(ioc, d->iova, d->size);
   1.647 +					sba_free_range(ioc, d->iova, d->size);
   1.648 +					d--;
   1.649 +				}
   1.650 +				ioc->saved_cnt = 0;
   1.651 +				READ_REG(ioc->ioc_hpa+IOC_PCOM);	/* flush purges */
   1.652 +				spin_unlock(&ioc->res_lock);
   1.653 +			}
   1.654 +			spin_unlock_irqrestore(&ioc->saved_lock, flags);
   1.655 +
   1.656 +			pide = sba_search_bitmap(ioc, pages_needed, 0);
   1.657 +			if (unlikely(pide >= (ioc->res_size << 3)))
   1.658 +				panic(__FILE__ ": I/O MMU @ %p is out of mapping resources\n",
   1.659 +				      ioc->ioc_hpa);
   1.660 +#else
   1.661 +			panic(__FILE__ ": I/O MMU @ %p is out of mapping resources\n",
   1.662 +			      ioc->ioc_hpa);
   1.663 +#endif
   1.664 +		}
   1.665 +	}
   1.666 +
   1.667 +#ifdef PDIR_SEARCH_TIMING
   1.668 +	ioc->avg_search[ioc->avg_idx++] = (ia64_get_itc() - itc_start) / pages_needed;
   1.669 +	ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
   1.670 +#endif
   1.671 +
   1.672 +	prefetchw(&(ioc->pdir_base[pide]));
   1.673 +
   1.674 +#ifdef ASSERT_PDIR_SANITY
   1.675 +	/* verify the first enable bit is clear */
   1.676 +	if(0x00 != ((u8 *) ioc->pdir_base)[pide*PDIR_ENTRY_SIZE + 7]) {
   1.677 +		sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
   1.678 +	}
   1.679 +#endif
   1.680 +
   1.681 +	DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
   1.682 +		__FUNCTION__, size, pages_needed, pide,
   1.683 +		(uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
   1.684 +		ioc->res_bitshift );
   1.685 +
   1.686 +	return (pide);
   1.687 +}
   1.688 +
   1.689 +
   1.690 +/**
   1.691 + * sba_free_range - unmark bits in IO PDIR resource bitmap
   1.692 + * @ioc: IO MMU structure which owns the pdir we are interested in.
   1.693 + * @iova: IO virtual address which was previously allocated.
   1.694 + * @size: number of bytes to create a mapping for
   1.695 + *
   1.696 + * clear bits in the ioc's resource map
   1.697 + */
   1.698 +static SBA_INLINE void
   1.699 +sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
   1.700 +{
   1.701 +	unsigned long iovp = SBA_IOVP(ioc, iova);
   1.702 +	unsigned int pide = PDIR_INDEX(iovp);
   1.703 +	unsigned int ridx = pide >> 3;	/* convert bit to byte address */
   1.704 +	unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
   1.705 +	int bits_not_wanted = size >> iovp_shift;
   1.706 +	unsigned long m;
   1.707 +
   1.708 +	/* Round up to power-of-two size: see AR2305 note above */
   1.709 +	bits_not_wanted = 1UL << get_iovp_order(bits_not_wanted << iovp_shift);
   1.710 +	for (; bits_not_wanted > 0 ; res_ptr++) {
   1.711 +		
   1.712 +		if (unlikely(bits_not_wanted > BITS_PER_LONG)) {
   1.713 +
   1.714 +			/* these mappings start 64bit aligned */
   1.715 +			*res_ptr = 0UL;
   1.716 +			bits_not_wanted -= BITS_PER_LONG;
   1.717 +			pide += BITS_PER_LONG;
   1.718 +
   1.719 +		} else {
   1.720 +
   1.721 +			/* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
   1.722 +			m = RESMAP_MASK(bits_not_wanted) << (pide & (BITS_PER_LONG - 1));
   1.723 +			bits_not_wanted = 0;
   1.724 +
   1.725 +			DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n", __FUNCTION__, (uint) iova, size,
   1.726 +		        	bits_not_wanted, m, pide, res_ptr, *res_ptr);
   1.727 +
   1.728 +			ASSERT(m != 0);
   1.729 +			ASSERT(bits_not_wanted);
   1.730 +			ASSERT((*res_ptr & m) == m); /* verify same bits are set */
   1.731 +			*res_ptr &= ~m;
   1.732 +		}
   1.733 +	}
   1.734 +}
   1.735 +
   1.736 +
   1.737 +/**************************************************************
   1.738 +*
   1.739 +*   "Dynamic DMA Mapping" support (aka "Coherent I/O")
   1.740 +*
   1.741 +***************************************************************/
   1.742 +
   1.743 +/**
   1.744 + * sba_io_pdir_entry - fill in one IO PDIR entry
   1.745 + * @pdir_ptr:  pointer to IO PDIR entry
   1.746 + * @vba: Virtual CPU address of buffer to map
   1.747 + *
   1.748 + * SBA Mapping Routine
   1.749 + *
   1.750 + * Given a virtual address (vba, arg1) sba_io_pdir_entry()
   1.751 + * loads the I/O PDIR entry pointed to by pdir_ptr (arg0).
   1.752 + * Each IO Pdir entry consists of 8 bytes as shown below
   1.753 + * (LSB == bit 0):
   1.754 + *
   1.755 + *  63                    40                                 11    7        0
   1.756 + * +-+---------------------+----------------------------------+----+--------+
   1.757 + * |V|        U            |            PPN[39:12]            | U  |   FF   |
   1.758 + * +-+---------------------+----------------------------------+----+--------+
   1.759 + *
   1.760 + *  V  == Valid Bit
   1.761 + *  U  == Unused
   1.762 + * PPN == Physical Page Number
   1.763 + *
   1.764 + * The physical address fields are filled with the results of virt_to_phys()
   1.765 + * on the vba.
   1.766 + */
   1.767 +
   1.768 +#if 1
   1.769 +#define sba_io_pdir_entry(pdir_ptr, vba) *pdir_ptr = ((vba & ~0xE000000000000FFFULL)	\
   1.770 +						      | 0x8000000000000000ULL)
   1.771 +#else
   1.772 +void SBA_INLINE
   1.773 +sba_io_pdir_entry(u64 *pdir_ptr, unsigned long vba)
   1.774 +{
   1.775 +	*pdir_ptr = ((vba & ~0xE000000000000FFFULL) | 0x80000000000000FFULL);
   1.776 +}
   1.777 +#endif
   1.778 +
   1.779 +#ifdef ENABLE_MARK_CLEAN
   1.780 +/**
   1.781 + * Since DMA is i-cache coherent, any (complete) pages that were written via
   1.782 + * DMA can be marked as "clean" so that lazy_mmu_prot_update() doesn't have to
   1.783 + * flush them when they get mapped into an executable vm-area.
   1.784 + */
   1.785 +static void
   1.786 +mark_clean (void *addr, size_t size)
   1.787 +{
   1.788 +	unsigned long pg_addr, end;
   1.789 +
   1.790 +	pg_addr = PAGE_ALIGN((unsigned long) addr);
   1.791 +	end = (unsigned long) addr + size;
   1.792 +	while (pg_addr + PAGE_SIZE <= end) {
   1.793 +		struct page *page = virt_to_page((void *)pg_addr);
   1.794 +		set_bit(PG_arch_1, &page->flags);
   1.795 +		pg_addr += PAGE_SIZE;
   1.796 +	}
   1.797 +}
   1.798 +#endif
   1.799 +
   1.800 +/**
   1.801 + * sba_mark_invalid - invalidate one or more IO PDIR entries
   1.802 + * @ioc: IO MMU structure which owns the pdir we are interested in.
   1.803 + * @iova:  IO Virtual Address mapped earlier
   1.804 + * @byte_cnt:  number of bytes this mapping covers.
   1.805 + *
   1.806 + * Marking the IO PDIR entry(ies) as Invalid and invalidate
   1.807 + * corresponding IO TLB entry. The PCOM (Purge Command Register)
   1.808 + * is to purge stale entries in the IO TLB when unmapping entries.
   1.809 + *
   1.810 + * The PCOM register supports purging of multiple pages, with a minium
   1.811 + * of 1 page and a maximum of 2GB. Hardware requires the address be
   1.812 + * aligned to the size of the range being purged. The size of the range
   1.813 + * must be a power of 2. The "Cool perf optimization" in the
   1.814 + * allocation routine helps keep that true.
   1.815 + */
   1.816 +static SBA_INLINE void
   1.817 +sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
   1.818 +{
   1.819 +	u32 iovp = (u32) SBA_IOVP(ioc,iova);
   1.820 +
   1.821 +	int off = PDIR_INDEX(iovp);
   1.822 +
   1.823 +	/* Must be non-zero and rounded up */
   1.824 +	ASSERT(byte_cnt > 0);
   1.825 +	ASSERT(0 == (byte_cnt & ~iovp_mask));
   1.826 +
   1.827 +#ifdef ASSERT_PDIR_SANITY
   1.828 +	/* Assert first pdir entry is set */
   1.829 +	if (!(ioc->pdir_base[off] >> 60)) {
   1.830 +		sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
   1.831 +	}
   1.832 +#endif
   1.833 +
   1.834 +	if (byte_cnt <= iovp_size)
   1.835 +	{
   1.836 +		ASSERT(off < ioc->pdir_size);
   1.837 +
   1.838 +		iovp |= iovp_shift;     /* set "size" field for PCOM */
   1.839 +
   1.840 +#ifndef FULL_VALID_PDIR
   1.841 +		/*
   1.842 +		** clear I/O PDIR entry "valid" bit
   1.843 +		** Do NOT clear the rest - save it for debugging.
   1.844 +		** We should only clear bits that have previously
   1.845 +		** been enabled.
   1.846 +		*/
   1.847 +		ioc->pdir_base[off] &= ~(0x80000000000000FFULL);
   1.848 +#else
   1.849 +		/*
   1.850 +  		** If we want to maintain the PDIR as valid, put in
   1.851 +		** the spill page so devices prefetching won't
   1.852 +		** cause a hard fail.
   1.853 +		*/
   1.854 +		ioc->pdir_base[off] = (0x80000000000000FFULL | prefetch_spill_page);
   1.855 +#endif
   1.856 +	} else {
   1.857 +		u32 t = get_iovp_order(byte_cnt) + iovp_shift;
   1.858 +
   1.859 +		iovp |= t;
   1.860 +		ASSERT(t <= 31);   /* 2GB! Max value of "size" field */
   1.861 +
   1.862 +		do {
   1.863 +			/* verify this pdir entry is enabled */
   1.864 +			ASSERT(ioc->pdir_base[off]  >> 63);
   1.865 +#ifndef FULL_VALID_PDIR
   1.866 +			/* clear I/O Pdir entry "valid" bit first */
   1.867 +			ioc->pdir_base[off] &= ~(0x80000000000000FFULL);
   1.868 +#else
   1.869 +			ioc->pdir_base[off] = (0x80000000000000FFULL | prefetch_spill_page);
   1.870 +#endif
   1.871 +			off++;
   1.872 +			byte_cnt -= iovp_size;
   1.873 +		} while (byte_cnt > 0);
   1.874 +	}
   1.875 +
   1.876 +	WRITE_REG(iovp | ioc->ibase, ioc->ioc_hpa+IOC_PCOM);
   1.877 +}
   1.878 +
   1.879 +/**
   1.880 + * sba_map_single - map one buffer and return IOVA for DMA
   1.881 + * @dev: instance of PCI owned by the driver that's asking.
   1.882 + * @addr:  driver buffer to map.
   1.883 + * @size:  number of bytes to map in driver buffer.
   1.884 + * @dir:  R/W or both.
   1.885 + *
   1.886 + * See Documentation/DMA-mapping.txt
   1.887 + */
   1.888 +dma_addr_t
   1.889 +sba_map_single(struct device *dev, void *addr, size_t size, int dir)
   1.890 +{
   1.891 +	struct ioc *ioc;
   1.892 +	dma_addr_t iovp;
   1.893 +	dma_addr_t offset;
   1.894 +	u64 *pdir_start;
   1.895 +	int pide;
   1.896 +#ifdef ASSERT_PDIR_SANITY
   1.897 +	unsigned long flags;
   1.898 +#endif
   1.899 +#ifdef ALLOW_IOV_BYPASS
   1.900 +	unsigned long pci_addr = virt_to_phys(addr);
   1.901 +#endif
   1.902 +
   1.903 +#ifdef ALLOW_IOV_BYPASS
   1.904 +	ASSERT(to_pci_dev(dev)->dma_mask);
   1.905 +	/*
   1.906 + 	** Check if the PCI device can DMA to ptr... if so, just return ptr
   1.907 + 	*/
   1.908 +	if (likely((pci_addr & ~to_pci_dev(dev)->dma_mask) == 0)) {
   1.909 +		/*
   1.910 + 		** Device is bit capable of DMA'ing to the buffer...
   1.911 +		** just return the PCI address of ptr
   1.912 + 		*/
   1.913 +		DBG_BYPASS("sba_map_single() bypass mask/addr: 0x%lx/0x%lx\n",
   1.914 +		           to_pci_dev(dev)->dma_mask, pci_addr);
   1.915 +		return pci_addr;
   1.916 +	}
   1.917 +#endif
   1.918 +	ioc = GET_IOC(dev);
   1.919 +	ASSERT(ioc);
   1.920 +
   1.921 +	prefetch(ioc->res_hint);
   1.922 +
   1.923 +	ASSERT(size > 0);
   1.924 +	ASSERT(size <= DMA_CHUNK_SIZE);
   1.925 +
   1.926 +	/* save offset bits */
   1.927 +	offset = ((dma_addr_t) (long) addr) & ~iovp_mask;
   1.928 +
   1.929 +	/* round up to nearest iovp_size */
   1.930 +	size = (size + offset + ~iovp_mask) & iovp_mask;
   1.931 +
   1.932 +#ifdef ASSERT_PDIR_SANITY
   1.933 +	spin_lock_irqsave(&ioc->res_lock, flags);
   1.934 +	if (sba_check_pdir(ioc,"Check before sba_map_single()"))
   1.935 +		panic("Sanity check failed");
   1.936 +	spin_unlock_irqrestore(&ioc->res_lock, flags);
   1.937 +#endif
   1.938 +
   1.939 +	pide = sba_alloc_range(ioc, size);
   1.940 +
   1.941 +	iovp = (dma_addr_t) pide << iovp_shift;
   1.942 +
   1.943 +	DBG_RUN("%s() 0x%p -> 0x%lx\n",
   1.944 +		__FUNCTION__, addr, (long) iovp | offset);
   1.945 +
   1.946 +	pdir_start = &(ioc->pdir_base[pide]);
   1.947 +
   1.948 +	while (size > 0) {
   1.949 +		ASSERT(((u8 *)pdir_start)[7] == 0); /* verify availability */
   1.950 +		sba_io_pdir_entry(pdir_start, (unsigned long) addr);
   1.951 +
   1.952 +		DBG_RUN("     pdir 0x%p %lx\n", pdir_start, *pdir_start);
   1.953 +
   1.954 +		addr += iovp_size;
   1.955 +		size -= iovp_size;
   1.956 +		pdir_start++;
   1.957 +	}
   1.958 +	/* force pdir update */
   1.959 +	wmb();
   1.960 +
   1.961 +	/* form complete address */
   1.962 +#ifdef ASSERT_PDIR_SANITY
   1.963 +	spin_lock_irqsave(&ioc->res_lock, flags);
   1.964 +	sba_check_pdir(ioc,"Check after sba_map_single()");
   1.965 +	spin_unlock_irqrestore(&ioc->res_lock, flags);
   1.966 +#endif
   1.967 +	return SBA_IOVA(ioc, iovp, offset);
   1.968 +}
   1.969 +
   1.970 +#ifdef ENABLE_MARK_CLEAN
   1.971 +static SBA_INLINE void
   1.972 +sba_mark_clean(struct ioc *ioc, dma_addr_t iova, size_t size)
   1.973 +{
   1.974 +	u32	iovp = (u32) SBA_IOVP(ioc,iova);
   1.975 +	int	off = PDIR_INDEX(iovp);
   1.976 +	void	*addr;
   1.977 +
   1.978 +	if (size <= iovp_size) {
   1.979 +		addr = phys_to_virt(ioc->pdir_base[off] &
   1.980 +		                    ~0xE000000000000FFFULL);
   1.981 +		mark_clean(addr, size);
   1.982 +	} else {
   1.983 +		do {
   1.984 +			addr = phys_to_virt(ioc->pdir_base[off] &
   1.985 +			                    ~0xE000000000000FFFULL);
   1.986 +			mark_clean(addr, min(size, iovp_size));
   1.987 +			off++;
   1.988 +			size -= iovp_size;
   1.989 +		} while (size > 0);
   1.990 +	}
   1.991 +}
   1.992 +#endif
   1.993 +
   1.994 +/**
   1.995 + * sba_unmap_single - unmap one IOVA and free resources
   1.996 + * @dev: instance of PCI owned by the driver that's asking.
   1.997 + * @iova:  IOVA of driver buffer previously mapped.
   1.998 + * @size:  number of bytes mapped in driver buffer.
   1.999 + * @dir:  R/W or both.
  1.1000 + *
  1.1001 + * See Documentation/DMA-mapping.txt
  1.1002 + */
  1.1003 +void sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size, int dir)
  1.1004 +{
  1.1005 +	struct ioc *ioc;
  1.1006 +#if DELAYED_RESOURCE_CNT > 0
  1.1007 +	struct sba_dma_pair *d;
  1.1008 +#endif
  1.1009 +	unsigned long flags;
  1.1010 +	dma_addr_t offset;
  1.1011 +
  1.1012 +	ioc = GET_IOC(dev);
  1.1013 +	ASSERT(ioc);
  1.1014 +
  1.1015 +#ifdef ALLOW_IOV_BYPASS
  1.1016 +	if (likely((iova & ioc->imask) != ioc->ibase)) {
  1.1017 +		/*
  1.1018 +		** Address does not fall w/in IOVA, must be bypassing
  1.1019 +		*/
  1.1020 +		DBG_BYPASS("sba_unmap_single() bypass addr: 0x%lx\n", iova);
  1.1021 +
  1.1022 +#ifdef ENABLE_MARK_CLEAN
  1.1023 +		if (dir == DMA_FROM_DEVICE) {
  1.1024 +			mark_clean(phys_to_virt(iova), size);
  1.1025 +		}
  1.1026 +#endif
  1.1027 +		return;
  1.1028 +	}
  1.1029 +#endif
  1.1030 +	offset = iova & ~iovp_mask;
  1.1031 +
  1.1032 +	DBG_RUN("%s() iovp 0x%lx/%x\n",
  1.1033 +		__FUNCTION__, (long) iova, size);
  1.1034 +
  1.1035 +	iova ^= offset;        /* clear offset bits */
  1.1036 +	size += offset;
  1.1037 +	size = ROUNDUP(size, iovp_size);
  1.1038 +
  1.1039 +#ifdef ENABLE_MARK_CLEAN
  1.1040 +	if (dir == DMA_FROM_DEVICE)
  1.1041 +		sba_mark_clean(ioc, iova, size);
  1.1042 +#endif
  1.1043 +
  1.1044 +#if DELAYED_RESOURCE_CNT > 0
  1.1045 +	spin_lock_irqsave(&ioc->saved_lock, flags);
  1.1046 +	d = &(ioc->saved[ioc->saved_cnt]);
  1.1047 +	d->iova = iova;
  1.1048 +	d->size = size;
  1.1049 +	if (unlikely(++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT)) {
  1.1050 +		int cnt = ioc->saved_cnt;
  1.1051 +		spin_lock(&ioc->res_lock);
  1.1052 +		while (cnt--) {
  1.1053 +			sba_mark_invalid(ioc, d->iova, d->size);
  1.1054 +			sba_free_range(ioc, d->iova, d->size);
  1.1055 +			d--;
  1.1056 +		}
  1.1057 +		ioc->saved_cnt = 0;
  1.1058 +		READ_REG(ioc->ioc_hpa+IOC_PCOM);	/* flush purges */
  1.1059 +		spin_unlock(&ioc->res_lock);
  1.1060 +	}
  1.1061 +	spin_unlock_irqrestore(&ioc->saved_lock, flags);
  1.1062 +#else /* DELAYED_RESOURCE_CNT == 0 */
  1.1063 +	spin_lock_irqsave(&ioc->res_lock, flags);
  1.1064 +	sba_mark_invalid(ioc, iova, size);
  1.1065 +	sba_free_range(ioc, iova, size);
  1.1066 +	READ_REG(ioc->ioc_hpa+IOC_PCOM);	/* flush purges */
  1.1067 +	spin_unlock_irqrestore(&ioc->res_lock, flags);
  1.1068 +#endif /* DELAYED_RESOURCE_CNT == 0 */
  1.1069 +}
  1.1070 +
  1.1071 +
  1.1072 +/**
  1.1073 + * sba_alloc_coherent - allocate/map shared mem for DMA
  1.1074 + * @dev: instance of PCI owned by the driver that's asking.
  1.1075 + * @size:  number of bytes mapped in driver buffer.
  1.1076 + * @dma_handle:  IOVA of new buffer.
  1.1077 + *
  1.1078 + * See Documentation/DMA-mapping.txt
  1.1079 + */
  1.1080 +void *
  1.1081 +sba_alloc_coherent (struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flags)
  1.1082 +{
  1.1083 +	struct ioc *ioc;
  1.1084 +	void *addr;
  1.1085 +
  1.1086 +	ioc = GET_IOC(dev);
  1.1087 +	ASSERT(ioc);
  1.1088 +
  1.1089 +#ifdef CONFIG_NUMA
  1.1090 +	{
  1.1091 +		struct page *page;
  1.1092 +		page = alloc_pages_node(ioc->node == MAX_NUMNODES ?
  1.1093 +		                        numa_node_id() : ioc->node, flags,
  1.1094 +		                        get_order(size));
  1.1095 +
  1.1096 +		if (unlikely(!page))
  1.1097 +			return NULL;
  1.1098 +
  1.1099 +		addr = page_address(page);
  1.1100 +	}
  1.1101 +#else
  1.1102 +	addr = (void *) __get_free_pages(flags, get_order(size));
  1.1103 +#endif
  1.1104 +	if (unlikely(!addr))
  1.1105 +		return NULL;
  1.1106 +
  1.1107 +	memset(addr, 0, size);
  1.1108 +	*dma_handle = virt_to_phys(addr);
  1.1109 +
  1.1110 +#ifdef ALLOW_IOV_BYPASS
  1.1111 +	ASSERT(dev->coherent_dma_mask);
  1.1112 +	/*
  1.1113 + 	** Check if the PCI device can DMA to ptr... if so, just return ptr
  1.1114 + 	*/
  1.1115 +	if (likely((*dma_handle & ~dev->coherent_dma_mask) == 0)) {
  1.1116 +		DBG_BYPASS("sba_alloc_coherent() bypass mask/addr: 0x%lx/0x%lx\n",
  1.1117 +		           dev->coherent_dma_mask, *dma_handle);
  1.1118 +
  1.1119 +		return addr;
  1.1120 +	}
  1.1121 +#endif
  1.1122 +
  1.1123 +	/*
  1.1124 +	 * If device can't bypass or bypass is disabled, pass the 32bit fake
  1.1125 +	 * device to map single to get an iova mapping.
  1.1126 +	 */
  1.1127 +	*dma_handle = sba_map_single(&ioc->sac_only_dev->dev, addr, size, 0);
  1.1128 +
  1.1129 +	return addr;
  1.1130 +}
  1.1131 +
  1.1132 +
  1.1133 +/**
  1.1134 + * sba_free_coherent - free/unmap shared mem for DMA
  1.1135 + * @dev: instance of PCI owned by the driver that's asking.
  1.1136 + * @size:  number of bytes mapped in driver buffer.
  1.1137 + * @vaddr:  virtual address IOVA of "consistent" buffer.
  1.1138 + * @dma_handler:  IO virtual address of "consistent" buffer.
  1.1139 + *
  1.1140 + * See Documentation/DMA-mapping.txt
  1.1141 + */
  1.1142 +void sba_free_coherent (struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle)
  1.1143 +{
  1.1144 +	sba_unmap_single(dev, dma_handle, size, 0);
  1.1145 +	free_pages((unsigned long) vaddr, get_order(size));
  1.1146 +}
  1.1147 +
  1.1148 +
  1.1149 +/*
  1.1150 +** Since 0 is a valid pdir_base index value, can't use that
  1.1151 +** to determine if a value is valid or not. Use a flag to indicate
  1.1152 +** the SG list entry contains a valid pdir index.
  1.1153 +*/
  1.1154 +#define PIDE_FLAG 0x1UL
  1.1155 +
  1.1156 +#ifdef DEBUG_LARGE_SG_ENTRIES
  1.1157 +int dump_run_sg = 0;
  1.1158 +#endif
  1.1159 +
  1.1160 +
  1.1161 +/**
  1.1162 + * sba_fill_pdir - write allocated SG entries into IO PDIR
  1.1163 + * @ioc: IO MMU structure which owns the pdir we are interested in.
  1.1164 + * @startsg:  list of IOVA/size pairs
  1.1165 + * @nents: number of entries in startsg list
  1.1166 + *
  1.1167 + * Take preprocessed SG list and write corresponding entries
  1.1168 + * in the IO PDIR.
  1.1169 + */
  1.1170 +
  1.1171 +static SBA_INLINE int
  1.1172 +sba_fill_pdir(
  1.1173 +	struct ioc *ioc,
  1.1174 +	struct scatterlist *startsg,
  1.1175 +	int nents)
  1.1176 +{
  1.1177 +	struct scatterlist *dma_sg = startsg;	/* pointer to current DMA */
  1.1178 +	int n_mappings = 0;
  1.1179 +	u64 *pdirp = NULL;
  1.1180 +	unsigned long dma_offset = 0;
  1.1181 +
  1.1182 +	dma_sg--;
  1.1183 +	while (nents-- > 0) {
  1.1184 +		int     cnt = startsg->dma_length;
  1.1185 +		startsg->dma_length = 0;
  1.1186 +
  1.1187 +#ifdef DEBUG_LARGE_SG_ENTRIES
  1.1188 +		if (dump_run_sg)
  1.1189 +			printk(" %2d : %08lx/%05x %p\n",
  1.1190 +				nents, startsg->dma_address, cnt,
  1.1191 +				sba_sg_address(startsg));
  1.1192 +#else
  1.1193 +		DBG_RUN_SG(" %d : %08lx/%05x %p\n",
  1.1194 +				nents, startsg->dma_address, cnt,
  1.1195 +				sba_sg_address(startsg));
  1.1196 +#endif
  1.1197 +		/*
  1.1198 +		** Look for the start of a new DMA stream
  1.1199 +		*/
  1.1200 +		if (startsg->dma_address & PIDE_FLAG) {
  1.1201 +			u32 pide = startsg->dma_address & ~PIDE_FLAG;
  1.1202 +			dma_offset = (unsigned long) pide & ~iovp_mask;
  1.1203 +			startsg->dma_address = 0;
  1.1204 +			dma_sg++;
  1.1205 +			dma_sg->dma_address = pide | ioc->ibase;
  1.1206 +			pdirp = &(ioc->pdir_base[pide >> iovp_shift]);
  1.1207 +			n_mappings++;
  1.1208 +		}
  1.1209 +
  1.1210 +		/*
  1.1211 +		** Look for a VCONTIG chunk
  1.1212 +		*/
  1.1213 +		if (cnt) {
  1.1214 +			unsigned long vaddr = (unsigned long) sba_sg_address(startsg);
  1.1215 +			ASSERT(pdirp);
  1.1216 +
  1.1217 +			/* Since multiple Vcontig blocks could make up
  1.1218 +			** one DMA stream, *add* cnt to dma_len.
  1.1219 +			*/
  1.1220 +			dma_sg->dma_length += cnt;
  1.1221 +			cnt += dma_offset;
  1.1222 +			dma_offset=0;	/* only want offset on first chunk */
  1.1223 +			cnt = ROUNDUP(cnt, iovp_size);
  1.1224 +			do {
  1.1225 +				sba_io_pdir_entry(pdirp, vaddr);
  1.1226 +				vaddr += iovp_size;
  1.1227 +				cnt -= iovp_size;
  1.1228 +				pdirp++;
  1.1229 +			} while (cnt > 0);
  1.1230 +		}
  1.1231 +		startsg++;
  1.1232 +	}
  1.1233 +	/* force pdir update */
  1.1234 +	wmb();
  1.1235 +
  1.1236 +#ifdef DEBUG_LARGE_SG_ENTRIES
  1.1237 +	dump_run_sg = 0;
  1.1238 +#endif
  1.1239 +	return(n_mappings);
  1.1240 +}
  1.1241 +
  1.1242 +
  1.1243 +/*
  1.1244 +** Two address ranges are DMA contiguous *iff* "end of prev" and
  1.1245 +** "start of next" are both on an IOV page boundary.
  1.1246 +**
  1.1247 +** (shift left is a quick trick to mask off upper bits)
  1.1248 +*/
  1.1249 +#define DMA_CONTIG(__X, __Y) \
  1.1250 +	(((((unsigned long) __X) | ((unsigned long) __Y)) << (BITS_PER_LONG - iovp_shift)) == 0UL)
  1.1251 +
  1.1252 +
  1.1253 +/**
  1.1254 + * sba_coalesce_chunks - preprocess the SG list
  1.1255 + * @ioc: IO MMU structure which owns the pdir we are interested in.
  1.1256 + * @startsg:  list of IOVA/size pairs
  1.1257 + * @nents: number of entries in startsg list
  1.1258 + *
  1.1259 + * First pass is to walk the SG list and determine where the breaks are
  1.1260 + * in the DMA stream. Allocates PDIR entries but does not fill them.
  1.1261 + * Returns the number of DMA chunks.
  1.1262 + *
  1.1263 + * Doing the fill separate from the coalescing/allocation keeps the
  1.1264 + * code simpler. Future enhancement could make one pass through
  1.1265 + * the sglist do both.
  1.1266 + */
  1.1267 +static SBA_INLINE int
  1.1268 +sba_coalesce_chunks( struct ioc *ioc,
  1.1269 +	struct scatterlist *startsg,
  1.1270 +	int nents)
  1.1271 +{
  1.1272 +	struct scatterlist *vcontig_sg;    /* VCONTIG chunk head */
  1.1273 +	unsigned long vcontig_len;         /* len of VCONTIG chunk */
  1.1274 +	unsigned long vcontig_end;
  1.1275 +	struct scatterlist *dma_sg;        /* next DMA stream head */
  1.1276 +	unsigned long dma_offset, dma_len; /* start/len of DMA stream */
  1.1277 +	int n_mappings = 0;
  1.1278 +
  1.1279 +	while (nents > 0) {
  1.1280 +		unsigned long vaddr = (unsigned long) sba_sg_address(startsg);
  1.1281 +
  1.1282 +		/*
  1.1283 +		** Prepare for first/next DMA stream
  1.1284 +		*/
  1.1285 +		dma_sg = vcontig_sg = startsg;
  1.1286 +		dma_len = vcontig_len = vcontig_end = startsg->length;
  1.1287 +		vcontig_end +=  vaddr;
  1.1288 +		dma_offset = vaddr & ~iovp_mask;
  1.1289 +
  1.1290 +		/* PARANOID: clear entries */
  1.1291 +		startsg->dma_address = startsg->dma_length = 0;
  1.1292 +
  1.1293 +		/*
  1.1294 +		** This loop terminates one iteration "early" since
  1.1295 +		** it's always looking one "ahead".
  1.1296 +		*/
  1.1297 +		while (--nents > 0) {
  1.1298 +			unsigned long vaddr;	/* tmp */
  1.1299 +
  1.1300 +			startsg++;
  1.1301 +
  1.1302 +			/* PARANOID */
  1.1303 +			startsg->dma_address = startsg->dma_length = 0;
  1.1304 +
  1.1305 +			/* catch brokenness in SCSI layer */
  1.1306 +			ASSERT(startsg->length <= DMA_CHUNK_SIZE);
  1.1307 +
  1.1308 +			/*
  1.1309 +			** First make sure current dma stream won't
  1.1310 +			** exceed DMA_CHUNK_SIZE if we coalesce the
  1.1311 +			** next entry.
  1.1312 +			*/
  1.1313 +			if (((dma_len + dma_offset + startsg->length + ~iovp_mask) & iovp_mask)
  1.1314 +			    > DMA_CHUNK_SIZE)
  1.1315 +				break;
  1.1316 +
  1.1317 +			/*
  1.1318 +			** Then look for virtually contiguous blocks.
  1.1319 +			**
  1.1320 +			** append the next transaction?
  1.1321 +			*/
  1.1322 +			vaddr = (unsigned long) sba_sg_address(startsg);
  1.1323 +			if  (vcontig_end == vaddr)
  1.1324 +			{
  1.1325 +				vcontig_len += startsg->length;
  1.1326 +				vcontig_end += startsg->length;
  1.1327 +				dma_len     += startsg->length;
  1.1328 +				continue;
  1.1329 +			}
  1.1330 +
  1.1331 +#ifdef DEBUG_LARGE_SG_ENTRIES
  1.1332 +			dump_run_sg = (vcontig_len > iovp_size);
  1.1333 +#endif
  1.1334 +
  1.1335 +			/*
  1.1336 +			** Not virtually contigous.
  1.1337 +			** Terminate prev chunk.
  1.1338 +			** Start a new chunk.
  1.1339 +			**
  1.1340 +			** Once we start a new VCONTIG chunk, dma_offset
  1.1341 +			** can't change. And we need the offset from the first
  1.1342 +			** chunk - not the last one. Ergo Successive chunks
  1.1343 +			** must start on page boundaries and dove tail
  1.1344 +			** with it's predecessor.
  1.1345 +			*/
  1.1346 +			vcontig_sg->dma_length = vcontig_len;
  1.1347 +
  1.1348 +			vcontig_sg = startsg;
  1.1349 +			vcontig_len = startsg->length;
  1.1350 +
  1.1351 +			/*
  1.1352 +			** 3) do the entries end/start on page boundaries?
  1.1353 +			**    Don't update vcontig_end until we've checked.
  1.1354 +			*/
  1.1355 +			if (DMA_CONTIG(vcontig_end, vaddr))
  1.1356 +			{
  1.1357 +				vcontig_end = vcontig_len + vaddr;
  1.1358 +				dma_len += vcontig_len;
  1.1359 +				continue;
  1.1360 +			} else {
  1.1361 +				break;
  1.1362 +			}
  1.1363 +		}
  1.1364 +
  1.1365 +		/*
  1.1366 +		** End of DMA Stream
  1.1367 +		** Terminate last VCONTIG block.
  1.1368 +		** Allocate space for DMA stream.
  1.1369 +		*/
  1.1370 +		vcontig_sg->dma_length = vcontig_len;
  1.1371 +		dma_len = (dma_len + dma_offset + ~iovp_mask) & iovp_mask;
  1.1372 +		ASSERT(dma_len <= DMA_CHUNK_SIZE);
  1.1373 +		dma_sg->dma_address = (dma_addr_t) (PIDE_FLAG
  1.1374 +			| (sba_alloc_range(ioc, dma_len) << iovp_shift)
  1.1375 +			| dma_offset);
  1.1376 +		n_mappings++;
  1.1377 +	}
  1.1378 +
  1.1379 +	return n_mappings;
  1.1380 +}
  1.1381 +
  1.1382 +
  1.1383 +/**
  1.1384 + * sba_map_sg - map Scatter/Gather list
  1.1385 + * @dev: instance of PCI owned by the driver that's asking.
  1.1386 + * @sglist:  array of buffer/length pairs
  1.1387 + * @nents:  number of entries in list
  1.1388 + * @dir:  R/W or both.
  1.1389 + *
  1.1390 + * See Documentation/DMA-mapping.txt
  1.1391 + */
  1.1392 +int sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents, int dir)
  1.1393 +{
  1.1394 +	struct ioc *ioc;
  1.1395 +	int coalesced, filled = 0;
  1.1396 +#ifdef ASSERT_PDIR_SANITY
  1.1397 +	unsigned long flags;
  1.1398 +#endif
  1.1399 +#ifdef ALLOW_IOV_BYPASS_SG
  1.1400 +	struct scatterlist *sg;
  1.1401 +#endif
  1.1402 +
  1.1403 +	DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
  1.1404 +	ioc = GET_IOC(dev);
  1.1405 +	ASSERT(ioc);
  1.1406 +
  1.1407 +#ifdef ALLOW_IOV_BYPASS_SG
  1.1408 +	ASSERT(to_pci_dev(dev)->dma_mask);
  1.1409 +	if (likely((ioc->dma_mask & ~to_pci_dev(dev)->dma_mask) == 0)) {
  1.1410 +		for (sg = sglist ; filled < nents ; filled++, sg++){
  1.1411 +			sg->dma_length = sg->length;
  1.1412 +			sg->dma_address = virt_to_phys(sba_sg_address(sg));
  1.1413 +		}
  1.1414 +		return filled;
  1.1415 +	}
  1.1416 +#endif
  1.1417 +	/* Fast path single entry scatterlists. */
  1.1418 +	if (nents == 1) {
  1.1419 +		sglist->dma_length = sglist->length;
  1.1420 +		sglist->dma_address = sba_map_single(dev, sba_sg_address(sglist), sglist->length, dir);
  1.1421 +		return 1;
  1.1422 +	}
  1.1423 +
  1.1424 +#ifdef ASSERT_PDIR_SANITY
  1.1425 +	spin_lock_irqsave(&ioc->res_lock, flags);
  1.1426 +	if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
  1.1427 +	{
  1.1428 +		sba_dump_sg(ioc, sglist, nents);
  1.1429 +		panic("Check before sba_map_sg()");
  1.1430 +	}
  1.1431 +	spin_unlock_irqrestore(&ioc->res_lock, flags);
  1.1432 +#endif
  1.1433 +
  1.1434 +	prefetch(ioc->res_hint);
  1.1435 +
  1.1436 +	/*
  1.1437 +	** First coalesce the chunks and allocate I/O pdir space
  1.1438 +	**
  1.1439 +	** If this is one DMA stream, we can properly map using the
  1.1440 +	** correct virtual address associated with each DMA page.
  1.1441 +	** w/o this association, we wouldn't have coherent DMA!
  1.1442 +	** Access to the virtual address is what forces a two pass algorithm.
  1.1443 +	*/
  1.1444 +	coalesced = sba_coalesce_chunks(ioc, sglist, nents);
  1.1445 +
  1.1446 +	/*
  1.1447 +	** Program the I/O Pdir
  1.1448 +	**
  1.1449 +	** map the virtual addresses to the I/O Pdir
  1.1450 +	** o dma_address will contain the pdir index
  1.1451 +	** o dma_len will contain the number of bytes to map
  1.1452 +	** o address contains the virtual address.
  1.1453 +	*/
  1.1454 +	filled = sba_fill_pdir(ioc, sglist, nents);
  1.1455 +
  1.1456 +#ifdef ASSERT_PDIR_SANITY
  1.1457 +	spin_lock_irqsave(&ioc->res_lock, flags);
  1.1458 +	if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
  1.1459 +	{
  1.1460 +		sba_dump_sg(ioc, sglist, nents);
  1.1461 +		panic("Check after sba_map_sg()\n");
  1.1462 +	}
  1.1463 +	spin_unlock_irqrestore(&ioc->res_lock, flags);
  1.1464 +#endif
  1.1465 +
  1.1466 +	ASSERT(coalesced == filled);
  1.1467 +	DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
  1.1468 +
  1.1469 +	return filled;
  1.1470 +}
  1.1471 +
  1.1472 +
  1.1473 +/**
  1.1474 + * sba_unmap_sg - unmap Scatter/Gather list
  1.1475 + * @dev: instance of PCI owned by the driver that's asking.
  1.1476 + * @sglist:  array of buffer/length pairs
  1.1477 + * @nents:  number of entries in list
  1.1478 + * @dir:  R/W or both.
  1.1479 + *
  1.1480 + * See Documentation/DMA-mapping.txt
  1.1481 + */
  1.1482 +void sba_unmap_sg (struct device *dev, struct scatterlist *sglist, int nents, int dir)
  1.1483 +{
  1.1484 +#ifdef ASSERT_PDIR_SANITY
  1.1485 +	struct ioc *ioc;
  1.1486 +	unsigned long flags;
  1.1487 +#endif
  1.1488 +
  1.1489 +	DBG_RUN_SG("%s() START %d entries,  %p,%x\n",
  1.1490 +		__FUNCTION__, nents, sba_sg_address(sglist), sglist->length);
  1.1491 +
  1.1492 +#ifdef ASSERT_PDIR_SANITY
  1.1493 +	ioc = GET_IOC(dev);
  1.1494 +	ASSERT(ioc);
  1.1495 +
  1.1496 +	spin_lock_irqsave(&ioc->res_lock, flags);
  1.1497 +	sba_check_pdir(ioc,"Check before sba_unmap_sg()");
  1.1498 +	spin_unlock_irqrestore(&ioc->res_lock, flags);
  1.1499 +#endif
  1.1500 +
  1.1501 +	while (nents && sglist->dma_length) {
  1.1502 +
  1.1503 +		sba_unmap_single(dev, sglist->dma_address, sglist->dma_length, dir);
  1.1504 +		sglist++;
  1.1505 +		nents--;
  1.1506 +	}
  1.1507 +
  1.1508 +	DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__,  nents);
  1.1509 +
  1.1510 +#ifdef ASSERT_PDIR_SANITY
  1.1511 +	spin_lock_irqsave(&ioc->res_lock, flags);
  1.1512 +	sba_check_pdir(ioc,"Check after sba_unmap_sg()");
  1.1513 +	spin_unlock_irqrestore(&ioc->res_lock, flags);
  1.1514 +#endif
  1.1515 +
  1.1516 +}
  1.1517 +
  1.1518 +/**************************************************************
  1.1519 +*
  1.1520 +*   Initialization and claim
  1.1521 +*
  1.1522 +***************************************************************/
  1.1523 +
  1.1524 +static void __init
  1.1525 +ioc_iova_init(struct ioc *ioc)
  1.1526 +{
  1.1527 +	int tcnfg;
  1.1528 +	int agp_found = 0;
  1.1529 +	struct pci_dev *device = NULL;
  1.1530 +#ifdef FULL_VALID_PDIR
  1.1531 +	unsigned long index;
  1.1532 +#endif
  1.1533 +
  1.1534 +	/*
  1.1535 +	** Firmware programs the base and size of a "safe IOVA space"
  1.1536 +	** (one that doesn't overlap memory or LMMIO space) in the
  1.1537 +	** IBASE and IMASK registers.
  1.1538 +	*/
  1.1539 +	ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE) & ~0x1UL;
  1.1540 +	ioc->imask = READ_REG(ioc->ioc_hpa + IOC_IMASK) | 0xFFFFFFFF00000000UL;
  1.1541 +
  1.1542 +	ioc->iov_size = ~ioc->imask + 1;
  1.1543 +
  1.1544 +	DBG_INIT("%s() hpa %p IOV base 0x%lx mask 0x%lx (%dMB)\n",
  1.1545 +		__FUNCTION__, ioc->ioc_hpa, ioc->ibase, ioc->imask,
  1.1546 +		ioc->iov_size >> 20);
  1.1547 +
  1.1548 +	switch (iovp_size) {
  1.1549 +		case  4*1024: tcnfg = 0; break;
  1.1550 +		case  8*1024: tcnfg = 1; break;
  1.1551 +		case 16*1024: tcnfg = 2; break;
  1.1552 +		case 64*1024: tcnfg = 3; break;
  1.1553 +		default:
  1.1554 +			panic(PFX "Unsupported IOTLB page size %ldK",
  1.1555 +				iovp_size >> 10);
  1.1556 +			break;
  1.1557 +	}
  1.1558 +	WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
  1.1559 +
  1.1560 +	ioc->pdir_size = (ioc->iov_size / iovp_size) * PDIR_ENTRY_SIZE;
  1.1561 +	ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
  1.1562 +						   get_order(ioc->pdir_size));
  1.1563 +	if (!ioc->pdir_base)
  1.1564 +		panic(PFX "Couldn't allocate I/O Page Table\n");
  1.1565 +
  1.1566 +	memset(ioc->pdir_base, 0, ioc->pdir_size);
  1.1567 +
  1.1568 +	DBG_INIT("%s() IOV page size %ldK pdir %p size %x\n", __FUNCTION__,
  1.1569 +		iovp_size >> 10, ioc->pdir_base, ioc->pdir_size);
  1.1570 +
  1.1571 +	ASSERT(ALIGN((unsigned long) ioc->pdir_base, 4*1024) == (unsigned long) ioc->pdir_base);
  1.1572 +	WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
  1.1573 +
  1.1574 +	/*
  1.1575 +	** If an AGP device is present, only use half of the IOV space
  1.1576 +	** for PCI DMA.  Unfortunately we can't know ahead of time
  1.1577 +	** whether GART support will actually be used, for now we
  1.1578 +	** can just key on an AGP device found in the system.
  1.1579 +	** We program the next pdir index after we stop w/ a key for
  1.1580 +	** the GART code to handshake on.
  1.1581 +	*/
  1.1582 +	for_each_pci_dev(device)	
  1.1583 +		agp_found |= pci_find_capability(device, PCI_CAP_ID_AGP);
  1.1584 +
  1.1585 +	if (agp_found && reserve_sba_gart) {
  1.1586 +		printk(KERN_INFO PFX "reserving %dMb of IOVA space at 0x%lx for agpgart\n",
  1.1587 +		      ioc->iov_size/2 >> 20, ioc->ibase + ioc->iov_size/2);
  1.1588 +		ioc->pdir_size /= 2;
  1.1589 +		((u64 *)ioc->pdir_base)[PDIR_INDEX(ioc->iov_size/2)] = ZX1_SBA_IOMMU_COOKIE;
  1.1590 +	}
  1.1591 +#ifdef FULL_VALID_PDIR
  1.1592 +	/*
  1.1593 +  	** Check to see if the spill page has been allocated, we don't need more than
  1.1594 +	** one across multiple SBAs.
  1.1595 +	*/
  1.1596 +	if (!prefetch_spill_page) {
  1.1597 +		char *spill_poison = "SBAIOMMU POISON";
  1.1598 +		int poison_size = 16;
  1.1599 +		void *poison_addr, *addr;
  1.1600 +
  1.1601 +		addr = (void *)__get_free_pages(GFP_KERNEL, get_order(iovp_size));
  1.1602 +		if (!addr)
  1.1603 +			panic(PFX "Couldn't allocate PDIR spill page\n");
  1.1604 +
  1.1605 +		poison_addr = addr;
  1.1606 +		for ( ; (u64) poison_addr < addr + iovp_size; poison_addr += poison_size)
  1.1607 +			memcpy(poison_addr, spill_poison, poison_size);
  1.1608 +
  1.1609 +		prefetch_spill_page = virt_to_phys(addr);
  1.1610 +
  1.1611 +		DBG_INIT("%s() prefetch spill addr: 0x%lx\n", __FUNCTION__, prefetch_spill_page);
  1.1612 +	}
  1.1613 +	/*
  1.1614 +  	** Set all the PDIR entries valid w/ the spill page as the target
  1.1615 +	*/
  1.1616 +	for (index = 0 ; index < (ioc->pdir_size / PDIR_ENTRY_SIZE) ; index++)
  1.1617 +		((u64 *)ioc->pdir_base)[index] = (0x80000000000000FF | prefetch_spill_page);
  1.1618 +#endif
  1.1619 +
  1.1620 +	/* Clear I/O TLB of any possible entries */
  1.1621 +	WRITE_REG(ioc->ibase | (get_iovp_order(ioc->iov_size) + iovp_shift), ioc->ioc_hpa + IOC_PCOM);
  1.1622 +	READ_REG(ioc->ioc_hpa + IOC_PCOM);
  1.1623 +
  1.1624 +	/* Enable IOVA translation */
  1.1625 +	WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
  1.1626 +	READ_REG(ioc->ioc_hpa + IOC_IBASE);
  1.1627 +}
  1.1628 +
  1.1629 +static void __init
  1.1630 +ioc_resource_init(struct ioc *ioc)
  1.1631 +{
  1.1632 +	spin_lock_init(&ioc->res_lock);
  1.1633 +#if DELAYED_RESOURCE_CNT > 0
  1.1634 +	spin_lock_init(&ioc->saved_lock);
  1.1635 +#endif
  1.1636 +
  1.1637 +	/* resource map size dictated by pdir_size */
  1.1638 +	ioc->res_size = ioc->pdir_size / PDIR_ENTRY_SIZE; /* entries */
  1.1639 +	ioc->res_size >>= 3;  /* convert bit count to byte count */
  1.1640 +	DBG_INIT("%s() res_size 0x%x\n", __FUNCTION__, ioc->res_size);
  1.1641 +
  1.1642 +	ioc->res_map = (char *) __get_free_pages(GFP_KERNEL,
  1.1643 +						 get_order(ioc->res_size));
  1.1644 +	if (!ioc->res_map)
  1.1645 +		panic(PFX "Couldn't allocate resource map\n");
  1.1646 +
  1.1647 +	memset(ioc->res_map, 0, ioc->res_size);
  1.1648 +	/* next available IOVP - circular search */
  1.1649 +	ioc->res_hint = (unsigned long *) ioc->res_map;
  1.1650 +
  1.1651 +#ifdef ASSERT_PDIR_SANITY
  1.1652 +	/* Mark first bit busy - ie no IOVA 0 */
  1.1653 +	ioc->res_map[0] = 0x1;
  1.1654 +	ioc->pdir_base[0] = 0x8000000000000000ULL | ZX1_SBA_IOMMU_COOKIE;
  1.1655 +#endif
  1.1656 +#ifdef FULL_VALID_PDIR
  1.1657 +	/* Mark the last resource used so we don't prefetch beyond IOVA space */
  1.1658 +	ioc->res_map[ioc->res_size - 1] |= 0x80UL; /* res_map is chars */
  1.1659 +	ioc->pdir_base[(ioc->pdir_size / PDIR_ENTRY_SIZE) - 1] = (0x80000000000000FF
  1.1660 +							      | prefetch_spill_page);
  1.1661 +#endif
  1.1662 +
  1.1663 +	DBG_INIT("%s() res_map %x %p\n", __FUNCTION__,
  1.1664 +		 ioc->res_size, (void *) ioc->res_map);
  1.1665 +}
  1.1666 +
  1.1667 +static void __init
  1.1668 +ioc_sac_init(struct ioc *ioc)
  1.1669 +{
  1.1670 +	struct pci_dev *sac = NULL;
  1.1671 +	struct pci_controller *controller = NULL;
  1.1672 +
  1.1673 +	/*
  1.1674 +	 * pci_alloc_coherent() must return a DMA address which is
  1.1675 +	 * SAC (single address cycle) addressable, so allocate a
  1.1676 +	 * pseudo-device to enforce that.
  1.1677 +	 */
  1.1678 +	sac = kmalloc(sizeof(*sac), GFP_KERNEL);
  1.1679 +	if (!sac)
  1.1680 +		panic(PFX "Couldn't allocate struct pci_dev");
  1.1681 +	memset(sac, 0, sizeof(*sac));
  1.1682 +
  1.1683 +	controller = kmalloc(sizeof(*controller), GFP_KERNEL);
  1.1684 +	if (!controller)
  1.1685 +		panic(PFX "Couldn't allocate struct pci_controller");
  1.1686 +	memset(controller, 0, sizeof(*controller));
  1.1687 +
  1.1688 +	controller->iommu = ioc;
  1.1689 +	sac->sysdata = controller;
  1.1690 +	sac->dma_mask = 0xFFFFFFFFUL;
  1.1691 +#ifdef CONFIG_PCI
  1.1692 +	sac->dev.bus = &pci_bus_type;
  1.1693 +#endif
  1.1694 +	ioc->sac_only_dev = sac;
  1.1695 +}
  1.1696 +
  1.1697 +static void __init
  1.1698 +ioc_zx1_init(struct ioc *ioc)
  1.1699 +{
  1.1700 +	unsigned long rope_config;
  1.1701 +	unsigned int i;
  1.1702 +
  1.1703 +	if (ioc->rev < 0x20)
  1.1704 +		panic(PFX "IOC 2.0 or later required for IOMMU support\n");
  1.1705 +
  1.1706 +	/* 38 bit memory controller + extra bit for range displaced by MMIO */
  1.1707 +	ioc->dma_mask = (0x1UL << 39) - 1;
  1.1708 +
  1.1709 +	/*
  1.1710 +	** Clear ROPE(N)_CONFIG AO bit.
  1.1711 +	** Disables "NT Ordering" (~= !"Relaxed Ordering")
  1.1712 +	** Overrides bit 1 in DMA Hint Sets.
  1.1713 +	** Improves netperf UDP_STREAM by ~10% for tg3 on bcm5701.
  1.1714 +	*/
  1.1715 +	for (i=0; i<(8*8); i+=8) {
  1.1716 +		rope_config = READ_REG(ioc->ioc_hpa + IOC_ROPE0_CFG + i);
  1.1717 +		rope_config &= ~IOC_ROPE_AO;
  1.1718 +		WRITE_REG(rope_config, ioc->ioc_hpa + IOC_ROPE0_CFG + i);
  1.1719 +	}
  1.1720 +}
  1.1721 +
  1.1722 +typedef void (initfunc)(struct ioc *);
  1.1723 +
  1.1724 +struct ioc_iommu {
  1.1725 +	u32 func_id;
  1.1726 +	char *name;
  1.1727 +	initfunc *init;
  1.1728 +};
  1.1729 +
  1.1730 +static struct ioc_iommu ioc_iommu_info[] __initdata = {
  1.1731 +	{ ZX1_IOC_ID, "zx1", ioc_zx1_init },
  1.1732 +	{ ZX2_IOC_ID, "zx2", NULL },
  1.1733 +	{ SX1000_IOC_ID, "sx1000", NULL },
  1.1734 +	{ SX2000_IOC_ID, "sx2000", NULL },
  1.1735 +};
  1.1736 +
  1.1737 +static struct ioc * __init
  1.1738 +ioc_init(u64 hpa, void *handle)
  1.1739 +{
  1.1740 +	struct ioc *ioc;
  1.1741 +	struct ioc_iommu *info;
  1.1742 +
  1.1743 +	ioc = kmalloc(sizeof(*ioc), GFP_KERNEL);
  1.1744 +	if (!ioc)
  1.1745 +		return NULL;
  1.1746 +
  1.1747 +	memset(ioc, 0, sizeof(*ioc));
  1.1748 +
  1.1749 +	ioc->next = ioc_list;
  1.1750 +	ioc_list = ioc;
  1.1751 +
  1.1752 +	ioc->handle = handle;
  1.1753 +	ioc->ioc_hpa = ioremap(hpa, 0x1000);
  1.1754 +
  1.1755 +	ioc->func_id = READ_REG(ioc->ioc_hpa + IOC_FUNC_ID);
  1.1756 +	ioc->rev = READ_REG(ioc->ioc_hpa + IOC_FCLASS) & 0xFFUL;
  1.1757 +	ioc->dma_mask = 0xFFFFFFFFFFFFFFFFUL;	/* conservative */
  1.1758 +
  1.1759 +	for (info = ioc_iommu_info; info < ioc_iommu_info + ARRAY_SIZE(ioc_iommu_info); info++) {
  1.1760 +		if (ioc->func_id == info->func_id) {
  1.1761 +			ioc->name = info->name;
  1.1762 +			if (info->init)
  1.1763 +				(info->init)(ioc);
  1.1764 +		}
  1.1765 +	}
  1.1766 +
  1.1767 +	iovp_size = (1 << iovp_shift);
  1.1768 +	iovp_mask = ~(iovp_size - 1);
  1.1769 +
  1.1770 +	DBG_INIT("%s: PAGE_SIZE %ldK, iovp_size %ldK\n", __FUNCTION__,
  1.1771 +		PAGE_SIZE >> 10, iovp_size >> 10);
  1.1772 +
  1.1773 +	if (!ioc->name) {
  1.1774 +		ioc->name = kmalloc(24, GFP_KERNEL);
  1.1775 +		if (ioc->name)
  1.1776 +			sprintf((char *) ioc->name, "Unknown (%04x:%04x)",
  1.1777 +				ioc->func_id & 0xFFFF, (ioc->func_id >> 16) & 0xFFFF);
  1.1778 +		else
  1.1779 +			ioc->name = "Unknown";
  1.1780 +	}
  1.1781 +
  1.1782 +	ioc_iova_init(ioc);
  1.1783 +	ioc_resource_init(ioc);
  1.1784 +	ioc_sac_init(ioc);
  1.1785 +
  1.1786 +	if ((long) ~iovp_mask > (long) ia64_max_iommu_merge_mask)
  1.1787 +		ia64_max_iommu_merge_mask = ~iovp_mask;
  1.1788 +
  1.1789 +	printk(KERN_INFO PFX
  1.1790 +		"%s %d.%d HPA 0x%lx IOVA space %dMb at 0x%lx\n",
  1.1791 +		ioc->name, (ioc->rev >> 4) & 0xF, ioc->rev & 0xF,
  1.1792 +		hpa, ioc->iov_size >> 20, ioc->ibase);
  1.1793 +
  1.1794 +	return ioc;
  1.1795 +}
  1.1796 +
  1.1797 +
  1.1798 +
  1.1799 +/**************************************************************************
  1.1800 +**
  1.1801 +**   SBA initialization code (HW and SW)
  1.1802 +**
  1.1803 +**   o identify SBA chip itself
  1.1804 +**   o FIXME: initialize DMA hints for reasonable defaults
  1.1805 +**
  1.1806 +**************************************************************************/
  1.1807 +
  1.1808 +#ifdef CONFIG_PROC_FS
  1.1809 +static void *
  1.1810 +ioc_start(struct seq_file *s, loff_t *pos)
  1.1811 +{
  1.1812 +	struct ioc *ioc;
  1.1813 +	loff_t n = *pos;
  1.1814 +
  1.1815 +	for (ioc = ioc_list; ioc; ioc = ioc->next)
  1.1816 +		if (!n--)
  1.1817 +			return ioc;
  1.1818 +
  1.1819 +	return NULL;
  1.1820 +}
  1.1821 +
  1.1822 +static void *
  1.1823 +ioc_next(struct seq_file *s, void *v, loff_t *pos)
  1.1824 +{
  1.1825 +	struct ioc *ioc = v;
  1.1826 +
  1.1827 +	++*pos;
  1.1828 +	return ioc->next;
  1.1829 +}
  1.1830 +
  1.1831 +static void
  1.1832 +ioc_stop(struct seq_file *s, void *v)
  1.1833 +{
  1.1834 +}
  1.1835 +
  1.1836 +static int
  1.1837 +ioc_show(struct seq_file *s, void *v)
  1.1838 +{
  1.1839 +	struct ioc *ioc = v;
  1.1840 +	unsigned long *res_ptr = (unsigned long *)ioc->res_map;
  1.1841 +	int i, used = 0;
  1.1842 +
  1.1843 +	seq_printf(s, "Hewlett Packard %s IOC rev %d.%d\n",
  1.1844 +		ioc->name, ((ioc->rev >> 4) & 0xF), (ioc->rev & 0xF));
  1.1845 +#ifdef CONFIG_NUMA
  1.1846 +	if (ioc->node != MAX_NUMNODES)
  1.1847 +		seq_printf(s, "NUMA node       : %d\n", ioc->node);
  1.1848 +#endif
  1.1849 +	seq_printf(s, "IOVA size       : %ld MB\n", ((ioc->pdir_size >> 3) * iovp_size)/(1024*1024));
  1.1850 +	seq_printf(s, "IOVA page size  : %ld kb\n", iovp_size/1024);
  1.1851 +
  1.1852 +	for (i = 0; i < (ioc->res_size / sizeof(unsigned long)); ++i, ++res_ptr)
  1.1853 +		used += hweight64(*res_ptr);
  1.1854 +
  1.1855 +	seq_printf(s, "PDIR size       : %d entries\n", ioc->pdir_size >> 3);
  1.1856 +	seq_printf(s, "PDIR used       : %d entries\n", used);
  1.1857 +
  1.1858 +#ifdef PDIR_SEARCH_TIMING
  1.1859 +	{
  1.1860 +		unsigned long i = 0, avg = 0, min, max;
  1.1861 +		min = max = ioc->avg_search[0];
  1.1862 +		for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
  1.1863 +			avg += ioc->avg_search[i];
  1.1864 +			if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
  1.1865 +			if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
  1.1866 +		}
  1.1867 +		avg /= SBA_SEARCH_SAMPLE;
  1.1868 +		seq_printf(s, "Bitmap search   : %ld/%ld/%ld (min/avg/max CPU Cycles/IOVA page)\n",
  1.1869 +		           min, avg, max);
  1.1870 +	}
  1.1871 +#endif
  1.1872 +#ifndef ALLOW_IOV_BYPASS
  1.1873 +	 seq_printf(s, "IOVA bypass disabled\n");
  1.1874 +#endif
  1.1875 +	return 0;
  1.1876 +}
  1.1877 +
  1.1878 +static struct seq_operations ioc_seq_ops = {
  1.1879 +	.start = ioc_start,
  1.1880 +	.next  = ioc_next,
  1.1881 +	.stop  = ioc_stop,
  1.1882 +	.show  = ioc_show
  1.1883 +};
  1.1884 +
  1.1885 +static int
  1.1886 +ioc_open(struct inode *inode, struct file *file)
  1.1887 +{
  1.1888 +	return seq_open(file, &ioc_seq_ops);
  1.1889 +}
  1.1890 +
  1.1891 +static struct file_operations ioc_fops = {
  1.1892 +	.open    = ioc_open,
  1.1893 +	.read    = seq_read,
  1.1894 +	.llseek  = seq_lseek,
  1.1895 +	.release = seq_release
  1.1896 +};
  1.1897 +
  1.1898 +static void __init
  1.1899 +ioc_proc_init(void)
  1.1900 +{
  1.1901 +	struct proc_dir_entry *dir, *entry;
  1.1902 +
  1.1903 +	dir = proc_mkdir("bus/mckinley", NULL);
  1.1904 +	if (!dir)
  1.1905 +		return;
  1.1906 +
  1.1907 +	entry = create_proc_entry(ioc_list->name, 0, dir);
  1.1908 +	if (entry)
  1.1909 +		entry->proc_fops = &ioc_fops;
  1.1910 +}
  1.1911 +#endif
  1.1912 +
  1.1913 +static void
  1.1914 +sba_connect_bus(struct pci_bus *bus)
  1.1915 +{
  1.1916 +	acpi_handle handle, parent;
  1.1917 +	acpi_status status;
  1.1918 +	struct ioc *ioc;
  1.1919 +
  1.1920 +	if (!PCI_CONTROLLER(bus))
  1.1921 +		panic(PFX "no sysdata on bus %d!\n", bus->number);
  1.1922 +
  1.1923 +	if (PCI_CONTROLLER(bus)->iommu)
  1.1924 +		return;
  1.1925 +
  1.1926 +	handle = PCI_CONTROLLER(bus)->acpi_handle;
  1.1927 +	if (!handle)
  1.1928 +		return;
  1.1929 +
  1.1930 +	/*
  1.1931 +	 * The IOC scope encloses PCI root bridges in the ACPI
  1.1932 +	 * namespace, so work our way out until we find an IOC we
  1.1933 +	 * claimed previously.
  1.1934 +	 */
  1.1935 +	do {
  1.1936 +		for (ioc = ioc_list; ioc; ioc = ioc->next)
  1.1937 +			if (ioc->handle == handle) {
  1.1938 +				PCI_CONTROLLER(bus)->iommu = ioc;
  1.1939 +				return;
  1.1940 +			}
  1.1941 +
  1.1942 +		status = acpi_get_parent(handle, &parent);
  1.1943 +		handle = parent;
  1.1944 +	} while (ACPI_SUCCESS(status));
  1.1945 +
  1.1946 +	printk(KERN_WARNING "No IOC for PCI Bus %04x:%02x in ACPI\n", pci_domain_nr(bus), bus->number);
  1.1947 +}
  1.1948 +
  1.1949 +#ifdef CONFIG_NUMA
  1.1950 +static void __init
  1.1951 +sba_map_ioc_to_node(struct ioc *ioc, acpi_handle handle)
  1.1952 +{
  1.1953 +	unsigned int node;
  1.1954 +	int pxm;
  1.1955 +
  1.1956 +	ioc->node = MAX_NUMNODES;
  1.1957 +
  1.1958 +	pxm = acpi_get_pxm(handle);
  1.1959 +
  1.1960 +	if (pxm < 0)
  1.1961 +		return;
  1.1962 +
  1.1963 +	node = pxm_to_node(pxm);
  1.1964 +
  1.1965 +	if (node >= MAX_NUMNODES || !node_online(node))
  1.1966 +		return;
  1.1967 +
  1.1968 +	ioc->node = node;
  1.1969 +	return;
  1.1970 +}
  1.1971 +#else
  1.1972 +#define sba_map_ioc_to_node(ioc, handle)
  1.1973 +#endif
  1.1974 +
  1.1975 +static int __init
  1.1976 +acpi_sba_ioc_add(struct acpi_device *device)
  1.1977 +{
  1.1978 +	struct ioc *ioc;
  1.1979 +	acpi_status status;
  1.1980 +	u64 hpa, length;
  1.1981 +	struct acpi_buffer buffer;
  1.1982 +	struct acpi_device_info *dev_info;
  1.1983 +
  1.1984 +	status = hp_acpi_csr_space(device->handle, &hpa, &length);
  1.1985 +	if (ACPI_FAILURE(status))
  1.1986 +		return 1;
  1.1987 +
  1.1988 +	buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER;
  1.1989 +	status = acpi_get_object_info(device->handle, &buffer);
  1.1990 +	if (ACPI_FAILURE(status))
  1.1991 +		return 1;
  1.1992 +	dev_info = buffer.pointer;
  1.1993 +
  1.1994 +	/*
  1.1995 +	 * For HWP0001, only SBA appears in ACPI namespace.  It encloses the PCI
  1.1996 +	 * root bridges, and its CSR space includes the IOC function.
  1.1997 +	 */
  1.1998 +	if (strncmp("HWP0001", dev_info->hardware_id.value, 7) == 0) {
  1.1999 +		hpa += ZX1_IOC_OFFSET;
  1.2000 +		/* zx1 based systems default to kernel page size iommu pages */
  1.2001 +		if (!iovp_shift)
  1.2002 +			iovp_shift = min(PAGE_SHIFT, 16);
  1.2003 +	}
  1.2004 +	kfree(dev_info);
  1.2005 +
  1.2006 +	/*
  1.2007 +	 * default anything not caught above or specified on cmdline to 4k
  1.2008 +	 * iommu page size
  1.2009 +	 */
  1.2010 +	if (!iovp_shift)
  1.2011 +		iovp_shift = 12;
  1.2012 +
  1.2013 +	ioc = ioc_init(hpa, device->handle);
  1.2014 +	if (!ioc)
  1.2015 +		return 1;
  1.2016 +
  1.2017 +	/* setup NUMA node association */
  1.2018 +	sba_map_ioc_to_node(ioc, device->handle);
  1.2019 +	return 0;
  1.2020 +}
  1.2021 +
  1.2022 +static struct acpi_driver acpi_sba_ioc_driver = {
  1.2023 +	.name		= "IOC IOMMU Driver",
  1.2024 +	.ids		= "HWP0001,HWP0004",
  1.2025 +	.ops		= {
  1.2026 +		.add	= acpi_sba_ioc_add,
  1.2027 +	},
  1.2028 +};
  1.2029 +
  1.2030 +static int __init
  1.2031 +sba_init(void)
  1.2032 +{
  1.2033 +	if (!ia64_platform_is("hpzx1") && !ia64_platform_is("hpzx1_swiotlb"))
  1.2034 +		return 0;
  1.2035 +
  1.2036 +	acpi_bus_register_driver(&acpi_sba_ioc_driver);
  1.2037 +	if (!ioc_list) {
  1.2038 +#ifdef CONFIG_IA64_GENERIC
  1.2039 +		extern int swiotlb_late_init_with_default_size (size_t size);
  1.2040 +
  1.2041 +		/*
  1.2042 +		 * If we didn't find something sba_iommu can claim, we
  1.2043 +		 * need to setup the swiotlb and switch to the dig machvec.
  1.2044 +		 */
  1.2045 +		if (swiotlb_late_init_with_default_size(64 * (1<<20)) != 0)
  1.2046 +			panic("Unable to find SBA IOMMU or initialize "
  1.2047 +			      "software I/O TLB: Try machvec=dig boot option");
  1.2048 +		machvec_init("dig");
  1.2049 +#else
  1.2050 +		panic("Unable to find SBA IOMMU: Try a generic or DIG kernel");
  1.2051 +#endif
  1.2052 +		return 0;
  1.2053 +	}
  1.2054 +
  1.2055 +#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_HP_ZX1_SWIOTLB)
  1.2056 +	/*
  1.2057 +	 * hpzx1_swiotlb needs to have a fairly small swiotlb bounce
  1.2058 +	 * buffer setup to support devices with smaller DMA masks than
  1.2059 +	 * sba_iommu can handle.
  1.2060 +	 */
  1.2061 +	if (ia64_platform_is("hpzx1_swiotlb")) {
  1.2062 +		extern void hwsw_init(void);
  1.2063 +
  1.2064 +		hwsw_init();
  1.2065 +	}
  1.2066 +#endif
  1.2067 +
  1.2068 +#ifdef CONFIG_PCI
  1.2069 +	{
  1.2070 +		struct pci_bus *b = NULL;
  1.2071 +		while ((b = pci_find_next_bus(b)) != NULL)
  1.2072 +			sba_connect_bus(b);
  1.2073 +	}
  1.2074 +#endif
  1.2075 +
  1.2076 +#ifdef CONFIG_PROC_FS
  1.2077 +	ioc_proc_init();
  1.2078 +#endif
  1.2079 +	return 0;
  1.2080 +}
  1.2081 +
  1.2082 +subsys_initcall(sba_init); /* must be initialized after ACPI etc., but before any drivers... */
  1.2083 +
  1.2084 +static int __init
  1.2085 +nosbagart(char *str)
  1.2086 +{
  1.2087 +	reserve_sba_gart = 0;
  1.2088 +	return 1;
  1.2089 +}
  1.2090 +
  1.2091 +int
  1.2092 +sba_dma_supported (struct device *dev, u64 mask)
  1.2093 +{
  1.2094 +	/* make sure it's at least 32bit capable */
  1.2095 +	return ((mask & 0xFFFFFFFFUL) == 0xFFFFFFFFUL);
  1.2096 +}
  1.2097 +
  1.2098 +int
  1.2099 +sba_dma_mapping_error (dma_addr_t dma_addr)
  1.2100 +{
  1.2101 +	return 0;
  1.2102 +}
  1.2103 +
  1.2104 +__setup("nosbagart", nosbagart);
  1.2105 +
  1.2106 +static int __init
  1.2107 +sba_page_override(char *str)
  1.2108 +{
  1.2109 +	unsigned long page_size;
  1.2110 +
  1.2111 +	page_size = memparse(str, &str);
  1.2112 +	switch (page_size) {
  1.2113 +		case 4096:
  1.2114 +		case 8192:
  1.2115 +		case 16384:
  1.2116 +		case 65536:
  1.2117 +			iovp_shift = ffs(page_size) - 1;
  1.2118 +			break;
  1.2119 +		default:
  1.2120 +			printk("%s: unknown/unsupported iommu page size %ld\n",
  1.2121 +			       __FUNCTION__, page_size);
  1.2122 +	}
  1.2123 +
  1.2124 +	return 1;
  1.2125 +}
  1.2126 +
  1.2127 +__setup("sbapagesize=",sba_page_override);
  1.2128 +
  1.2129 +EXPORT_SYMBOL(sba_dma_mapping_error);
  1.2130 +EXPORT_SYMBOL(sba_map_single);
  1.2131 +EXPORT_SYMBOL(sba_unmap_single);
  1.2132 +EXPORT_SYMBOL(sba_map_sg);
  1.2133 +EXPORT_SYMBOL(sba_unmap_sg);
  1.2134 +EXPORT_SYMBOL(sba_dma_supported);
  1.2135 +EXPORT_SYMBOL(sba_alloc_coherent);
  1.2136 +EXPORT_SYMBOL(sba_free_coherent);
     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/linux-2.6-xen-sparse/arch/ia64/xen/swiotlb.c	Sun May 06 20:29:45 2007 -0600
     2.3 @@ -0,0 +1,803 @@
     2.4 +/*
     2.5 + * Dynamic DMA mapping support.
     2.6 + *
     2.7 + * This implementation is for IA-64 and EM64T platforms that do not support
     2.8 + * I/O TLBs (aka DMA address translation hardware).
     2.9 + * Copyright (C) 2000 Asit Mallick <Asit.K.Mallick@intel.com>
    2.10 + * Copyright (C) 2000 Goutham Rao <goutham.rao@intel.com>
    2.11 + * Copyright (C) 2000, 2003 Hewlett-Packard Co
    2.12 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    2.13 + *
    2.14 + * 03/05/07 davidm	Switch from PCI-DMA to generic device DMA API.
    2.15 + * 00/12/13 davidm	Rename to swiotlb.c and add mark_clean() to avoid
    2.16 + *			unnecessary i-cache flushing.
    2.17 + * 04/07/.. ak		Better overflow handling. Assorted fixes.
    2.18 + * 05/09/10 linville	Add support for syncing ranges, support syncing for
    2.19 + *			DMA_BIDIRECTIONAL mappings, miscellaneous cleanup.
    2.20 + */
    2.21 +
    2.22 +#include <linux/cache.h>
    2.23 +#include <linux/dma-mapping.h>
    2.24 +#include <linux/mm.h>
    2.25 +#include <linux/module.h>
    2.26 +#include <linux/spinlock.h>
    2.27 +#include <linux/string.h>
    2.28 +#include <linux/types.h>
    2.29 +#include <linux/ctype.h>
    2.30 +
    2.31 +#include <asm/io.h>
    2.32 +#include <asm/dma.h>
    2.33 +#include <asm/scatterlist.h>
    2.34 +
    2.35 +#include <linux/init.h>
    2.36 +#include <linux/bootmem.h>
    2.37 +
    2.38 +#define OFFSET(val,align) ((unsigned long)	\
    2.39 +	                   ( (val) & ( (align) - 1)))
    2.40 +
    2.41 +#define SG_ENT_VIRT_ADDRESS(sg)	(page_address((sg)->page) + (sg)->offset)
    2.42 +#define SG_ENT_PHYS_ADDRESS(SG)	virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))
    2.43 +
    2.44 +/*
    2.45 + * Maximum allowable number of contiguous slabs to map,
    2.46 + * must be a power of 2.  What is the appropriate value ?
    2.47 + * The complexity of {map,unmap}_single is linearly dependent on this value.
    2.48 + */
    2.49 +#define IO_TLB_SEGSIZE	128
    2.50 +
    2.51 +/*
    2.52 + * log of the size of each IO TLB slab.  The number of slabs is command line
    2.53 + * controllable.
    2.54 + */
    2.55 +#define IO_TLB_SHIFT 11
    2.56 +
    2.57 +#define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT))
    2.58 +
    2.59 +/*
    2.60 + * Minimum IO TLB size to bother booting with.  Systems with mainly
    2.61 + * 64bit capable cards will only lightly use the swiotlb.  If we can't
    2.62 + * allocate a contiguous 1MB, we're probably in trouble anyway.
    2.63 + */
    2.64 +#define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT)
    2.65 +
    2.66 +/*
    2.67 + * Enumeration for sync targets
    2.68 + */
    2.69 +enum dma_sync_target {
    2.70 +	SYNC_FOR_CPU = 0,
    2.71 +	SYNC_FOR_DEVICE = 1,
    2.72 +};
    2.73 +
    2.74 +int swiotlb_force;
    2.75 +
    2.76 +/*
    2.77 + * Used to do a quick range check in swiotlb_unmap_single and
    2.78 + * swiotlb_sync_single_*, to see if the memory was in fact allocated by this
    2.79 + * API.
    2.80 + */
    2.81 +static char *io_tlb_start, *io_tlb_end;
    2.82 +
    2.83 +/*
    2.84 + * The number of IO TLB blocks (in groups of 64) betweeen io_tlb_start and
    2.85 + * io_tlb_end.  This is command line adjustable via setup_io_tlb_npages.
    2.86 + */
    2.87 +static unsigned long io_tlb_nslabs;
    2.88 +
    2.89 +/*
    2.90 + * When the IOMMU overflows we return a fallback buffer. This sets the size.
    2.91 + */
    2.92 +static unsigned long io_tlb_overflow = 32*1024;
    2.93 +
    2.94 +void *io_tlb_overflow_buffer;
    2.95 +
    2.96 +/*
    2.97 + * This is a free list describing the number of free entries available from
    2.98 + * each index
    2.99 + */
   2.100 +static unsigned int *io_tlb_list;
   2.101 +static unsigned int io_tlb_index;
   2.102 +
   2.103 +/*
   2.104 + * We need to save away the original address corresponding to a mapped entry
   2.105 + * for the sync operations.
   2.106 + */
   2.107 +static unsigned char **io_tlb_orig_addr;
   2.108 +
   2.109 +/*
   2.110 + * Protect the above data structures in the map and unmap calls
   2.111 + */
   2.112 +static DEFINE_SPINLOCK(io_tlb_lock);
   2.113 +
   2.114 +static int __init
   2.115 +setup_io_tlb_npages(char *str)
   2.116 +{
   2.117 +	if (isdigit(*str)) {
   2.118 +		io_tlb_nslabs = simple_strtoul(str, &str, 0);
   2.119 +		/* avoid tail segment of size < IO_TLB_SEGSIZE */
   2.120 +		io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE);
   2.121 +	}
   2.122 +	if (*str == ',')
   2.123 +		++str;
   2.124 +	if (!strcmp(str, "force"))
   2.125 +		swiotlb_force = 1;
   2.126 +	return 1;
   2.127 +}
   2.128 +__setup("swiotlb=", setup_io_tlb_npages);
   2.129 +/* make io_tlb_overflow tunable too? */
   2.130 +
   2.131 +/*
   2.132 + * Statically reserve bounce buffer space and initialize bounce buffer data
   2.133 + * structures for the software IO TLB used to implement the DMA API.
   2.134 + */
   2.135 +void
   2.136 +swiotlb_init_with_default_size (size_t default_size)
   2.137 +{
   2.138 +	unsigned long i;
   2.139 +
   2.140 +	if (!io_tlb_nslabs) {
   2.141 +		io_tlb_nslabs = (default_size >> IO_TLB_SHIFT);
   2.142 +		io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE);
   2.143 +	}
   2.144 +
   2.145 +	/*
   2.146 +	 * Get IO TLB memory from the low pages
   2.147 +	 */
   2.148 +	io_tlb_start = alloc_bootmem_low_pages(io_tlb_nslabs * (1 << IO_TLB_SHIFT));
   2.149 +	if (!io_tlb_start)
   2.150 +		panic("Cannot allocate SWIOTLB buffer");
   2.151 +	io_tlb_end = io_tlb_start + io_tlb_nslabs * (1 << IO_TLB_SHIFT);
   2.152 +
   2.153 +	/*
   2.154 +	 * Allocate and initialize the free list array.  This array is used
   2.155 +	 * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE
   2.156 +	 * between io_tlb_start and io_tlb_end.
   2.157 +	 */
   2.158 +	io_tlb_list = alloc_bootmem(io_tlb_nslabs * sizeof(int));
   2.159 +	for (i = 0; i < io_tlb_nslabs; i++)
   2.160 + 		io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE);
   2.161 +	io_tlb_index = 0;
   2.162 +	io_tlb_orig_addr = alloc_bootmem(io_tlb_nslabs * sizeof(char *));
   2.163 +
   2.164 +	/*
   2.165 +	 * Get the overflow emergency buffer
   2.166 +	 */
   2.167 +	io_tlb_overflow_buffer = alloc_bootmem_low(io_tlb_overflow);
   2.168 +	printk(KERN_INFO "Placing software IO TLB between 0x%lx - 0x%lx\n",
   2.169 +	       virt_to_phys(io_tlb_start), virt_to_phys(io_tlb_end));
   2.170 +}
   2.171 +
   2.172 +void
   2.173 +swiotlb_init (void)
   2.174 +{
   2.175 +	swiotlb_init_with_default_size(64 * (1<<20));	/* default to 64MB */
   2.176 +}
   2.177 +
   2.178 +/*
   2.179 + * Systems with larger DMA zones (those that don't support ISA) can
   2.180 + * initialize the swiotlb later using the slab allocator if needed.
   2.181 + * This should be just like above, but with some error catching.
   2.182 + */
   2.183 +int
   2.184 +swiotlb_late_init_with_default_size (size_t default_size)
   2.185 +{
   2.186 +	unsigned long i, req_nslabs = io_tlb_nslabs;
   2.187 +	unsigned int order;
   2.188 +
   2.189 +	if (!io_tlb_nslabs) {
   2.190 +		io_tlb_nslabs = (default_size >> IO_TLB_SHIFT);
   2.191 +		io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE);
   2.192 +	}
   2.193 +
   2.194 +	/*
   2.195 +	 * Get IO TLB memory from the low pages
   2.196 +	 */
   2.197 +	order = get_order(io_tlb_nslabs * (1 << IO_TLB_SHIFT));
   2.198 +	io_tlb_nslabs = SLABS_PER_PAGE << order;
   2.199 +
   2.200 +	while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) {
   2.201 +		io_tlb_start = (char *)__get_free_pages(GFP_DMA | __GFP_NOWARN,
   2.202 +		                                        order);
   2.203 +		if (io_tlb_start)
   2.204 +			break;
   2.205 +		order--;
   2.206 +	}
   2.207 +
   2.208 +	if (!io_tlb_start)
   2.209 +		goto cleanup1;
   2.210 +
   2.211 +	if (order != get_order(io_tlb_nslabs * (1 << IO_TLB_SHIFT))) {
   2.212 +		printk(KERN_WARNING "Warning: only able to allocate %ld MB "
   2.213 +		       "for software IO TLB\n", (PAGE_SIZE << order) >> 20);
   2.214 +		io_tlb_nslabs = SLABS_PER_PAGE << order;
   2.215 +	}
   2.216 +	io_tlb_end = io_tlb_start + io_tlb_nslabs * (1 << IO_TLB_SHIFT);
   2.217 +	memset(io_tlb_start, 0, io_tlb_nslabs * (1 << IO_TLB_SHIFT));
   2.218 +
   2.219 +	/*
   2.220 +	 * Allocate and initialize the free list array.  This array is used
   2.221 +	 * to find contiguous free memory regions of size up to IO_TLB_SEGSIZE
   2.222 +	 * between io_tlb_start and io_tlb_end.
   2.223 +	 */
   2.224 +	io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL,
   2.225 +	                              get_order(io_tlb_nslabs * sizeof(int)));
   2.226 +	if (!io_tlb_list)
   2.227 +		goto cleanup2;
   2.228 +
   2.229 +	for (i = 0; i < io_tlb_nslabs; i++)
   2.230 + 		io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE);
   2.231 +	io_tlb_index = 0;
   2.232 +
   2.233 +	io_tlb_orig_addr = (unsigned char **)__get_free_pages(GFP_KERNEL,
   2.234 +	                           get_order(io_tlb_nslabs * sizeof(char *)));
   2.235 +	if (!io_tlb_orig_addr)
   2.236 +		goto cleanup3;
   2.237 +
   2.238 +	memset(io_tlb_orig_addr, 0, io_tlb_nslabs * sizeof(char *));
   2.239 +
   2.240 +	/*
   2.241 +	 * Get the overflow emergency buffer
   2.242 +	 */
   2.243 +	io_tlb_overflow_buffer = (void *)__get_free_pages(GFP_DMA,
   2.244 +	                                          get_order(io_tlb_overflow));
   2.245 +	if (!io_tlb_overflow_buffer)
   2.246 +		goto cleanup4;
   2.247 +
   2.248 +	printk(KERN_INFO "Placing %ldMB software IO TLB between 0x%lx - "
   2.249 +	       "0x%lx\n", (io_tlb_nslabs * (1 << IO_TLB_SHIFT)) >> 20,
   2.250 +	       virt_to_phys(io_tlb_start), virt_to_phys(io_tlb_end));
   2.251 +
   2.252 +	return 0;
   2.253 +
   2.254 +cleanup4:
   2.255 +	free_pages((unsigned long)io_tlb_orig_addr, get_order(io_tlb_nslabs *
   2.256 +	                                                      sizeof(char *)));
   2.257 +	io_tlb_orig_addr = NULL;
   2.258 +cleanup3:
   2.259 +	free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs *
   2.260 +	                                                 sizeof(int)));
   2.261 +	io_tlb_list = NULL;
   2.262 +	io_tlb_end = NULL;
   2.263 +cleanup2:
   2.264 +	free_pages((unsigned long)io_tlb_start, order);
   2.265 +	io_tlb_start = NULL;
   2.266 +cleanup1:
   2.267 +	io_tlb_nslabs = req_nslabs;
   2.268 +	return -ENOMEM;
   2.269 +}
   2.270 +
   2.271 +static inline int
   2.272 +address_needs_mapping(struct device *hwdev, dma_addr_t addr)
   2.273 +{
   2.274 +	dma_addr_t mask = 0xffffffff;
   2.275 +	/* If the device has a mask, use it, otherwise default to 32 bits */
   2.276 +	if (hwdev && hwdev->dma_mask)
   2.277 +		mask = *hwdev->dma_mask;
   2.278 +	return (addr & ~mask) != 0;
   2.279 +}
   2.280 +
   2.281 +/*
   2.282 + * Allocates bounce buffer and returns its kernel virtual address.
   2.283 + */
   2.284 +static void *
   2.285 +map_single(struct device *hwdev, char *buffer, size_t size, int dir)
   2.286 +{
   2.287 +	unsigned long flags;
   2.288 +	char *dma_addr;
   2.289 +	unsigned int nslots, stride, index, wrap;
   2.290 +	int i;
   2.291 +
   2.292 +	/*
   2.293 +	 * For mappings greater than a page, we limit the stride (and
   2.294 +	 * hence alignment) to a page size.
   2.295 +	 */
   2.296 +	nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT;
   2.297 +	if (size > PAGE_SIZE)
   2.298 +		stride = (1 << (PAGE_SHIFT - IO_TLB_SHIFT));
   2.299 +	else
   2.300 +		stride = 1;
   2.301 +
   2.302 +	BUG_ON(!nslots);
   2.303 +
   2.304 +	/*
   2.305 +	 * Find suitable number of IO TLB entries size that will fit this
   2.306 +	 * request and allocate a buffer from that IO TLB pool.
   2.307 +	 */
   2.308 +	spin_lock_irqsave(&io_tlb_lock, flags);
   2.309 +	{
   2.310 +		wrap = index = ALIGN(io_tlb_index, stride);
   2.311 +
   2.312 +		if (index >= io_tlb_nslabs)
   2.313 +			wrap = index = 0;
   2.314 +
   2.315 +		do {
   2.316 +			/*
   2.317 +			 * If we find a slot that indicates we have 'nslots'
   2.318 +			 * number of contiguous buffers, we allocate the
   2.319 +			 * buffers from that slot and mark the entries as '0'
   2.320 +			 * indicating unavailable.
   2.321 +			 */
   2.322 +			if (io_tlb_list[index] >= nslots) {
   2.323 +				int count = 0;
   2.324 +
   2.325 +				for (i = index; i < (int) (index + nslots); i++)
   2.326 +					io_tlb_list[i] = 0;
   2.327 +				for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) && io_tlb_list[i]; i--)
   2.328 +					io_tlb_list[i] = ++count;
   2.329 +				dma_addr = io_tlb_start + (index << IO_TLB_SHIFT);
   2.330 +
   2.331 +				/*
   2.332 +				 * Update the indices to avoid searching in
   2.333 +				 * the next round.
   2.334 +				 */
   2.335 +				io_tlb_index = ((index + nslots) < io_tlb_nslabs
   2.336 +						? (index + nslots) : 0);
   2.337 +
   2.338 +				goto found;
   2.339 +			}
   2.340 +			index += stride;
   2.341 +			if (index >= io_tlb_nslabs)
   2.342 +				index = 0;
   2.343 +		} while (index != wrap);
   2.344 +
   2.345 +		spin_unlock_irqrestore(&io_tlb_lock, flags);
   2.346 +		return NULL;
   2.347 +	}
   2.348 +  found:
   2.349 +	spin_unlock_irqrestore(&io_tlb_lock, flags);
   2.350 +
   2.351 +	/*
   2.352 +	 * Save away the mapping from the original address to the DMA address.
   2.353 +	 * This is needed when we sync the memory.  Then we sync the buffer if
   2.354 +	 * needed.
   2.355 +	 */
   2.356 +	io_tlb_orig_addr[index] = buffer;
   2.357 +	if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)
   2.358 +		memcpy(dma_addr, buffer, size);
   2.359 +
   2.360 +	return dma_addr;
   2.361 +}
   2.362 +
   2.363 +/*
   2.364 + * dma_addr is the kernel virtual address of the bounce buffer to unmap.
   2.365 + */
   2.366 +static void
   2.367 +unmap_single(struct device *hwdev, char *dma_addr, size_t size, int dir)
   2.368 +{
   2.369 +	unsigned long flags;
   2.370 +	int i, count, nslots = ALIGN(size, 1 << IO_TLB_SHIFT) >> IO_TLB_SHIFT;
   2.371 +	int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT;
   2.372 +	char *buffer = io_tlb_orig_addr[index];
   2.373 +
   2.374 +	/*
   2.375 +	 * First, sync the memory before unmapping the entry
   2.376 +	 */
   2.377 +	if (buffer && ((dir == DMA_FROM_DEVICE) || (dir == DMA_BIDIRECTIONAL)))
   2.378 +		/*
   2.379 +		 * bounce... copy the data back into the original buffer * and
   2.380 +		 * delete the bounce buffer.
   2.381 +		 */
   2.382 +		memcpy(buffer, dma_addr, size);
   2.383 +
   2.384 +	/*
   2.385 +	 * Return the buffer to the free list by setting the corresponding
   2.386 +	 * entries to indicate the number of contigous entries available.
   2.387 +	 * While returning the entries to the free list, we merge the entries
   2.388 +	 * with slots below and above the pool being returned.
   2.389 +	 */
   2.390 +	spin_lock_irqsave(&io_tlb_lock, flags);
   2.391 +	{
   2.392 +		count = ((index + nslots) < ALIGN(index + 1, IO_TLB_SEGSIZE) ?
   2.393 +			 io_tlb_list[index + nslots] : 0);
   2.394 +		/*
   2.395 +		 * Step 1: return the slots to the free list, merging the
   2.396 +		 * slots with superceeding slots
   2.397 +		 */
   2.398 +		for (i = index + nslots - 1; i >= index; i--)
   2.399 +			io_tlb_list[i] = ++count;
   2.400 +		/*
   2.401 +		 * Step 2: merge the returned slots with the preceding slots,
   2.402 +		 * if available (non zero)
   2.403 +		 */
   2.404 +		for (i = index - 1; (OFFSET(i, IO_TLB_SEGSIZE) != IO_TLB_SEGSIZE -1) && io_tlb_list[i]; i--)
   2.405 +			io_tlb_list[i] = ++count;
   2.406 +	}
   2.407 +	spin_unlock_irqrestore(&io_tlb_lock, flags);
   2.408 +}
   2.409 +
   2.410 +static void
   2.411 +sync_single(struct device *hwdev, char *dma_addr, size_t size,
   2.412 +	    int dir, int target)
   2.413 +{
   2.414 +	int index = (dma_addr - io_tlb_start) >> IO_TLB_SHIFT;
   2.415 +	char *buffer = io_tlb_orig_addr[index];
   2.416 +
   2.417 +	switch (target) {
   2.418 +	case SYNC_FOR_CPU:
   2.419 +		if (likely(dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL))
   2.420 +			memcpy(buffer, dma_addr, size);
   2.421 +		else
   2.422 +			BUG_ON(dir != DMA_TO_DEVICE);
   2.423 +		break;
   2.424 +	case SYNC_FOR_DEVICE:
   2.425 +		if (likely(dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL))
   2.426 +			memcpy(dma_addr, buffer, size);
   2.427 +		else
   2.428 +			BUG_ON(dir != DMA_FROM_DEVICE);
   2.429 +		break;
   2.430 +	default:
   2.431 +		BUG();
   2.432 +	}
   2.433 +}
   2.434 +
   2.435 +void *
   2.436 +swiotlb_alloc_coherent(struct device *hwdev, size_t size,
   2.437 +		       dma_addr_t *dma_handle, gfp_t flags)
   2.438 +{
   2.439 +	unsigned long dev_addr;
   2.440 +	void *ret;
   2.441 +	int order = get_order(size);
   2.442 +
   2.443 +	/*
   2.444 +	 * XXX fix me: the DMA API should pass us an explicit DMA mask
   2.445 +	 * instead, or use ZONE_DMA32 (ia64 overloads ZONE_DMA to be a ~32
   2.446 +	 * bit range instead of a 16MB one).
   2.447 +	 */
   2.448 +	flags |= GFP_DMA;
   2.449 +
   2.450 +	ret = (void *)__get_free_pages(flags, order);
   2.451 +	if (ret && address_needs_mapping(hwdev, virt_to_phys(ret))) {
   2.452 +		/*
   2.453 +		 * The allocated memory isn't reachable by the device.
   2.454 +		 * Fall back on swiotlb_map_single().
   2.455 +		 */
   2.456 +		free_pages((unsigned long) ret, order);
   2.457 +		ret = NULL;
   2.458 +	}
   2.459 +	if (!ret) {
   2.460 +		/*
   2.461 +		 * We are either out of memory or the device can't DMA
   2.462 +		 * to GFP_DMA memory; fall back on
   2.463 +		 * swiotlb_map_single(), which will grab memory from
   2.464 +		 * the lowest available address range.
   2.465 +		 */
   2.466 +		dma_addr_t handle;
   2.467 +		handle = swiotlb_map_single(NULL, NULL, size, DMA_FROM_DEVICE);
   2.468 +		if (swiotlb_dma_mapping_error(handle))
   2.469 +			return NULL;
   2.470 +
   2.471 +		ret = phys_to_virt(handle);
   2.472 +	}
   2.473 +
   2.474 +	memset(ret, 0, size);
   2.475 +	dev_addr = virt_to_phys(ret);
   2.476 +
   2.477 +	/* Confirm address can be DMA'd by device */
   2.478 +	if (address_needs_mapping(hwdev, dev_addr)) {
   2.479 +		printk("hwdev DMA mask = 0x%016Lx, dev_addr = 0x%016lx\n",
   2.480 +		       (unsigned long long)*hwdev->dma_mask, dev_addr);
   2.481 +		panic("swiotlb_alloc_coherent: allocated memory is out of "
   2.482 +		      "range for device");
   2.483 +	}
   2.484 +	*dma_handle = dev_addr;
   2.485 +	return ret;
   2.486 +}
   2.487 +
   2.488 +void
   2.489 +swiotlb_free_coherent(struct device *hwdev, size_t size, void *vaddr,
   2.490 +		      dma_addr_t dma_handle)
   2.491 +{
   2.492 +	if (!(vaddr >= (void *)io_tlb_start
   2.493 +                    && vaddr < (void *)io_tlb_end))
   2.494 +		free_pages((unsigned long) vaddr, get_order(size));
   2.495 +	else
   2.496 +		/* DMA_TO_DEVICE to avoid memcpy in unmap_single */
   2.497 +		swiotlb_unmap_single (hwdev, dma_handle, size, DMA_TO_DEVICE);
   2.498 +}
   2.499 +
   2.500 +static void
   2.501 +swiotlb_full(struct device *dev, size_t size, int dir, int do_panic)
   2.502 +{
   2.503 +	/*
   2.504 +	 * Ran out of IOMMU space for this operation. This is very bad.
   2.505 +	 * Unfortunately the drivers cannot handle this operation properly.
   2.506 +	 * unless they check for dma_mapping_error (most don't)
   2.507 +	 * When the mapping is small enough return a static buffer to limit
   2.508 +	 * the damage, or panic when the transfer is too big.
   2.509 +	 */
   2.510 +	printk(KERN_ERR "DMA: Out of SW-IOMMU space for %lu bytes at "
   2.511 +	       "device %s\n", size, dev ? dev->bus_id : "?");
   2.512 +
   2.513 +	if (size > io_tlb_overflow && do_panic) {
   2.514 +		if (dir == DMA_FROM_DEVICE || dir == DMA_BIDIRECTIONAL)
   2.515 +			panic("DMA: Memory would be corrupted\n");
   2.516 +		if (dir == DMA_TO_DEVICE || dir == DMA_BIDIRECTIONAL)
   2.517 +			panic("DMA: Random memory would be DMAed\n");
   2.518 +	}
   2.519 +}
   2.520 +
   2.521 +/*
   2.522 + * Map a single buffer of the indicated size for DMA in streaming mode.  The
   2.523 + * physical address to use is returned.
   2.524 + *
   2.525 + * Once the device is given the dma address, the device owns this memory until
   2.526 + * either swiotlb_unmap_single or swiotlb_dma_sync_single is performed.
   2.527 + */
   2.528 +dma_addr_t
   2.529 +swiotlb_map_single(struct device *hwdev, void *ptr, size_t size, int dir)
   2.530 +{
   2.531 +	unsigned long dev_addr = virt_to_phys(ptr);
   2.532 +	void *map;
   2.533 +
   2.534 +	BUG_ON(dir == DMA_NONE);
   2.535 +	/*
   2.536 +	 * If the pointer passed in happens to be in the device's DMA window,
   2.537 +	 * we can safely return the device addr and not worry about bounce
   2.538 +	 * buffering it.
   2.539 +	 */
   2.540 +	if (!address_needs_mapping(hwdev, dev_addr) && !swiotlb_force)
   2.541 +		return dev_addr;
   2.542 +
   2.543 +	/*
   2.544 +	 * Oh well, have to allocate and map a bounce buffer.
   2.545 +	 */
   2.546 +	map = map_single(hwdev, ptr, size, dir);
   2.547 +	if (!map) {
   2.548 +		swiotlb_full(hwdev, size, dir, 1);
   2.549 +		map = io_tlb_overflow_buffer;
   2.550 +	}
   2.551 +
   2.552 +	dev_addr = virt_to_phys(map);
   2.553 +
   2.554 +	/*
   2.555 +	 * Ensure that the address returned is DMA'ble
   2.556 +	 */
   2.557 +	if (address_needs_mapping(hwdev, dev_addr))
   2.558 +		panic("map_single: bounce buffer is not DMA'ble");
   2.559 +
   2.560 +	return dev_addr;
   2.561 +}
   2.562 +
   2.563 +/*
   2.564 + * Since DMA is i-cache coherent, any (complete) pages that were written via
   2.565 + * DMA can be marked as "clean" so that lazy_mmu_prot_update() doesn't have to
   2.566 + * flush them when they get mapped into an executable vm-area.
   2.567 + */
   2.568 +static void
   2.569 +mark_clean(void *addr, size_t size)
   2.570 +{
   2.571 +	unsigned long pg_addr, end;
   2.572 +
   2.573 +	pg_addr = PAGE_ALIGN((unsigned long) addr);
   2.574 +	end = (unsigned long) addr + size;
   2.575 +	while (pg_addr + PAGE_SIZE <= end) {
   2.576 +		struct page *page = virt_to_page(pg_addr);
   2.577 +		set_bit(PG_arch_1, &page->flags);
   2.578 +		pg_addr += PAGE_SIZE;
   2.579 +	}
   2.580 +}
   2.581 +
   2.582 +/*
   2.583 + * Unmap a single streaming mode DMA translation.  The dma_addr and size must
   2.584 + * match what was provided for in a previous swiotlb_map_single call.  All
   2.585 + * other usages are undefined.
   2.586 + *
   2.587 + * After this call, reads by the cpu to the buffer are guaranteed to see
   2.588 + * whatever the device wrote there.
   2.589 + */
   2.590 +void
   2.591 +swiotlb_unmap_single(struct device *hwdev, dma_addr_t dev_addr, size_t size,
   2.592 +		     int dir)
   2.593 +{
   2.594 +	char *dma_addr = phys_to_virt(dev_addr);
   2.595 +
   2.596 +	BUG_ON(dir == DMA_NONE);
   2.597 +	if (dma_addr >= io_tlb_start && dma_addr < io_tlb_end)
   2.598 +		unmap_single(hwdev, dma_addr, size, dir);
   2.599 +	else if (dir == DMA_FROM_DEVICE)
   2.600 +		mark_clean(dma_addr, size);
   2.601 +}
   2.602 +
   2.603 +/*
   2.604 + * Make physical memory consistent for a single streaming mode DMA translation
   2.605 + * after a transfer.
   2.606 + *
   2.607 + * If you perform a swiotlb_map_single() but wish to interrogate the buffer
   2.608 + * using the cpu, yet do not wish to teardown the dma mapping, you must
   2.609 + * call this function before doing so.  At the next point you give the dma
   2.610 + * address back to the card, you must first perform a
   2.611 + * swiotlb_dma_sync_for_device, and then the device again owns the buffer
   2.612 + */
   2.613 +static inline void
   2.614 +swiotlb_sync_single(struct device *hwdev, dma_addr_t dev_addr,
   2.615 +		    size_t size, int dir, int target)
   2.616 +{
   2.617 +	char *dma_addr = phys_to_virt(dev_addr);
   2.618 +
   2.619 +	BUG_ON(dir == DMA_NONE);
   2.620 +	if (dma_addr >= io_tlb_start && dma_addr < io_tlb_end)
   2.621 +		sync_single(hwdev, dma_addr, size, dir, target);
   2.622 +	else if (dir == DMA_FROM_DEVICE)
   2.623 +		mark_clean(dma_addr, size);
   2.624 +}
   2.625 +
   2.626 +void
   2.627 +swiotlb_sync_single_for_cpu(struct device *hwdev, dma_addr_t dev_addr,
   2.628 +			    size_t size, int dir)
   2.629 +{
   2.630 +	swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_CPU);
   2.631 +}
   2.632 +
   2.633 +void
   2.634 +swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr,
   2.635 +			       size_t size, int dir)
   2.636 +{
   2.637 +	swiotlb_sync_single(hwdev, dev_addr, size, dir, SYNC_FOR_DEVICE);
   2.638 +}
   2.639 +
   2.640 +/*
   2.641 + * Same as above, but for a sub-range of the mapping.
   2.642 + */
   2.643 +static inline void
   2.644 +swiotlb_sync_single_range(struct device *hwdev, dma_addr_t dev_addr,
   2.645 +			  unsigned long offset, size_t size,
   2.646 +			  int dir, int target)
   2.647 +{
   2.648 +	char *dma_addr = phys_to_virt(dev_addr) + offset;
   2.649 +
   2.650 +	BUG_ON(dir == DMA_NONE);
   2.651 +	if (dma_addr >= io_tlb_start && dma_addr < io_tlb_end)
   2.652 +		sync_single(hwdev, dma_addr, size, dir, target);
   2.653 +	else if (dir == DMA_FROM_DEVICE)
   2.654 +		mark_clean(dma_addr, size);
   2.655 +}
   2.656 +
   2.657 +void
   2.658 +swiotlb_sync_single_range_for_cpu(struct device *hwdev, dma_addr_t dev_addr,
   2.659 +				  unsigned long offset, size_t size, int dir)
   2.660 +{
   2.661 +	swiotlb_sync_single_range(hwdev, dev_addr, offset, size, dir,
   2.662 +				  SYNC_FOR_CPU);
   2.663 +}
   2.664 +
   2.665 +void
   2.666 +swiotlb_sync_single_range_for_device(struct device *hwdev, dma_addr_t dev_addr,
   2.667 +				     unsigned long offset, size_t size, int dir)
   2.668 +{
   2.669 +	swiotlb_sync_single_range(hwdev, dev_addr, offset, size, dir,
   2.670 +				  SYNC_FOR_DEVICE);
   2.671 +}
   2.672 +
   2.673 +/*
   2.674 + * Map a set of buffers described by scatterlist in streaming mode for DMA.
   2.675 + * This is the scatter-gather version of the above swiotlb_map_single
   2.676 + * interface.  Here the scatter gather list elements are each tagged with the
   2.677 + * appropriate dma address and length.  They are obtained via
   2.678 + * sg_dma_{address,length}(SG).
   2.679 + *
   2.680 + * NOTE: An implementation may be able to use a smaller number of
   2.681 + *       DMA address/length pairs than there are SG table elements.
   2.682 + *       (for example via virtual mapping capabilities)
   2.683 + *       The routine returns the number of addr/length pairs actually
   2.684 + *       used, at most nents.
   2.685 + *
   2.686 + * Device ownership issues as mentioned above for swiotlb_map_single are the
   2.687 + * same here.
   2.688 + */
   2.689 +int
   2.690 +swiotlb_map_sg(struct device *hwdev, struct scatterlist *sg, int nelems,
   2.691 +	       int dir)
   2.692 +{
   2.693 +	void *addr;
   2.694 +	unsigned long dev_addr;
   2.695 +	int i;
   2.696 +
   2.697 +	BUG_ON(dir == DMA_NONE);
   2.698 +
   2.699 +	for (i = 0; i < nelems; i++, sg++) {
   2.700 +		addr = SG_ENT_VIRT_ADDRESS(sg);
   2.701 +		dev_addr = virt_to_phys(addr);
   2.702 +		if (swiotlb_force || address_needs_mapping(hwdev, dev_addr)) {
   2.703 +			void *map = map_single(hwdev, addr, sg->length, dir);
   2.704 +			sg->dma_address = virt_to_bus(map);
   2.705 +			if (!map) {
   2.706 +				/* Don't panic here, we expect map_sg users
   2.707 +				   to do proper error handling. */
   2.708 +				swiotlb_full(hwdev, sg->length, dir, 0);
   2.709 +				swiotlb_unmap_sg(hwdev, sg - i, i, dir);
   2.710 +				sg[0].dma_length = 0;
   2.711 +				return 0;
   2.712 +			}
   2.713 +		} else
   2.714 +			sg->dma_address = dev_addr;
   2.715 +		sg->dma_length = sg->length;
   2.716 +	}
   2.717 +	return nelems;
   2.718 +}
   2.719 +
   2.720 +/*
   2.721 + * Unmap a set of streaming mode DMA translations.  Again, cpu read rules
   2.722 + * concerning calls here are the same as for swiotlb_unmap_single() above.
   2.723 + */
   2.724 +void
   2.725 +swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sg, int nelems,
   2.726 +		 int dir)
   2.727 +{
   2.728 +	int i;
   2.729 +
   2.730 +	BUG_ON(dir == DMA_NONE);
   2.731 +
   2.732 +	for (i = 0; i < nelems; i++, sg++)
   2.733 +		if (sg->dma_address != SG_ENT_PHYS_ADDRESS(sg))
   2.734 +			unmap_single(hwdev, (void *) phys_to_virt(sg->dma_address), sg->dma_length, dir);
   2.735 +		else if (dir == DMA_FROM_DEVICE)
   2.736 +			mark_clean(SG_ENT_VIRT_ADDRESS(sg), sg->dma_length);
   2.737 +}
   2.738 +
   2.739 +/*
   2.740 + * Make physical memory consistent for a set of streaming mode DMA translations
   2.741 + * after a transfer.
   2.742 + *
   2.743 + * The same as swiotlb_sync_single_* but for a scatter-gather list, same rules
   2.744 + * and usage.
   2.745 + */
   2.746 +static inline void
   2.747 +swiotlb_sync_sg(struct device *hwdev, struct scatterlist *sg,
   2.748 +		int nelems, int dir, int target)
   2.749 +{
   2.750 +	int i;
   2.751 +
   2.752 +	BUG_ON(dir == DMA_NONE);
   2.753 +
   2.754 +	for (i = 0; i < nelems; i++, sg++)
   2.755 +		if (sg->dma_address != SG_ENT_PHYS_ADDRESS(sg))
   2.756 +			sync_single(hwdev, (void *) sg->dma_address,
   2.757 +				    sg->dma_length, dir, target);
   2.758 +}
   2.759 +
   2.760 +void
   2.761 +swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg,
   2.762 +			int nelems, int dir)
   2.763 +{
   2.764 +	swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_CPU);
   2.765 +}
   2.766 +
   2.767 +void
   2.768 +swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg,
   2.769 +			   int nelems, int dir)
   2.770 +{
   2.771 +	swiotlb_sync_sg(hwdev, sg, nelems, dir, SYNC_FOR_DEVICE);
   2.772 +}
   2.773 +
   2.774 +int
   2.775 +swiotlb_dma_mapping_error(dma_addr_t dma_addr)
   2.776 +{
   2.777 +	return (dma_addr == virt_to_phys(io_tlb_overflow_buffer));
   2.778 +}
   2.779 +
   2.780 +/*
   2.781 + * Return whether the given device DMA address mask can be supported
   2.782 + * properly.  For example, if your device can only drive the low 24-bits
   2.783 + * during bus mastering, then you would pass 0x00ffffff as the mask to
   2.784 + * this function.
   2.785 + */
   2.786 +int
   2.787 +swiotlb_dma_supported (struct device *hwdev, u64 mask)
   2.788 +{
   2.789 +	return (virt_to_phys (io_tlb_end) - 1) <= mask;
   2.790 +}
   2.791 +
   2.792 +EXPORT_SYMBOL(swiotlb_init);
   2.793 +EXPORT_SYMBOL(swiotlb_map_single);
   2.794 +EXPORT_SYMBOL(swiotlb_unmap_single);
   2.795 +EXPORT_SYMBOL(swiotlb_map_sg);
   2.796 +EXPORT_SYMBOL(swiotlb_unmap_sg);
   2.797 +EXPORT_SYMBOL(swiotlb_sync_single_for_cpu);
   2.798 +EXPORT_SYMBOL(swiotlb_sync_single_for_device);
   2.799 +EXPORT_SYMBOL_GPL(swiotlb_sync_single_range_for_cpu);
   2.800 +EXPORT_SYMBOL_GPL(swiotlb_sync_single_range_for_device);
   2.801 +EXPORT_SYMBOL(swiotlb_sync_sg_for_cpu);
   2.802 +EXPORT_SYMBOL(swiotlb_sync_sg_for_device);
   2.803 +EXPORT_SYMBOL(swiotlb_dma_mapping_error);
   2.804 +EXPORT_SYMBOL(swiotlb_alloc_coherent);
   2.805 +EXPORT_SYMBOL(swiotlb_free_coherent);
   2.806 +EXPORT_SYMBOL(swiotlb_dma_supported);