direct-io.hg

changeset 6514:dc93023f4221

PCNET NIC card support for qemu

Based on:
http://cyberkinetica.homeunix.net/qemu/qemu-pcnet.patch6.gz

Signed-off-by: Nitin Kamble <nitin.a.kamble@intel.com>
Signed-off-by: Arun Sharma <arun.sharma@intel.com>
author adsharma@los-vmm.sc.intel.com
date Tue Aug 16 13:39:55 2005 -0800 (2005-08-16)
parents 1ae656509f02
children 6a6c4a422780
files tools/ioemu/hw/pc.c tools/ioemu/hw/pcnet.c tools/ioemu/hw/pcnet.h tools/ioemu/target-i386-dm/Makefile tools/ioemu/vl.c tools/ioemu/vl.h
line diff
     1.1 --- a/tools/ioemu/hw/pc.c	Tue Aug 16 10:09:07 2005 -0800
     1.2 +++ b/tools/ioemu/hw/pc.c	Tue Aug 16 13:39:55 2005 -0800
     1.3 @@ -540,7 +540,10 @@ void pc_init(int ram_size, int vga_ram_s
     1.4  
     1.5      if (pci_enabled) {
     1.6          for(i = 0; i < nb_nics; i++) {
     1.7 -            pci_ne2000_init(pci_bus, &nd_table[i]);
     1.8 +            if (nic_pcnet)
     1.9 +                pci_pcnet_init(pci_bus, &nd_table[i]);
    1.10 +            else
    1.11 +                pci_ne2000_init(pci_bus, &nd_table[i]); 
    1.12          }
    1.13          pci_piix3_ide_init(pci_bus, bs_table);
    1.14  #ifdef APIC_SUPPORT
     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/tools/ioemu/hw/pcnet.c	Tue Aug 16 13:39:55 2005 -0800
     2.3 @@ -0,0 +1,1205 @@
     2.4 +/*
     2.5 + * QEMU AMD PC-Net II (Am79C970A) emulation
     2.6 + * 
     2.7 + * Copyright (c) 2004 Antony T Curtis
     2.8 + * 
     2.9 + * Permission is hereby granted, free of charge, to any person obtaining a copy
    2.10 + * of this software and associated documentation files (the "Software"), to deal
    2.11 + * in the Software without restriction, including without limitation the rights
    2.12 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    2.13 + * copies of the Software, and to permit persons to whom the Software is
    2.14 + * furnished to do so, subject to the following conditions:
    2.15 + *
    2.16 + * The above copyright notice and this permission notice shall be included in
    2.17 + * all copies or substantial portions of the Software.
    2.18 + *
    2.19 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    2.20 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    2.21 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
    2.22 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    2.23 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    2.24 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    2.25 + * THE SOFTWARE.
    2.26 + */
    2.27 + 
    2.28 +/* This software was written to be compatible with the specification:
    2.29 + * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
    2.30 + * AMD Publication# 19436  Rev:E  Amendment/0  Issue Date: June 2000
    2.31 + */
    2.32 + 
    2.33 +#include "vl.h"
    2.34 +#include <sys/times.h>
    2.35 +#include <arpa/inet.h>
    2.36 +#include <net/ethernet.h>
    2.37 +
    2.38 +//#define PCNET_DEBUG
    2.39 +//#define PCNET_DEBUG_IO
    2.40 +//#define PCNET_DEBUG_BCR
    2.41 +//#define PCNET_DEBUG_CSR
    2.42 +//#define PCNET_DEBUG_RMD
    2.43 +//#define PCNET_DEBUG_TMD
    2.44 +//#define PCNET_DEBUG_MATCH
    2.45 +
    2.46 +
    2.47 +#define PCNET_IOPORT_SIZE       0x20
    2.48 +#define PCNET_PNPMMIO_SIZE      0x20
    2.49 +
    2.50 +
    2.51 +typedef struct PCNetState_st PCNetState;
    2.52 +
    2.53 +struct PCNetState_st {
    2.54 +    PCIDevice dev;
    2.55 +    NetDriverState *nd;
    2.56 +    QEMUTimer *poll_timer;
    2.57 +    int mmio_io_addr, rap, isr, lnkst;
    2.58 +    target_phys_addr_t rdra, tdra;
    2.59 +    uint8_t prom[16];
    2.60 +    uint16_t csr[128];
    2.61 +    uint16_t bcr[32];
    2.62 +    uint64_t timer;
    2.63 +    int xmit_pos, recv_pos;
    2.64 +    uint8_t buffer[4096];
    2.65 +};
    2.66 +
    2.67 +#include "pcnet.h"
    2.68 +
    2.69 +static void pcnet_poll(PCNetState *s);
    2.70 +static void pcnet_poll_timer(void *opaque);
    2.71 +
    2.72 +static uint32_t pcnet_csr_readw(PCNetState *s, uint32_t rap);
    2.73 +static void pcnet_csr_writew(PCNetState *s, uint32_t rap, uint32_t new_value);
    2.74 +static void pcnet_bcr_writew(PCNetState *s, uint32_t rap, uint32_t val);
    2.75 +static uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap);
    2.76 +
    2.77 +static void pcnet_s_reset(PCNetState *s)
    2.78 +{
    2.79 +#ifdef PCNET_DEBUG
    2.80 +    printf("pcnet_s_reset\n");
    2.81 +#endif
    2.82 +
    2.83 +    s->lnkst = 0x40;
    2.84 +    s->rdra = 0;
    2.85 +    s->tdra = 0;
    2.86 +    s->rap = 0;
    2.87 +    
    2.88 +    s->bcr[BCR_BSBC] &= ~0x0080;
    2.89 +
    2.90 +    s->csr[0]   = 0x0004;
    2.91 +    s->csr[3]   = 0x0000;
    2.92 +    s->csr[4]   = 0x0115;
    2.93 +    s->csr[5]   = 0x0000;
    2.94 +    s->csr[6]   = 0x0000;
    2.95 +    s->csr[8]   = 0;
    2.96 +    s->csr[9]   = 0;
    2.97 +    s->csr[10]  = 0;
    2.98 +    s->csr[11]  = 0;
    2.99 +    s->csr[12]  = le16_to_cpu(((uint16_t *)&s->prom[0])[0]);
   2.100 +    s->csr[13]  = le16_to_cpu(((uint16_t *)&s->prom[0])[1]);
   2.101 +    s->csr[14]  = le16_to_cpu(((uint16_t *)&s->prom[0])[2]);
   2.102 +    s->csr[15] &= 0x21c4;
   2.103 +    s->csr[72]  = 1;
   2.104 +    s->csr[74]  = 1;
   2.105 +    s->csr[76]  = 1;
   2.106 +    s->csr[78]  = 1;
   2.107 +    s->csr[80]  = 0x1410;
   2.108 +    s->csr[88]  = 0x1003;
   2.109 +    s->csr[89]  = 0x0262;
   2.110 +    s->csr[94]  = 0x0000;
   2.111 +    s->csr[100] = 0x0200;
   2.112 +    s->csr[103] = 0x0105;
   2.113 +    s->csr[103] = 0x0105;
   2.114 +    s->csr[112] = 0x0000;
   2.115 +    s->csr[114] = 0x0000;
   2.116 +    s->csr[122] = 0x0000;
   2.117 +    s->csr[124] = 0x0000;
   2.118 +}
   2.119 +
   2.120 +static void pcnet_update_irq(PCNetState *s)
   2.121 +{
   2.122 +    int isr = 0;
   2.123 +    s->csr[0] &= ~0x0080;
   2.124 +    
   2.125 +#if 1
   2.126 +    if (((s->csr[0] & ~s->csr[3]) & 0x5f00) ||
   2.127 +        (((s->csr[4]>>1) & ~s->csr[4]) & 0x0115) ||
   2.128 +        (((s->csr[5]>>1) & s->csr[5]) & 0x0048))
   2.129 +#else
   2.130 +    if ((!(s->csr[3] & 0x4000) && !!(s->csr[0] & 0x4000)) /* BABL */ ||
   2.131 +        (!(s->csr[3] & 0x1000) && !!(s->csr[0] & 0x1000)) /* MISS */ ||
   2.132 +        (!(s->csr[3] & 0x0100) && !!(s->csr[0] & 0x0100)) /* IDON */ ||
   2.133 +        (!(s->csr[3] & 0x0200) && !!(s->csr[0] & 0x0200)) /* TINT */ ||
   2.134 +        (!(s->csr[3] & 0x0400) && !!(s->csr[0] & 0x0400)) /* RINT */ ||
   2.135 +        (!(s->csr[3] & 0x0800) && !!(s->csr[0] & 0x0800)) /* MERR */ ||
   2.136 +        (!(s->csr[4] & 0x0001) && !!(s->csr[4] & 0x0002)) /* JAB */ ||
   2.137 +        (!(s->csr[4] & 0x0004) && !!(s->csr[4] & 0x0008)) /* TXSTRT */ ||
   2.138 +        (!(s->csr[4] & 0x0010) && !!(s->csr[4] & 0x0020)) /* RCVO */ ||
   2.139 +        (!(s->csr[4] & 0x0100) && !!(s->csr[4] & 0x0200)) /* MFCO */ ||
   2.140 +        (!!(s->csr[5] & 0x0040) && !!(s->csr[5] & 0x0080)) /* EXDINT */ ||
   2.141 +        (!!(s->csr[5] & 0x0008) && !!(s->csr[5] & 0x0010)) /* MPINT */)
   2.142 +#endif
   2.143 +    {
   2.144 +       
   2.145 +        isr = CSR_INEA(s);
   2.146 +        s->csr[0] |= 0x0080;
   2.147 +    }
   2.148 +    
   2.149 +    if (!!(s->csr[4] & 0x0080) && CSR_INEA(s)) { /* UINT */
   2.150 +        s->csr[4] &= ~0x0080;
   2.151 +        s->csr[4] |= 0x0040;
   2.152 +        s->csr[0] |= 0x0080;
   2.153 +        isr = 1;
   2.154 +#ifdef PCNET_DEBUG
   2.155 +        printf("pcnet user int\n");
   2.156 +#endif
   2.157 +    }
   2.158 +
   2.159 +#if 1
   2.160 +    if (((s->csr[5]>>1) & s->csr[5]) & 0x0500) 
   2.161 +#else
   2.162 +    if ((!!(s->csr[5] & 0x0400) && !!(s->csr[5] & 0x0800)) /* SINT */ ||
   2.163 +        (!!(s->csr[5] & 0x0100) && !!(s->csr[5] & 0x0200)) /* SLPINT */ )
   2.164 +#endif
   2.165 +    {
   2.166 +        isr = 1;
   2.167 +        s->csr[0] |= 0x0080;
   2.168 +    }
   2.169 +
   2.170 +    if (isr != s->isr) {
   2.171 +#ifdef PCNET_DEBUG
   2.172 +        printf("pcnet: INTA=%d\n", isr);
   2.173 +#endif
   2.174 +    }
   2.175 +        pci_set_irq(&s->dev, 0, isr);
   2.176 +        s->isr = isr;
   2.177 +}
   2.178 +
   2.179 +static void pcnet_init(PCNetState *s)
   2.180 +{
   2.181 +#ifdef PCNET_DEBUG
   2.182 +    printf("pcnet_init init_addr=0x%08x\n", PHYSADDR(s,CSR_IADR(s)));
   2.183 +#endif
   2.184 +    
   2.185 +#define PCNET_INIT() do { \
   2.186 +        cpu_physical_memory_read(PHYSADDR(s,CSR_IADR(s)),       \
   2.187 +                (uint8_t *)&initblk, sizeof(initblk));          \
   2.188 +        s->csr[15] = le16_to_cpu(initblk.mode);                 \
   2.189 +        CSR_RCVRL(s) = (initblk.rlen < 9) ? (1 << initblk.rlen) : 512;  \
   2.190 +        CSR_XMTRL(s) = (initblk.tlen < 9) ? (1 << initblk.tlen) : 512;  \
   2.191 +        s->csr[ 6] = (initblk.tlen << 12) | (initblk.rlen << 8);        \
   2.192 +        s->csr[ 8] = le16_to_cpu(initblk.ladrf1);                       \
   2.193 +        s->csr[ 9] = le16_to_cpu(initblk.ladrf2);                       \
   2.194 +        s->csr[10] = le16_to_cpu(initblk.ladrf3);                       \
   2.195 +        s->csr[11] = le16_to_cpu(initblk.ladrf4);                       \
   2.196 +        s->csr[12] = le16_to_cpu(initblk.padr1);                        \
   2.197 +        s->csr[13] = le16_to_cpu(initblk.padr2);                        \
   2.198 +        s->csr[14] = le16_to_cpu(initblk.padr3);                        \
   2.199 +        s->rdra = PHYSADDR(s,initblk.rdra);                             \
   2.200 +        s->tdra = PHYSADDR(s,initblk.tdra);                             \
   2.201 +} while (0)
   2.202 +    
   2.203 +    if (BCR_SSIZE32(s)) {
   2.204 +        struct pcnet_initblk32 initblk;
   2.205 +        PCNET_INIT();
   2.206 +#ifdef PCNET_DEBUG
   2.207 +        printf("initblk.rlen=0x%02x, initblk.tlen=0x%02x\n",
   2.208 +                initblk.rlen, initblk.tlen);
   2.209 +#endif
   2.210 +    } else {
   2.211 +        struct pcnet_initblk16 initblk;
   2.212 +        PCNET_INIT();
   2.213 +#ifdef PCNET_DEBUG
   2.214 +        printf("initblk.rlen=0x%02x, initblk.tlen=0x%02x\n",
   2.215 +                initblk.rlen, initblk.tlen);
   2.216 +#endif
   2.217 +    }
   2.218 +
   2.219 +#undef PCNET_INIT
   2.220 +
   2.221 +    CSR_RCVRC(s) = CSR_RCVRL(s);
   2.222 +    CSR_XMTRC(s) = CSR_XMTRL(s);
   2.223 +
   2.224 +#ifdef PCNET_DEBUG
   2.225 +    printf("pcnet ss32=%d rdra=0x%08x[%d] tdra=0x%08x[%d]\n", 
   2.226 +        BCR_SSIZE32(s),
   2.227 +        s->rdra, CSR_RCVRL(s), s->tdra, CSR_XMTRL(s));
   2.228 +#endif
   2.229 +
   2.230 +    s->csr[0] |= 0x0101;    
   2.231 +    s->csr[0] &= ~0x0004;       /* clear STOP bit */
   2.232 +}
   2.233 +
   2.234 +static void pcnet_start(PCNetState *s)
   2.235 +{
   2.236 +#ifdef PCNET_DEBUG
   2.237 +    printf("pcnet_start\n");
   2.238 +#endif
   2.239 +
   2.240 +    if (!CSR_DTX(s))
   2.241 +        s->csr[0] |= 0x0010;    /* set TXON */
   2.242 +        
   2.243 +    if (!CSR_DRX(s))
   2.244 +        s->csr[0] |= 0x0020;    /* set RXON */
   2.245 +
   2.246 +    s->csr[0] &= ~0x0004;       /* clear STOP bit */
   2.247 +    s->csr[0] |= 0x0002;
   2.248 +}
   2.249 +
   2.250 +static void pcnet_stop(PCNetState *s)
   2.251 +{
   2.252 +#ifdef PCNET_DEBUG
   2.253 +    printf("pcnet_stop\n");
   2.254 +#endif
   2.255 +    s->csr[0] &= ~0x7feb;
   2.256 +    s->csr[0] |= 0x0014;
   2.257 +    s->csr[4] &= ~0x02c2;
   2.258 +    s->csr[5] &= ~0x0011;
   2.259 +    pcnet_poll_timer(s);
   2.260 +}
   2.261 +
   2.262 +static void pcnet_rdte_poll(PCNetState *s)
   2.263 +{
   2.264 +    s->csr[28] = s->csr[29] = 0;
   2.265 +    if (s->rdra) {
   2.266 +        int bad = 0;
   2.267 +#if 1
   2.268 +        target_phys_addr_t crda = pcnet_rdra_addr(s, CSR_RCVRC(s));
   2.269 +        target_phys_addr_t nrda = pcnet_rdra_addr(s, -1 + CSR_RCVRC(s));
   2.270 +        target_phys_addr_t nnrd = pcnet_rdra_addr(s, -2 + CSR_RCVRC(s));
   2.271 +#else
   2.272 +        target_phys_addr_t crda = s->rdra + 
   2.273 +            (CSR_RCVRL(s) - CSR_RCVRC(s)) *
   2.274 +            (BCR_SWSTYLE(s) ? 16 : 8 );
   2.275 +        int nrdc = CSR_RCVRC(s)<=1 ? CSR_RCVRL(s) : CSR_RCVRC(s)-1;
   2.276 +        target_phys_addr_t nrda = s->rdra + 
   2.277 +            (CSR_RCVRL(s) - nrdc) *
   2.278 +            (BCR_SWSTYLE(s) ? 16 : 8 );
   2.279 +        int nnrc = nrdc<=1 ? CSR_RCVRL(s) : nrdc-1;
   2.280 +        target_phys_addr_t nnrd = s->rdra + 
   2.281 +            (CSR_RCVRL(s) - nnrc) *
   2.282 +            (BCR_SWSTYLE(s) ? 16 : 8 );
   2.283 +#endif
   2.284 +
   2.285 +        CHECK_RMD(PHYSADDR(s,crda), bad);
   2.286 +        if (!bad) {
   2.287 +            CHECK_RMD(PHYSADDR(s,nrda), bad);
   2.288 +            if (bad || (nrda == crda)) nrda = 0;
   2.289 +            CHECK_RMD(PHYSADDR(s,nnrd), bad);
   2.290 +            if (bad || (nnrd == crda)) nnrd = 0;
   2.291 +
   2.292 +            s->csr[28] = crda & 0xffff;
   2.293 +            s->csr[29] = crda >> 16;
   2.294 +            s->csr[26] = nrda & 0xffff;
   2.295 +            s->csr[27] = nrda >> 16;
   2.296 +            s->csr[36] = nnrd & 0xffff;
   2.297 +            s->csr[37] = nnrd >> 16;
   2.298 +#ifdef PCNET_DEBUG
   2.299 +            if (bad) {
   2.300 +                printf("pcnet: BAD RMD RECORDS AFTER 0x%08x\n",
   2.301 +                       PHYSADDR(s,crda));
   2.302 +            }
   2.303 +        } else {
   2.304 +            printf("pcnet: BAD RMD RDA=0x%08x\n", PHYSADDR(s,crda));
   2.305 +#endif
   2.306 +        }
   2.307 +    }
   2.308 +    
   2.309 +    if (CSR_CRDA(s)) {
   2.310 +        struct pcnet_RMD rmd;
   2.311 +        RMDLOAD(&rmd, PHYSADDR(s,CSR_CRDA(s)));
   2.312 +        CSR_CRBC(s) = rmd.rmd1.bcnt;
   2.313 +        CSR_CRST(s) = ((uint32_t *)&rmd)[1] >> 16;
   2.314 +#ifdef PCNET_DEBUG_RMD_X
   2.315 +        printf("CRDA=0x%08x CRST=0x%04x RCVRC=%d RMD1=0x%08x RMD2=0x%08x\n",
   2.316 +                PHYSADDR(s,CSR_CRDA(s)), CSR_CRST(s), CSR_RCVRC(s),
   2.317 +                ((uint32_t *)&rmd)[1], ((uint32_t *)&rmd)[2]);
   2.318 +        PRINT_RMD(&rmd);
   2.319 +#endif
   2.320 +    } else {
   2.321 +        CSR_CRBC(s) = CSR_CRST(s) = 0;
   2.322 +    }
   2.323 +    
   2.324 +    if (CSR_NRDA(s)) {
   2.325 +        struct pcnet_RMD rmd;
   2.326 +        RMDLOAD(&rmd, PHYSADDR(s,CSR_NRDA(s)));
   2.327 +        CSR_NRBC(s) = rmd.rmd1.bcnt;
   2.328 +        CSR_NRST(s) = ((uint32_t *)&rmd)[1] >> 16;
   2.329 +    } else {
   2.330 +        CSR_NRBC(s) = CSR_NRST(s) = 0;
   2.331 +    }
   2.332 +
   2.333 +}
   2.334 +
   2.335 +static int pcnet_tdte_poll(PCNetState *s)
   2.336 +{
   2.337 +    s->csr[34] = s->csr[35] = 0;
   2.338 +    if (s->tdra) {
   2.339 +        target_phys_addr_t cxda = s->tdra + 
   2.340 +            (CSR_XMTRL(s) - CSR_XMTRC(s)) *
   2.341 +            (BCR_SWSTYLE(s) ? 16 : 8 );
   2.342 +        int bad = 0;
   2.343 +        CHECK_TMD(PHYSADDR(s, cxda),bad);
   2.344 +        if (!bad) {
   2.345 +            if (CSR_CXDA(s) != cxda) {
   2.346 +                s->csr[60] = s->csr[34];
   2.347 +                s->csr[61] = s->csr[35];
   2.348 +                s->csr[62] = CSR_CXBC(s);
   2.349 +                s->csr[63] = CSR_CXST(s);
   2.350 +            }
   2.351 +            s->csr[34] = cxda & 0xffff;
   2.352 +            s->csr[35] = cxda >> 16;
   2.353 +#ifdef PCNET_DEBUG
   2.354 +        } else {
   2.355 +            printf("pcnet: BAD TMD XDA=0x%08x\n", PHYSADDR(s,cxda));
   2.356 +#endif
   2.357 +        }
   2.358 +    }
   2.359 +
   2.360 +    if (CSR_CXDA(s)) {
   2.361 +        struct pcnet_TMD tmd;
   2.362 +
   2.363 +        TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));                
   2.364 +
   2.365 +        CSR_CXBC(s) = tmd.tmd1.bcnt;
   2.366 +        CSR_CXST(s) = ((uint32_t *)&tmd)[1] >> 16;
   2.367 +    } else {
   2.368 +        CSR_CXBC(s) = CSR_CXST(s) = 0;
   2.369 +    }
   2.370 +    
   2.371 +    return !!(CSR_CXST(s) & 0x8000);
   2.372 +}
   2.373 +
   2.374 +static int pcnet_can_receive(void *opaque)
   2.375 +{
   2.376 +    PCNetState *s = opaque;
   2.377 +    if (CSR_STOP(s) || CSR_SPND(s))
   2.378 +        return 0;
   2.379 +        
   2.380 +    if (s->recv_pos > 0)
   2.381 +        return 0;
   2.382 +
   2.383 +    return sizeof(s->buffer)-16;
   2.384 +}
   2.385 +
   2.386 +static void pcnet_receive(void *opaque, const uint8_t *buf, int size)
   2.387 +{
   2.388 +    PCNetState *s = opaque;
   2.389 +    int is_padr = 0, is_bcast = 0, is_ladr = 0;
   2.390 +
   2.391 +    if (CSR_DRX(s) || CSR_STOP(s) || CSR_SPND(s) || !size)
   2.392 +        return;
   2.393 +
   2.394 +#ifdef PCNET_DEBUG
   2.395 +    printf("pcnet_receive size=%d\n", size);
   2.396 +#endif
   2.397 +
   2.398 +    if (CSR_PROM(s) 
   2.399 +        || (is_padr=padr_match(s, buf, size)) 
   2.400 +        || (is_bcast=padr_bcast(s, buf, size))
   2.401 +        || (is_ladr=ladr_match(s, buf, size))) {
   2.402 +
   2.403 +        pcnet_rdte_poll(s);
   2.404 +
   2.405 +        if (!(CSR_CRST(s) & 0x8000) && s->rdra) {
   2.406 +            struct pcnet_RMD rmd;
   2.407 +            int rcvrc = CSR_RCVRC(s)-1,i;
   2.408 +            target_phys_addr_t nrda;
   2.409 +            for (i = CSR_RCVRL(s)-1; i > 0; i--, rcvrc--) {
   2.410 +                if (rcvrc <= 1)
   2.411 +                    rcvrc = CSR_RCVRL(s);
   2.412 +                nrda = s->rdra +
   2.413 +                    (CSR_RCVRL(s) - rcvrc) *
   2.414 +                    (BCR_SWSTYLE(s) ? 16 : 8 );
   2.415 +                RMDLOAD(&rmd, PHYSADDR(s,nrda));                  
   2.416 +                if (rmd.rmd1.own) {                
   2.417 +#ifdef PCNET_DEBUG_RMD
   2.418 +                    printf("pcnet - scan buffer: RCVRC=%d PREV_RCVRC=%d\n", 
   2.419 +                                rcvrc, CSR_RCVRC(s));
   2.420 +#endif
   2.421 +                    CSR_RCVRC(s) = rcvrc;
   2.422 +                    pcnet_rdte_poll(s);
   2.423 +                    break;
   2.424 +                }
   2.425 +            }
   2.426 +        }
   2.427 +
   2.428 +        if (!(CSR_CRST(s) & 0x8000)) {
   2.429 +#ifdef PCNET_DEBUG_RMD
   2.430 +            printf("pcnet - no buffer: RCVRC=%d\n", CSR_RCVRC(s));
   2.431 +#endif
   2.432 +            s->csr[0] |= 0x1000; /* Set MISS flag */
   2.433 +            CSR_MISSC(s)++;
   2.434 +        } else {
   2.435 +            uint8_t *src = &s->buffer[8];
   2.436 +            target_phys_addr_t crda = CSR_CRDA(s);
   2.437 +            struct pcnet_RMD rmd;
   2.438 +            int pktcount = 0;
   2.439 +
   2.440 +            memcpy(src, buf, size);
   2.441 +            
   2.442 +            if (!CSR_ASTRP_RCV(s)) {
   2.443 +                uint32_t fcs = ~0;
   2.444 +#if 0            
   2.445 +                uint8_t *p = s->buffer;
   2.446 +                
   2.447 +                ((uint32_t *)p)[0] = ((uint32_t *)p)[1] = 0xaaaaaaaa;
   2.448 +                p[7] = 0xab;
   2.449 +#else
   2.450 +                uint8_t *p = src;
   2.451 +#endif
   2.452 +
   2.453 +                while (size < 46) {
   2.454 +                    src[size++] = 0;
   2.455 +                }
   2.456 +                
   2.457 +                while (p != &src[size]) {
   2.458 +                    CRC(fcs, *p++);
   2.459 +                }
   2.460 +                ((uint32_t *)&src[size])[0] = htonl(fcs);
   2.461 +                size += 4; /* FCS at end of packet */
   2.462 +            } else size += 4;
   2.463 +
   2.464 +#ifdef PCNET_DEBUG_MATCH
   2.465 +            PRINT_PKTHDR(buf);
   2.466 +#endif
   2.467 +
   2.468 +            RMDLOAD(&rmd, PHYSADDR(s,crda));
   2.469 +            /*if (!CSR_LAPPEN(s))*/
   2.470 +                rmd.rmd1.stp = 1;
   2.471 +
   2.472 +#define PCNET_RECV_STORE() do {                                 \
   2.473 +    int count = MIN(4096 - rmd.rmd1.bcnt,size);                 \
   2.474 +    target_phys_addr_t rbadr = PHYSADDR(s, rmd.rmd0.rbadr);     \
   2.475 +    cpu_physical_memory_write(rbadr, src, count);               \
   2.476 +    cpu_physical_memory_set_dirty(rbadr);                       \
   2.477 +    cpu_physical_memory_set_dirty(rbadr+count);                 \
   2.478 +    src += count; size -= count;                                \
   2.479 +    rmd.rmd2.mcnt = count; rmd.rmd1.own = 0;                    \
   2.480 +    RMDSTORE(&rmd, PHYSADDR(s,crda));                           \
   2.481 +    pktcount++;                                                 \
   2.482 +} while (0)
   2.483 +
   2.484 +            PCNET_RECV_STORE();
   2.485 +            if ((size > 0) && CSR_NRDA(s)) {
   2.486 +                target_phys_addr_t nrda = CSR_NRDA(s);
   2.487 +                RMDLOAD(&rmd, PHYSADDR(s,nrda));
   2.488 +                if (rmd.rmd1.own) {
   2.489 +                    crda = nrda;
   2.490 +                    PCNET_RECV_STORE();
   2.491 +                    if ((size > 0) && (nrda=CSR_NNRD(s))) {
   2.492 +                        RMDLOAD(&rmd, PHYSADDR(s,nrda));
   2.493 +                        if (rmd.rmd1.own) {
   2.494 +                            crda = nrda;
   2.495 +                            PCNET_RECV_STORE();
   2.496 +                        }
   2.497 +                    }
   2.498 +                }                
   2.499 +            }
   2.500 +
   2.501 +#undef PCNET_RECV_STORE
   2.502 +
   2.503 +            RMDLOAD(&rmd, PHYSADDR(s,crda));
   2.504 +            if (size == 0) {
   2.505 +                rmd.rmd1.enp = 1;
   2.506 +                rmd.rmd1.pam = !CSR_PROM(s) && is_padr;
   2.507 +                rmd.rmd1.lafm = !CSR_PROM(s) && is_ladr;
   2.508 +                rmd.rmd1.bam = !CSR_PROM(s) && is_bcast;
   2.509 +            } else {
   2.510 +                rmd.rmd1.oflo = 1;
   2.511 +                rmd.rmd1.buff = 1;
   2.512 +                rmd.rmd1.err = 1;
   2.513 +            }
   2.514 +            RMDSTORE(&rmd, PHYSADDR(s,crda));
   2.515 +            s->csr[0] |= 0x0400;
   2.516 +
   2.517 +#ifdef PCNET_DEBUG
   2.518 +            printf("RCVRC=%d CRDA=0x%08x BLKS=%d\n", 
   2.519 +                CSR_RCVRC(s), PHYSADDR(s,CSR_CRDA(s)), pktcount);
   2.520 +#endif
   2.521 +#ifdef PCNET_DEBUG_RMD
   2.522 +            PRINT_RMD(&rmd);
   2.523 +#endif        
   2.524 +
   2.525 +            while (pktcount--) {
   2.526 +                if (CSR_RCVRC(s) <= 1)
   2.527 +                    CSR_RCVRC(s) = CSR_RCVRL(s);
   2.528 +                else
   2.529 +                    CSR_RCVRC(s)--;            
   2.530 +            }
   2.531 +            
   2.532 +            pcnet_rdte_poll(s);
   2.533 +
   2.534 +        }        
   2.535 +    }
   2.536 +
   2.537 +    pcnet_poll(s);
   2.538 +    pcnet_update_irq(s);    
   2.539 +}
   2.540 +
   2.541 +static void pcnet_transmit(PCNetState *s)
   2.542 +{
   2.543 +    target_phys_addr_t xmit_cxda = 0;
   2.544 +    int count = CSR_XMTRL(s)-1;
   2.545 +    s->xmit_pos = -1;
   2.546 +    
   2.547 +    if (!CSR_TXON(s)) {
   2.548 +        s->csr[0] &= ~0x0008;
   2.549 +        return;
   2.550 +    }
   2.551 +    
   2.552 +    txagain:
   2.553 +    if (pcnet_tdte_poll(s)) {
   2.554 +        struct pcnet_TMD tmd;
   2.555 +
   2.556 +        TMDLOAD(&tmd, PHYSADDR(s,CSR_CXDA(s)));                
   2.557 +
   2.558 +#ifdef PCNET_DEBUG_TMD
   2.559 +        printf("  TMDLOAD 0x%08x\n", PHYSADDR(s,CSR_CXDA(s)));
   2.560 +        PRINT_TMD(&tmd);
   2.561 +#endif
   2.562 +        if (tmd.tmd1.stp) {
   2.563 +            s->xmit_pos = 0;                
   2.564 +            if (!tmd.tmd1.enp) {
   2.565 +                cpu_physical_memory_read(PHYSADDR(s, tmd.tmd0.tbadr),
   2.566 +                        s->buffer, 4096 - tmd.tmd1.bcnt);
   2.567 +                s->xmit_pos += 4096 - tmd.tmd1.bcnt;
   2.568 +            } 
   2.569 +            xmit_cxda = PHYSADDR(s,CSR_CXDA(s));
   2.570 +        }
   2.571 +        if (tmd.tmd1.enp && (s->xmit_pos >= 0)) {
   2.572 +            cpu_physical_memory_read(PHYSADDR(s, tmd.tmd0.tbadr),
   2.573 +                    s->buffer + s->xmit_pos, 4096 - tmd.tmd1.bcnt);
   2.574 +            s->xmit_pos += 4096 - tmd.tmd1.bcnt;
   2.575 +#ifdef PCNET_DEBUG
   2.576 +            printf("pcnet_transmit size=%d\n", s->xmit_pos);
   2.577 +#endif            
   2.578 +            if (CSR_LOOP(s))
   2.579 +                pcnet_receive(s, s->buffer, s->xmit_pos);
   2.580 +            else
   2.581 +                qemu_send_packet(s->nd, s->buffer, s->xmit_pos);
   2.582 +
   2.583 +            s->csr[0] &= ~0x0008;   /* clear TDMD */
   2.584 +            s->csr[4] |= 0x0004;    /* set TXSTRT */
   2.585 +            s->xmit_pos = -1;
   2.586 +        }
   2.587 +
   2.588 +        tmd.tmd1.own = 0;
   2.589 +        TMDSTORE(&tmd, PHYSADDR(s,CSR_CXDA(s)));
   2.590 +        if (!CSR_TOKINTD(s) || (CSR_LTINTEN(s) && tmd.tmd1.ltint))
   2.591 +            s->csr[0] |= 0x0200;    /* set TINT */
   2.592 +
   2.593 +        if (CSR_XMTRC(s)<=1)
   2.594 +            CSR_XMTRC(s) = CSR_XMTRL(s);
   2.595 +        else
   2.596 +            CSR_XMTRC(s)--;
   2.597 +        if (count--)
   2.598 +            goto txagain;
   2.599 +
   2.600 +    } else 
   2.601 +    if (s->xmit_pos >= 0) {
   2.602 +        struct pcnet_TMD tmd;
   2.603 +        TMDLOAD(&tmd, PHYSADDR(s,xmit_cxda));                
   2.604 +        tmd.tmd2.buff = tmd.tmd2.uflo = tmd.tmd1.err = 1;
   2.605 +        tmd.tmd1.own = 0;
   2.606 +        TMDSTORE(&tmd, PHYSADDR(s,xmit_cxda));
   2.607 +        s->csr[0] |= 0x0200;    /* set TINT */
   2.608 +        if (!CSR_DXSUFLO(s)) {
   2.609 +            s->csr[0] &= ~0x0010;
   2.610 +        } else
   2.611 +        if (count--)
   2.612 +          goto txagain;
   2.613 +    }
   2.614 +}
   2.615 +
   2.616 +static void pcnet_poll(PCNetState *s)
   2.617 +{
   2.618 +    if (CSR_RXON(s)) {
   2.619 +        pcnet_rdte_poll(s);
   2.620 +    }
   2.621 +
   2.622 +    if (CSR_TDMD(s) || 
   2.623 +        (CSR_TXON(s) && !CSR_DPOLL(s) && pcnet_tdte_poll(s)))
   2.624 +        pcnet_transmit(s);
   2.625 +}
   2.626 +
   2.627 +static void pcnet_poll_timer(void *opaque)
   2.628 +{
   2.629 +    PCNetState *s = opaque;
   2.630 +
   2.631 +    qemu_del_timer(s->poll_timer);
   2.632 +
   2.633 +    if (CSR_TDMD(s)) {
   2.634 +        pcnet_transmit(s);
   2.635 +    }
   2.636 +
   2.637 +    pcnet_update_irq(s);    
   2.638 +
   2.639 +    if (!CSR_STOP(s) && !CSR_SPND(s) && !CSR_DPOLL(s)) {
   2.640 +        uint64_t now = qemu_get_clock(vm_clock) * 33;
   2.641 +        if (!s->timer || !now)
   2.642 +            s->timer = now;
   2.643 +        else {
   2.644 +            uint64_t t = now - s->timer + CSR_POLL(s);
   2.645 +            if (t > 0xffffLL) {
   2.646 +                pcnet_poll(s);
   2.647 +                CSR_POLL(s) = CSR_PINT(s);
   2.648 +            } else
   2.649 +                CSR_POLL(s) = t;
   2.650 +        }
   2.651 +        qemu_mod_timer(s->poll_timer, 
   2.652 +            pcnet_get_next_poll_time(s,qemu_get_clock(vm_clock)));
   2.653 +    }
   2.654 +}
   2.655 +
   2.656 +
   2.657 +static void pcnet_csr_writew(PCNetState *s, uint32_t rap, uint32_t new_value)
   2.658 +{
   2.659 +    uint16_t val = new_value;
   2.660 +#ifdef PCNET_DEBUG_CSR
   2.661 +    printf("pcnet_csr_writew rap=%d val=0x%04x\n", rap, val);
   2.662 +#endif
   2.663 +    switch (rap) {
   2.664 +    case 0:
   2.665 +        s->csr[0] &= ~(val & 0x7f00); /* Clear any interrupt flags */
   2.666 +
   2.667 +        s->csr[0] = (s->csr[0] & ~0x0040) | (val & 0x0048);
   2.668 +
   2.669 +        val = (val & 0x007f) | (s->csr[0] & 0x7f00);
   2.670 +
   2.671 +        /* IFF STOP, STRT and INIT are set, clear STRT and INIT */
   2.672 +        if ((val&7) == 7)
   2.673 +          val &= ~3;
   2.674 +
   2.675 +        if (!CSR_STOP(s) && (val & 4))
   2.676 +            pcnet_stop(s);
   2.677 +
   2.678 +        if (!CSR_INIT(s) && (val & 1))
   2.679 +            pcnet_init(s);
   2.680 +
   2.681 +        if (!CSR_STRT(s) && (val & 2))
   2.682 +            pcnet_start(s);
   2.683 +
   2.684 +        if (CSR_TDMD(s)) 
   2.685 +            pcnet_transmit(s);
   2.686 +
   2.687 +        return;
   2.688 +    case 1:
   2.689 +    case 2:
   2.690 +    case 8:
   2.691 +    case 9:
   2.692 +    case 10:
   2.693 +    case 11:
   2.694 +    case 12:
   2.695 +    case 13:
   2.696 +    case 14:
   2.697 +    case 15:
   2.698 +    case 18: /* CRBAL */
   2.699 +    case 19: /* CRBAU */
   2.700 +    case 20: /* CXBAL */
   2.701 +    case 21: /* CXBAU */
   2.702 +    case 22: /* NRBAU */
   2.703 +    case 23: /* NRBAU */
   2.704 +    case 24:
   2.705 +    case 25:
   2.706 +    case 26:
   2.707 +    case 27:
   2.708 +    case 28:
   2.709 +    case 29:
   2.710 +    case 30:
   2.711 +    case 31:
   2.712 +    case 32:
   2.713 +    case 33:
   2.714 +    case 34:
   2.715 +    case 35:
   2.716 +    case 36:
   2.717 +    case 37:
   2.718 +    case 38:
   2.719 +    case 39:
   2.720 +    case 40: /* CRBC */
   2.721 +    case 41:
   2.722 +    case 42: /* CXBC */
   2.723 +    case 43:
   2.724 +    case 44:
   2.725 +    case 45:
   2.726 +    case 46: /* POLL */
   2.727 +    case 47: /* POLLINT */
   2.728 +    case 72:
   2.729 +    case 74:
   2.730 +    case 76: /* RCVRL */
   2.731 +    case 78: /* XMTRL */
   2.732 +    case 112:
   2.733 +       if (CSR_STOP(s) || CSR_SPND(s))
   2.734 +           break;
   2.735 +       return;
   2.736 +    case 3:
   2.737 +        break;
   2.738 +    case 4:
   2.739 +        s->csr[4] &= ~(val & 0x026a); 
   2.740 +        val &= ~0x026a; val |= s->csr[4] & 0x026a;
   2.741 +        break;
   2.742 +    case 5:
   2.743 +        s->csr[5] &= ~(val & 0x0a90); 
   2.744 +        val &= ~0x0a90; val |= s->csr[5] & 0x0a90;
   2.745 +        break;
   2.746 +    case 16:
   2.747 +        pcnet_csr_writew(s,1,val);
   2.748 +        return;
   2.749 +    case 17:
   2.750 +        pcnet_csr_writew(s,2,val);
   2.751 +        return;
   2.752 +    case 58:
   2.753 +        pcnet_bcr_writew(s,BCR_SWS,val);
   2.754 +        break;
   2.755 +    default:
   2.756 +        return;
   2.757 +    }
   2.758 +    s->csr[rap] = val;
   2.759 +}
   2.760 +
   2.761 +static uint32_t pcnet_csr_readw(PCNetState *s, uint32_t rap)
   2.762 +{
   2.763 +    uint32_t val;
   2.764 +    switch (rap) {
   2.765 +    case 0:
   2.766 +        pcnet_update_irq(s);
   2.767 +        val = s->csr[0];
   2.768 +        val |= (val & 0x7800) ? 0x8000 : 0;
   2.769 +        break;
   2.770 +    case 16:
   2.771 +        return pcnet_csr_readw(s,1);
   2.772 +    case 17:
   2.773 +        return pcnet_csr_readw(s,2);
   2.774 +    case 58:
   2.775 +        return pcnet_bcr_readw(s,BCR_SWS);
   2.776 +    case 88:
   2.777 +        val = s->csr[89];
   2.778 +        val <<= 16;
   2.779 +        val |= s->csr[88];
   2.780 +        break;
   2.781 +    default:
   2.782 +        val = s->csr[rap];
   2.783 +    }
   2.784 +#ifdef PCNET_DEBUG_CSR
   2.785 +    printf("pcnet_csr_readw rap=%d val=0x%04x\n", rap, val);
   2.786 +#endif
   2.787 +    return val;
   2.788 +}
   2.789 +
   2.790 +static void pcnet_bcr_writew(PCNetState *s, uint32_t rap, uint32_t val)
   2.791 +{
   2.792 +    rap &= 127;
   2.793 +#ifdef PCNET_DEBUG_BCR
   2.794 +    printf("pcnet_bcr_writew rap=%d val=0x%04x\n", rap, val);
   2.795 +#endif
   2.796 +    switch (rap) {
   2.797 +    case BCR_SWS:
   2.798 +        if (!(CSR_STOP(s) || CSR_SPND(s)))
   2.799 +            return;
   2.800 +        val &= ~0x0300;
   2.801 +        switch (val & 0x00ff) {
   2.802 +        case 0:
   2.803 +            val |= 0x0200;
   2.804 +            break;
   2.805 +        case 1:
   2.806 +            val |= 0x0100;
   2.807 +            break;
   2.808 +        case 2:
   2.809 +        case 3:
   2.810 +            val |= 0x0300;
   2.811 +            break;
   2.812 +        default:
   2.813 +            printf("Bad SWSTYLE=0x%02x\n", val & 0xff);
   2.814 +            val = 0x0200;
   2.815 +            break;
   2.816 +        }
   2.817 +#ifdef PCNET_DEBUG
   2.818 +       printf("BCR_SWS=0x%04x\n", val);
   2.819 +#endif
   2.820 +    case BCR_LNKST:
   2.821 +    case BCR_LED1:
   2.822 +    case BCR_LED2:
   2.823 +    case BCR_LED3:
   2.824 +    case BCR_MC:
   2.825 +    case BCR_FDC:
   2.826 +    case BCR_BSBC:
   2.827 +    case BCR_EECAS:
   2.828 +    case BCR_PLAT:
   2.829 +        s->bcr[rap] = val;
   2.830 +        break;
   2.831 +    default:
   2.832 +        break;
   2.833 +    }
   2.834 +}
   2.835 +
   2.836 +static uint32_t pcnet_bcr_readw(PCNetState *s, uint32_t rap)
   2.837 +{
   2.838 +    uint32_t val;
   2.839 +    rap &= 127;
   2.840 +    switch (rap) {
   2.841 +    case BCR_LNKST:
   2.842 +    case BCR_LED1:
   2.843 +    case BCR_LED2:
   2.844 +    case BCR_LED3:
   2.845 +        val = s->bcr[rap] & ~0x8000;
   2.846 +        val |= (val & 0x017f & s->lnkst) ? 0x8000 : 0;
   2.847 +        break;
   2.848 +    default:
   2.849 +        val = rap < 32 ? s->bcr[rap] : 0;
   2.850 +        break;
   2.851 +    }
   2.852 +#ifdef PCNET_DEBUG_BCR
   2.853 +    printf("pcnet_bcr_readw rap=%d val=0x%04x\n", rap, val);
   2.854 +#endif
   2.855 +    return val;
   2.856 +}
   2.857 +
   2.858 +static void pcnet_h_reset(PCNetState *s)
   2.859 +{
   2.860 +    int i;
   2.861 +    uint16_t checksum;
   2.862 +
   2.863 +    /* Initialize the PROM */
   2.864 +
   2.865 +    memcpy(s->prom, s->nd->macaddr, 6);
   2.866 +    s->prom[12] = s->prom[13] = 0x00;
   2.867 +    s->prom[14] = s->prom[15] = 0x57;
   2.868 +
   2.869 +    for (i = 0,checksum = 0; i < 16; i++)
   2.870 +        checksum += s->prom[i];
   2.871 +    *(uint16_t *)&s->prom[12] = cpu_to_le16(checksum);
   2.872 +
   2.873 +
   2.874 +    s->bcr[BCR_MSRDA] = 0x0005;
   2.875 +    s->bcr[BCR_MSWRA] = 0x0005;
   2.876 +    s->bcr[BCR_MC   ] = 0x0002;
   2.877 +    s->bcr[BCR_LNKST] = 0x00c0;
   2.878 +    s->bcr[BCR_LED1 ] = 0x0084;
   2.879 +    s->bcr[BCR_LED2 ] = 0x0088;
   2.880 +    s->bcr[BCR_LED3 ] = 0x0090;
   2.881 +    s->bcr[BCR_FDC  ] = 0x0000;
   2.882 +    s->bcr[BCR_BSBC ] = 0x9001;
   2.883 +    s->bcr[BCR_EECAS] = 0x0002;
   2.884 +    s->bcr[BCR_SWS  ] = 0x0200;
   2.885 +    s->bcr[BCR_PLAT ] = 0xff06;
   2.886 +
   2.887 +    pcnet_s_reset(s);
   2.888 +}
   2.889 +
   2.890 +static void pcnet_aprom_writeb(void *opaque, uint32_t addr, uint32_t val)
   2.891 +{
   2.892 +    PCNetState *s = opaque;
   2.893 +#ifdef PCNET_DEBUG
   2.894 +    printf("pcnet_aprom_writeb addr=0x%08x val=0x%02x\n", addr, val);
   2.895 +#endif    
   2.896 +    /* Check APROMWE bit to enable write access */
   2.897 +    if (pcnet_bcr_readw(s,2) & 0x80)
   2.898 +        s->prom[addr & 15] = val;
   2.899 +}       
   2.900 +
   2.901 +static uint32_t pcnet_aprom_readb(void *opaque, uint32_t addr)
   2.902 +{
   2.903 +    PCNetState *s = opaque;
   2.904 +    uint32_t val = s->prom[addr &= 15];
   2.905 +#ifdef PCNET_DEBUG
   2.906 +    printf("pcnet_aprom_readb addr=0x%08x val=0x%02x\n", addr, val);
   2.907 +#endif
   2.908 +    return val;
   2.909 +}
   2.910 +
   2.911 +static void pcnet_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
   2.912 +{
   2.913 +    PCNetState *s = opaque;
   2.914 +    pcnet_poll_timer(s);
   2.915 +#ifdef PCNET_DEBUG_IO
   2.916 +    printf("pcnet_ioport_writew addr=0x%08x val=0x%04x\n", addr, val);
   2.917 +#endif
   2.918 +    if (!BCR_DWIO(s)) {
   2.919 +        switch (addr & 0x0f) {
   2.920 +        case 0x00: /* RDP */
   2.921 +            pcnet_csr_writew(s, s->rap, val);
   2.922 +            break;
   2.923 +        case 0x02:
   2.924 +            s->rap = val & 0x7f;
   2.925 +            break;
   2.926 +        case 0x06:
   2.927 +            pcnet_bcr_writew(s, s->rap, val);
   2.928 +            break;
   2.929 +        }
   2.930 +    }
   2.931 +    pcnet_update_irq(s);
   2.932 +}
   2.933 +
   2.934 +static uint32_t pcnet_ioport_readw(void *opaque, uint32_t addr)
   2.935 +{
   2.936 +    PCNetState *s = opaque;
   2.937 +    uint32_t val = -1;
   2.938 +    pcnet_poll_timer(s);
   2.939 +    if (!BCR_DWIO(s)) {
   2.940 +        switch (addr & 0x0f) {
   2.941 +        case 0x00: /* RDP */
   2.942 +            val = pcnet_csr_readw(s, s->rap);
   2.943 +            break;
   2.944 +        case 0x02:
   2.945 +            val = s->rap;
   2.946 +            break;
   2.947 +        case 0x04:
   2.948 +            pcnet_s_reset(s);
   2.949 +            val = 0;
   2.950 +            break;
   2.951 +        case 0x06:
   2.952 +            val = pcnet_bcr_readw(s, s->rap);
   2.953 +            break;
   2.954 +        }
   2.955 +    }
   2.956 +    pcnet_update_irq(s);
   2.957 +#ifdef PCNET_DEBUG_IO
   2.958 +    printf("pcnet_ioport_readw addr=0x%08x val=0x%04x\n", addr, val & 0xffff);
   2.959 +#endif
   2.960 +    return val;
   2.961 +}
   2.962 +
   2.963 +static void pcnet_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
   2.964 +{
   2.965 +    PCNetState *s = opaque;
   2.966 +    pcnet_poll_timer(s);
   2.967 +#ifdef PCNET_DEBUG_IO
   2.968 +    printf("pcnet_ioport_writel addr=0x%08x val=0x%08x\n", addr, val);
   2.969 +#endif
   2.970 +    if (BCR_DWIO(s)) {
   2.971 +        switch (addr & 0x0f) {
   2.972 +        case 0x00: /* RDP */
   2.973 +            pcnet_csr_writew(s, s->rap, val & 0xffff);
   2.974 +            break;
   2.975 +        case 0x04:
   2.976 +            s->rap = val & 0x7f;
   2.977 +            break;
   2.978 +        case 0x0c:
   2.979 +            pcnet_bcr_writew(s, s->rap, val & 0xffff);
   2.980 +            break;
   2.981 +        }
   2.982 +    } else
   2.983 +    if ((addr & 0x0f) == 0) {
   2.984 +        /* switch device to dword i/o mode */
   2.985 +        pcnet_bcr_writew(s, BCR_BSBC, pcnet_bcr_readw(s, BCR_BSBC) | 0x0080);
   2.986 +#ifdef PCNET_DEBUG_IO
   2.987 +        printf("device switched into dword i/o mode\n");
   2.988 +#endif        
   2.989 +    }
   2.990 +    pcnet_update_irq(s);
   2.991 +}
   2.992 +
   2.993 +static uint32_t pcnet_ioport_readl(void *opaque, uint32_t addr)
   2.994 +{
   2.995 +    PCNetState *s = opaque;
   2.996 +    uint32_t val = -1;
   2.997 +    pcnet_poll_timer(s);
   2.998 +    if (BCR_DWIO(s)) {  
   2.999 +        switch (addr & 0x0f) {
  2.1000 +        case 0x00: /* RDP */
  2.1001 +            val = pcnet_csr_readw(s, s->rap);
  2.1002 +            break;
  2.1003 +        case 0x04:
  2.1004 +            val = s->rap;
  2.1005 +            break;
  2.1006 +        case 0x08:
  2.1007 +            pcnet_s_reset(s);
  2.1008 +            val = 0;
  2.1009 +            break;
  2.1010 +        case 0x0c:
  2.1011 +            val = pcnet_bcr_readw(s, s->rap);
  2.1012 +            break;
  2.1013 +        }
  2.1014 +    }
  2.1015 +    pcnet_update_irq(s);
  2.1016 +#ifdef PCNET_DEBUG_IO
  2.1017 +    printf("pcnet_ioport_readl addr=0x%08x val=0x%08x\n", addr, val);
  2.1018 +#endif
  2.1019 +    return val;
  2.1020 +}
  2.1021 +
  2.1022 +static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num, 
  2.1023 +                             uint32_t addr, uint32_t size, int type)
  2.1024 +{
  2.1025 +    PCNetState *d = (PCNetState *)pci_dev;
  2.1026 +
  2.1027 +#ifdef PCNET_DEBUG_IO
  2.1028 +    printf("pcnet_ioport_map addr=0x%04x size=0x%04x\n", addr, size);
  2.1029 +#endif
  2.1030 +
  2.1031 +    register_ioport_write(addr, 16, 1, pcnet_aprom_writeb, d);
  2.1032 +    register_ioport_read(addr, 16, 1, pcnet_aprom_readb, d);
  2.1033 +    
  2.1034 +    register_ioport_write(addr + 0x10, 0x10, 2, pcnet_ioport_writew, d);
  2.1035 +    register_ioport_read(addr + 0x10, 0x10, 2, pcnet_ioport_readw, d);
  2.1036 +    register_ioport_write(addr + 0x10, 0x10, 4, pcnet_ioport_writel, d);
  2.1037 +    register_ioport_read(addr + 0x10, 0x10, 4, pcnet_ioport_readl, d);
  2.1038 +}
  2.1039 +
  2.1040 +static void pcnet_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  2.1041 +{
  2.1042 +    PCNetState *d = opaque;
  2.1043 +#ifdef PCNET_DEBUG_IO
  2.1044 +    printf("pcnet_mmio_writeb addr=0x%08x val=0x%02x\n", addr, val);
  2.1045 +#endif
  2.1046 +    if (!(addr & 0x10))
  2.1047 +        pcnet_aprom_writeb(d, addr & 0x0f, val);
  2.1048 +}
  2.1049 +
  2.1050 +static uint32_t pcnet_mmio_readb(void *opaque, target_phys_addr_t addr) 
  2.1051 +{
  2.1052 +    PCNetState *d = opaque;
  2.1053 +    uint32_t val = -1;
  2.1054 +    if (!(addr & 0x10))
  2.1055 +        val = pcnet_aprom_readb(d, addr & 0x0f);
  2.1056 +#ifdef PCNET_DEBUG_IO
  2.1057 +    printf("pcnet_mmio_readb addr=0x%08x val=0x%02x\n", addr, val & 0xff);
  2.1058 +#endif
  2.1059 +    return val;
  2.1060 +}
  2.1061 +
  2.1062 +static void pcnet_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
  2.1063 +{
  2.1064 +    PCNetState *d = opaque;
  2.1065 +#ifdef PCNET_DEBUG_IO
  2.1066 +    printf("pcnet_mmio_writew addr=0x%08x val=0x%04x\n", addr, val);
  2.1067 +#endif
  2.1068 +    if (addr & 0x10)
  2.1069 +        pcnet_ioport_writew(d, addr & 0x0f, val);
  2.1070 +    else {
  2.1071 +        addr &= 0x0f;
  2.1072 +        pcnet_aprom_writeb(d, addr, val & 0xff);
  2.1073 +        pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
  2.1074 +    }
  2.1075 +}
  2.1076 +
  2.1077 +static uint32_t pcnet_mmio_readw(void *opaque, target_phys_addr_t addr) 
  2.1078 +{
  2.1079 +    PCNetState *d = opaque;
  2.1080 +    uint32_t val = -1;
  2.1081 +    if (addr & 0x10)
  2.1082 +        val = pcnet_ioport_readw(d, addr & 0x0f);
  2.1083 +    else {
  2.1084 +        addr &= 0x0f;
  2.1085 +        val = pcnet_aprom_readb(d, addr+1);
  2.1086 +        val <<= 8;
  2.1087 +        val |= pcnet_aprom_readb(d, addr);
  2.1088 +    }
  2.1089 +#ifdef PCNET_DEBUG_IO
  2.1090 +    printf("pcnet_mmio_readw addr=0x%08x val = 0x%04x\n", addr, val & 0xffff);
  2.1091 +#endif
  2.1092 +    return val;
  2.1093 +}
  2.1094 +
  2.1095 +static void pcnet_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  2.1096 +{
  2.1097 +    PCNetState *d = opaque;
  2.1098 +#ifdef PCNET_DEBUG_IO
  2.1099 +    printf("pcnet_mmio_writel addr=0x%08x val=0x%08x\n", addr, val);
  2.1100 +#endif
  2.1101 +    if (addr & 0x10)
  2.1102 +        pcnet_ioport_writel(d, addr & 0x0f, val);
  2.1103 +    else {
  2.1104 +        addr &= 0x0f;
  2.1105 +        pcnet_aprom_writeb(d, addr, val & 0xff);
  2.1106 +        pcnet_aprom_writeb(d, addr+1, (val & 0xff00) >> 8);
  2.1107 +        pcnet_aprom_writeb(d, addr+2, (val & 0xff0000) >> 16);
  2.1108 +        pcnet_aprom_writeb(d, addr+3, (val & 0xff000000) >> 24);
  2.1109 +    }
  2.1110 +}
  2.1111 +
  2.1112 +static uint32_t pcnet_mmio_readl(void *opaque, target_phys_addr_t addr) 
  2.1113 +{
  2.1114 +    PCNetState *d = opaque;
  2.1115 +    uint32_t val;
  2.1116 +    if (addr & 0x10)
  2.1117 +        val = pcnet_ioport_readl(d, addr & 0x0f);
  2.1118 +    else {
  2.1119 +        addr &= 0x0f;
  2.1120 +        val = pcnet_aprom_readb(d, addr+3);
  2.1121 +        val <<= 8;
  2.1122 +        val |= pcnet_aprom_readb(d, addr+2);
  2.1123 +        val <<= 8;
  2.1124 +        val |= pcnet_aprom_readb(d, addr+1);
  2.1125 +        val <<= 8;
  2.1126 +        val |= pcnet_aprom_readb(d, addr);
  2.1127 +    }
  2.1128 +#ifdef PCNET_DEBUG_IO
  2.1129 +    printf("pcnet_mmio_readl addr=0x%08x val=0x%08x\n", addr, val);
  2.1130 +#endif
  2.1131 +    return val;
  2.1132 +}
  2.1133 +
  2.1134 +
  2.1135 +static CPUWriteMemoryFunc *pcnet_mmio_write[] = {
  2.1136 +    (CPUWriteMemoryFunc *)&pcnet_mmio_writeb,
  2.1137 +    (CPUWriteMemoryFunc *)&pcnet_mmio_writew,
  2.1138 +    (CPUWriteMemoryFunc *)&pcnet_mmio_writel
  2.1139 +};
  2.1140 +
  2.1141 +static CPUReadMemoryFunc *pcnet_mmio_read[] = {
  2.1142 +    (CPUReadMemoryFunc *)&pcnet_mmio_readb,
  2.1143 +    (CPUReadMemoryFunc *)&pcnet_mmio_readw,
  2.1144 +    (CPUReadMemoryFunc *)&pcnet_mmio_readl
  2.1145 +};
  2.1146 +
  2.1147 +static void pcnet_mmio_map(PCIDevice *pci_dev, int region_num, 
  2.1148 +                            uint32_t addr, uint32_t size, int type)
  2.1149 +{
  2.1150 +    PCNetState *d = (PCNetState *)pci_dev;
  2.1151 +
  2.1152 +#ifdef PCNET_DEBUG_IO
  2.1153 +    printf("pcnet_ioport_map addr=0x%08x 0x%08x\n", addr, size);
  2.1154 +#endif
  2.1155 +
  2.1156 +    cpu_register_physical_memory(addr, PCNET_PNPMMIO_SIZE, d->mmio_io_addr);
  2.1157 +}
  2.1158 +
  2.1159 +void pci_pcnet_init(PCIBus *bus, NetDriverState *nd)
  2.1160 +{
  2.1161 +    PCNetState *d;
  2.1162 +    uint8_t *pci_conf;
  2.1163 +
  2.1164 +#if 0
  2.1165 +    printf("sizeof(RMD)=%d, sizeof(TMD)=%d\n", 
  2.1166 +        sizeof(struct pcnet_RMD), sizeof(struct pcnet_TMD));
  2.1167 +#endif
  2.1168 +
  2.1169 +    d = (PCNetState *)pci_register_device(bus, "PCNet", sizeof(PCNetState),
  2.1170 +                                          -1, NULL, NULL);
  2.1171 +                                          
  2.1172 +    pci_conf = d->dev.config;
  2.1173 +    
  2.1174 +    *(uint16_t *)&pci_conf[0x00] = cpu_to_le16(0x1022);
  2.1175 +    *(uint16_t *)&pci_conf[0x02] = cpu_to_le16(0x2000);    
  2.1176 +    *(uint16_t *)&pci_conf[0x04] = cpu_to_le16(0x0007); 
  2.1177 +    *(uint16_t *)&pci_conf[0x06] = cpu_to_le16(0x0280);
  2.1178 +    pci_conf[0x08] = 0x10;
  2.1179 +    pci_conf[0x09] = 0x00;
  2.1180 +    pci_conf[0x0a] = 0x00; // ethernet network controller 
  2.1181 +    pci_conf[0x0b] = 0x02;
  2.1182 +    pci_conf[0x0e] = 0x00; // header_type
  2.1183 +    
  2.1184 +    *(uint32_t *)&pci_conf[0x10] = cpu_to_le32(0x00000001);
  2.1185 +    *(uint32_t *)&pci_conf[0x14] = cpu_to_le32(0x00000000);
  2.1186 +    
  2.1187 +    pci_conf[0x3d] = 1; // interrupt pin 0
  2.1188 +    pci_conf[0x3e] = 0x06;
  2.1189 +    pci_conf[0x3f] = 0xff;
  2.1190 +
  2.1191 +    /* Handler for memory-mapped I/O */
  2.1192 +    d->mmio_io_addr =
  2.1193 +      cpu_register_io_memory(0, pcnet_mmio_read, pcnet_mmio_write, d);
  2.1194 +
  2.1195 +    pci_register_io_region((PCIDevice *)d, 0, PCNET_IOPORT_SIZE, 
  2.1196 +                           PCI_ADDRESS_SPACE_IO, pcnet_ioport_map);
  2.1197 +                           
  2.1198 +    pci_register_io_region((PCIDevice *)d, 1, PCNET_PNPMMIO_SIZE, 
  2.1199 +                           PCI_ADDRESS_SPACE_MEM, pcnet_mmio_map);
  2.1200 +                           
  2.1201 +    d->poll_timer = qemu_new_timer(vm_clock, pcnet_poll_timer, d);
  2.1202 +
  2.1203 +    d->nd = nd;
  2.1204 +
  2.1205 +    pcnet_h_reset(d);
  2.1206 +
  2.1207 +    qemu_add_read_packet(nd, pcnet_can_receive, pcnet_receive, d);
  2.1208 +}
     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/tools/ioemu/hw/pcnet.h	Tue Aug 16 13:39:55 2005 -0800
     3.3 @@ -0,0 +1,583 @@
     3.4 +/*
     3.5 + * QEMU AMD PC-Net II (Am79C970A) emulation
     3.6 + * 
     3.7 + * Copyright (c) 2004 Antony T Curtis
     3.8 + * 
     3.9 + * Permission is hereby granted, free of charge, to any person obtaining a copy
    3.10 + * of this software and associated documentation files (the "Software"), to deal
    3.11 + * in the Software without restriction, including without limitation the rights
    3.12 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    3.13 + * copies of the Software, and to permit persons to whom the Software is
    3.14 + * furnished to do so, subject to the following conditions:
    3.15 + *
    3.16 + * The above copyright notice and this permission notice shall be included in
    3.17 + * all copies or substantial portions of the Software.
    3.18 + *
    3.19 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    3.20 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    3.21 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
    3.22 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    3.23 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    3.24 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    3.25 + * THE SOFTWARE.
    3.26 + */
    3.27 +
    3.28 +/* This software was written to be compatible with the specification:
    3.29 + * AMD Am79C970A PCnet-PCI II Ethernet Controller Data-Sheet
    3.30 + * AMD Publication# 19436  Rev:E  Amendment/0  Issue Date: June 2000
    3.31 + */
    3.32 +
    3.33 +#ifdef __GNUC__
    3.34 +#define PACKED(A) A __attribute__ ((packed))
    3.35 +#else
    3.36 +#error FixMe
    3.37 +#endif
    3.38 +
    3.39 +/* BUS CONFIGURATION REGISTERS */
    3.40 +#define BCR_MSRDA    0
    3.41 +#define BCR_MSWRA    1
    3.42 +#define BCR_MC       2
    3.43 +#define BCR_LNKST    4
    3.44 +#define BCR_LED1     5
    3.45 +#define BCR_LED2     6
    3.46 +#define BCR_LED3     7
    3.47 +#define BCR_FDC      9
    3.48 +#define BCR_BSBC     18
    3.49 +#define BCR_EECAS    19
    3.50 +#define BCR_SWS      20
    3.51 +#define BCR_PLAT     22
    3.52 +
    3.53 +#define BCR_DWIO(S)      !!((S)->bcr[BCR_BSBC] & 0x0080)
    3.54 +#define BCR_SSIZE32(S)   !!((S)->bcr[BCR_SWS ] & 0x0100)
    3.55 +#define BCR_SWSTYLE(S)     ((S)->bcr[BCR_SWS ] & 0x00FF)
    3.56 +
    3.57 +#define CSR_INIT(S)      !!(((S)->csr[0])&0x0001)
    3.58 +#define CSR_STRT(S)      !!(((S)->csr[0])&0x0002)
    3.59 +#define CSR_STOP(S)      !!(((S)->csr[0])&0x0004)
    3.60 +#define CSR_TDMD(S)      !!(((S)->csr[0])&0x0008)
    3.61 +#define CSR_TXON(S)      !!(((S)->csr[0])&0x0010)
    3.62 +#define CSR_RXON(S)      !!(((S)->csr[0])&0x0020)
    3.63 +#define CSR_INEA(S)      !!(((S)->csr[0])&0x0040)
    3.64 +#define CSR_LAPPEN(S)    !!(((S)->csr[3])&0x0020)
    3.65 +#define CSR_DXSUFLO(S)   !!(((S)->csr[3])&0x0040)
    3.66 +#define CSR_ASTRP_RCV(S) !!(((S)->csr[4])&0x0800)
    3.67 +#define CSR_DPOLL(S)     !!(((S)->csr[4])&0x1000)
    3.68 +#define CSR_SPND(S)      !!(((S)->csr[5])&0x0001)
    3.69 +#define CSR_LTINTEN(S)   !!(((S)->csr[5])&0x4000)
    3.70 +#define CSR_TOKINTD(S)   !!(((S)->csr[5])&0x8000)
    3.71 +#define CSR_DRX(S)       !!(((S)->csr[15])&0x0001)
    3.72 +#define CSR_DTX(S)       !!(((S)->csr[15])&0x0002)
    3.73 +#define CSR_LOOP(S)      !!(((S)->csr[15])&0x0004)
    3.74 +#define CSR_DRCVPA(S)    !!(((S)->csr[15])&0x2000)
    3.75 +#define CSR_DRCVBC(S)    !!(((S)->csr[15])&0x4000)
    3.76 +#define CSR_PROM(S)      !!(((S)->csr[15])&0x8000)
    3.77 +
    3.78 +#define CSR_CRBC(S)      ((S)->csr[40])
    3.79 +#define CSR_CRST(S)      ((S)->csr[41])
    3.80 +#define CSR_CXBC(S)      ((S)->csr[42])
    3.81 +#define CSR_CXST(S)      ((S)->csr[43])
    3.82 +#define CSR_NRBC(S)      ((S)->csr[44])
    3.83 +#define CSR_NRST(S)      ((S)->csr[45])
    3.84 +#define CSR_POLL(S)      ((S)->csr[46])
    3.85 +#define CSR_PINT(S)      ((S)->csr[47])
    3.86 +#define CSR_RCVRC(S)     ((S)->csr[72])
    3.87 +#define CSR_XMTRC(S)     ((S)->csr[74])
    3.88 +#define CSR_RCVRL(S)     ((S)->csr[76])
    3.89 +#define CSR_XMTRL(S)     ((S)->csr[78])
    3.90 +#define CSR_MISSC(S)     ((S)->csr[112])
    3.91 +
    3.92 +#define CSR_IADR(S)      ((S)->csr[ 1] | ((S)->csr[ 2] << 16))
    3.93 +#define CSR_CRBA(S)      ((S)->csr[18] | ((S)->csr[19] << 16))
    3.94 +#define CSR_CXBA(S)      ((S)->csr[20] | ((S)->csr[21] << 16))
    3.95 +#define CSR_NRBA(S)      ((S)->csr[22] | ((S)->csr[23] << 16))
    3.96 +#define CSR_BADR(S)      ((S)->csr[24] | ((S)->csr[25] << 16))
    3.97 +#define CSR_NRDA(S)      ((S)->csr[26] | ((S)->csr[27] << 16))
    3.98 +#define CSR_CRDA(S)      ((S)->csr[28] | ((S)->csr[29] << 16))
    3.99 +#define CSR_BADX(S)      ((S)->csr[30] | ((S)->csr[31] << 16))
   3.100 +#define CSR_NXDA(S)      ((S)->csr[32] | ((S)->csr[33] << 16))
   3.101 +#define CSR_CXDA(S)      ((S)->csr[34] | ((S)->csr[35] << 16))
   3.102 +#define CSR_NNRD(S)      ((S)->csr[36] | ((S)->csr[37] << 16))
   3.103 +#define CSR_NNXD(S)      ((S)->csr[38] | ((S)->csr[39] << 16))
   3.104 +#define CSR_PXDA(S)      ((S)->csr[60] | ((S)->csr[61] << 16))
   3.105 +#define CSR_NXBA(S)      ((S)->csr[64] | ((S)->csr[65] << 16))
   3.106 +
   3.107 +#define PHYSADDR(S,A) \
   3.108 +  (BCR_SSIZE32(S) ? (A) : (A) | ((0xff00 & (uint32_t)(s)->csr[2])<<16))
   3.109 +
   3.110 +struct pcnet_initblk16 {
   3.111 +    uint16_t mode;
   3.112 +    uint16_t padr1;
   3.113 +    uint16_t padr2;
   3.114 +    uint16_t padr3;
   3.115 +    uint16_t ladrf1;
   3.116 +    uint16_t ladrf2;
   3.117 +    uint16_t ladrf3;
   3.118 +    uint16_t ladrf4;
   3.119 +    unsigned PACKED(rdra:24);
   3.120 +    unsigned PACKED(res1:5);
   3.121 +    unsigned PACKED(rlen:3);
   3.122 +    unsigned PACKED(tdra:24);
   3.123 +    unsigned PACKED(res2:5);
   3.124 +    unsigned PACKED(tlen:3);
   3.125 +};
   3.126 +
   3.127 +struct pcnet_initblk32 {
   3.128 +    uint16_t mode;
   3.129 +    unsigned PACKED(res1:4);
   3.130 +    unsigned PACKED(rlen:4);
   3.131 +    unsigned PACKED(res2:4);
   3.132 +    unsigned PACKED(tlen:4);
   3.133 +    uint16_t padr1;
   3.134 +    uint16_t padr2;
   3.135 +    uint16_t padr3;
   3.136 +    uint16_t _res;
   3.137 +    uint16_t ladrf1;
   3.138 +    uint16_t ladrf2;
   3.139 +    uint16_t ladrf3;
   3.140 +    uint16_t ladrf4;
   3.141 +    uint32_t rdra;
   3.142 +    uint32_t tdra;
   3.143 +};
   3.144 +
   3.145 +struct pcnet_TMD {
   3.146 +    struct {
   3.147 +        unsigned tbadr:32;
   3.148 +    } tmd0;
   3.149 +    struct {
   3.150 +        unsigned PACKED(bcnt:12), PACKED(ones:4), PACKED(res:7), PACKED(bpe:1);
   3.151 +        unsigned PACKED(enp:1), PACKED(stp:1), PACKED(def:1), PACKED(one:1);
   3.152 +        unsigned PACKED(ltint:1), PACKED(nofcs:1), PACKED(err:1), PACKED(own:1);
   3.153 +    } tmd1;
   3.154 +    struct {
   3.155 +        unsigned PACKED(trc:4), PACKED(res:12);
   3.156 +        unsigned PACKED(tdr:10), PACKED(rtry:1), PACKED(lcar:1);
   3.157 +        unsigned PACKED(lcol:1), PACKED(exdef:1), PACKED(uflo:1), PACKED(buff:1);
   3.158 +    } tmd2;
   3.159 +    struct {
   3.160 +        unsigned res:32;
   3.161 +    } tmd3;    
   3.162 +};
   3.163 +
   3.164 +struct pcnet_RMD {
   3.165 +    struct {
   3.166 +        unsigned rbadr:32;
   3.167 +    } rmd0;
   3.168 +    struct {
   3.169 +        unsigned PACKED(bcnt:12), PACKED(ones:4), PACKED(res:4);
   3.170 +        unsigned PACKED(bam:1), PACKED(lafm:1), PACKED(pam:1), PACKED(bpe:1);
   3.171 +        unsigned PACKED(enp:1), PACKED(stp:1), PACKED(buff:1), PACKED(crc:1);
   3.172 +        unsigned PACKED(oflo:1), PACKED(fram:1), PACKED(err:1), PACKED(own:1);
   3.173 +    } rmd1;
   3.174 +    struct {
   3.175 +        unsigned PACKED(mcnt:12), PACKED(zeros:4);
   3.176 +        unsigned PACKED(rpc:8), PACKED(rcc:8);
   3.177 +    } rmd2;    
   3.178 +    struct {
   3.179 +        unsigned res:32;
   3.180 +    } rmd3;    
   3.181 +};
   3.182 +
   3.183 +
   3.184 +#define PRINT_TMD(T) printf(    \
   3.185 +        "TMD0 : TBADR=0x%08x\n" \
   3.186 +        "TMD1 : OWN=%d, ERR=%d, FCS=%d, LTI=%d, "       \
   3.187 +        "ONE=%d, DEF=%d, STP=%d, ENP=%d,\n"             \
   3.188 +        "       BPE=%d, BCNT=%d\n"                      \
   3.189 +        "TMD2 : BUF=%d, UFL=%d, EXD=%d, LCO=%d, "       \
   3.190 +        "LCA=%d, RTR=%d,\n"                             \
   3.191 +        "       TDR=%d, TRC=%d\n",                      \
   3.192 +        (T)->tmd0.tbadr,                                \
   3.193 +        (T)->tmd1.own, (T)->tmd1.err, (T)->tmd1.nofcs,  \
   3.194 +        (T)->tmd1.ltint, (T)->tmd1.one, (T)->tmd1.def,  \
   3.195 +        (T)->tmd1.stp, (T)->tmd1.enp, (T)->tmd1.bpe,    \
   3.196 +        4096-(T)->tmd1.bcnt,                            \
   3.197 +        (T)->tmd2.buff, (T)->tmd2.uflo, (T)->tmd2.exdef,\
   3.198 +        (T)->tmd2.lcol, (T)->tmd2.lcar, (T)->tmd2.rtry, \
   3.199 +        (T)->tmd2.tdr, (T)->tmd2.trc)
   3.200 +
   3.201 +#define PRINT_RMD(R) printf(    \
   3.202 +        "RMD0 : RBADR=0x%08x\n" \
   3.203 +        "RMD1 : OWN=%d, ERR=%d, FRAM=%d, OFLO=%d, "     \
   3.204 +        "CRC=%d, BUFF=%d, STP=%d, ENP=%d,\n       "     \
   3.205 +        "BPE=%d, PAM=%d, LAFM=%d, BAM=%d, ONES=%d, BCNT=%d\n"    \
   3.206 +        "RMD2 : RCC=%d, RPC=%d, MCNT=%d, ZEROS=%d\n",   \
   3.207 +        (R)->rmd0.rbadr,                                \
   3.208 +        (R)->rmd1.own, (R)->rmd1.err, (R)->rmd1.fram,   \
   3.209 +        (R)->rmd1.oflo, (R)->rmd1.crc, (R)->rmd1.buff,  \
   3.210 +        (R)->rmd1.stp, (R)->rmd1.enp, (R)->rmd1.bpe,    \
   3.211 +        (R)->rmd1.pam, (R)->rmd1.lafm, (R)->rmd1.bam,   \
   3.212 +        (R)->rmd1.ones, 4096-(R)->rmd1.bcnt,            \
   3.213 +        (R)->rmd2.rcc, (R)->rmd2.rpc, (R)->rmd2.mcnt,   \
   3.214 +        (R)->rmd2.zeros)
   3.215 +
   3.216 +static inline void pcnet_tmd_load(PCNetState *s, struct pcnet_TMD *tmd, target_phys_addr_t addr)
   3.217 +{
   3.218 +    if (!BCR_SWSTYLE(s)) {
   3.219 +        uint16_t xda[4];
   3.220 +        cpu_physical_memory_read(addr,
   3.221 +                (void *)&xda[0], sizeof(xda));
   3.222 +        ((uint32_t *)tmd)[0] = (xda[0]&0xffff) |
   3.223 +                ((xda[1]&0x00ff) << 16);
   3.224 +        ((uint32_t *)tmd)[1] = (xda[2]&0xffff)|
   3.225 +                ((xda[1] & 0xff00) << 16);
   3.226 +        ((uint32_t *)tmd)[2] =
   3.227 +                (xda[3] & 0xffff) << 16;
   3.228 +        ((uint32_t *)tmd)[3] = 0;
   3.229 +    }
   3.230 +    else
   3.231 +    if (BCR_SWSTYLE(s) != 3)
   3.232 +        cpu_physical_memory_read(addr, (void *)tmd, 16);
   3.233 +    else {
   3.234 +        uint32_t xda[4];
   3.235 +        cpu_physical_memory_read(addr,
   3.236 +                (void *)&xda[0], sizeof(xda));
   3.237 +        ((uint32_t *)tmd)[0] = xda[2];
   3.238 +        ((uint32_t *)tmd)[1] = xda[1];
   3.239 +        ((uint32_t *)tmd)[2] = xda[0];
   3.240 +        ((uint32_t *)tmd)[3] = xda[3];
   3.241 +    }
   3.242 +}
   3.243 +
   3.244 +static inline void pcnet_tmd_store(PCNetState *s, struct pcnet_TMD *tmd, target_phys_addr_t addr)
   3.245 +{
   3.246 +    cpu_physical_memory_set_dirty(addr);
   3.247 +    if (!BCR_SWSTYLE(s)) {
   3.248 +        uint16_t xda[4];
   3.249 +        xda[0] = ((uint32_t *)tmd)[0] & 0xffff;
   3.250 +        xda[1] = ((((uint32_t *)tmd)[0]>>16)&0x00ff) |
   3.251 +            ((((uint32_t *)tmd)[1]>>16)&0xff00);
   3.252 +        xda[2] = ((uint32_t *)tmd)[1] & 0xffff;
   3.253 +        xda[3] = ((uint32_t *)tmd)[2] >> 16;
   3.254 +        cpu_physical_memory_write(addr,
   3.255 +                (void *)&xda[0], sizeof(xda));
   3.256 +        cpu_physical_memory_set_dirty(addr+7);
   3.257 +    }
   3.258 +    else {
   3.259 +        if (BCR_SWSTYLE(s) != 3)
   3.260 +            cpu_physical_memory_write(addr, (void *)tmd, 16);
   3.261 +        else {
   3.262 +            uint32_t xda[4];
   3.263 +            xda[0] = ((uint32_t *)tmd)[2];
   3.264 +            xda[1] = ((uint32_t *)tmd)[1];
   3.265 +            xda[2] = ((uint32_t *)tmd)[0];
   3.266 +            xda[3] = ((uint32_t *)tmd)[3];
   3.267 +            cpu_physical_memory_write(addr,
   3.268 +                    (void *)&xda[0], sizeof(xda));
   3.269 +        }
   3.270 +        cpu_physical_memory_set_dirty(addr+15);
   3.271 +    }
   3.272 +}
   3.273 +
   3.274 +static inline void pcnet_rmd_load(PCNetState *s, struct pcnet_RMD *rmd, target_phys_addr_t addr)
   3.275 +{
   3.276 +    if (!BCR_SWSTYLE(s)) {
   3.277 +        uint16_t rda[4];
   3.278 +        cpu_physical_memory_read(addr,
   3.279 +                (void *)&rda[0], sizeof(rda));
   3.280 +        ((uint32_t *)rmd)[0] = (rda[0]&0xffff)|
   3.281 +                ((rda[1] & 0x00ff) << 16);
   3.282 +        ((uint32_t *)rmd)[1] = (rda[2]&0xffff)|
   3.283 +                ((rda[1] & 0xff00) << 16);
   3.284 +        ((uint32_t *)rmd)[2] = rda[3] & 0xffff;
   3.285 +        ((uint32_t *)rmd)[3] = 0;
   3.286 +    }
   3.287 +    else
   3.288 +    if (BCR_SWSTYLE(s) != 3)
   3.289 +        cpu_physical_memory_read(addr, (void *)rmd, 16);
   3.290 +    else {
   3.291 +        uint32_t rda[4];
   3.292 +        cpu_physical_memory_read(addr,
   3.293 +                (void *)&rda[0], sizeof(rda));
   3.294 +        ((uint32_t *)rmd)[0] = rda[2];
   3.295 +        ((uint32_t *)rmd)[1] = rda[1];
   3.296 +        ((uint32_t *)rmd)[2] = rda[0];
   3.297 +        ((uint32_t *)rmd)[3] = rda[3];
   3.298 +    }
   3.299 +}
   3.300 +
   3.301 +static inline void pcnet_rmd_store(PCNetState *s, struct pcnet_RMD *rmd, target_phys_addr_t addr)
   3.302 +{
   3.303 +    cpu_physical_memory_set_dirty(addr);
   3.304 +    if (!BCR_SWSTYLE(s)) {
   3.305 +        uint16_t rda[4];                        \
   3.306 +        rda[0] = ((uint32_t *)rmd)[0] & 0xffff; \
   3.307 +        rda[1] = ((((uint32_t *)rmd)[0]>>16)&0xff)|\
   3.308 +            ((((uint32_t *)rmd)[1]>>16)&0xff00);\
   3.309 +        rda[2] = ((uint32_t *)rmd)[1] & 0xffff; \
   3.310 +        rda[3] = ((uint32_t *)rmd)[2] & 0xffff; \
   3.311 +        cpu_physical_memory_write(addr,         \
   3.312 +                (void *)&rda[0], sizeof(rda));  \
   3.313 +        cpu_physical_memory_set_dirty(addr+7);
   3.314 +    }
   3.315 +    else {
   3.316 +        if (BCR_SWSTYLE(s) != 3)
   3.317 +            cpu_physical_memory_write(addr, (void *)rmd, 16);
   3.318 +        else {
   3.319 +            uint32_t rda[4];
   3.320 +            rda[0] = ((uint32_t *)rmd)[2];
   3.321 +            rda[1] = ((uint32_t *)rmd)[1];
   3.322 +            rda[2] = ((uint32_t *)rmd)[0];
   3.323 +            rda[3] = ((uint32_t *)rmd)[3];
   3.324 +            cpu_physical_memory_write(addr,
   3.325 +                    (void *)&rda[0], sizeof(rda));
   3.326 +        }
   3.327 +        cpu_physical_memory_set_dirty(addr+15);
   3.328 +    }
   3.329 +}
   3.330 +
   3.331 +
   3.332 +#define TMDLOAD(TMD,ADDR) pcnet_tmd_load(s,TMD,ADDR)
   3.333 +
   3.334 +#define TMDSTORE(TMD,ADDR) pcnet_tmd_store(s,TMD,ADDR)
   3.335 +
   3.336 +#define RMDLOAD(RMD,ADDR) pcnet_rmd_load(s,RMD,ADDR)
   3.337 +
   3.338 +#define RMDSTORE(RMD,ADDR) pcnet_rmd_store(s,RMD,ADDR)
   3.339 +
   3.340 +#if 1
   3.341 +
   3.342 +#define CHECK_RMD(ADDR,RES) do {                \
   3.343 +    struct pcnet_RMD rmd;                       \
   3.344 +    RMDLOAD(&rmd,(ADDR));                       \
   3.345 +    (RES) |= (rmd.rmd1.ones != 15)              \
   3.346 +          || (rmd.rmd2.zeros != 0);             \
   3.347 +} while (0)
   3.348 +
   3.349 +#define CHECK_TMD(ADDR,RES) do {                \
   3.350 +    struct pcnet_TMD tmd;                       \
   3.351 +    TMDLOAD(&tmd,(ADDR));                       \
   3.352 +    (RES) |= (tmd.tmd1.ones != 15);             \
   3.353 +} while (0)
   3.354 +
   3.355 +#else
   3.356 +
   3.357 +#define CHECK_RMD(ADDR,RES) do {                \
   3.358 +    switch (BCR_SWSTYLE(s)) {                   \
   3.359 +    case 0x00:                                  \
   3.360 +        do {                                    \
   3.361 +            uint16_t rda[4];                    \
   3.362 +            cpu_physical_memory_read((ADDR),    \
   3.363 +                (void *)&rda[0], sizeof(rda));  \
   3.364 +            (RES) |= (rda[2] & 0xf000)!=0xf000; \
   3.365 +            (RES) |= (rda[3] & 0xf000)!=0x0000; \
   3.366 +        } while (0);                            \
   3.367 +        break;                                  \
   3.368 +    case 0x01:                                  \
   3.369 +    case 0x02:                                  \
   3.370 +        do {                                    \
   3.371 +            uint32_t rda[4];                    \
   3.372 +            cpu_physical_memory_read((ADDR),    \
   3.373 +                (void *)&rda[0], sizeof(rda)); \
   3.374 +            (RES) |= (rda[1] & 0x0000f000L)!=0x0000f000L; \
   3.375 +            (RES) |= (rda[2] & 0x0000f000L)!=0x00000000L; \
   3.376 +        } while (0);                            \
   3.377 +        break;                                  \
   3.378 +    case 0x03:                                  \
   3.379 +        do {                                    \
   3.380 +            uint32_t rda[4];                    \
   3.381 +            cpu_physical_memory_read((ADDR),    \
   3.382 +                (void *)&rda[0], sizeof(rda)); \
   3.383 +            (RES) |= (rda[0] & 0x0000f000L)!=0x00000000L; \
   3.384 +            (RES) |= (rda[1] & 0x0000f000L)!=0x0000f000L; \
   3.385 +        } while (0);                            \
   3.386 +        break;                                  \
   3.387 +    }                                           \
   3.388 +} while (0)
   3.389 +
   3.390 +#define CHECK_TMD(ADDR,RES) do {                \
   3.391 +    switch (BCR_SWSTYLE(s)) {                   \
   3.392 +    case 0x00:                                  \
   3.393 +        do {                                    \
   3.394 +            uint16_t xda[4];                    \
   3.395 +            cpu_physical_memory_read((ADDR),    \
   3.396 +                (void *)&xda[0], sizeof(xda));  \
   3.397 +            (RES) |= (xda[2] & 0xf000)!=0xf000;\
   3.398 +        } while (0);                            \
   3.399 +        break;                                  \
   3.400 +    case 0x01:                                  \
   3.401 +    case 0x02:                                  \
   3.402 +    case 0x03:                                  \
   3.403 +        do {                                    \
   3.404 +            uint32_t xda[4];                    \
   3.405 +            cpu_physical_memory_read((ADDR),    \
   3.406 +                (void *)&xda[0], sizeof(xda));  \
   3.407 +            (RES) |= (xda[1] & 0x0000f000L)!=0x0000f000L; \
   3.408 +        } while (0);                            \
   3.409 +        break;                                  \
   3.410 +    }                                           \
   3.411 +} while (0)
   3.412 +
   3.413 +#endif
   3.414 +
   3.415 +#define PRINT_PKTHDR(BUF) do {                  \
   3.416 +    struct ether_header *hdr = (void *)(BUF);   \
   3.417 +    printf("packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, "       \
   3.418 +           "shost=%02x:%02x:%02x:%02x:%02x:%02x, "              \
   3.419 +           "type=0x%04x (bcast=%d)\n",                          \
   3.420 +           hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2], \
   3.421 +           hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5], \
   3.422 +           hdr->ether_shost[0],hdr->ether_shost[1],hdr->ether_shost[2], \
   3.423 +           hdr->ether_shost[3],hdr->ether_shost[4],hdr->ether_shost[5], \
   3.424 +           htons(hdr->ether_type),                                      \
   3.425 +           !!ETHER_IS_MULTICAST(hdr->ether_dhost));                     \
   3.426 +} while (0)
   3.427 +
   3.428 +#define MULTICAST_FILTER_LEN 8
   3.429 +
   3.430 +static inline uint32_t lnc_mchash(const uint8_t *ether_addr)
   3.431 +{
   3.432 +#define LNC_POLYNOMIAL          0xEDB88320UL
   3.433 +    uint32_t crc = 0xFFFFFFFF;
   3.434 +    int idx, bit;
   3.435 +    uint8_t data;
   3.436 +
   3.437 +    for (idx = 0; idx < ETHER_ADDR_LEN; idx++) {
   3.438 +        for (data = *ether_addr++, bit = 0; bit < MULTICAST_FILTER_LEN; bit++) {
   3.439 +            crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LNC_POLYNOMIAL : 0);
   3.440 +            data >>= 1;
   3.441 +        }
   3.442 +    }
   3.443 +    return crc;
   3.444 +#undef LNC_POLYNOMIAL
   3.445 +}
   3.446 +
   3.447 +#define MIN(X,Y) ((X>Y) ? (Y) : (X))
   3.448 +
   3.449 +#define CRC(crc, ch)	 (crc = (crc >> 8) ^ crctab[(crc ^ (ch)) & 0xff])
   3.450 +
   3.451 +/* generated using the AUTODIN II polynomial
   3.452 + *	x^32 + x^26 + x^23 + x^22 + x^16 +
   3.453 + *	x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x^1 + 1
   3.454 + */
   3.455 +static const uint32_t crctab[256] = {
   3.456 +	0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
   3.457 +	0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
   3.458 +	0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
   3.459 +	0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
   3.460 +	0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
   3.461 +	0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
   3.462 +	0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
   3.463 +	0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
   3.464 +	0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
   3.465 +	0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
   3.466 +	0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
   3.467 +	0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
   3.468 +	0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
   3.469 +	0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
   3.470 +	0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
   3.471 +	0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
   3.472 +	0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
   3.473 +	0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
   3.474 +	0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
   3.475 +	0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
   3.476 +	0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
   3.477 +	0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
   3.478 +	0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
   3.479 +	0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
   3.480 +	0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
   3.481 +	0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
   3.482 +	0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
   3.483 +	0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
   3.484 +	0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
   3.485 +	0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
   3.486 +	0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
   3.487 +	0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
   3.488 +	0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
   3.489 +	0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
   3.490 +	0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
   3.491 +	0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
   3.492 +	0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
   3.493 +	0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
   3.494 +	0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
   3.495 +	0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
   3.496 +	0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
   3.497 +	0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
   3.498 +	0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
   3.499 +	0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
   3.500 +	0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
   3.501 +	0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
   3.502 +	0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
   3.503 +	0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
   3.504 +	0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
   3.505 +	0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
   3.506 +	0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
   3.507 +	0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
   3.508 +	0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
   3.509 +	0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
   3.510 +	0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
   3.511 +	0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
   3.512 +	0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
   3.513 +	0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
   3.514 +	0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
   3.515 +	0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
   3.516 +	0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
   3.517 +	0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
   3.518 +	0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
   3.519 +	0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d,
   3.520 +};
   3.521 +
   3.522 +static inline int padr_match(PCNetState *s, const uint8_t *buf, int size)
   3.523 +{
   3.524 +    struct ether_header *hdr = (void *)buf;
   3.525 +    uint8_t padr[6] = { 
   3.526 +        s->csr[12] & 0xff, s->csr[12] >> 8,
   3.527 +        s->csr[13] & 0xff, s->csr[13] >> 8,
   3.528 +        s->csr[14] & 0xff, s->csr[14] >> 8 
   3.529 +    };
   3.530 +    int result = (!CSR_DRCVPA(s)) && !bcmp(hdr->ether_dhost, padr, 6);
   3.531 +#ifdef PCNET_DEBUG_MATCH
   3.532 +    printf("packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, "
   3.533 +           "padr=%02x:%02x:%02x:%02x:%02x:%02x\n",
   3.534 +           hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2],
   3.535 +           hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5],
   3.536 +           padr[0],padr[1],padr[2],padr[3],padr[4],padr[5]);
   3.537 +    printf("padr_match result=%d\n", result);
   3.538 +#endif
   3.539 +    return result;
   3.540 +}
   3.541 +
   3.542 +static inline int padr_bcast(PCNetState *s, const uint8_t *buf, int size)
   3.543 +{
   3.544 +    static uint8_t BCAST[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
   3.545 +    struct ether_header *hdr = (void *)buf;
   3.546 +    int result = !CSR_DRCVBC(s) && !bcmp(hdr->ether_dhost, BCAST, 6);
   3.547 +#ifdef PCNET_DEBUG_MATCH
   3.548 +    printf("padr_bcast result=%d\n", result);
   3.549 +#endif
   3.550 +    return result;
   3.551 +}
   3.552 +
   3.553 +static inline int ladr_match(PCNetState *s, const uint8_t *buf, int size)
   3.554 +{
   3.555 +    struct ether_header *hdr = (void *)buf;
   3.556 +    if ((*(hdr->ether_dhost)&0x01) && 
   3.557 +        ((uint64_t *)&s->csr[8])[0] != 0LL) {
   3.558 +        uint8_t ladr[8] = { 
   3.559 +            s->csr[8] & 0xff, s->csr[8] >> 8,
   3.560 +            s->csr[9] & 0xff, s->csr[9] >> 8,
   3.561 +            s->csr[10] & 0xff, s->csr[10] >> 8, 
   3.562 +            s->csr[11] & 0xff, s->csr[11] >> 8 
   3.563 +        };
   3.564 +        int index = lnc_mchash(hdr->ether_dhost) >> 26;
   3.565 +        return !!(ladr[index >> 3] & (1 << (index & 7)));
   3.566 +    }
   3.567 +    return 0;
   3.568 +}
   3.569 +
   3.570 +static inline target_phys_addr_t pcnet_rdra_addr(PCNetState *s, int idx) 
   3.571 +{
   3.572 +    while (idx < 1) idx += CSR_RCVRL(s);
   3.573 +    return s->rdra + ((CSR_RCVRL(s) - idx) * (BCR_SWSTYLE(s) ? 16 : 8));
   3.574 +}
   3.575 +
   3.576 +static inline int64_t pcnet_get_next_poll_time(PCNetState *s, int64_t current_time)
   3.577 +{
   3.578 +    int64_t next_time = current_time + 
   3.579 +        muldiv64(65536 - (CSR_SPND(s) ? 0 : CSR_POLL(s)), 
   3.580 +                 ticks_per_sec, 33000000L);
   3.581 +    if (next_time <= current_time)
   3.582 +        next_time = current_time + 1;
   3.583 +    return next_time;
   3.584 +}
   3.585 +
   3.586 +
     4.1 --- a/tools/ioemu/target-i386-dm/Makefile	Tue Aug 16 10:09:07 2005 -0800
     4.2 +++ b/tools/ioemu/target-i386-dm/Makefile	Tue Aug 16 13:39:55 2005 -0800
     4.3 @@ -272,7 +272,7 @@ endif
     4.4  # Hardware support
     4.5  VL_OBJS+= ide.o ne2000.o pckbd.o vga.o dma.o
     4.6  VL_OBJS+= fdc.o mc146818rtc.o serial.o i8259.o i8254.o pc.o port-e9.o
     4.7 -VL_OBJS+= cirrus_vga.o
     4.8 +VL_OBJS+= cirrus_vga.o pcnet.o
     4.9  
    4.10  ifeq ($(TARGET_ARCH), ppc)
    4.11  VL_OBJS+= ppc.o ide.o ne2000.o pckbd.o vga.o $(SOUND_HW) dma.o $(AUDIODRV)
     5.1 --- a/tools/ioemu/vl.c	Tue Aug 16 10:09:07 2005 -0800
     5.2 +++ b/tools/ioemu/vl.c	Tue Aug 16 13:39:55 2005 -0800
     5.3 @@ -125,6 +125,7 @@ QEMUTimer *gui_timer;
     5.4  QEMUTimer *polling_timer;
     5.5  int vm_running;
     5.6  int audio_enabled = 0;
     5.7 +int nic_pcnet = 1;
     5.8  int sb16_enabled = 1;
     5.9  int adlib_enabled = 1;
    5.10  int gus_enabled = 1;
    5.11 @@ -2115,6 +2116,7 @@ void help(void)
    5.12             "-prep           Simulate a PREP system (default is PowerMAC)\n"
    5.13             "-g WxH[xDEPTH]  Set the initial VGA graphic mode\n"
    5.14  #endif
    5.15 +           "-nic-pcnet     simulate an AMD PC-Net PCI ethernet adaptor\n"
    5.16             "\n"
    5.17             "Network options:\n"
    5.18             "-nics n         simulate 'n' network cards [default=1]\n"
    5.19 @@ -2229,6 +2231,7 @@ enum {
    5.20      QEMU_OPTION_L,
    5.21      QEMU_OPTION_no_code_copy,
    5.22      QEMU_OPTION_pci,
    5.23 +    QEMU_OPTION_nic_pcnet,
    5.24      QEMU_OPTION_isa,
    5.25      QEMU_OPTION_prep,
    5.26      QEMU_OPTION_k,
    5.27 @@ -2313,6 +2316,7 @@ const QEMUOption qemu_options[] = {
    5.28      
    5.29      /* temporary options */
    5.30      { "pci", 0, QEMU_OPTION_pci },
    5.31 +    { "nic-pcnet", 0, QEMU_OPTION_nic_pcnet },
    5.32      { "cirrusvga", 0, QEMU_OPTION_cirrusvga },
    5.33      { NULL },
    5.34  };
    5.35 @@ -2640,6 +2644,9 @@ int main(int argc, char **argv)
    5.36              case QEMU_OPTION_pci:
    5.37                  pci_enabled = 1;
    5.38                  break;
    5.39 +            case QEMU_OPTION_nic_pcnet:
    5.40 +                nic_pcnet = 1;
    5.41 +                break;
    5.42              case QEMU_OPTION_isa:
    5.43                  pci_enabled = 0;
    5.44                  break;
     6.1 --- a/tools/ioemu/vl.h	Tue Aug 16 10:09:07 2005 -0800
     6.2 +++ b/tools/ioemu/vl.h	Tue Aug 16 13:39:55 2005 -0800
     6.3 @@ -600,6 +600,12 @@ int fdctrl_get_drive_type(fdctrl_t *fdct
     6.4  void isa_ne2000_init(int base, int irq, NetDriverState *nd);
     6.5  void pci_ne2000_init(PCIBus *bus, NetDriverState *nd);
     6.6  
     6.7 +/* pcnet.c */
     6.8 +
     6.9 +extern int nic_pcnet;
    6.10 +
    6.11 +void pci_pcnet_init(PCIBus *bus, NetDriverState *nd);
    6.12 +
    6.13  /* pckbd.c */
    6.14  
    6.15  void kbd_init(void);