direct-io.hg

changeset 8369:dc8122d90670

Fix the issue when guest OS clear TS bit by mov to cr0 instead of
clts instruction for floating point context save and restore.
clts instruction is already handled in vmx exit handler while
vmx_set_cr0 has not handled it yet.

Signed-off-by: Xiaofeng Ling <xiaofeng.ling@intel.com>
author kaf24@firebug.cl.cam.ac.uk
date Wed Dec 14 19:47:16 2005 +0100 (2005-12-14)
parents 50640456147b
children 237b2a4d2499
files xen/arch/x86/vmx.c
line diff
     1.1 --- a/xen/arch/x86/vmx.c	Wed Dec 14 19:44:42 2005 +0100
     1.2 +++ b/xen/arch/x86/vmx.c	Wed Dec 14 19:47:16 2005 +0100
     1.3 @@ -1094,11 +1094,21 @@ static int vmx_set_cr0(unsigned long val
     1.4      unsigned long eip;
     1.5      int paging_enabled;
     1.6      unsigned long vm_entry_value;
     1.7 +    unsigned long old_cr0;
     1.8  
     1.9      /*
    1.10       * CR0: We don't want to lose PE and PG.
    1.11       */
    1.12 -    paging_enabled = vmx_paging_enabled(v);
    1.13 +    __vmread_vcpu(v, CR0_READ_SHADOW, &old_cr0);
    1.14 +    paging_enabled = (old_cr0 & X86_CR0_PE) && (old_cr0 & X86_CR0_PG);
    1.15 +    /* If OS don't use clts to clear TS bit...*/
    1.16 +    if((old_cr0 & X86_CR0_TS) && !(value & X86_CR0_TS))
    1.17 +    {
    1.18 +            clts();
    1.19 +            setup_fpu(v);
    1.20 +    }
    1.21 +
    1.22 +
    1.23      __vmwrite(GUEST_CR0, value | X86_CR0_PE | X86_CR0_PG | X86_CR0_NE);
    1.24      __vmwrite(CR0_READ_SHADOW, value);
    1.25