direct-io.hg

changeset 5605:da2752f150a0

bitkeeper revision 1.1771 (42c314a41N8GOY476cnW9IejbgNDJw)

Merge bk://xen.bkbits.net/xeno-unstable.bk
into bkbits.net:/repos/x/xen-ia64/xeno-unstable-ia64.bk
author xen-ia64.adm@bkbits.net
date Wed Jun 29 21:37:40 2005 +0000 (2005-06-29)
parents f66a730a2c3d 2d8651ec10b9
children 6a65fe0f84c8
files xen/arch/ia64/asm-offsets.c xen/arch/ia64/domain.c xen/arch/ia64/grant_table.c xen/arch/ia64/hypercall.c xen/arch/ia64/hyperprivop.S xen/arch/ia64/ivt.S xen/arch/ia64/privop.c xen/arch/ia64/process.c xen/include/asm-ia64/xensystem.h
line diff
     1.1 --- a/xen/arch/ia64/asm-offsets.c	Wed Jun 29 17:12:12 2005 +0000
     1.2 +++ b/xen/arch/ia64/asm-offsets.c	Wed Jun 29 21:37:40 2005 +0000
     1.3 @@ -88,6 +88,7 @@ void foo(void)
     1.4  
     1.5  	BLANK();
     1.6  	DEFINE(IA64_CPUINFO_ITM_NEXT_OFFSET, offsetof (struct cpuinfo_ia64, itm_next));
     1.7 +	DEFINE(IA64_CPUINFO_PGD_QUICK_OFFSET, offsetof (struct cpuinfo_ia64, pgd_quick));
     1.8  
     1.9  	//DEFINE(IA64_SIGHAND_SIGLOCK_OFFSET,offsetof (struct sighand_struct, siglock));
    1.10  
     2.1 --- a/xen/arch/ia64/domain.c	Wed Jun 29 17:12:12 2005 +0000
     2.2 +++ b/xen/arch/ia64/domain.c	Wed Jun 29 21:37:40 2005 +0000
     2.3 @@ -50,7 +50,7 @@ unsigned long dom0_size = 512*1024*1024;
     2.4  //FIXME: alignment should be 256MB, lest Linux use a 256MB page size
     2.5  unsigned long dom0_align = 256*1024*1024;
     2.6  #else // CONFIG_VTI
     2.7 -unsigned long dom0_size = 256*1024*1024; //FIXME: Should be configurable
     2.8 +unsigned long dom0_size = 512*1024*1024; //FIXME: Should be configurable
     2.9  //FIXME: alignment should be 256MB, lest Linux use a 256MB page size
    2.10  unsigned long dom0_align = 64*1024*1024;
    2.11  #endif // CONFIG_VTI
    2.12 @@ -465,10 +465,44 @@ if (unlikely(page_to_phys(p) > vhpt_padd
    2.13  		set_pte(pte, pfn_pte(page_to_phys(p) >> PAGE_SHIFT,
    2.14  			__pgprot(__DIRTY_BITS | _PAGE_PL_2 | _PAGE_AR_RWX)));
    2.15  	}
    2.16 -	else printk("map_new_domain_page: page %p already mapped!\n",p);
    2.17 +	else printk("map_new_domain_page: mpaddr %lx already mapped!\n",mpaddr);
    2.18  	return p;
    2.19  }
    2.20  
    2.21 +/* map a physical address to the specified metaphysical addr */
    2.22 +void map_domain_page(struct domain *d, unsigned long mpaddr, unsigned long physaddr)
    2.23 +{
    2.24 +	struct mm_struct *mm = d->arch.mm;
    2.25 +	pgd_t *pgd;
    2.26 +	pud_t *pud;
    2.27 +	pmd_t *pmd;
    2.28 +	pte_t *pte;
    2.29 +
    2.30 +	if (!mm->pgd) {
    2.31 +		printk("map_domain_page: domain pgd must exist!\n");
    2.32 +		return;
    2.33 +	}
    2.34 +	pgd = pgd_offset(mm,mpaddr);
    2.35 +	if (pgd_none(*pgd))
    2.36 +		pgd_populate(mm, pgd, pud_alloc_one(mm,mpaddr));
    2.37 +
    2.38 +	pud = pud_offset(pgd, mpaddr);
    2.39 +	if (pud_none(*pud))
    2.40 +		pud_populate(mm, pud, pmd_alloc_one(mm,mpaddr));
    2.41 +
    2.42 +	pmd = pmd_offset(pud, mpaddr);
    2.43 +	if (pmd_none(*pmd))
    2.44 +		pmd_populate_kernel(mm, pmd, pte_alloc_one_kernel(mm,mpaddr));
    2.45 +//		pmd_populate(mm, pmd, pte_alloc_one(mm,mpaddr));
    2.46 +
    2.47 +	pte = pte_offset_map(pmd, mpaddr);
    2.48 +	if (pte_none(*pte)) {
    2.49 +		set_pte(pte, pfn_pte(physaddr >> PAGE_SHIFT,
    2.50 +			__pgprot(__DIRTY_BITS | _PAGE_PL_2 | _PAGE_AR_RWX)));
    2.51 +	}
    2.52 +	else printk("map_domain_page: mpaddr %lx already mapped!\n",mpaddr);
    2.53 +}
    2.54 +
    2.55  void mpafoo(unsigned long mpaddr)
    2.56  {
    2.57  	extern unsigned long privop_trace;
     3.1 --- a/xen/arch/ia64/grant_table.c	Wed Jun 29 17:12:12 2005 +0000
     3.2 +++ b/xen/arch/ia64/grant_table.c	Wed Jun 29 21:37:40 2005 +0000
     3.3 @@ -570,13 +570,13 @@ static int
     3.4          /* Frame is now unmapped for device access. */
     3.5      }
     3.6  
     3.7 -#ifdef __ia64__
     3.8 -// FIXME-ia64: any error checking need to be done here?
     3.9 -#else
    3.10      if ( (virt != 0) &&
    3.11           (flags & GNTMAP_host_map) &&
    3.12           ((act->pin & (GNTPIN_hstw_mask | GNTPIN_hstr_mask)) > 0))
    3.13      {
    3.14 +#ifdef __ia64__
    3.15 +// FIXME-ia64: any error checking need to be done here?
    3.16 +#else
    3.17          l1_pgentry_t   *pl1e;
    3.18          unsigned long   _ol1e;
    3.19  
    3.20 @@ -609,6 +609,7 @@ static int
    3.21              rc = -EINVAL;
    3.22              goto unmap_out;
    3.23          }
    3.24 +#endif
    3.25  
    3.26          map->ref_and_flags &= ~GNTMAP_host_map;
    3.27  
    3.28 @@ -627,7 +628,6 @@ static int
    3.29          rc = 0;
    3.30          *va = virt;
    3.31      }
    3.32 -#endif
    3.33  
    3.34      if ( (map->ref_and_flags & (GNTMAP_device_map|GNTMAP_host_map)) == 0)
    3.35      {
    3.36 @@ -696,6 +696,7 @@ gnttab_setup_table(
    3.37      gnttab_setup_table_t  op;
    3.38      struct domain        *d;
    3.39      int                   i;
    3.40 +    unsigned long addr;
    3.41  
    3.42      if ( count != 1 )
    3.43          return -EINVAL;
    3.44 @@ -735,10 +736,24 @@ gnttab_setup_table(
    3.45      {
    3.46          ASSERT(d->grant_table != NULL);
    3.47          (void)put_user(GNTST_okay, &uop->status);
    3.48 +#ifdef __ia64__
    3.49 +	if (d == dom0) {
    3.50 +            for ( i = 0; i < op.nr_frames; i++ )
    3.51 +                (void)put_user(
    3.52 +                    (virt_to_phys(d->grant_table->shared) >> PAGE_SHIFT) + i,
    3.53 +                    &uop->frame_list[i]);
    3.54 +	} else {
    3.55 +            /* IA64 hack - need to map it somewhere */
    3.56 +            addr = (1UL << 40);
    3.57 +            map_domain_page(d, addr, virt_to_phys(d->grant_table->shared));
    3.58 +            (void)put_user(addr >> PAGE_SHIFT, &uop->frame_list[0]);
    3.59 +        }
    3.60 +#else
    3.61          for ( i = 0; i < op.nr_frames; i++ )
    3.62              (void)put_user(
    3.63                  (virt_to_phys(d->grant_table->shared) >> PAGE_SHIFT) + i,
    3.64                  &uop->frame_list[i]);
    3.65 +#endif
    3.66      }
    3.67  
    3.68      put_domain(d);
     4.1 --- a/xen/arch/ia64/hypercall.c	Wed Jun 29 17:12:12 2005 +0000
     4.2 +++ b/xen/arch/ia64/hypercall.c	Wed Jun 29 21:37:40 2005 +0000
     4.3 @@ -43,7 +43,8 @@ ia64_hypercall (struct pt_regs *regs)
     4.4  #if 1
     4.5  #define SPURIOUS_VECTOR 15
     4.6  			if (vcpu_check_pending_interrupts(v)!=SPURIOUS_VECTOR) {
     4.7 -//printf("Domain trying to go idle when interrupt pending!\n");
     4.8 +//				int pi = vcpu_check_pending_interrupts(v);
     4.9 +//printf("idle w/int#%d pending!\n",pi);
    4.10  //this shouldn't happen, but it apparently does quite a bit!  so don't
    4.11  //allow it to happen... i.e. if a domain has an interrupt pending and
    4.12  //it tries to halt itself because it thinks it is idle, just return here
     5.1 --- a/xen/arch/ia64/hyperprivop.S	Wed Jun 29 17:12:12 2005 +0000
     5.2 +++ b/xen/arch/ia64/hyperprivop.S	Wed Jun 29 21:37:40 2005 +0000
     5.3 @@ -17,6 +17,10 @@
     5.4  #define FAST_HYPERPRIVOP_CNT
     5.5  #define FAST_REFLECT_CNT
     5.6  
     5.7 +// FIXME: This is defined in include/asm-ia64/hw_irq.h but this
     5.8 +// doesn't appear to be include'able from assembly?
     5.9 +#define IA64_TIMER_VECTOR 0xef
    5.10 +
    5.11  // Should be included from common header file (also in process.c)
    5.12  //  NO PSR_CLR IS DIFFERENT! (CPL)
    5.13  #define IA64_PSR_CPL1	(__IA64_UL(1) << IA64_PSR_CPL1_BIT)
    5.14 @@ -241,14 +245,23 @@ ENTRY(hyper_ssm_i)
    5.15  	adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
    5.16  	adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
    5.17  	bsw.1;;
    5.18 -	st8 [r2]=r16,16; st8 [r3]=r17,16 ;;
    5.19 -	st8 [r2]=r18,16; st8 [r3]=r19,16 ;;
    5.20 -	st8 [r2]=r20,16; st8 [r3]=r21,16 ;;
    5.21 -	st8 [r2]=r22,16; st8 [r3]=r23,16 ;;
    5.22 -	st8 [r2]=r24,16; st8 [r3]=r25,16 ;;
    5.23 -	st8 [r2]=r26,16; st8 [r3]=r27,16 ;;
    5.24 -	st8 [r2]=r28,16; st8 [r3]=r29,16 ;;
    5.25 -	st8 [r2]=r30,16; st8 [r3]=r31,16 ;;
    5.26 +	// FIXME: need to handle ar.unat!
    5.27 +	.mem.offset 0,0; st8.spill [r2]=r16,16;
    5.28 +	.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
    5.29 +	.mem.offset 0,0; st8.spill [r2]=r18,16;
    5.30 +	.mem.offset 8,0; st8.spill [r3]=r19,16 ;;
    5.31 +	.mem.offset 0,0; st8.spill [r2]=r20,16;
    5.32 +	.mem.offset 8,0; st8.spill [r3]=r21,16 ;;
    5.33 +	.mem.offset 0,0; st8.spill [r2]=r22,16;
    5.34 +	.mem.offset 8,0; st8.spill [r3]=r23,16 ;;
    5.35 +	.mem.offset 0,0; st8.spill [r2]=r24,16;
    5.36 +	.mem.offset 8,0; st8.spill [r3]=r25,16 ;;
    5.37 +	.mem.offset 0,0; st8.spill [r2]=r26,16;
    5.38 +	.mem.offset 8,0; st8.spill [r3]=r27,16 ;;
    5.39 +	.mem.offset 0,0; st8.spill [r2]=r28,16;
    5.40 +	.mem.offset 8,0; st8.spill [r3]=r29,16 ;;
    5.41 +	.mem.offset 0,0; st8.spill [r2]=r30,16;
    5.42 +	.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
    5.43  	movl r31=XSI_IPSR;;
    5.44  	bsw.0 ;;
    5.45  	mov r2=r30; mov r3=r29;;
    5.46 @@ -258,6 +271,174 @@ ENTRY(hyper_ssm_i)
    5.47  	rfi
    5.48  	;;
    5.49  
    5.50 +// reflect domain clock interrupt
    5.51 +//	r31 == pr
    5.52 +//	r30 == cr.ivr
    5.53 +//	r29 == rp
    5.54 +GLOBAL_ENTRY(fast_tick_reflect)
    5.55 +#define FAST_TICK
    5.56 +#ifndef FAST_TICK
    5.57 +	br.cond.sptk.many rp;;
    5.58 +#endif
    5.59 +	mov r28=IA64_TIMER_VECTOR;;
    5.60 +	cmp.ne p6,p0=r28,r30
    5.61 +(p6)	br.cond.spnt.few rp;;
    5.62 +	movl r20=(PERCPU_ADDR)+IA64_CPUINFO_ITM_NEXT_OFFSET;;
    5.63 +	ld8 r21=[r20];;
    5.64 +	mov r27=ar.itc;;
    5.65 +	cmp.ltu p6,p0=r21,r27
    5.66 +(p6)	br.cond.spnt.few rp;;
    5.67 +	mov r17=cr.ipsr;;
    5.68 +	// slow path if: ipsr.be==1, ipsr.pp==1
    5.69 +	extr.u r21=r17,IA64_PSR_BE_BIT,1 ;;
    5.70 +	cmp.ne p6,p0=r21,r0
    5.71 +(p6)	br.cond.spnt.few rp;;
    5.72 +	extr.u r21=r17,IA64_PSR_PP_BIT,1 ;;
    5.73 +	cmp.ne p6,p0=r21,r0
    5.74 +(p6)	br.cond.spnt.few rp;;
    5.75 +#ifdef FAST_REFLECT_CNT
    5.76 +	movl r20=fast_reflect_count+((0x3000>>8)*8);;
    5.77 +	ld8 r21=[r20];;
    5.78 +	adds r21=1,r21;;
    5.79 +	st8 [r20]=r21;;
    5.80 +#endif
    5.81 +	mov cr.eoi=r0;;
    5.82 +	mov rp=r29;;
    5.83 +	// vcpu_pend_timer(current)
    5.84 +	movl r18=XSI_PSR_IC;;
    5.85 +	adds r20=XSI_ITV_OFS-XSI_PSR_IC_OFS,r18 ;;
    5.86 +	ld8 r20=[r20];;
    5.87 +	cmp.eq p6,p0=r20,r0	// if cr.itv==0 done
    5.88 +(p6)	br.cond.spnt.few fast_tick_reflect_done;;
    5.89 +	tbit.nz p6,p0=r20,16;;	// check itv.m (discard) bit
    5.90 +(p6)	br.cond.spnt.few fast_tick_reflect_done;;
    5.91 +	extr.u r27=r20,0,6	// r27 has low 6 bits of itv.vector
    5.92 +	extr.u r26=r20,6,2;;	// r26 has irr index of itv.vector
    5.93 +	mov r19=IA64_KR(CURRENT);;
    5.94 +	adds r22=IA64_VCPU_DOMAIN_ITM_LAST_OFFSET,r19
    5.95 +	adds r23=IA64_VCPU_DOMAIN_ITM_OFFSET,r19;;
    5.96 +	ld8 r24=[r22];;
    5.97 +	ld8 r23=[r23];;
    5.98 +	cmp.eq p6,p0=r23,r24	// skip if this tick already delivered
    5.99 +(p6)	br.cond.spnt.few fast_tick_reflect_done;;
   5.100 +	// set irr bit
   5.101 +	adds r21=IA64_VCPU_IRR0_OFFSET,r19;
   5.102 +	shl r26=r26,3;;
   5.103 +	add r21=r21,r26;;
   5.104 +	mov r25=1;;
   5.105 +	shl r22=r25,r27;;
   5.106 +	ld8 r23=[r21];;
   5.107 +	or r22=r22,r23;;
   5.108 +	st8 [r21]=r22;;
   5.109 +	// set PSCB(pending_interruption)!
   5.110 +	adds r20=XSI_PEND_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.111 +	st4 [r20]=r25;;
   5.112 +	
   5.113 +	// if interrupted at pl0, we're done
   5.114 +	extr.u r16=r17,IA64_PSR_CPL0_BIT,2;;
   5.115 +	cmp.eq p6,p0=r16,r0;;
   5.116 +(p6)	br.cond.spnt.few fast_tick_reflect_done;;
   5.117 +	// if guest vpsr.i is off, we're done
   5.118 +	adds r21=XSI_PSR_I_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.119 +	ld4 r21=[r21];;
   5.120 +	cmp.eq p6,p0=r21,r0
   5.121 +(p6)	br.cond.spnt.few fast_tick_reflect_done;;
   5.122 +
   5.123 +	// OK, we have a clock tick to deliver to the active domain!
   5.124 +	// so deliver to iva+0x3000
   5.125 +	//	r17 == cr.ipsr
   5.126 +	//	r18 == XSI_PSR_IC
   5.127 +	//	r19 == IA64_KR(CURRENT)
   5.128 +	//	r31 == pr
   5.129 +	mov r16=cr.isr;;
   5.130 +	mov r29=cr.iip;;
   5.131 +	adds r21=XSI_IIP_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.132 +	st8 [r21]=r29 ;;
   5.133 +	// set shared_mem isr
   5.134 +	extr.u r16=r16,38,1;;	// grab cr.isr.ir bit
   5.135 +	dep r16=r16,r0,38,1 ;;	// insert into cr.isr (rest of bits zero)
   5.136 +	extr.u r20=r17,41,2 ;;	// get ipsr.ri
   5.137 +	dep r16=r20,r16,41,2 ;; // deposit cr.isr.ei
   5.138 +	adds r21=XSI_ISR_OFS-XSI_PSR_IC_OFS,r18 ;; 
   5.139 +	st8 [r21]=r16 ;;
   5.140 +	// set cr.ipsr (make sure cpl==2!)
   5.141 +	mov r29=r17 ;;
   5.142 +	movl r28=DELIVER_PSR_SET;;
   5.143 +	movl r27=~(DELIVER_PSR_CLR|IA64_PSR_CPL0);;
   5.144 +	or r29=r29,r28;;
   5.145 +	and r29=r29,r27;;
   5.146 +	mov cr.ipsr=r29;;
   5.147 +	// set shared_mem ipsr (from ipsr in r17 with ipsr.ri already set)
   5.148 +	extr.u r29=r17,IA64_PSR_CPL0_BIT,2;;
   5.149 +	cmp.eq p6,p7=3,r29;;
   5.150 +(p6)	dep r17=-1,r17,IA64_PSR_CPL0_BIT,2
   5.151 +(p7)	dep r17=0,r17,IA64_PSR_CPL0_BIT,2
   5.152 +	;;
   5.153 +	movl r28=(IA64_PSR_DT|IA64_PSR_IT|IA64_PSR_RT);;
   5.154 +	movl r27=~(IA64_PSR_BE|IA64_PSR_PP|IA64_PSR_BN|IA64_PSR_I|IA64_PSR_IC);;
   5.155 +	dep r21=-1,r21,IA64_PSR_CPL1_BIT,1 ;;
   5.156 +	or r17=r17,r28;;
   5.157 +	and r17=r17,r27;;
   5.158 +	ld4 r16=[r18],4;;
   5.159 +	cmp.ne p6,p0=r16,r0;;
   5.160 +(p6)	dep r17=-1,r17,IA64_PSR_IC_BIT,1 ;;
   5.161 +	ld4 r16=[r18],-4;;
   5.162 +	cmp.ne p6,p0=r16,r0;;
   5.163 +(p6)	dep r17=-1,r17,IA64_PSR_I_BIT,1 ;;
   5.164 +	adds r21=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.165 +	st8 [r21]=r17 ;;
   5.166 +	// set shared_mem interrupt_delivery_enabled to 0
   5.167 +	// set shared_mem interrupt_collection_enabled to 0
   5.168 +	st8 [r18]=r0;;
   5.169 +	// cover and set shared_mem precover_ifs to cr.ifs
   5.170 +	// set shared_mem ifs and incomplete_regframe to 0
   5.171 +	cover ;;
   5.172 +	mov r20=cr.ifs;;
   5.173 +	adds r21=XSI_INCOMPL_REG_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.174 +	st4 [r21]=r0 ;;
   5.175 +	adds r21=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.176 +	st8 [r21]=r0 ;;
   5.177 +	adds r21=XSI_PRECOVER_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.178 +	st8 [r21]=r20 ;;
   5.179 +	// leave cr.ifs alone for later rfi
   5.180 +	// set iip to go to domain IVA break instruction vector
   5.181 +	adds r22=IA64_VCPU_IVA_OFFSET,r19;;
   5.182 +	ld8 r23=[r22];;
   5.183 +	movl r24=0x3000;;
   5.184 +	add r24=r24,r23;;
   5.185 +	mov cr.iip=r24;;
   5.186 +	// OK, now all set to go except for switch to virtual bank0
   5.187 +	mov r30=r2; mov r29=r3;;
   5.188 +	adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
   5.189 +	adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
   5.190 +	bsw.1;;
   5.191 +	// FIXME: need to handle ar.unat!
   5.192 +	.mem.offset 0,0; st8.spill [r2]=r16,16;
   5.193 +	.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
   5.194 +	.mem.offset 0,0; st8.spill [r2]=r18,16;
   5.195 +	.mem.offset 8,0; st8.spill [r3]=r19,16 ;;
   5.196 +	.mem.offset 0,0; st8.spill [r2]=r20,16;
   5.197 +	.mem.offset 8,0; st8.spill [r3]=r21,16 ;;
   5.198 +	.mem.offset 0,0; st8.spill [r2]=r22,16;
   5.199 +	.mem.offset 8,0; st8.spill [r3]=r23,16 ;;
   5.200 +	.mem.offset 0,0; st8.spill [r2]=r24,16;
   5.201 +	.mem.offset 8,0; st8.spill [r3]=r25,16 ;;
   5.202 +	.mem.offset 0,0; st8.spill [r2]=r26,16;
   5.203 +	.mem.offset 8,0; st8.spill [r3]=r27,16 ;;
   5.204 +	.mem.offset 0,0; st8.spill [r2]=r28,16;
   5.205 +	.mem.offset 8,0; st8.spill [r3]=r29,16 ;;
   5.206 +	.mem.offset 0,0; st8.spill [r2]=r30,16;
   5.207 +	.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
   5.208 +	movl r31=XSI_IPSR;;
   5.209 +	bsw.0 ;;
   5.210 +	mov r2=r30; mov r3=r29;;
   5.211 +	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.212 +	st4 [r20]=r0 ;;
   5.213 +fast_tick_reflect_done:
   5.214 +	mov pr=r31,-1 ;;
   5.215 +	rfi
   5.216 +END(fast_tick_reflect)
   5.217 +
   5.218  // reflect domain breaks directly to domain
   5.219  // FIXME: DOES NOT WORK YET
   5.220  //	r16 == cr.isr
   5.221 @@ -274,21 +455,21 @@ GLOBAL_ENTRY(fast_break_reflect)
   5.222  	mov r29=cr.iip;;
   5.223  	extr.u r21=r30,IA64_PSR_BE_BIT,1 ;;
   5.224  	cmp.ne p7,p0=r21,r0 ;;
   5.225 -(p7)	br.sptk.many dispatch_break_fault ;;
   5.226 +(p7)	br.spnt.few dispatch_break_fault ;;
   5.227  	extr.u r21=r30,IA64_PSR_PP_BIT,1 ;;
   5.228  	cmp.ne p7,p0=r21,r0 ;;
   5.229 -(p7)	br.sptk.many dispatch_break_fault ;;
   5.230 +(p7)	br.spnt.few dispatch_break_fault ;;
   5.231  #if 1 /* special handling in case running on simulator */
   5.232  	movl r20=first_break;;
   5.233  	ld4 r23=[r20];;
   5.234  	movl r21=0x80001;
   5.235  	movl r22=0x80002;;
   5.236  	cmp.ne p7,p0=r23,r0;;
   5.237 -(p7)	br.sptk.many dispatch_break_fault ;;
   5.238 +(p7)	br.spnt.few dispatch_break_fault ;;
   5.239  	cmp.eq p7,p0=r21,r17;
   5.240 -(p7)	br.sptk.many dispatch_break_fault ;;
   5.241 +(p7)	br.spnt.few dispatch_break_fault ;;
   5.242  	cmp.eq p7,p0=r22,r17;
   5.243 -(p7)	br.sptk.many dispatch_break_fault ;;
   5.244 +(p7)	br.spnt.few dispatch_break_fault ;;
   5.245  #endif
   5.246  #ifdef FAST_REFLECT_CNT
   5.247  	movl r20=fast_reflect_count+((0x2c00>>8)*8);;
   5.248 @@ -397,24 +578,26 @@ 1:
   5.249  	extr.u r22=r21,IA64_PSR_BE_BIT,1 ;;
   5.250  	// if turning on psr.be, give up for now and do it the slow way
   5.251  	cmp.ne p7,p0=r22,r0
   5.252 -(p7)	br.sptk.many dispatch_break_fault ;;
   5.253 +(p7)	br.spnt.few dispatch_break_fault ;;
   5.254  	// if (!(vpsr.dt && vpsr.rt && vpsr.it)), do it the slow way
   5.255  	movl r20=(IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_IT);;
   5.256  	and r22=r20,r21
   5.257  	;;
   5.258  	cmp.ne p7,p0=r22,r20
   5.259 -(p7)	br.sptk.many dispatch_break_fault ;;
   5.260 +(p7)	br.spnt.few dispatch_break_fault ;;
   5.261  	// if was in metaphys mode, do it the slow way (FIXME later?)
   5.262  	adds r20=XSI_METAPHYS_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.263  	ld4 r20=[r20];;
   5.264  	cmp.ne p7,p0=r20,r0
   5.265 -(p7)	br.sptk.many dispatch_break_fault ;;
   5.266 +(p7)	br.spnt.few dispatch_break_fault ;;
   5.267  	// if domain hasn't already done virtual bank switch
   5.268  	//  do it the slow way (FIXME later?)
   5.269 +#if 0
   5.270  	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.271  	ld4 r20=[r20];;
   5.272  	cmp.eq p7,p0=r20,r0
   5.273 -(p7)	br.sptk.many dispatch_break_fault ;;
   5.274 +(p7)	br.spnt.few dispatch_break_fault ;;
   5.275 +#endif
   5.276  	// validate vcr.iip, if in Xen range, do it the slow way
   5.277  	adds r20=XSI_IIP_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.278  	ld8 r22=[r20];;
   5.279 @@ -422,7 +605,11 @@ 1:
   5.280  	movl r24=XEN_VIRT_SPACE_HIGH ;;
   5.281  	cmp.ltu p0,p7=r22,r23 ;;	// if !(iip<low) &&
   5.282  (p7)	cmp.geu p0,p7=r22,r24 ;;	//    !(iip>=high)
   5.283 -(p7)	br.sptk.many dispatch_break_fault ;;
   5.284 +(p7)	br.spnt.few dispatch_break_fault ;;
   5.285 +#ifndef RFI_TO_INTERRUPT
   5.286 +	cmp.ne p6,p0=r30,r0
   5.287 +(p6)	br.cond.spnt.few dispatch_break_fault ;;
   5.288 +#endif
   5.289  
   5.290  1:	// OK now, let's do an rfi.
   5.291  #ifdef FAST_HYPERPRIVOP_CNT
   5.292 @@ -431,9 +618,12 @@ 1:	// OK now, let's do an rfi.
   5.293  	adds r23=1,r23;;
   5.294  	st8 [r20]=r23;;
   5.295  #endif
   5.296 +#ifdef RFI_TO_INTERRUPT
   5.297 +	// maybe do an immediate interrupt delivery?
   5.298  	cmp.ne p6,p0=r30,r0
   5.299 -(p6)	br.cond.sptk.many check_extint;
   5.300 -	;;
   5.301 +(p6)	br.cond.spnt.few rfi_check_extint;;
   5.302 +#endif
   5.303 +
   5.304  just_do_rfi:
   5.305  	// r18=&vpsr.i|vpsr.ic, r21==vpsr, r22=vcr.iip
   5.306  	mov cr.iip=r22;;
   5.307 @@ -461,43 +651,75 @@ just_do_rfi:
   5.308  	or r21=r21,r20
   5.309  	;;
   5.310  	mov cr.ipsr=r21
   5.311 -	mov pr=r31,-1
   5.312 +	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.313 +	ld4 r21=[r20];;
   5.314 +	cmp.ne p7,p0=r21,r0	// domain already did "bank 1 switch?"
   5.315 +(p7)	br.cond.spnt.few 1f;
   5.316 +	// OK, now all set to go except for switch to virtual bank1
   5.317 +	mov r22=1;; st4 [r20]=r22;
   5.318 +	mov r30=r2; mov r29=r3;;
   5.319 +	adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
   5.320 +	adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
   5.321 +	bsw.1;;
   5.322 +	// FIXME: need to handle ar.unat!
   5.323 +	.mem.offset 0,0; ld8.fill r16=[r2],16 ;
   5.324 +	.mem.offset 8,0; ld8.fill r17=[r3],16 ;;
   5.325 +	.mem.offset 0,0; ld8.fill r18=[r2],16 ;
   5.326 +	.mem.offset 0,0; ld8.fill r19=[r3],16 ;;
   5.327 +	.mem.offset 8,0; ld8.fill r20=[r2],16 ;
   5.328 +	.mem.offset 8,0; ld8.fill r21=[r3],16 ;;
   5.329 +	.mem.offset 8,0; ld8.fill r22=[r2],16 ;
   5.330 +	.mem.offset 8,0; ld8.fill r23=[r3],16 ;;
   5.331 +	.mem.offset 8,0; ld8.fill r24=[r2],16 ;
   5.332 +	.mem.offset 8,0; ld8.fill r25=[r3],16 ;;
   5.333 +	.mem.offset 8,0; ld8.fill r26=[r2],16 ;
   5.334 +	.mem.offset 8,0; ld8.fill r27=[r3],16 ;;
   5.335 +	.mem.offset 8,0; ld8.fill r28=[r2],16 ;
   5.336 +	.mem.offset 8,0; ld8.fill r29=[r3],16 ;;
   5.337 +	.mem.offset 8,0; ld8.fill r30=[r2],16 ;
   5.338 +	.mem.offset 8,0; ld8.fill r31=[r3],16 ;;
   5.339 +	bsw.0 ;;
   5.340 +	mov r2=r30; mov r3=r29;;
   5.341 +1:	mov pr=r31,-1
   5.342  	;;
   5.343  	rfi
   5.344  	;;
   5.345  
   5.346 -check_extint:
   5.347 -	br.sptk.many dispatch_break_fault ;;
   5.348 +#ifdef RFI_TO_INTERRUPT
   5.349 +GLOBAL_ENTRY(rfi_check_extint)
   5.350 +	//br.sptk.many dispatch_break_fault ;;
   5.351  
   5.352  	// r18=&vpsr.i|vpsr.ic, r21==vpsr, r22=vcr.iip
   5.353 +	// make sure none of these get trashed in case going to just_do_rfi
   5.354  	mov r30=IA64_KR(CURRENT);;
   5.355  	adds r24=IA64_VCPU_INSVC3_OFFSET,r30;;
   5.356  	mov r25=192
   5.357 -	adds r22=IA64_VCPU_IRR3_OFFSET,r30;;
   5.358 -	ld8 r23=[r22];;
   5.359 +	adds r16=IA64_VCPU_IRR3_OFFSET,r30;;
   5.360 +	ld8 r23=[r16];;
   5.361  	cmp.eq p6,p0=r23,r0;;
   5.362 -(p6)	adds r22=-8,r22;;
   5.363 +(p6)	adds r16=-8,r16;;
   5.364  (p6)	adds r24=-8,r24;;
   5.365  (p6)	adds r25=-64,r25;;
   5.366 -(p6)	ld8 r23=[r22];;
   5.367 +(p6)	ld8 r23=[r16];;
   5.368  (p6)	cmp.eq p6,p0=r23,r0;;
   5.369 -(p6)	adds r22=-8,r22;;
   5.370 +(p6)	adds r16=-8,r16;;
   5.371  (p6)	adds r24=-8,r24;;
   5.372  (p6)	adds r25=-64,r25;;
   5.373 -(p6)	ld8 r23=[r22];;
   5.374 +(p6)	ld8 r23=[r16];;
   5.375  (p6)	cmp.eq p6,p0=r23,r0;;
   5.376 -(p6)	adds r22=-8,r22;;
   5.377 +(p6)	adds r16=-8,r16;;
   5.378  (p6)	adds r24=-8,r24;;
   5.379  (p6)	adds r25=-64,r25;;
   5.380 -(p6)	ld8 r23=[r22];;
   5.381 +(p6)	ld8 r23=[r16];;
   5.382  (p6)	cmp.eq p6,p0=r23,r0;;
   5.383  	cmp.eq p6,p0=r23,r0
   5.384 -(p6)	br.cond.sptk.many 1f;	// this is actually an error
   5.385 -	// r22 points to non-zero element of irr, r23 has value
   5.386 +(p6)	br.cond.spnt.few just_do_rfi;	// this is actually an error
   5.387 +	// r16 points to non-zero element of irr, r23 has value
   5.388  	// r24 points to corr element of insvc, r25 has elt*64
   5.389  	ld8 r26=[r24];;
   5.390  	cmp.geu p6,p0=r26,r23
   5.391 -(p6)	br.cond.spnt.many 1f;
   5.392 +(p6)	br.cond.spnt.many just_do_rfi;
   5.393 +
   5.394  	// not masked by insvc, get vector number
   5.395  	shr.u r26=r23,1;;
   5.396  	or r26=r23,r26;;
   5.397 @@ -524,21 +746,109 @@ check_extint:
   5.398  	ld8 r20=[r20] ;;
   5.399  	extr.u r28=r20,16,1
   5.400  	extr.u r29=r20,4,4 ;;
   5.401 -	cmp.ne p6,p0=r28,r0	// if tpr.mmi is set, return SPURIOUS
   5.402 -(p6)	br.cond.sptk.many 1f;
   5.403 +	cmp.ne p6,p0=r28,r0	// if tpr.mmi is set, just rfi
   5.404 +(p6)	br.cond.spnt.few just_do_rfi;;
   5.405  	shl r29=r29,4;;
   5.406  	adds r29=15,r29;;
   5.407 -	cmp.ge p6,p0=r29,r26
   5.408 -(p6)	br.cond.sptk.many 1f;
   5.409 -	// OK, have an unmasked vector to process/return
   5.410 -	ld8 r25=[r24];;
   5.411 -	or r25=r25,r27;;
   5.412 -	st8 [r24]=r25;;
   5.413 -	ld8 r25=[r22];;
   5.414 -	andcm r25=r25,r27;;
   5.415 -	st8 [r22]=r25;;
   5.416 -	mov r8=r26;;
   5.417 -	// not done yet
   5.418 +	cmp.ge p6,p0=r29,r26	// if tpr masks interrupt, just rfi
   5.419 +(p6)	br.cond.spnt.few just_do_rfi;;
   5.420 +
   5.421 +// this doesn't work yet (dies early after getting to user mode)
   5.422 +// but happens relatively infrequently, so fix it later.
   5.423 +// NOTE that these will be counted incorrectly for now (for privcnt output)
   5.424 +GLOBAL_ENTRY(rfi_with_interrupt)
   5.425 +#if 1
   5.426 +	br.sptk.many dispatch_break_fault ;;
   5.427 +#endif
   5.428 +
   5.429 +	// OK, have an unmasked vector, so deliver extint to vcr.iva+0x3000
   5.430 +	//	r18 == XSI_PSR_IC
   5.431 +	//	r21 == vipsr (ipsr in shared_mem)
   5.432 +	//	r30 == IA64_KR(CURRENT)
   5.433 +	//	r31 == pr
   5.434 +	mov r17=cr.ipsr;;
   5.435 +	mov r16=cr.isr;;
   5.436 +	// set shared_mem isr
   5.437 +	extr.u r16=r16,38,1;;	// grab cr.isr.ir bit
   5.438 +	dep r16=r16,r0,38,1 ;;	// insert into cr.isr (rest of bits zero)
   5.439 +	extr.u r20=r21,41,2 ;;	// get v(!)psr.ri
   5.440 +	dep r16=r20,r16,41,2 ;; // deposit cr.isr.ei
   5.441 +	adds r22=XSI_ISR_OFS-XSI_PSR_IC_OFS,r18 ;; 
   5.442 +	st8 [r22]=r16 ;;
   5.443 +	// set cr.ipsr (make sure cpl==2!)
   5.444 +	mov r29=r17 ;;
   5.445 +	movl r28=DELIVER_PSR_SET;;
   5.446 +	movl r27=~(DELIVER_PSR_CLR|IA64_PSR_CPL0);;
   5.447 +	or r29=r29,r28;;
   5.448 +	and r29=r29,r27;;
   5.449 +	mov cr.ipsr=r29;;
   5.450 +	// v.ipsr and v.iip are already set (and v.iip validated) as rfi target
   5.451 +	// set shared_mem interrupt_delivery_enabled to 0
   5.452 +	// set shared_mem interrupt_collection_enabled to 0
   5.453 +	st8 [r18]=r0;;
   5.454 +	// cover and set shared_mem precover_ifs to cr.ifs
   5.455 +	// set shared_mem ifs and incomplete_regframe to 0
   5.456 +#if 0
   5.457 +	cover ;;
   5.458 +	mov r20=cr.ifs;;
   5.459 +	adds r22=XSI_INCOMPL_REG_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.460 +	st4 [r22]=r0 ;;
   5.461 +	adds r22=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.462 +	st8 [r22]=r0 ;;
   5.463 +	adds r22=XSI_PRECOVER_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.464 +	st8 [r22]=r20 ;;
   5.465 +	// leave cr.ifs alone for later rfi
   5.466 +#else
   5.467 +	adds r22=XSI_INCOMPL_REG_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.468 +	st4 [r22]=r0 ;;
   5.469 +	adds r22=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.470 +	ld8 r20=[r22];;
   5.471 +	st8 [r22]=r0 ;;
   5.472 +	adds r22=XSI_PRECOVER_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.473 +	st8 [r22]=r20 ;;
   5.474 +#endif
   5.475 +	// set iip to go to domain IVA break instruction vector
   5.476 +	adds r22=IA64_VCPU_IVA_OFFSET,r30;;
   5.477 +	ld8 r23=[r22];;
   5.478 +	movl r24=0x3000;;
   5.479 +	add r24=r24,r23;;
   5.480 +	mov cr.iip=r24;;
   5.481 +#if 0
   5.482 +	// OK, now all set to go except for switch to virtual bank0
   5.483 +	mov r30=r2; mov r29=r3;;
   5.484 +	adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
   5.485 +	adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
   5.486 +	bsw.1;;
   5.487 +	// FIXME: need to handle ar.unat!
   5.488 +	.mem.offset 0,0; st8.spill [r2]=r16,16;
   5.489 +	.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
   5.490 +	.mem.offset 0,0; st8.spill [r2]=r18,16;
   5.491 +	.mem.offset 8,0; st8.spill [r3]=r19,16 ;;
   5.492 +	.mem.offset 0,0; st8.spill [r2]=r20,16;
   5.493 +	.mem.offset 8,0; st8.spill [r3]=r21,16 ;;
   5.494 +	.mem.offset 0,0; st8.spill [r2]=r22,16;
   5.495 +	.mem.offset 8,0; st8.spill [r3]=r23,16 ;;
   5.496 +	.mem.offset 0,0; st8.spill [r2]=r24,16;
   5.497 +	.mem.offset 8,0; st8.spill [r3]=r25,16 ;;
   5.498 +	.mem.offset 0,0; st8.spill [r2]=r26,16;
   5.499 +	.mem.offset 8,0; st8.spill [r3]=r27,16 ;;
   5.500 +	.mem.offset 0,0; st8.spill [r2]=r28,16;
   5.501 +	.mem.offset 8,0; st8.spill [r3]=r29,16 ;;
   5.502 +	.mem.offset 0,0; st8.spill [r2]=r30,16;
   5.503 +	.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
   5.504 +	movl r31=XSI_IPSR;;
   5.505 +	bsw.0 ;;
   5.506 +	mov r2=r30; mov r3=r29;;
   5.507 +#else
   5.508 +	bsw.1;;
   5.509 +	movl r31=XSI_IPSR;;
   5.510 +	bsw.0 ;;
   5.511 +#endif
   5.512 +	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.513 +	st4 [r20]=r0 ;;
   5.514 +	mov pr=r31,-1 ;;
   5.515 +	rfi
   5.516 +#endif // RFI_TO_INTERRUPT
   5.517  
   5.518  ENTRY(hyper_cover)
   5.519  #ifdef FAST_HYPERPRIVOP_CNT
   5.520 @@ -737,7 +1047,7 @@ ENTRY(hyper_get_ivr)
   5.521  (p6)	ld8 r23=[r22];;
   5.522  (p6)	cmp.eq p6,p0=r23,r0;;
   5.523  	cmp.eq p6,p0=r23,r0
   5.524 -(p6)	br.cond.sptk.many 1f;	// this is actually an error
   5.525 +(p6)	br.cond.spnt.few 1f;	// this is actually an error
   5.526  	// r22 points to non-zero element of irr, r23 has value
   5.527  	// r24 points to corr element of insvc, r25 has elt*64
   5.528  	ld8 r26=[r24];;
   5.529 @@ -770,11 +1080,11 @@ ENTRY(hyper_get_ivr)
   5.530  	extr.u r28=r20,16,1
   5.531  	extr.u r29=r20,4,4 ;;
   5.532  	cmp.ne p6,p0=r28,r0	// if tpr.mmi is set, return SPURIOUS
   5.533 -(p6)	br.cond.sptk.many 1f;
   5.534 +(p6)	br.cond.spnt.few 1f;
   5.535  	shl r29=r29,4;;
   5.536  	adds r29=15,r29;;
   5.537  	cmp.ge p6,p0=r29,r26
   5.538 -(p6)	br.cond.sptk.many 1f;
   5.539 +(p6)	br.cond.spnt.few 1f;
   5.540  	// OK, have an unmasked vector to process/return
   5.541  	ld8 r25=[r24];;
   5.542  	or r25=r25,r27;;
   5.543 @@ -834,7 +1144,7 @@ ENTRY(hyper_eoi)
   5.544  (p6)	ld8 r23=[r22];;
   5.545  (p6)	cmp.eq p6,p0=r23,r0;;
   5.546  	cmp.eq p6,p0=r23,r0
   5.547 -(p6)	br.cond.sptk.many 1f;	// this is actually an error
   5.548 +(p6)	br.cond.spnt.few 1f;	// this is actually an error
   5.549  	// r22 points to non-zero element of insvc, r23 has value
   5.550  	shr.u r24=r23,1;;
   5.551  	or r24=r23,r24;;
   5.552 @@ -964,7 +1274,7 @@ ENTRY(hyper_set_rr)
   5.553  	adds r24=IA64_VCPU_META_SAVED_RR0_OFFSET,r20;;
   5.554  	add r22=r26,r22;;
   5.555  	cmp.geu p6,p0=r22,r23	// if r9.rid + starting_rid >= ending_rid
   5.556 -(p6)	br.cond.sptk.many 1f;	// this is an error, but just ignore/return
   5.557 +(p6)	br.cond.spnt.few 1f;	// this is an error, but just ignore/return
   5.558  	// r21=starting_rid
   5.559  	adds r20=XSI_RR0_OFS-XSI_PSR_IC_OFS,r18 ;;
   5.560  	shl r25=r25,3;;
     6.1 --- a/xen/arch/ia64/ivt.S	Wed Jun 29 17:12:12 2005 +0000
     6.2 +++ b/xen/arch/ia64/ivt.S	Wed Jun 29 21:37:40 2005 +0000
     6.3 @@ -919,6 +919,21 @@ ENTRY(interrupt)
     6.4  	DBG_FAULT(12)
     6.5  	mov r31=pr		// prepare to save predicates
     6.6  	;;
     6.7 +#ifdef XEN
     6.8 +	mov r30=cr.ivr		// pass cr.ivr as first arg
     6.9 +	// FIXME: this is a hack... use cpuinfo.pgd_quick because its
    6.10 +	// not used anywhere else and we need a place to stash ivr and
    6.11 +	// there's no registers available unused by SAVE_MIN/REST
    6.12 +	movl r29=(PERCPU_ADDR)+IA64_CPUINFO_PGD_QUICK_OFFSET;;
    6.13 +	st8 [r29]=r30;;
    6.14 +	movl r28=slow_interrupt;;
    6.15 +	mov r29=rp;;
    6.16 +	mov rp=r28;;
    6.17 +	br.cond.sptk.many fast_tick_reflect
    6.18 +	;;
    6.19 +slow_interrupt:
    6.20 +	mov rp=r29;;
    6.21 +#endif
    6.22  	SAVE_MIN_WITH_COVER	// uses r31; defines r2 and r3
    6.23  	ssm psr.ic | PSR_DEFAULT_BITS
    6.24  	;;
    6.25 @@ -928,7 +943,12 @@ ENTRY(interrupt)
    6.26  	SAVE_REST
    6.27  	;;
    6.28  	alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
    6.29 +#ifdef XEN
    6.30 +	movl out0=(PERCPU_ADDR)+IA64_CPUINFO_PGD_QUICK_OFFSET;;
    6.31 +	ld8 out0=[out0];;
    6.32 +#else
    6.33  	mov out0=cr.ivr		// pass cr.ivr as first arg
    6.34 +#endif
    6.35  	add out1=16,sp		// pass pointer to pt_regs as second arg
    6.36  	;;
    6.37  	srlz.d			// make sure we see the effect of cr.ivr
     7.1 --- a/xen/arch/ia64/privop.c	Wed Jun 29 17:12:12 2005 +0000
     7.2 +++ b/xen/arch/ia64/privop.c	Wed Jun 29 21:37:40 2005 +0000
     7.3 @@ -693,8 +693,8 @@ priv_handle_op(VCPU *vcpu, REGS *regs, i
     7.4  		break;
     7.5  	}
     7.6          //printf("We who are about do die salute you\n");
     7.7 -	printf("handle_op: can't handle privop at 0x%lx (op=0x%016lx) slot %d (type=%d)\n",
     7.8 -		 iip, (UINT64)inst.inst, slot, slot_type);
     7.9 +	printf("handle_op: can't handle privop at 0x%lx (op=0x%016lx) slot %d (type=%d), ipsr=%p\n",
    7.10 +		 iip, (UINT64)inst.inst, slot, slot_type, ipsr);
    7.11          //printf("vtop(0x%lx)==0x%lx\n", iip, tr_vtop(iip));
    7.12          //thread_mozambique("privop fault\n");
    7.13  	return (IA64_ILLOP_FAULT);
    7.14 @@ -734,6 +734,8 @@ priv_emulate(VCPU *vcpu, REGS *regs, UIN
    7.15  		// update iip/ipsr to point to the next instruction
    7.16  		(void)vcpu_increment_iip(vcpu);
    7.17  	}
    7.18 +	if (fault == IA64_ILLOP_FAULT)
    7.19 +		printf("priv_emulate: priv_handle_op fails, isr=%p\n",isr);
    7.20  	return fault;
    7.21  }
    7.22  
    7.23 @@ -781,6 +783,7 @@ ia64_hyperprivop(unsigned long iim, REGS
    7.24  // FIXME: Handle faults appropriately for these
    7.25  	if (!iim || iim > HYPERPRIVOP_MAX) {
    7.26  		printf("bad hyperprivop; ignored\n");
    7.27 +		printf("iim=%d, iip=%p\n",iim,regs->cr_iip);
    7.28  		return 1;
    7.29  	}
    7.30  	slow_hyperpriv_cnt[iim]++;
     8.1 --- a/xen/arch/ia64/process.c	Wed Jun 29 17:12:12 2005 +0000
     8.2 +++ b/xen/arch/ia64/process.c	Wed Jun 29 21:37:40 2005 +0000
     8.3 @@ -191,8 +191,8 @@ void reflect_interruption(unsigned long 
     8.4  		if (vector != IA64_DATA_TLB_VECTOR &&
     8.5  		    vector != IA64_ALT_DATA_TLB_VECTOR &&
     8.6  		    vector != IA64_VHPT_TRANS_VECTOR) {
     8.7 -panic_domain(regs,"psr.ic off, delivering fault=%lx,iip=%p,ifa=%p,isr=%p,PSCB.iip=%p\n",
     8.8 -	vector,regs->cr_iip,ifa,isr,PSCB(v,iip));
     8.9 +panic_domain(regs,"psr.ic off, delivering fault=%lx,ipsr=%p,iip=%p,ifa=%p,isr=%p,PSCB.iip=%p\n",
    8.10 +	vector,regs->cr_ipsr,regs->cr_iip,ifa,isr,PSCB(v,iip));
    8.11  			
    8.12  		}
    8.13  //printf("Delivering NESTED DATA TLB fault\n");
    8.14 @@ -754,7 +754,8 @@ if (!running_on_sim) { printf("SSC_OPEN,
    8.15  		vcpu_set_gr(current,8,-1L);
    8.16  		break;
    8.17  	    default:
    8.18 -		printf("ia64_handle_break: bad ssc code %lx, iip=%p, b0=%p\n",ssc,regs->cr_iip,regs->b0);
    8.19 +		printf("ia64_handle_break: bad ssc code %lx, iip=%p, b0=%p... spinning\n",ssc,regs->cr_iip,regs->b0);
    8.20 +		while(1);
    8.21  		break;
    8.22  	}
    8.23  	vcpu_increment_iip(current);
    8.24 @@ -845,6 +846,7 @@ ia64_handle_reflection (unsigned long if
    8.25  		break;
    8.26  	    case 26:
    8.27  printf("*** NaT fault... attempting to handle as privop\n");
    8.28 +printf("isr=%p, ifa=%p,iip=%p,ipsr=%p\n",isr,ifa,regs->cr_iip,psr);
    8.29  		vector = priv_emulate(v,regs,isr);
    8.30  		if (vector == IA64_NO_FAULT) {
    8.31  printf("*** Handled privop masquerading as NaT fault\n");
     9.1 --- a/xen/include/asm-ia64/xensystem.h	Wed Jun 29 17:12:12 2005 +0000
     9.2 +++ b/xen/include/asm-ia64/xensystem.h	Wed Jun 29 21:37:40 2005 +0000
     9.3 @@ -66,13 +66,12 @@ extern struct task_struct *vmx_ia64_swit
     9.4  	register long __gu_r8 asm ("r8");				\
     9.5  	register long __gu_r9 asm ("r9");				\
     9.6  	asm volatile ("mov ar.ccv=%0;;" :: "rO"(old));			\
     9.7 -	asm volatile ("mov %2=r0;;\n"					\
     9.8 -		"[1:]\tcmpxchg"_size".acq %0=[%3],%4,ar.ccv\n"		\
     9.9 -		"\t.xdata4 \"__ex_table\", 1b-., 1f-.+4\n"		\
    9.10 +	asm volatile ("mov %1=r0;;\n"					\
    9.11 +		"[1:]\tcmpxchg"_size".acq %0=[%2],%3,ar.ccv\n"		\
    9.12 +		"\t.xdata4 \"__ex_table\", 1b-., 1f-.\n"		\
    9.13  		"[1:]"							\
    9.14 -		: "=r"(old), "=r"(__gu_r9), "=r"(__gu_r8) :		\
    9.15 +		: "=r"(old), "=r"(__gu_r8) :				\
    9.16  		"r"(ptr), "r"(new) : "memory");				\
    9.17 -	(old) = __gu_r9;						\
    9.18  	__gu_r8;							\
    9.19  })
    9.20