direct-io.hg

changeset 11495:ccdaa3ea71a7

[POWERPC][XEN] move setting of MSR[RI] till after SRR0/1

This also frees up space so we can properly/safely blow away larx/stcx
reservations.

Signed-off-by: Jimi Xenidis <jimix@watson.ibm.com>
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
author Jimi Xenidis <jimix@watson.ibm.com>
date Tue Sep 05 15:25:06 2006 -0400 (2006-09-05)
parents 94aa7e921ccd
children a817acb39386
files xen/arch/powerpc/powerpc64/exceptions.S
line diff
     1.1 --- a/xen/arch/powerpc/powerpc64/exceptions.S	Fri Sep 01 13:14:53 2006 -0400
     1.2 +++ b/xen/arch/powerpc/powerpc64/exceptions.S	Tue Sep 05 15:25:06 2006 -0400
     1.3 @@ -116,12 +116,8 @@ 1:
     1.4      std r0, UREGS_r13(r1)           /* save R13 from HSPRG1 */
     1.5  
     1.6      /* Blow away any reservation according to 970 errata after saving CR */
     1.7 -    stdcx. r1, 0, r1
     1.8 -
     1.9 -    /* done with processor_area; re-enable MSR:RI */ 
    1.10 -    mfmsr r0
    1.11 -    ori r0, r0, MSR_RI@l
    1.12 -    mtmsrd r0
    1.13 +    ldx r0, 0, r1
    1.14 +    stdcx. r0, 0, r1
    1.15  
    1.16      /* save CTR and use it to jump */
    1.17      mfctr r0
    1.18 @@ -147,6 +143,13 @@ 1:
    1.19      li r0, -1 /* we clobbered the OS's SRR0/SRR1 to get here. */
    1.20      std r0, UREGS_srr0(\uregs)
    1.21      std r0, UREGS_srr1(\uregs)
    1.22 +
    1.23 +    /* done with processor_area; re-enable MSR:RI */ 
    1.24 +    mfmsr r0
    1.25 +    ori r0, r0, MSR_RI@l
    1.26 +    mtmsrd r0
    1.27 +
    1.28 +
    1.29  .endm
    1.30  
    1.31  /* For exceptions that use HSRR0/1 (preserving the OS's SRR0/1). */
    1.32 @@ -167,6 +170,12 @@ 1:
    1.33      std r0, UREGS_srr0(\uregs)
    1.34      mfspr r0, SPRN_SRR1
    1.35      std r0, UREGS_srr1(\uregs)
    1.36 +
    1.37 +    /* done with processor_area; re-enable MSR:RI */ 
    1.38 +    mfmsr r0
    1.39 +    ori r0, r0, MSR_RI@l
    1.40 +    mtmsrd r0
    1.41 +
    1.42  .endm
    1.43  
    1.44  /* Hypervisor exception handling code; copied to physical address zero. */
    1.45 @@ -374,6 +383,7 @@ ex_hcall_continued:
    1.46      mfmsr r14
    1.47      ori r14, r14, MSR_EE
    1.48      xori r15, r14, MSR_EE
    1.49 +
    1.50  hcall_test_all_events:
    1.51      mtmsrd r15, 1                       /* disable interrupts */
    1.52      ld r3, PAREA_vcpu(r13)