direct-io.hg

changeset 12277:cba947bc8450

[HVM] VIOAPIC and VPIC cleanups.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Tue Nov 07 17:46:40 2006 +0000 (2006-11-07)
parents 9fbb26d47b83
children 2b89ebf00fc8
files xen/arch/ia64/vmx/vlsapic.c xen/arch/ia64/vmx/vmx_init.c xen/arch/x86/hvm/hvm.c xen/arch/x86/hvm/i8259.c xen/arch/x86/hvm/rtc.c xen/arch/x86/hvm/svm/intr.c xen/arch/x86/hvm/vioapic.c xen/arch/x86/hvm/vlapic.c xen/arch/x86/hvm/vmx/io.c xen/include/asm-ia64/vmx_platform.h xen/include/asm-x86/hvm/domain.h xen/include/asm-x86/hvm/vioapic.h xen/include/asm-x86/hvm/vpic.h
line diff
     1.1 --- a/xen/arch/ia64/vmx/vlsapic.c	Tue Nov 07 15:48:10 2006 +0000
     1.2 +++ b/xen/arch/ia64/vmx/vlsapic.c	Tue Nov 07 17:46:40 2006 +0000
     1.3 @@ -324,7 +324,7 @@ void vtm_domain_in(VCPU *vcpu)
     1.4   */
     1.5  
     1.6  #ifdef V_IOSAPIC_READY
     1.7 -int ioapic_match_logical_addr(hvm_vioapic_t *s, int number, uint16_t dest)
     1.8 +int ioapic_match_logical_addr(struct vioapic *s, int number, uint16_t dest)
     1.9  {
    1.10      return (VLAPIC_ID(s->lapic_info[number]) == dest);
    1.11  }
    1.12 @@ -335,14 +335,14 @@ struct vlapic* apic_round_robin(struct d
    1.13  				uint32_t bitmap)
    1.14  {
    1.15      uint8_t bit;
    1.16 -    hvm_vioapic_t *s;
    1.17 +    struct vioapic *s;
    1.18      
    1.19      if (!bitmap) {
    1.20  	printk("<apic_round_robin> no bit on bitmap\n");
    1.21  	return NULL;
    1.22      }
    1.23  
    1.24 -    s = &d->arch.vmx_platform.vioapic;
    1.25 +    s = domain_vioapic(d);
    1.26      for (bit = 0; bit < s->lapic_count; bit++) {
    1.27  	if (bitmap & (1 << bit))
    1.28  	    return s->lapic_info[bit];
    1.29 @@ -375,7 +375,7 @@ void vlsapic_reset(VCPU *vcpu)
    1.30  
    1.31  #ifdef V_IOSAPIC_READY
    1.32      vcpu->arch.arch_vmx.vlapic.vcpu = vcpu;
    1.33 -    hvm_vioapic_add_lapic(&vcpu->arch.arch_vmx.vlapic, vcpu);
    1.34 +    vioapic_add_lapic(&vcpu->arch.arch_vmx.vlapic, vcpu);
    1.35  #endif
    1.36      dprintk(XENLOG_INFO, "VLSAPIC inservice base=%p\n", &VLSAPIC_INSVC(vcpu,0) );
    1.37  }
     2.1 --- a/xen/arch/ia64/vmx/vmx_init.c	Tue Nov 07 15:48:10 2006 +0000
     2.2 +++ b/xen/arch/ia64/vmx/vmx_init.c	Tue Nov 07 17:46:40 2006 +0000
     2.3 @@ -456,7 +456,7 @@ void vmx_setup_platform(struct domain *d
     2.4  	spin_lock_init(&d->arch.arch_vmx.virq_assist_lock);
     2.5  
     2.6  	/* Initialize iosapic model within hypervisor */
     2.7 -	hvm_vioapic_init(d);
     2.8 +	vioapic_init(d);
     2.9  }
    2.10  
    2.11  void vmx_do_launch(struct vcpu *v)
     3.1 --- a/xen/arch/x86/hvm/hvm.c	Tue Nov 07 15:48:10 2006 +0000
     3.2 +++ b/xen/arch/x86/hvm/hvm.c	Tue Nov 07 17:46:40 2006 +0000
     3.3 @@ -133,7 +133,7 @@ int hvm_domain_initialise(struct domain 
     3.4      pic_init(&platform->vpic, pic_irq_request, &platform->interrupt_request);
     3.5      register_pic_io_hook(d);
     3.6  
     3.7 -    hvm_vioapic_init(d);
     3.8 +    vioapic_init(d);
     3.9  
    3.10      return 0;
    3.11  }
    3.12 @@ -219,15 +219,15 @@ u64 hvm_get_guest_time(struct vcpu *v)
    3.13  int cpu_get_interrupt(struct vcpu *v, int *type)
    3.14  {
    3.15      int intno;
    3.16 -    struct hvm_virpic *s = &v->domain->arch.hvm_domain.vpic;
    3.17 +    struct vpic *vpic = domain_vpic(v->domain);
    3.18      unsigned long flags;
    3.19  
    3.20      if ( (intno = cpu_get_apic_interrupt(v, type)) != -1 ) {
    3.21          /* set irq request if a PIC irq is still pending */
    3.22          /* XXX: improve that */
    3.23 -        spin_lock_irqsave(&s->lock, flags);
    3.24 -        pic_update_irq(s);
    3.25 -        spin_unlock_irqrestore(&s->lock, flags);
    3.26 +        spin_lock_irqsave(&vpic->lock, flags);
    3.27 +        pic_update_irq(vpic);
    3.28 +        spin_unlock_irqrestore(&vpic->lock, flags);
    3.29          return intno;
    3.30      }
    3.31      /* read the irq from the PIC */
    3.32 @@ -674,7 +674,7 @@ long do_hvm_op(unsigned long op, XEN_GUE
    3.33          rc = -EINVAL;
    3.34          if ( is_hvm_domain(d) )
    3.35          {
    3.36 -            pic_set_irq(&d->arch.hvm_domain.vpic, op.irq, op.level);
    3.37 +            pic_set_irq(domain_vpic(d), op.irq, op.level);
    3.38              rc = 0;
    3.39          }
    3.40  
     4.1 --- a/xen/arch/x86/hvm/i8259.c	Tue Nov 07 15:48:10 2006 +0000
     4.2 +++ b/xen/arch/x86/hvm/i8259.c	Tue Nov 07 17:46:40 2006 +0000
     4.3 @@ -5,10 +5,10 @@
     4.4   * Copyright (c) 2005 Intel Corperation
     4.5   * 
     4.6   * Permission is hereby granted, free of charge, to any person obtaining a copy
     4.7 - * of this software and associated documentation files (the "Software"), to deal
     4.8 - * in the Software without restriction, including without limitation the rights
     4.9 - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    4.10 - * copies of the Software, and to permit persons to whom the Software is
    4.11 + * of this software and associated documentation files (the "Software"), to
    4.12 + * deal in the Software without restriction, including without limitation the
    4.13 + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
    4.14 + * sell copies of the Software, and to permit persons to whom the Software is
    4.15   * furnished to do so, subject to the following conditions:
    4.16   *
    4.17   * The above copyright notice and this permission notice shall be included in
    4.18 @@ -18,10 +18,11 @@
    4.19   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    4.20   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
    4.21   * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    4.22 - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    4.23 - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    4.24 - * THE SOFTWARE.
    4.25 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
    4.26 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
    4.27 + * IN THE SOFTWARE.
    4.28   */
    4.29 +
    4.30  #include <xen/config.h>
    4.31  #include <xen/types.h>
    4.32  #include <xen/mm.h>
    4.33 @@ -34,6 +35,8 @@
    4.34  #include <asm/hvm/support.h>
    4.35  #include <asm/current.h>
    4.36  
    4.37 +#define hw_error(x) ((void)0)
    4.38 +
    4.39  /* set irq level. If an edge is detected, then the IRR is set to 1 */
    4.40  static inline void pic_set_irq1(PicState *s, int irq, int level)
    4.41  {
    4.42 @@ -108,38 +111,38 @@ static int pic_get_irq(PicState *s)
    4.43  /* raise irq to CPU if necessary. must be called every time the active
    4.44     irq may change */
    4.45  /* XXX: should not export it, but it is needed for an APIC kludge */
    4.46 -void pic_update_irq(struct hvm_virpic *s)
    4.47 +void pic_update_irq(struct vpic *vpic)
    4.48  {
    4.49      int irq2, irq;
    4.50  
    4.51 -    ASSERT(spin_is_locked(&s->lock));
    4.52 +    ASSERT(spin_is_locked(&vpic->lock));
    4.53  
    4.54      /* first look at slave pic */
    4.55 -    irq2 = pic_get_irq(&s->pics[1]);
    4.56 +    irq2 = pic_get_irq(&vpic->pics[1]);
    4.57      if (irq2 >= 0) {
    4.58          /* if irq request by slave pic, signal master PIC */
    4.59 -        pic_set_irq1(&s->pics[0], 2, 1);
    4.60 -        pic_set_irq1(&s->pics[0], 2, 0);
    4.61 +        pic_set_irq1(&vpic->pics[0], 2, 1);
    4.62 +        pic_set_irq1(&vpic->pics[0], 2, 0);
    4.63      }
    4.64      /* look at requested irq */
    4.65 -    irq = pic_get_irq(&s->pics[0]);
    4.66 +    irq = pic_get_irq(&vpic->pics[0]);
    4.67      if (irq >= 0) {
    4.68 -        s->irq_request(s->irq_request_opaque, 1);
    4.69 +        vpic->irq_request(vpic->irq_request_opaque, 1);
    4.70      }
    4.71  }
    4.72  
    4.73  void pic_set_xen_irq(void *opaque, int irq, int level)
    4.74  {
    4.75 -    struct hvm_virpic *s = opaque;
    4.76 +    struct vpic *vpic = opaque;
    4.77      unsigned long flags;
    4.78      PicState *ps;
    4.79  
    4.80 -    spin_lock_irqsave(&s->lock, flags);
    4.81 +    spin_lock_irqsave(&vpic->lock, flags);
    4.82  
    4.83 -    hvm_vioapic_set_xen_irq(current->domain, irq, level);
    4.84 +    vioapic_set_xen_irq(current->domain, irq, level);
    4.85  
    4.86      /* Set it on the 8259s */
    4.87 -    ps = &s->pics[irq >> 3];
    4.88 +    ps = &vpic->pics[irq >> 3];
    4.89      if (!(ps->elcr & (1 << (irq & 7))))
    4.90  	gdprintk(XENLOG_WARNING, "edge-triggered override IRQ?\n");
    4.91      if (level) {
    4.92 @@ -148,26 +151,25 @@ void pic_set_xen_irq(void *opaque, int i
    4.93  	ps->irr_xen &= ~(1 << (irq & 7));
    4.94      }
    4.95  
    4.96 -    pic_update_irq(s);
    4.97 -    spin_unlock_irqrestore(&s->lock, flags);
    4.98 +    pic_update_irq(vpic);
    4.99 +    spin_unlock_irqrestore(&vpic->lock, flags);
   4.100  }
   4.101  
   4.102 -void pic_set_irq(struct hvm_virpic *s, int irq, int level)
   4.103 +void pic_set_irq(struct vpic *vpic, int irq, int level)
   4.104  {
   4.105      unsigned long flags;
   4.106  
   4.107      if ( irq < 0 )
   4.108          return;
   4.109  
   4.110 -    spin_lock_irqsave(&s->lock, flags);
   4.111 -    hvm_vioapic_set_irq(container_of(s, struct domain, arch.hvm_domain.vpic),
   4.112 -                        irq, level);
   4.113 +    spin_lock_irqsave(&vpic->lock, flags);
   4.114 +    vioapic_set_irq(vpic_domain(vpic), irq, level);
   4.115      if ( irq < 16 )
   4.116      {
   4.117 -        pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
   4.118 -        pic_update_irq(s);
   4.119 +        pic_set_irq1(&vpic->pics[irq >> 3], irq & 7, level);
   4.120 +        pic_update_irq(vpic);
   4.121      }
   4.122 -    spin_unlock_irqrestore(&s->lock, flags);
   4.123 +    spin_unlock_irqrestore(&vpic->lock, flags);
   4.124  }
   4.125  
   4.126  /* acknowledge interrupt 'irq' */
   4.127 @@ -186,37 +188,37 @@ static inline void pic_intack(PicState *
   4.128          s->irr &= ~(1 << irq);
   4.129  }
   4.130  
   4.131 -static int pic_read_irq(struct hvm_virpic *s)
   4.132 +static int pic_read_irq(struct vpic *vpic)
   4.133  {
   4.134      int irq, irq2, intno;
   4.135      unsigned long flags;
   4.136  
   4.137 -    spin_lock_irqsave(&s->lock, flags);
   4.138 -    irq = pic_get_irq(&s->pics[0]);
   4.139 +    spin_lock_irqsave(&vpic->lock, flags);
   4.140 +    irq = pic_get_irq(&vpic->pics[0]);
   4.141      if (irq >= 0) {
   4.142 -        pic_intack(&s->pics[0], irq);
   4.143 +        pic_intack(&vpic->pics[0], irq);
   4.144          if (irq == 2) {
   4.145 -            irq2 = pic_get_irq(&s->pics[1]);
   4.146 +            irq2 = pic_get_irq(&vpic->pics[1]);
   4.147              if (irq2 >= 0) {
   4.148 -                pic_intack(&s->pics[1], irq2);
   4.149 +                pic_intack(&vpic->pics[1], irq2);
   4.150              } else {
   4.151                  /* spurious IRQ on slave controller */
   4.152  		gdprintk(XENLOG_WARNING, "Spurious irq on slave i8259.\n");
   4.153                  irq2 = 7;
   4.154              }
   4.155 -            intno = s->pics[1].irq_base + irq2;
   4.156 +            intno = vpic->pics[1].irq_base + irq2;
   4.157              irq = irq2 + 8;
   4.158          } else {
   4.159 -            intno = s->pics[0].irq_base + irq;
   4.160 +            intno = vpic->pics[0].irq_base + irq;
   4.161          }
   4.162      } else {
   4.163          /* spurious IRQ on host controller */
   4.164          irq = 7;
   4.165 -        intno = s->pics[0].irq_base + irq;
   4.166 +        intno = vpic->pics[0].irq_base + irq;
   4.167  	gdprintk(XENLOG_WARNING, "Spurious irq on master i8259.\n");
   4.168      }
   4.169 -    pic_update_irq(s);
   4.170 -    spin_unlock_irqrestore(&s->lock, flags);
   4.171 +    pic_update_irq(vpic);
   4.172 +    spin_unlock_irqrestore(&vpic->lock, flags);
   4.173  
   4.174      return intno;
   4.175  }
   4.176 @@ -414,28 +416,28 @@ static void pic_init1(int io_addr, int e
   4.177      s->elcr = 0xff & s->elcr_mask;
   4.178  }
   4.179  
   4.180 -void pic_init(struct hvm_virpic *s, void (*irq_request)(void *, int),
   4.181 +void pic_init(struct vpic *vpic, void (*irq_request)(void *, int),
   4.182                void *irq_request_opaque)
   4.183  {
   4.184      unsigned long flags;
   4.185  
   4.186 -    memset(s, 0, sizeof(*s));
   4.187 -    spin_lock_init(&s->lock);
   4.188 -    s->pics[0].pics_state = s;
   4.189 -    s->pics[1].pics_state = s;
   4.190 -    s->pics[0].elcr_mask = 0xf8;
   4.191 -    s->pics[1].elcr_mask = 0xde;
   4.192 -    spin_lock_irqsave(&s->lock, flags);
   4.193 -    pic_init1(0x20, 0x4d0, &s->pics[0]);
   4.194 -    pic_init1(0xa0, 0x4d1, &s->pics[1]);
   4.195 -    spin_unlock_irqrestore(&s->lock, flags);
   4.196 -    s->irq_request = irq_request;
   4.197 -    s->irq_request_opaque = irq_request_opaque;
   4.198 +    memset(vpic, 0, sizeof(*vpic));
   4.199 +    spin_lock_init(&vpic->lock);
   4.200 +    vpic->pics[0].pics_state = vpic;
   4.201 +    vpic->pics[1].pics_state = vpic;
   4.202 +    vpic->pics[0].elcr_mask = 0xf8;
   4.203 +    vpic->pics[1].elcr_mask = 0xde;
   4.204 +    spin_lock_irqsave(&vpic->lock, flags);
   4.205 +    pic_init1(0x20, 0x4d0, &vpic->pics[0]);
   4.206 +    pic_init1(0xa0, 0x4d1, &vpic->pics[1]);
   4.207 +    spin_unlock_irqrestore(&vpic->lock, flags);
   4.208 +    vpic->irq_request = irq_request;
   4.209 +    vpic->irq_request_opaque = irq_request_opaque;
   4.210  }
   4.211  
   4.212  static int intercept_pic_io(ioreq_t *p)
   4.213  {
   4.214 -    struct hvm_virpic *pic;
   4.215 +    struct vpic *pic;
   4.216      uint32_t data;
   4.217      unsigned long flags;
   4.218  
   4.219 @@ -444,7 +446,7 @@ static int intercept_pic_io(ioreq_t *p)
   4.220          return 1;
   4.221      }
   4.222  
   4.223 -    pic = &current->domain->arch.hvm_domain.vpic;
   4.224 +    pic = domain_vpic(current->domain);
   4.225      if ( p->dir == IOREQ_WRITE ) {
   4.226          if ( p->data_is_ptr )
   4.227              (void)hvm_copy_from_guest_phys(&data, p->data, p->size);
   4.228 @@ -470,7 +472,7 @@ static int intercept_pic_io(ioreq_t *p)
   4.229  
   4.230  static int intercept_elcr_io(ioreq_t *p)
   4.231  {
   4.232 -    struct hvm_virpic *s;
   4.233 +    struct vpic *vpic;
   4.234      uint32_t data;
   4.235      unsigned long flags;
   4.236  
   4.237 @@ -479,20 +481,20 @@ static int intercept_elcr_io(ioreq_t *p)
   4.238          return 1;
   4.239      }
   4.240  
   4.241 -    s = &current->domain->arch.hvm_domain.vpic;
   4.242 +    vpic = domain_vpic(current->domain);
   4.243      if ( p->dir == IOREQ_WRITE ) {
   4.244          if ( p->data_is_ptr )
   4.245              (void)hvm_copy_from_guest_phys(&data, p->data, p->size);
   4.246          else
   4.247              data = p->data;
   4.248 -        spin_lock_irqsave(&s->lock, flags);
   4.249 -        elcr_ioport_write((void*)&s->pics[p->addr&1],
   4.250 +        spin_lock_irqsave(&vpic->lock, flags);
   4.251 +        elcr_ioport_write((void*)&vpic->pics[p->addr&1],
   4.252                  (uint32_t) p->addr, (uint32_t)( data & 0xff));
   4.253 -        spin_unlock_irqrestore(&s->lock, flags);
   4.254 +        spin_unlock_irqrestore(&vpic->lock, flags);
   4.255      }
   4.256      else {
   4.257          data = (u64) elcr_ioport_read(
   4.258 -                (void*)&s->pics[p->addr&1], (uint32_t) p->addr);
   4.259 +                (void*)&vpic->pics[p->addr&1], (uint32_t) p->addr);
   4.260          if ( p->data_is_ptr )
   4.261              (void)hvm_copy_to_guest_phys(p->data, &data, p->size);
   4.262          else
   4.263 @@ -514,7 +516,7 @@ void register_pic_io_hook(struct domain 
   4.264  int cpu_get_pic_interrupt(struct vcpu *v, int *type)
   4.265  {
   4.266      int intno;
   4.267 -    struct hvm_virpic *s = &v->domain->arch.hvm_domain.vpic;
   4.268 +    struct vpic *vpic = domain_vpic(v->domain);
   4.269      struct hvm_domain *plat = &v->domain->arch.hvm_domain;
   4.270  
   4.271      if ( !vlapic_accept_pic_intr(v) )
   4.272 @@ -524,7 +526,7 @@ int cpu_get_pic_interrupt(struct vcpu *v
   4.273          return -1;
   4.274  
   4.275      /* read the irq from the PIC */
   4.276 -    intno = pic_read_irq(s);
   4.277 +    intno = pic_read_irq(vpic);
   4.278      *type = APIC_DM_EXTINT;
   4.279      return intno;
   4.280  }
   4.281 @@ -539,10 +541,9 @@ int is_periodic_irq(struct vcpu *v, int 
   4.282  
   4.283      if (pt->irq == 0) { /* Is it pit irq? */
   4.284          if (type == APIC_DM_EXTINT)
   4.285 -            vec = v->domain->arch.hvm_domain.vpic.pics[0].irq_base;
   4.286 +            vec = domain_vpic(v->domain)->pics[0].irq_base;
   4.287          else
   4.288 -            vec =
   4.289 -              v->domain->arch.hvm_domain.vioapic.redirtbl[0].RedirForm.vector;
   4.290 +            vec = domain_vioapic(v->domain)->redirtbl[0].fields.vector;
   4.291  
   4.292          if (irq == vec)
   4.293              return 1;
   4.294 @@ -550,10 +551,9 @@ int is_periodic_irq(struct vcpu *v, int 
   4.295  
   4.296      if (pt->irq == 8) { /* Or rtc irq? */
   4.297          if (type == APIC_DM_EXTINT)
   4.298 -            vec = v->domain->arch.hvm_domain.vpic.pics[1].irq_base;
   4.299 +            vec = domain_vpic(v->domain)->pics[1].irq_base;
   4.300          else
   4.301 -            vec =
   4.302 -              v->domain->arch.hvm_domain.vioapic.redirtbl[8].RedirForm.vector;
   4.303 +            vec = domain_vioapic(v->domain)->redirtbl[8].fields.vector;
   4.304  
   4.305          if (irq == vec)
   4.306              return is_rtc_periodic_irq(vrtc);
   4.307 @@ -564,10 +564,10 @@ int is_periodic_irq(struct vcpu *v, int 
   4.308  
   4.309  int is_irq_enabled(struct vcpu *v, int irq)
   4.310  {
   4.311 -    struct hvm_vioapic *vioapic = &v->domain->arch.hvm_domain.vioapic;
   4.312 -    struct hvm_virpic *vpic=&v->domain->arch.hvm_domain.vpic;
   4.313 +    struct vioapic *vioapic = domain_vioapic(v->domain);
   4.314 +    struct vpic    *vpic    = domain_vpic(v->domain);
   4.315  
   4.316 -    if (vioapic->redirtbl[irq].RedirForm.mask == 0)
   4.317 +    if (vioapic->redirtbl[irq].fields.mask == 0)
   4.318         return 1;
   4.319  
   4.320      if ( irq & 8 ) {
     5.1 --- a/xen/arch/x86/hvm/rtc.c	Tue Nov 07 15:48:10 2006 +0000
     5.2 +++ b/xen/arch/x86/hvm/rtc.c	Tue Nov 07 17:46:40 2006 +0000
     5.3 @@ -4,10 +4,10 @@
     5.4   * Copyright (c) 2003-2004 Fabrice Bellard
     5.5   * 
     5.6   * Permission is hereby granted, free of charge, to any person obtaining a copy
     5.7 - * of this software and associated documentation files (the "Software"), to deal
     5.8 - * in the Software without restriction, including without limitation the rights
     5.9 - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    5.10 - * copies of the Software, and to permit persons to whom the Software is
    5.11 + * of this software and associated documentation files (the "Software"), to
    5.12 + * deal in the Software without restriction, including without limitation the
    5.13 + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
    5.14 + * sell copies of the Software, and to permit persons to whom the Software is
    5.15   * furnished to do so, subject to the following conditions:
    5.16   *
    5.17   * The above copyright notice and this permission notice shall be included in
    5.18 @@ -17,9 +17,9 @@
    5.19   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    5.20   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
    5.21   * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    5.22 - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    5.23 - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    5.24 - * THE SOFTWARE.
    5.25 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
    5.26 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
    5.27 + * IN THE SOFTWARE.
    5.28   */
    5.29  
    5.30  #include <asm/mc146818rtc.h>
    5.31 @@ -263,8 +263,8 @@ static void rtc_update_second(void *opaq
    5.32  static void rtc_update_second2(void *opaque)
    5.33  {
    5.34      RTCState *s = opaque;
    5.35 -    struct hvm_domain *plat=&s->vcpu->domain->arch.hvm_domain;
    5.36 -    struct hvm_virpic *pic= &plat->vpic;
    5.37 +    struct hvm_domain *plat = &s->vcpu->domain->arch.hvm_domain;
    5.38 +    struct vpic       *pic  = &plat->vpic;
    5.39  
    5.40      if (!(s->cmos_data[RTC_REG_B] & RTC_SET)) {
    5.41          rtc_copy_date(s);
    5.42 @@ -302,8 +302,8 @@ static void rtc_update_second2(void *opa
    5.43  static uint32_t rtc_ioport_read(void *opaque, uint32_t addr)
    5.44  {
    5.45      RTCState *s = opaque;
    5.46 -    struct hvm_domain *plat=&s->vcpu->domain->arch.hvm_domain;
    5.47 -    struct hvm_virpic *pic= &plat->vpic;
    5.48 +    struct hvm_domain *plat = &s->vcpu->domain->arch.hvm_domain;
    5.49 +    struct vpic       *pic  = &plat->vpic;
    5.50      int ret;
    5.51  
    5.52      if ((addr & 1) == 0) {
     6.1 --- a/xen/arch/x86/hvm/svm/intr.c	Tue Nov 07 15:48:10 2006 +0000
     6.2 +++ b/xen/arch/x86/hvm/svm/intr.c	Tue Nov 07 17:46:40 2006 +0000
     6.3 @@ -65,7 +65,7 @@ asmlinkage void svm_intr_assist(void)
     6.4      struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
     6.5      struct hvm_domain *plat=&v->domain->arch.hvm_domain;
     6.6      struct periodic_time *pt = &plat->pl_time.periodic_tm;
     6.7 -    struct hvm_virpic *pic= &plat->vpic;
     6.8 +    struct vpic *pic= &plat->vpic;
     6.9      int callback_irq;
    6.10      int intr_type = APIC_DM_EXTINT;
    6.11      int intr_vector = -1;
     7.1 --- a/xen/arch/x86/hvm/vioapic.c	Tue Nov 07 15:48:10 2006 +0000
     7.2 +++ b/xen/arch/x86/hvm/vioapic.c	Tue Nov 07 17:46:40 2006 +0000
     7.3 @@ -1,31 +1,29 @@
     7.4  /*
     7.5 -*  Copyright (C) 2001  MandrakeSoft S.A.
     7.6 -*
     7.7 -*    MandrakeSoft S.A.
     7.8 -*    43, rue d'Aboukir
     7.9 -*    75002 Paris - France
    7.10 -*    http://www.linux-mandrake.com/
    7.11 -*    http://www.mandrakesoft.com/
    7.12 -*
    7.13 -*  This library is free software; you can redistribute it and/or
    7.14 -*  modify it under the terms of the GNU Lesser General Public
    7.15 -*  License as published by the Free Software Foundation; either
    7.16 -*  version 2 of the License, or (at your option) any later version.
    7.17 -*
    7.18 -*  This library is distributed in the hope that it will be useful,
    7.19 -*  but WITHOUT ANY WARRANTY; without even the implied warranty of
    7.20 -*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
    7.21 -*  Lesser General Public License for more details.
    7.22 -*
    7.23 -*  You should have received a copy of the GNU Lesser General Public
    7.24 -*  License along with this library; if not, write to the Free Software
    7.25 -*  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
    7.26 -*/
    7.27 -
    7.28 -/*
    7.29 -*  Yunhong Jiang <yunhong.jiang@intel.com>
    7.30 -*  Ported to xen by using virtual IRQ line.
    7.31 -*/
    7.32 + *  Copyright (C) 2001  MandrakeSoft S.A.
    7.33 + *
    7.34 + *    MandrakeSoft S.A.
    7.35 + *    43, rue d'Aboukir
    7.36 + *    75002 Paris - France
    7.37 + *    http://www.linux-mandrake.com/
    7.38 + *    http://www.mandrakesoft.com/
    7.39 + *
    7.40 + *  This library is free software; you can redistribute it and/or
    7.41 + *  modify it under the terms of the GNU Lesser General Public
    7.42 + *  License as published by the Free Software Foundation; either
    7.43 + *  version 2 of the License, or (at your option) any later version.
    7.44 + *
    7.45 + *  This library is distributed in the hope that it will be useful,
    7.46 + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    7.47 + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
    7.48 + *  Lesser General Public License for more details.
    7.49 + *
    7.50 + *  You should have received a copy of the GNU Lesser General Public
    7.51 + *  License along with this library; if not, write to the Free Software
    7.52 + *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
    7.53 + *
    7.54 + *  Yunhong Jiang <yunhong.jiang@intel.com>
    7.55 + *  Ported to xen by using virtual IRQ line.
    7.56 + */
    7.57  
    7.58  #include <xen/config.h>
    7.59  #include <xen/types.h>
    7.60 @@ -51,14 +49,6 @@ static int redir_warning_done = 0;
    7.61  #define opt_hvm_debug_level opt_vmx_debug_level
    7.62  #endif
    7.63  
    7.64 -static void ioapic_enable(hvm_vioapic_t *s, uint8_t enable)
    7.65 -{
    7.66 -    if (enable)
    7.67 -        s->flags |= IOAPIC_ENABLE_FLAG;
    7.68 -    else
    7.69 -        s->flags &= ~IOAPIC_ENABLE_FLAG;
    7.70 -}
    7.71 -
    7.72  #ifdef HVM_DOMAIN_SAVE_RESTORE
    7.73  void ioapic_save(QEMUFile* f, void* opaque)
    7.74  {
    7.75 @@ -72,183 +62,179 @@ int ioapic_load(QEMUFile* f, void* opaqu
    7.76  }
    7.77  #endif
    7.78  
    7.79 -static unsigned long hvm_vioapic_read_indirect(struct hvm_vioapic *s,
    7.80 -                                              unsigned long addr,
    7.81 -                                              unsigned long length)
    7.82 +static unsigned long vioapic_read_indirect(struct vioapic *vioapic,
    7.83 +                                           unsigned long addr,
    7.84 +                                           unsigned long length)
    7.85  {
    7.86      unsigned long result = 0;
    7.87  
    7.88 -    ASSERT(s);
    7.89 -
    7.90 -    switch (s->ioregsel) {
    7.91 -    case IOAPIC_REG_VERSION:
    7.92 -        result = ((((IOAPIC_NUM_PINS-1) & 0xff) << 16)
    7.93 -                  | (IOAPIC_VERSION_ID & 0xff));
    7.94 +    switch ( vioapic->ioregsel )
    7.95 +    {
    7.96 +    case VIOAPIC_REG_VERSION:
    7.97 +        result = ((((VIOAPIC_NUM_PINS-1) & 0xff) << 16)
    7.98 +                  | (VIOAPIC_VERSION_ID & 0xff));
    7.99          break;
   7.100  
   7.101 -#ifndef __ia64__
   7.102 -    case IOAPIC_REG_APIC_ID:
   7.103 -        result = ((s->id & 0xf) << 24);
   7.104 -        break;
   7.105 -
   7.106 -    case IOAPIC_REG_ARB_ID:
   7.107 -        /* XXX how arb_id used on p4? */
   7.108 -        result = ((s->arb_id & 0xf) << 24);
   7.109 +#if !VIOAPIC_IS_IOSAPIC
   7.110 +    case VIOAPIC_REG_APIC_ID:
   7.111 +    case VIOAPIC_REG_ARB_ID:
   7.112 +        result = ((vioapic->id & 0xf) << 24);
   7.113          break;
   7.114  #endif
   7.115  
   7.116      default:
   7.117 -        {
   7.118 -            uint32_t redir_index = 0;
   7.119 -            uint64_t redir_content = 0;
   7.120 -
   7.121 -            redir_index = (s->ioregsel - 0x10) >> 1;
   7.122 -
   7.123 -            if (redir_index >= 0 && redir_index < IOAPIC_NUM_PINS) {
   7.124 -                redir_content = s->redirtbl[redir_index].value;
   7.125 +    {
   7.126 +        uint32_t redir_index = (vioapic->ioregsel - 0x10) >> 1;
   7.127 +        uint64_t redir_content;
   7.128  
   7.129 -                result = (s->ioregsel & 0x1)?
   7.130 -                           (redir_content >> 32) & 0xffffffff :
   7.131 -                           redir_content & 0xffffffff;
   7.132 -            } else {
   7.133 -                printk("apic_mem_readl:undefined ioregsel %x\n",
   7.134 -                        s->ioregsel);
   7.135 -                domain_crash_synchronous();
   7.136 -            }
   7.137 +        if ( redir_index >= VIOAPIC_NUM_PINS )
   7.138 +        {
   7.139 +            gdprintk(XENLOG_WARNING, "apic_mem_readl:undefined ioregsel %x\n",
   7.140 +                     vioapic->ioregsel);
   7.141              break;
   7.142          }
   7.143 -    } /* switch */
   7.144 +
   7.145 +        redir_content = vioapic->redirtbl[redir_index].bits;
   7.146 +        result = (vioapic->ioregsel & 0x1)?
   7.147 +            (redir_content >> 32) & 0xffffffff :
   7.148 +            redir_content & 0xffffffff;
   7.149 +        break;
   7.150 +    }
   7.151 +    }
   7.152  
   7.153      return result;
   7.154  }
   7.155  
   7.156 -static unsigned long hvm_vioapic_read(struct vcpu *v,
   7.157 -                                     unsigned long addr,
   7.158 -                                     unsigned long length)
   7.159 +static unsigned long vioapic_read(struct vcpu *v,
   7.160 +                                  unsigned long addr,
   7.161 +                                  unsigned long length)
   7.162  {
   7.163 -    struct hvm_vioapic *s = &(v->domain->arch.hvm_domain.vioapic);
   7.164 -    uint32_t    result = 0;
   7.165 +    struct vioapic *vioapic = domain_vioapic(v->domain);
   7.166 +    uint32_t result;
   7.167  
   7.168 -    HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "hvm_vioapic_read addr %lx\n", addr);
   7.169 -
   7.170 -    ASSERT(s);
   7.171 +    HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "vioapic_read addr %lx\n", addr);
   7.172  
   7.173      addr &= 0xff;
   7.174  
   7.175 -    switch (addr) {
   7.176 -    case IOAPIC_REG_SELECT:
   7.177 -        result = s->ioregsel;
   7.178 +    switch ( addr )
   7.179 +    {
   7.180 +    case VIOAPIC_REG_SELECT:
   7.181 +        result = vioapic->ioregsel;
   7.182          break;
   7.183  
   7.184 -    case IOAPIC_REG_WINDOW:
   7.185 -        result = hvm_vioapic_read_indirect(s, addr, length);
   7.186 +    case VIOAPIC_REG_WINDOW:
   7.187 +        result = vioapic_read_indirect(vioapic, addr, length);
   7.188          break;
   7.189  
   7.190      default:
   7.191 -          break;
   7.192 +        result = 0;
   7.193 +        break;
   7.194      }
   7.195  
   7.196      return result;
   7.197  }
   7.198  
   7.199 -static void hvm_vioapic_update_imr(struct hvm_vioapic *s, int index)
   7.200 +static void vioapic_update_imr(struct vioapic *vioapic, int index)
   7.201  {
   7.202 -   if (s->redirtbl[index].RedirForm.mask)
   7.203 -       set_bit(index, &s->imr);
   7.204 -   else
   7.205 -       clear_bit(index, &s->imr);
   7.206 +    if ( vioapic->redirtbl[index].fields.mask )
   7.207 +        set_bit(index, &vioapic->imr);
   7.208 +    else
   7.209 +        clear_bit(index, &vioapic->imr);
   7.210  }
   7.211  
   7.212  
   7.213 -static void hvm_vioapic_write_indirect(struct hvm_vioapic *s,
   7.214 -                                      unsigned long addr,
   7.215 -                                      unsigned long length,
   7.216 -                                      unsigned long val)
   7.217 +static void vioapic_write_indirect(struct vioapic *vioapic,
   7.218 +                                   unsigned long addr,
   7.219 +                                   unsigned long length,
   7.220 +                                   unsigned long val)
   7.221  {
   7.222 -    switch (s->ioregsel) {
   7.223 -    case IOAPIC_REG_VERSION:
   7.224 -        printk("hvm_vioapic_write_indirect: version register read only\n");
   7.225 +    switch ( vioapic->ioregsel )
   7.226 +    {
   7.227 +    case VIOAPIC_REG_VERSION:
   7.228 +        /* Writes are ignored. */
   7.229          break;
   7.230  
   7.231 -#ifndef __ia64__
   7.232 -    case IOAPIC_REG_APIC_ID:
   7.233 -        s->id = (val >> 24) & 0xf;
   7.234 +#if !VIOAPIC_IS_IOSAPIC
   7.235 +    case VIOAPIC_REG_APIC_ID:
   7.236 +        vioapic->id = (val >> 24) & 0xf;
   7.237          break;
   7.238  
   7.239 -    case IOAPIC_REG_ARB_ID:
   7.240 -        s->arb_id = val;
   7.241 +    case VIOAPIC_REG_ARB_ID:
   7.242          break;
   7.243  #endif
   7.244  
   7.245      default:
   7.246 -        {
   7.247 -            uint32_t redir_index = 0;
   7.248 -
   7.249 -            redir_index = (s->ioregsel - 0x10) >> 1;
   7.250 -
   7.251 -            HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "hvm_vioapic_write_indirect "
   7.252 -              "change redir index %x val %lx\n",
   7.253 -              redir_index, val);
   7.254 -
   7.255 -            if (redir_index >= 0 && redir_index < IOAPIC_NUM_PINS) {
   7.256 -                uint64_t redir_content;
   7.257 -
   7.258 -                redir_content = s->redirtbl[redir_index].value;
   7.259 +    {
   7.260 +        uint32_t redir_index = (vioapic->ioregsel - 0x10) >> 1;
   7.261 +        uint64_t redir_content;
   7.262  
   7.263 -                if (s->ioregsel & 0x1) {
   7.264 -#ifdef IRQ0_SPECIAL_ROUTING
   7.265 -                    if ( !redir_warning_done && (redir_index == 0) &&
   7.266 -                         ((val >> 24) != 0) ) {
   7.267 -                        /*
   7.268 -                         * Cannot yet handle delivering PIT interrupts to
   7.269 -                         * any VCPU != 0. Needs proper fixing, but for now
   7.270 -                         * simply spit a warning that we're going to ignore
   7.271 -                         * the target in practice & always deliver to VCPU 0
   7.272 -                         */
   7.273 -                        printk("IO-APIC: PIT (IRQ0) redirect to VCPU %lx "
   7.274 -                               "will be ignored.\n", val >> 24); 
   7.275 -                        redir_warning_done = 1;
   7.276 -                    }
   7.277 -#endif
   7.278 -                    redir_content = (((uint64_t)val & 0xffffffff) << 32) |
   7.279 -                                    (redir_content & 0xffffffff);
   7.280 -                } else
   7.281 -                    redir_content = ((redir_content >> 32) << 32) |
   7.282 -                                    (val & 0xffffffff);
   7.283 -                s->redirtbl[redir_index].value = redir_content;
   7.284 -                hvm_vioapic_update_imr(s, redir_index);
   7.285 -            } else  {
   7.286 -                printk("hvm_vioapic_write_indirect "
   7.287 -                  "error register %x\n", s->ioregsel);
   7.288 -            }
   7.289 +        HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "vioapic_write_indirect "
   7.290 +                    "change redir index %x val %lx\n",
   7.291 +                    redir_index, val);
   7.292 +
   7.293 +        if ( redir_index >= VIOAPIC_NUM_PINS )
   7.294 +        {
   7.295 +            gdprintk(XENLOG_WARNING, "vioapic_write_indirect "
   7.296 +                     "error register %x\n", vioapic->ioregsel);
   7.297              break;
   7.298          }
   7.299 +
   7.300 +        redir_content = vioapic->redirtbl[redir_index].bits;
   7.301 +
   7.302 +        if ( vioapic->ioregsel & 0x1 )
   7.303 +        {
   7.304 +#ifdef IRQ0_SPECIAL_ROUTING
   7.305 +            if ( !redir_warning_done && (redir_index == 0) &&
   7.306 +                 ((val >> 24) != 0) )
   7.307 +            {
   7.308 +                /*
   7.309 +                 * Cannot yet handle delivering PIT interrupts to any VCPU != 
   7.310 +                 * 0. Needs proper fixing, but for now simply spit a warning 
   7.311 +                 * that we're going to ignore the target in practice and always
   7.312 +                 * deliver to VCPU 0.
   7.313 +                 */
   7.314 +                printk("IO-APIC: PIT (IRQ0) redirect to VCPU %lx "
   7.315 +                       "will be ignored.\n", val >> 24); 
   7.316 +                redir_warning_done = 1;
   7.317 +            }
   7.318 +#endif
   7.319 +            redir_content = (((uint64_t)val & 0xffffffff) << 32) |
   7.320 +                (redir_content & 0xffffffff);
   7.321 +        }
   7.322 +        else
   7.323 +        {
   7.324 +            redir_content = ((redir_content >> 32) << 32) |
   7.325 +                (val & 0xffffffff);
   7.326 +        }
   7.327 +        vioapic->redirtbl[redir_index].bits = redir_content;
   7.328 +        vioapic_update_imr(vioapic, redir_index);
   7.329 +        break;
   7.330 +    }
   7.331      } /* switch */
   7.332  }
   7.333  
   7.334 -static void hvm_vioapic_write(struct vcpu *v,
   7.335 -                             unsigned long addr,
   7.336 -                             unsigned long length,
   7.337 -                             unsigned long val)
   7.338 +static void vioapic_write(struct vcpu *v,
   7.339 +                          unsigned long addr,
   7.340 +                          unsigned long length,
   7.341 +                          unsigned long val)
   7.342  {
   7.343 -    hvm_vioapic_t *s = &(v->domain->arch.hvm_domain.vioapic);
   7.344 -
   7.345 -    ASSERT(s);
   7.346 +    struct vioapic *vioapic = domain_vioapic(v->domain);
   7.347  
   7.348      addr &= 0xff;
   7.349  
   7.350 -    switch (addr) {
   7.351 -    case IOAPIC_REG_SELECT:
   7.352 -        s->ioregsel = val;
   7.353 +    switch ( addr )
   7.354 +    {
   7.355 +    case VIOAPIC_REG_SELECT:
   7.356 +        vioapic->ioregsel = val;
   7.357          break;
   7.358  
   7.359 -    case IOAPIC_REG_WINDOW:
   7.360 -        hvm_vioapic_write_indirect(s, addr, length, val);
   7.361 +    case VIOAPIC_REG_WINDOW:
   7.362 +        vioapic_write_indirect(vioapic, addr, length, val);
   7.363          break;
   7.364  
   7.365 -#ifdef __ia64__
   7.366 -    case IOAPIC_REG_EOI:
   7.367 -        ioapic_update_EOI(v->domain, val);
   7.368 +#if VIOAPIC_IS_IOSAPIC
   7.369 +    case VIOAPIC_REG_EOI:
   7.370 +        vioapic_update_EOI(v->domain, val);
   7.371          break;
   7.372  #endif
   7.373  
   7.374 @@ -257,49 +243,34 @@ static void hvm_vioapic_write(struct vcp
   7.375      }
   7.376  }
   7.377  
   7.378 -static int hvm_vioapic_range(struct vcpu *v, unsigned long addr)
   7.379 +static int vioapic_range(struct vcpu *v, unsigned long addr)
   7.380  {
   7.381 -    hvm_vioapic_t *s = &(v->domain->arch.hvm_domain.vioapic);
   7.382 +    struct vioapic *vioapic = domain_vioapic(v->domain);
   7.383  
   7.384 -    if ((s->flags & IOAPIC_ENABLE_FLAG) &&
   7.385 -        (addr >= s->base_address &&
   7.386 -        (addr < s->base_address + IOAPIC_MEM_LENGTH)))
   7.387 -        return 1;
   7.388 -    else
   7.389 -        return 0;
   7.390 +    return ((addr >= vioapic->base_address &&
   7.391 +             (addr < vioapic->base_address + VIOAPIC_MEM_LENGTH)));
   7.392  }
   7.393  
   7.394  struct hvm_mmio_handler vioapic_mmio_handler = {
   7.395 -    .check_handler = hvm_vioapic_range,
   7.396 -    .read_handler = hvm_vioapic_read,
   7.397 -    .write_handler = hvm_vioapic_write
   7.398 +    .check_handler = vioapic_range,
   7.399 +    .read_handler = vioapic_read,
   7.400 +    .write_handler = vioapic_write
   7.401  };
   7.402  
   7.403 -static void hvm_vioapic_reset(hvm_vioapic_t *s)
   7.404 +static void vioapic_reset(struct vioapic *vioapic)
   7.405  {
   7.406      int i;
   7.407  
   7.408 -    memset(s, 0, sizeof(hvm_vioapic_t));
   7.409 +    memset(vioapic, 0, sizeof(*vioapic));
   7.410  
   7.411 -    for (i = 0; i < IOAPIC_NUM_PINS; i++) {
   7.412 -        s->redirtbl[i].RedirForm.mask = 0x1;
   7.413 -        hvm_vioapic_update_imr(s, i);
   7.414 +    for ( i = 0; i < VIOAPIC_NUM_PINS; i++ )
   7.415 +    {
   7.416 +        vioapic->redirtbl[i].fields.mask = 0x1;
   7.417 +        vioapic_update_imr(vioapic, i);
   7.418      }
   7.419  }
   7.420  
   7.421 -static void ioapic_update_config(hvm_vioapic_t *s,
   7.422 -                                 unsigned long address,
   7.423 -                                 uint8_t enable)
   7.424 -{
   7.425 -    ASSERT(s);
   7.426 -
   7.427 -    ioapic_enable(s, enable);
   7.428 -
   7.429 -    if (address != s->base_address)
   7.430 -        s->base_address = address;
   7.431 -}
   7.432 -
   7.433 -static int ioapic_inj_irq(hvm_vioapic_t *s,
   7.434 +static int ioapic_inj_irq(struct vioapic *vioapic,
   7.435                            struct vlapic * target,
   7.436                            uint8_t vector,
   7.437                            uint8_t trig_mode,
   7.438 @@ -307,65 +278,64 @@ static int ioapic_inj_irq(hvm_vioapic_t 
   7.439  {
   7.440      int result = 0;
   7.441  
   7.442 -    ASSERT(s && target);
   7.443 +    HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "ioapic_inj_irq "
   7.444 +                "irq %d trig %d delive mode %d\n",
   7.445 +                vector, trig_mode, delivery_mode);
   7.446  
   7.447 -    HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "ioapic_inj_irq "
   7.448 -      "irq %d trig %d delive mode %d\n",
   7.449 -      vector, trig_mode, delivery_mode);
   7.450 -
   7.451 -    switch (delivery_mode) {
   7.452 +    switch ( delivery_mode )
   7.453 +    {
   7.454      case dest_Fixed:
   7.455      case dest_LowestPrio:
   7.456 -        if (vlapic_set_irq(target, vector, trig_mode) && (trig_mode == 1))
   7.457 -            printk("<ioapic_inj_irq> level interrupt happen before cleared\n");
   7.458 +        if ( vlapic_set_irq(target, vector, trig_mode) && (trig_mode == 1) )
   7.459 +            gdprintk(XENLOG_WARNING, "level interrupt before cleared\n");
   7.460          result = 1;
   7.461          break;
   7.462      default:
   7.463 -        printk("<ioapic_inj_irq> error delivery mode %d\n",
   7.464 -                delivery_mode);
   7.465 +        gdprintk(XENLOG_WARNING, "error delivery mode %d\n", delivery_mode);
   7.466          break;
   7.467 -   }
   7.468 +    }
   7.469  
   7.470 -   return result;
   7.471 +    return result;
   7.472  }
   7.473  
   7.474  #ifndef __ia64__
   7.475 -static int ioapic_match_logical_addr(hvm_vioapic_t *s, int number, uint8_t dest)
   7.476 +static int ioapic_match_logical_addr(
   7.477 +    struct vioapic *vioapic, int number, uint8_t dest)
   7.478  {
   7.479      int result = 0;
   7.480 -    uint32_t logical_dest = vlapic_get_reg(s->lapic_info[number], APIC_LDR);
   7.481 -
   7.482 -    ASSERT(s && s->lapic_info[number]);
   7.483 +    uint32_t logical_dest;
   7.484  
   7.485      HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "ioapic_match_logical_addr "
   7.486 -      "number %i dest %x\n",
   7.487 -      number, dest);
   7.488 +                "number %i dest %x\n",
   7.489 +                number, dest);
   7.490  
   7.491 -    switch (vlapic_get_reg(s->lapic_info[number], APIC_DFR))
   7.492 +    logical_dest = vlapic_get_reg(vioapic->lapic_info[number], APIC_LDR);
   7.493 +
   7.494 +    switch ( vlapic_get_reg(vioapic->lapic_info[number], APIC_DFR) )
   7.495      {
   7.496      case APIC_DFR_FLAT:
   7.497 -        result =
   7.498 -          (dest & GET_APIC_LOGICAL_ID(logical_dest)) != 0;
   7.499 +        result = ((dest & GET_APIC_LOGICAL_ID(logical_dest)) != 0);
   7.500          break;
   7.501      case APIC_DFR_CLUSTER:
   7.502          /* Should we support flat cluster mode ?*/
   7.503          if ( (GET_APIC_LOGICAL_ID(logical_dest) >> 4
   7.504 -               == ((dest >> 0x4) & 0xf)) &&
   7.505 +              == ((dest >> 0x4) & 0xf)) &&
   7.506               (logical_dest & (dest  & 0xf)) )
   7.507              result = 1;
   7.508          break;
   7.509      default:
   7.510 -        printk("error DFR value for %x local apic\n", number);
   7.511 +        gdprintk(XENLOG_WARNING, "error DFR value for %x lapic\n", number);
   7.512          break;
   7.513      }
   7.514  
   7.515      return result;
   7.516  }
   7.517  #else
   7.518 -extern int ioapic_match_logical_addr(hvm_vioapic_t *s, int number, uint8_t dest);
   7.519 +extern int ioapic_match_logical_addr(
   7.520 +    struct vioapic *vioapic, int number, uint8_t dest);
   7.521  #endif
   7.522  
   7.523 -static uint32_t ioapic_get_delivery_bitmask(hvm_vioapic_t *s,
   7.524 +static uint32_t ioapic_get_delivery_bitmask(struct vioapic *vioapic,
   7.525                                              uint16_t dest,
   7.526                                              uint8_t dest_mode,
   7.527                                              uint8_t vector,
   7.528 @@ -375,18 +345,16 @@ static uint32_t ioapic_get_delivery_bitm
   7.529      int i;
   7.530  
   7.531      HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "ioapic_get_delivery_bitmask "
   7.532 -      "dest %d dest_mode %d "
   7.533 -      "vector %d del_mode %d, lapic_count %d\n",
   7.534 -      dest, dest_mode, vector, delivery_mode, s->lapic_count);
   7.535 -
   7.536 -    ASSERT(s);
   7.537 +                "dest %d dest_mode %d "
   7.538 +                "vector %d del_mode %d, lapic_count %d\n",
   7.539 +                dest, dest_mode, vector, delivery_mode, vioapic->lapic_count);
   7.540  
   7.541      if ( dest_mode == 0 )
   7.542      {
   7.543          /* Physical mode. */
   7.544 -        for ( i = 0; i < s->lapic_count; i++ )
   7.545 +        for ( i = 0; i < vioapic->lapic_count; i++ )
   7.546          {
   7.547 -            if ( VLAPIC_ID(s->lapic_info[i]) == dest )
   7.548 +            if ( VLAPIC_ID(vioapic->lapic_info[i]) == dest )
   7.549              {
   7.550                  mask = 1 << i;
   7.551                  break;
   7.552 @@ -396,7 +364,7 @@ static uint32_t ioapic_get_delivery_bitm
   7.553          /* Broadcast. */
   7.554          if ( dest == 0xFF )
   7.555          {
   7.556 -            for ( i = 0; i < s->lapic_count; i++ )
   7.557 +            for ( i = 0; i < vioapic->lapic_count; i++ )
   7.558                  mask |= ( 1 << i );
   7.559          }
   7.560      }
   7.561 @@ -405,63 +373,67 @@ static uint32_t ioapic_get_delivery_bitm
   7.562          /* Logical destination. Call match_logical_addr for each APIC. */
   7.563          if ( dest != 0 )
   7.564          {
   7.565 -            for ( i = 0; i < s->lapic_count; i++ )
   7.566 +            for ( i = 0; i < vioapic->lapic_count; i++ )
   7.567              {
   7.568 -                if ( s->lapic_info[i] &&
   7.569 -                     ioapic_match_logical_addr(s, i, dest) )
   7.570 +                if ( vioapic->lapic_info[i] &&
   7.571 +                     ioapic_match_logical_addr(vioapic, i, dest) )
   7.572                      mask |= (1<<i);
   7.573              }
   7.574          }
   7.575      }
   7.576  
   7.577      HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "ioapic_get_delivery_bitmask "
   7.578 -      "mask %x\n", mask);
   7.579 +                "mask %x\n", mask);
   7.580  
   7.581      return mask;
   7.582  }
   7.583  
   7.584 -static void ioapic_deliver(hvm_vioapic_t *s, int irqno)
   7.585 +static void ioapic_deliver(struct vioapic *vioapic, int irq)
   7.586  {
   7.587 -    uint16_t dest = s->redirtbl[irqno].RedirForm.dest_id;
   7.588 -    uint8_t dest_mode = s->redirtbl[irqno].RedirForm.destmode;
   7.589 -    uint8_t delivery_mode = s->redirtbl[irqno].RedirForm.deliver_mode;
   7.590 -    uint8_t vector = s->redirtbl[irqno].RedirForm.vector;
   7.591 -    uint8_t trig_mode = s->redirtbl[irqno].RedirForm.trigmod;
   7.592 +    uint16_t dest = vioapic->redirtbl[irq].fields.dest_id;
   7.593 +    uint8_t dest_mode = vioapic->redirtbl[irq].fields.dest_mode;
   7.594 +    uint8_t delivery_mode = vioapic->redirtbl[irq].fields.delivery_mode;
   7.595 +    uint8_t vector = vioapic->redirtbl[irq].fields.vector;
   7.596 +    uint8_t trig_mode = vioapic->redirtbl[irq].fields.trig_mode;
   7.597      uint32_t deliver_bitmask;
   7.598      struct vlapic *target;
   7.599  
   7.600      HVM_DBG_LOG(DBG_LEVEL_IOAPIC,
   7.601 -      "dest %x dest_mode %x delivery_mode %x vector %x trig_mode %x\n",
   7.602 -      dest, dest_mode, delivery_mode, vector, trig_mode);
   7.603 +                "dest %x dest_mode %x delivery_mode %x vector %x trig_mode %x\n",
   7.604 +                dest, dest_mode, delivery_mode, vector, trig_mode);
   7.605  
   7.606      deliver_bitmask = ioapic_get_delivery_bitmask(
   7.607 -        s, dest, dest_mode, vector, delivery_mode);
   7.608 -
   7.609 -    if (!deliver_bitmask) {
   7.610 +        vioapic, dest, dest_mode, vector, delivery_mode);
   7.611 +    if ( !deliver_bitmask )
   7.612 +    {
   7.613          HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "ioapic deliver "
   7.614 -          "no target on destination\n");
   7.615 -
   7.616 +                    "no target on destination\n");
   7.617          return;
   7.618      }
   7.619  
   7.620 -    switch (delivery_mode) {
   7.621 +    switch ( delivery_mode )
   7.622 +    {
   7.623      case dest_LowestPrio:
   7.624      {
   7.625  #ifdef IRQ0_SPECIAL_ROUTING
   7.626          /* Force round-robin to pick VCPU 0 */
   7.627 -        if (irqno == 0)
   7.628 -            target = s->lapic_info[0];
   7.629 +        if ( irq == 0 )
   7.630 +            target = vioapic->lapic_info[0];
   7.631          else
   7.632  #endif
   7.633 -            target = apic_round_robin(s->domain, dest_mode,
   7.634 +            target = apic_round_robin(vioapic_domain(vioapic), dest_mode,
   7.635                                        vector, deliver_bitmask);
   7.636 -        if (target) {
   7.637 -            ioapic_inj_irq(s, target, vector, trig_mode, delivery_mode);
   7.638 +        if ( target != NULL )
   7.639 +        {
   7.640 +            ioapic_inj_irq(vioapic, target, vector, trig_mode, delivery_mode);
   7.641              vcpu_kick(vlapic_vcpu(target));
   7.642 -        } else
   7.643 +        }
   7.644 +        else
   7.645 +        {
   7.646              HVM_DBG_LOG(DBG_LEVEL_IOAPIC,
   7.647 -              "null round robin mask %x vector %x delivery_mode %x\n",
   7.648 -              deliver_bitmask, vector, dest_LowestPrio);
   7.649 +                        "null round robin mask %x vector %x delivery_mode %x\n",
   7.650 +                        deliver_bitmask, vector, dest_LowestPrio);
   7.651 +        }
   7.652          break;
   7.653      }
   7.654  
   7.655 @@ -469,18 +441,21 @@ static void ioapic_deliver(hvm_vioapic_t
   7.656      case dest_ExtINT:
   7.657      {
   7.658          uint8_t bit;
   7.659 -        for (bit = 0; bit < s->lapic_count; bit++) {
   7.660 +        for ( bit = 0; bit < vioapic->lapic_count; bit++ )
   7.661 +        {
   7.662              if ( !(deliver_bitmask & (1 << bit)) )
   7.663                  continue;
   7.664  #ifdef IRQ0_SPECIAL_ROUTING
   7.665              /* Do not deliver timer interrupts to VCPU != 0 */
   7.666 -            if ( (irqno == 0) && (bit !=0 ) )
   7.667 -                target = s->lapic_info[0];
   7.668 +            if ( (irq == 0) && (bit != 0) )
   7.669 +                target = vioapic->lapic_info[0];
   7.670              else
   7.671  #endif
   7.672 -                target = s->lapic_info[bit];
   7.673 -            if (target) {
   7.674 -                ioapic_inj_irq(s, target, vector, trig_mode, delivery_mode);
   7.675 +                target = vioapic->lapic_info[bit];
   7.676 +            if ( target != NULL )
   7.677 +            {
   7.678 +                ioapic_inj_irq(vioapic, target, vector,
   7.679 +                               trig_mode, delivery_mode);
   7.680                  vcpu_kick(vlapic_vcpu(target));
   7.681              }
   7.682          }
   7.683 @@ -492,164 +467,160 @@ static void ioapic_deliver(hvm_vioapic_t
   7.684      case dest_INIT:
   7.685      case dest__reserved_2:
   7.686      default:
   7.687 -        printk("Not support delivey mode %d\n", delivery_mode);
   7.688 +        gdprintk(XENLOG_WARNING, "Unsupported delivery mode %d\n",
   7.689 +                 delivery_mode);
   7.690          break;
   7.691      }
   7.692  }
   7.693  
   7.694 -static int ioapic_get_highest_irq(hvm_vioapic_t *s)
   7.695 +static int ioapic_get_highest_irq(struct vioapic *vioapic)
   7.696  {
   7.697 -    uint32_t irqs = (s->irr | s->irr_xen) & ~s->isr & ~s->imr;
   7.698 +    uint32_t irqs = vioapic->irr | vioapic->irr_xen;
   7.699 +    irqs &= ~vioapic->isr & ~vioapic->imr;
   7.700      return fls(irqs) - 1;
   7.701  }
   7.702  
   7.703 -static void service_ioapic(hvm_vioapic_t *s)
   7.704 +static void service_ioapic(struct vioapic *vioapic)
   7.705  {
   7.706 -    int irqno;
   7.707 +    int irq;
   7.708  
   7.709 -    while ((irqno = ioapic_get_highest_irq(s)) != -1) {
   7.710 -
   7.711 -        HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "service_ioapic "
   7.712 -          "highest irqno %x\n", irqno);
   7.713 +    while ( (irq = ioapic_get_highest_irq(vioapic)) != -1 )
   7.714 +    {
   7.715 +        HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "service_ioapic highest irq %x\n", irq);
   7.716  
   7.717 -        if (!test_bit(irqno, &s->imr)) {
   7.718 -            ioapic_deliver(s, irqno);
   7.719 -        }
   7.720 +        if ( !test_bit(irq, &vioapic->imr) )
   7.721 +            ioapic_deliver(vioapic, irq);
   7.722  
   7.723 -        if (s->redirtbl[irqno].RedirForm.trigmod == IOAPIC_LEVEL_TRIGGER) {
   7.724 -            s->isr |= (1 << irqno);
   7.725 -        }
   7.726 +        if ( vioapic->redirtbl[irq].fields.trig_mode == VIOAPIC_LEVEL_TRIG )
   7.727 +            vioapic->isr |= (1 << irq);
   7.728  
   7.729 -        s->irr &= ~(1 << irqno);
   7.730 -	s->irr_xen &= ~(1 << irqno);
   7.731 +        vioapic->irr     &= ~(1 << irq);
   7.732 +        vioapic->irr_xen &= ~(1 << irq);
   7.733      }
   7.734  }
   7.735  
   7.736 -void hvm_vioapic_set_xen_irq(struct domain *d, int irq, int level)
   7.737 +void vioapic_set_xen_irq(struct domain *d, int irq, int level)
   7.738  {
   7.739 -    hvm_vioapic_t *s = &d->arch.hvm_domain.vioapic;
   7.740 +    struct vioapic *vioapic = domain_vioapic(d);
   7.741  
   7.742 -    if (!IOAPICEnabled(s) || s->redirtbl[irq].RedirForm.mask)
   7.743 +    if ( vioapic->redirtbl[irq].fields.mask )
   7.744          return;
   7.745  
   7.746 -    if (s->redirtbl[irq].RedirForm.trigmod != IOAPIC_LEVEL_TRIGGER)
   7.747 -	gdprintk(XENLOG_WARNING, "Forcing edge triggered APIC irq %d?\n", irq);
   7.748 +    if ( vioapic->redirtbl[irq].fields.trig_mode == VIOAPIC_EDGE_TRIG )
   7.749 +        gdprintk(XENLOG_WARNING, "Forcing edge triggered APIC irq %d?\n", irq);
   7.750  
   7.751 -    if (level)
   7.752 -	s->irr_xen |= 1 << irq;
   7.753 +    if ( level )
   7.754 +        vioapic->irr_xen |= 1 << irq;
   7.755      else
   7.756 -	s->irr_xen &= ~(1 << irq);
   7.757 +        vioapic->irr_xen &= ~(1 << irq);
   7.758  }
   7.759  
   7.760 -void hvm_vioapic_set_irq(struct domain *d, int irq, int level)
   7.761 +void vioapic_set_irq(struct domain *d, int irq, int level)
   7.762  {
   7.763 -    hvm_vioapic_t *s = &(d->arch.hvm_domain.vioapic);
   7.764 +    struct vioapic *vioapic = domain_vioapic(d);
   7.765  
   7.766      HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "ioapic_set_irq "
   7.767 -      "irq %x level %x\n", irq, level);
   7.768 +                "irq %x level %x\n", irq, level);
   7.769  
   7.770 -    if ( (irq < 0) || (irq >= IOAPIC_NUM_PINS) )
   7.771 +    if ( (irq < 0) || (irq >= VIOAPIC_NUM_PINS) )
   7.772 +        return;
   7.773 +
   7.774 +    if ( vioapic->redirtbl[irq].fields.mask )
   7.775          return;
   7.776  
   7.777 -    if ( !IOAPICEnabled(s) || s->redirtbl[irq].RedirForm.mask )
   7.778 -        return;
   7.779 +    HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "vioapic_set_irq entry %x "
   7.780 +                "vector %x delivery_mode %x dest_mode %x delivery_status %x "
   7.781 +                "polarity %x remote_irr %x trig_mode %x mask %x dest_id %x\n",
   7.782 +                irq,
   7.783 +                vioapic->redirtbl[irq].fields.vector,
   7.784 +                vioapic->redirtbl[irq].fields.delivery_mode,
   7.785 +                vioapic->redirtbl[irq].fields.dest_mode,
   7.786 +                vioapic->redirtbl[irq].fields.delivery_status,
   7.787 +                vioapic->redirtbl[irq].fields.polarity,
   7.788 +                vioapic->redirtbl[irq].fields.remote_irr,
   7.789 +                vioapic->redirtbl[irq].fields.trig_mode,
   7.790 +                vioapic->redirtbl[irq].fields.mask,
   7.791 +                vioapic->redirtbl[irq].fields.dest_id);
   7.792  
   7.793 -    HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "hvm_vioapic_set_irq entry %x "
   7.794 -      "vector %x deliver_mod %x destmode %x delivestatus %x "
   7.795 -      "polarity %x remote_irr %x trigmod %x mask %x dest_id %x\n",
   7.796 -      irq,
   7.797 -      s->redirtbl[irq].RedirForm.vector,
   7.798 -      s->redirtbl[irq].RedirForm.deliver_mode,
   7.799 -      s->redirtbl[irq].RedirForm.destmode,
   7.800 -      s->redirtbl[irq].RedirForm.delivestatus,
   7.801 -      s->redirtbl[irq].RedirForm.polarity,
   7.802 -      s->redirtbl[irq].RedirForm.remoteirr,
   7.803 -      s->redirtbl[irq].RedirForm.trigmod,
   7.804 -      s->redirtbl[irq].RedirForm.mask,
   7.805 -      s->redirtbl[irq].RedirForm.dest_id);
   7.806 -
   7.807 -    if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
   7.808 +    if ( (irq >= 0) && (irq < VIOAPIC_NUM_PINS) )
   7.809 +    {
   7.810          uint32_t bit = 1 << irq;
   7.811 -        if (s->redirtbl[irq].RedirForm.trigmod == IOAPIC_LEVEL_TRIGGER) {
   7.812 -            if (level)
   7.813 -                s->irr |= bit;
   7.814 +        if ( vioapic->redirtbl[irq].fields.trig_mode == VIOAPIC_LEVEL_TRIG )
   7.815 +        {
   7.816 +            if ( level )
   7.817 +                vioapic->irr |= bit;
   7.818              else
   7.819 -                s->irr &= ~bit;
   7.820 -        } else {
   7.821 -            if (level)
   7.822 +                vioapic->irr &= ~bit;
   7.823 +        }
   7.824 +        else
   7.825 +        {
   7.826 +            if ( level )
   7.827                  /* XXX No irr clear for edge interrupt */
   7.828 -                s->irr |= bit;
   7.829 +                vioapic->irr |= bit;
   7.830          }
   7.831      }
   7.832  
   7.833 -    service_ioapic(s);
   7.834 +    service_ioapic(vioapic);
   7.835  }
   7.836  
   7.837  /* XXX If level interrupt, use vector->irq table for performance */
   7.838 -static int get_redir_num(hvm_vioapic_t *s, int vector)
   7.839 +static int get_redir_num(struct vioapic *vioapic, int vector)
   7.840  {
   7.841 -    int i = 0;
   7.842 +    int i;
   7.843  
   7.844 -    ASSERT(s);
   7.845 -
   7.846 -    for(i = 0; i < IOAPIC_NUM_PINS; i++) {
   7.847 -        if (s->redirtbl[i].RedirForm.vector == vector)
   7.848 +    for ( i = 0; i < VIOAPIC_NUM_PINS; i++ )
   7.849 +        if ( vioapic->redirtbl[i].fields.vector == vector )
   7.850              return i;
   7.851 -    }
   7.852  
   7.853      return -1;
   7.854  }
   7.855  
   7.856 -void ioapic_update_EOI(struct domain *d, int vector)
   7.857 +void vioapic_update_EOI(struct domain *d, int vector)
   7.858  {
   7.859 -    hvm_vioapic_t *s = &(d->arch.hvm_domain.vioapic);
   7.860 +    struct vioapic *vioapic = domain_vioapic(d);
   7.861      int redir_num;
   7.862  
   7.863 -    if ((redir_num = get_redir_num(s, vector)) == -1) {
   7.864 -        printk("Can't find redir item for %d EOI \n", vector);
   7.865 +    if ( (redir_num = get_redir_num(vioapic, vector)) == -1 )
   7.866 +    {
   7.867 +        gdprintk(XENLOG_WARNING, "Can't find redir item for %d EOI\n", vector);
   7.868          return;
   7.869      }
   7.870  
   7.871 -    if (!test_and_clear_bit(redir_num, &s->isr)) {
   7.872 -        printk("redir %d not set for %d  EOI\n", redir_num, vector);
   7.873 +    if ( !test_and_clear_bit(redir_num, &vioapic->isr) )
   7.874 +    {
   7.875 +        gdprintk(XENLOG_WARNING, "redir %d not set for %d EOI\n",
   7.876 +                 redir_num, vector);
   7.877          return;
   7.878      }
   7.879  }
   7.880  
   7.881 -int hvm_vioapic_add_lapic(struct vlapic *vlapic, struct vcpu *v)
   7.882 +int vioapic_add_lapic(struct vlapic *vlapic, struct vcpu *v)
   7.883  {
   7.884 -    hvm_vioapic_t *s = &(v->domain->arch.hvm_domain.vioapic);
   7.885 +    struct vioapic *vioapic = domain_vioapic(v->domain);
   7.886  
   7.887 -    if (v->vcpu_id != s->lapic_count) {
   7.888 -        printk("hvm_vioapic_add_lapic "
   7.889 -           "cpu_id not match vcpu_id %x lapic_count %x\n",
   7.890 -           v->vcpu_id, s->lapic_count);
   7.891 +    if ( v->vcpu_id != vioapic->lapic_count )
   7.892 +    {
   7.893 +        gdprintk(XENLOG_ERR, "vioapic_add_lapic "
   7.894 +                 "cpu_id not match vcpu_id %x lapic_count %x\n",
   7.895 +                 v->vcpu_id, vioapic->lapic_count);
   7.896          domain_crash_synchronous();
   7.897      }
   7.898  
   7.899 -    /* update count later for race condition on interrupt */
   7.900 -    s->lapic_info[s->lapic_count] = vlapic;
   7.901 -    s->lapic_count ++;
   7.902 +    /* Update count later for race condition on interrupt. */
   7.903 +    vioapic->lapic_info[vioapic->lapic_count] = vlapic;
   7.904 +    wmb();
   7.905 +    vioapic->lapic_count++;
   7.906  
   7.907 -    return s->lapic_count;
   7.908 +    return vioapic->lapic_count;
   7.909  }
   7.910  
   7.911 -hvm_vioapic_t * hvm_vioapic_init(struct domain *d)
   7.912 +void vioapic_init(struct domain *d)
   7.913  {
   7.914 -    int i = 0;
   7.915 -    hvm_vioapic_t *s = &(d->arch.hvm_domain.vioapic);
   7.916 -
   7.917 -    HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "hvm_vioapic_init\n");
   7.918 -
   7.919 -    hvm_vioapic_reset(s);
   7.920 +    struct vioapic *vioapic = domain_vioapic(d);
   7.921  
   7.922 -    s->domain = d;
   7.923 -
   7.924 -    for (i = 0; i < MAX_LAPIC_NUM; i++)
   7.925 -        s->lapic_info[i] = NULL;
   7.926 +    HVM_DBG_LOG(DBG_LEVEL_IOAPIC, "vioapic_init\n");
   7.927  
   7.928 -    /* Remove after GFW ready */
   7.929 -    ioapic_update_config(s, IOAPIC_DEFAULT_BASE_ADDRESS, 1);
   7.930 +    vioapic_reset(vioapic);
   7.931  
   7.932 -    return s;
   7.933 +    vioapic->base_address = VIOAPIC_DEFAULT_BASE_ADDRESS;
   7.934  }
     8.1 --- a/xen/arch/x86/hvm/vlapic.c	Tue Nov 07 15:48:10 2006 +0000
     8.2 +++ b/xen/arch/x86/hvm/vlapic.c	Tue Nov 07 17:46:40 2006 +0000
     8.3 @@ -432,7 +432,7 @@ void vlapic_EOI_set(struct vlapic *vlapi
     8.4      vlapic_clear_vector(vector, vlapic->regs + APIC_ISR);
     8.5  
     8.6      if ( vlapic_test_and_clear_vector(vector, vlapic->regs + APIC_TMR) )
     8.7 -        ioapic_update_EOI(vlapic_domain(vlapic), vector);
     8.8 +        vioapic_update_EOI(vlapic_domain(vlapic), vector);
     8.9  }
    8.10  
    8.11  static void vlapic_ipi(struct vlapic *vlapic)
    8.12 @@ -1001,7 +1001,7 @@ int vlapic_init(struct vcpu *v)
    8.13      if ( v->vcpu_id == 0 )
    8.14          vlapic->apic_base_msr |= MSR_IA32_APICBASE_BSP;
    8.15  
    8.16 -    hvm_vioapic_add_lapic(vlapic, v);
    8.17 +    vioapic_add_lapic(vlapic, v);
    8.18  
    8.19      init_timer(&vlapic->vlapic_timer,
    8.20                    vlapic_timer_fn, vlapic, v->processor);
     9.1 --- a/xen/arch/x86/hvm/vmx/io.c	Tue Nov 07 15:48:10 2006 +0000
     9.2 +++ b/xen/arch/x86/hvm/vmx/io.c	Tue Nov 07 17:46:40 2006 +0000
     9.3 @@ -99,7 +99,7 @@ asmlinkage void vmx_intr_assist(void)
     9.4      struct vlapic *vlapic = vcpu_vlapic(v);
     9.5      struct hvm_domain *plat=&v->domain->arch.hvm_domain;
     9.6      struct periodic_time *pt = &plat->pl_time.periodic_tm;
     9.7 -    struct hvm_virpic *pic= &plat->vpic;
     9.8 +    struct vpic *pic= &plat->vpic;
     9.9      unsigned int idtv_info_field;
    9.10      unsigned long inst_len;
    9.11      int    has_ext_irq;
    10.1 --- a/xen/include/asm-ia64/vmx_platform.h	Tue Nov 07 15:48:10 2006 +0000
    10.2 +++ b/xen/include/asm-ia64/vmx_platform.h	Tue Nov 07 17:46:40 2006 +0000
    10.3 @@ -32,7 +32,7 @@ typedef struct virtual_platform_def {
    10.4      unsigned long       params[HVM_NR_PARAMS];
    10.5      struct mmio_list    *mmio;
    10.6      /* One IOSAPIC now... */
    10.7 -    struct hvm_vioapic  vioapic;
    10.8 +    struct vioapic      vioapic;
    10.9  } vir_plat_t;
   10.10  
   10.11  static inline int __fls(uint32_t word)
    11.1 --- a/xen/include/asm-x86/hvm/domain.h	Tue Nov 07 15:48:10 2006 +0000
    11.2 +++ b/xen/include/asm-x86/hvm/domain.h	Tue Nov 07 17:46:40 2006 +0000
    11.3 @@ -35,8 +35,8 @@ struct hvm_domain {
    11.4      s64                    tsc_frequency;
    11.5      struct pl_time         pl_time;
    11.6  
    11.7 -    struct hvm_virpic      vpic;
    11.8 -    struct hvm_vioapic     vioapic;
    11.9 +    struct vpic            vpic;
   11.10 +    struct vioapic         vioapic;
   11.11      struct hvm_io_handler  io_handler;
   11.12  
   11.13      unsigned char          round_info[256];
    12.1 --- a/xen/include/asm-x86/hvm/vioapic.h	Tue Nov 07 15:48:10 2006 +0000
    12.2 +++ b/xen/include/asm-x86/hvm/vioapic.h	Tue Nov 07 17:46:40 2006 +0000
    12.3 @@ -23,97 +23,90 @@
    12.4   *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
    12.5   */
    12.6  
    12.7 -#ifndef __ASM_X86_HVM_IOAPIC_H__
    12.8 -#define __ASM_X86_HVM_IOAPIC_H__
    12.9 +#ifndef __ASM_X86_HVM_VIOAPIC_H__
   12.10 +#define __ASM_X86_HVM_VIOAPIC_H__
   12.11  
   12.12  #include <xen/config.h>
   12.13  #include <xen/types.h>
   12.14  #include <xen/smp.h>
   12.15  
   12.16 -#ifndef __ia64__
   12.17 -#define IOAPIC_VERSION_ID 0x11
   12.18 +#ifdef __ia64__
   12.19 +#define VIOAPIC_IS_IOSAPIC 1
   12.20 +#endif
   12.21 +
   12.22 +#if !VIOAPIC_IS_IOSAPIC
   12.23 +#define VIOAPIC_VERSION_ID 0x11 /* IOAPIC version */
   12.24  #else
   12.25 -#define IOAPIC_VERSION_ID 0x21
   12.26 +#define VIOAPIC_VERSION_ID 0x21 /* IOSAPIC version */
   12.27  #endif
   12.28  
   12.29 -#define IOAPIC_NUM_PINS 24
   12.30 -#define MAX_LAPIC_NUM   32
   12.31 +#define VIOAPIC_NUM_PINS 24
   12.32  
   12.33 -#define IOAPIC_LEVEL_TRIGGER 1
   12.34 +#define VIOAPIC_EDGE_TRIG  0
   12.35 +#define VIOAPIC_LEVEL_TRIG 1
   12.36  
   12.37 -#define IOAPIC_DEFAULT_BASE_ADDRESS  0xfec00000
   12.38 -#define IOAPIC_MEM_LENGTH            0x100
   12.39 +#define VIOAPIC_DEFAULT_BASE_ADDRESS  0xfec00000
   12.40 +#define VIOAPIC_MEM_LENGTH            0x100
   12.41  
   12.42 -#define IOAPIC_ENABLE_MASK  0x0
   12.43 -#define IOAPIC_ENABLE_FLAG  (1 << IOAPIC_ENABLE_MASK)
   12.44 -#define IOAPICEnabled(s)    (s->flags & IOAPIC_ENABLE_FLAG)
   12.45 -
   12.46 -#define IOAPIC_REG_SELECT  0x0
   12.47 -#define IOAPIC_REG_WINDOW  0x10
   12.48 +/* Direct registers. */
   12.49 +#define VIOAPIC_REG_SELECT  0x00
   12.50 +#define VIOAPIC_REG_WINDOW  0x10
   12.51 +#define VIOAPIC_REG_EOI     0x40 /* IA64 IOSAPIC only */
   12.52  
   12.53 -#ifdef __ia64__
   12.54 -#define IOAPIC_REG_ASSERTION    0x20
   12.55 -#define IOAPIC_REG_EOI          0x40
   12.56 -#endif
   12.57 +/* Indirect registers. */
   12.58 +#define VIOAPIC_REG_APIC_ID 0x00 /* x86 IOAPIC only */
   12.59 +#define VIOAPIC_REG_VERSION 0x01
   12.60 +#define VIOAPIC_REG_ARB_ID  0x02 /* x86 IOAPIC only */
   12.61  
   12.62 -#ifndef __ia64__
   12.63 -#define IOAPIC_REG_APIC_ID 0x0
   12.64 -#define IOAPIC_REG_ARB_ID  0x2
   12.65 -#endif
   12.66 +#define domain_vioapic(d) (&(d)->arch.hvm_domain.vioapic)
   12.67 +#define vioapic_domain(v) (container_of((v), struct domain, \
   12.68 +                                        arch.hvm_domain.vioapic))
   12.69  
   12.70 -#define IOAPIC_REG_VERSION 0x1
   12.71 -
   12.72 -typedef union RedirStatus
   12.73 +union vioapic_redir_entry
   12.74  {
   12.75 -    uint64_t value;
   12.76 +    uint64_t bits;
   12.77      struct {
   12.78          uint8_t vector;
   12.79 -        uint8_t deliver_mode:3;
   12.80 -        uint8_t destmode:1;
   12.81 -        uint8_t delivestatus:1;
   12.82 +        uint8_t delivery_mode:3;
   12.83 +        uint8_t dest_mode:1;
   12.84 +        uint8_t delivery_status:1;
   12.85          uint8_t polarity:1;
   12.86 -        uint8_t remoteirr:1;
   12.87 -        uint8_t trigmod:1;
   12.88 -        uint8_t mask:1;         /* interrupt mask*/
   12.89 +        uint8_t remote_irr:1;
   12.90 +        uint8_t trig_mode:1;
   12.91 +        uint8_t mask:1;
   12.92          uint8_t reserve:7;
   12.93 -#ifndef __ia64__
   12.94 +#if !VIOAPIC_IS_IOSAPIC
   12.95          uint8_t reserved[4];
   12.96          uint8_t dest_id;
   12.97  #else
   12.98          uint8_t reserved[3];
   12.99          uint16_t dest_id;
  12.100  #endif
  12.101 -    } RedirForm;
  12.102 -} RedirStatus;
  12.103 +    } fields;
  12.104 +};
  12.105  
  12.106 -typedef struct hvm_vioapic {
  12.107 +struct vioapic {
  12.108      uint32_t irr;
  12.109      uint32_t irr_xen; /* interrupts forced on by the hypervisor. */
  12.110 -    uint32_t isr;           /* This is used for level trigger */
  12.111 +    uint32_t isr;     /* This is used for level trigger */
  12.112      uint32_t imr;
  12.113      uint32_t ioregsel;
  12.114 -    uint32_t flags;
  12.115 -    uint32_t lapic_count;
  12.116      uint32_t id;
  12.117 -    uint32_t arb_id;
  12.118      unsigned long base_address;
  12.119 -    RedirStatus redirtbl[IOAPIC_NUM_PINS];
  12.120 -    struct vlapic *lapic_info[MAX_LAPIC_NUM];
  12.121 -    struct domain *domain;
  12.122 -} hvm_vioapic_t;
  12.123 -
  12.124 -hvm_vioapic_t *hvm_vioapic_init(struct domain *d);
  12.125 +    union vioapic_redir_entry redirtbl[VIOAPIC_NUM_PINS];
  12.126 +    struct vlapic *lapic_info[32];
  12.127 +    uint32_t lapic_count;
  12.128 +};
  12.129  
  12.130 -void hvm_vioapic_set_xen_irq(struct domain *d, int irq, int level);
  12.131 -void hvm_vioapic_set_irq(struct domain *d, int irq, int level);
  12.132 -
  12.133 -int hvm_vioapic_add_lapic(struct vlapic *vlapic, struct vcpu *v);
  12.134 -
  12.135 -void ioapic_update_EOI(struct domain *d, int vector);
  12.136 +void vioapic_init(struct domain *d);
  12.137 +void vioapic_set_xen_irq(struct domain *d, int irq, int level);
  12.138 +void vioapic_set_irq(struct domain *d, int irq, int level);
  12.139 +int  vioapic_add_lapic(struct vlapic *vlapic, struct vcpu *v);
  12.140 +void vioapic_update_EOI(struct domain *d, int vector);
  12.141  
  12.142  #ifdef HVM_DOMAIN_SAVE_RESTORE
  12.143  void ioapic_save(QEMUFile* f, void* opaque);
  12.144  int ioapic_load(QEMUFile* f, void* opaque, int version_id);
  12.145  #endif
  12.146  
  12.147 -#endif /* __ASM_X86_HVM_IOAPIC_H__ */
  12.148 +#endif /* __ASM_X86_HVM_VIOAPIC_H__ */
    13.1 --- a/xen/include/asm-x86/hvm/vpic.h	Tue Nov 07 15:48:10 2006 +0000
    13.2 +++ b/xen/include/asm-x86/hvm/vpic.h	Tue Nov 07 17:46:40 2006 +0000
    13.3 @@ -5,10 +5,10 @@
    13.4   * Copyright (c) 2005 Intel Corp
    13.5   * 
    13.6   * Permission is hereby granted, free of charge, to any person obtaining a copy
    13.7 - * of this software and associated documentation files (the "Software"), to deal
    13.8 - * in the Software without restriction, including without limitation the rights
    13.9 - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
   13.10 - * copies of the Software, and to permit persons to whom the Software is
   13.11 + * of this software and associated documentation files (the "Software"), to
   13.12 + * deal in the Software without restriction, including without limitation the
   13.13 + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
   13.14 + * sell copies of the Software, and to permit persons to whom the Software is
   13.15   * furnished to do so, subject to the following conditions:
   13.16   *
   13.17   * The above copyright notice and this permission notice shall be included in
   13.18 @@ -18,19 +18,17 @@
   13.19   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
   13.20   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
   13.21   * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   13.22 - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   13.23 - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
   13.24 - * THE SOFTWARE.
   13.25 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
   13.26 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
   13.27 + * IN THE SOFTWARE.
   13.28   */
   13.29  
   13.30  #ifndef __ASM_X86_HVM_VPIC_H__
   13.31  #define __ASM_X86_HVM_VPIC_H__
   13.32  
   13.33 -#define hw_error(x)  do {} while (0);
   13.34 -
   13.35 +#define domain_vpic(d) (&(d)->arch.hvm_domain.vpic)
   13.36 +#define vpic_domain(v) (container_of((v), struct domain, arch.hvm_domain.vpic))
   13.37  
   13.38 -/* i8259.c */
   13.39 -typedef struct IOAPICState IOAPICState;
   13.40  typedef struct PicState {
   13.41      uint8_t last_irr; /* edge detection */
   13.42      uint8_t irr; /* interrupt request register */
   13.43 @@ -50,12 +48,11 @@ typedef struct PicState {
   13.44      uint8_t init4; /* true if 4 byte init */
   13.45      uint8_t elcr; /* PIIX edge/trigger selection*/
   13.46      uint8_t elcr_mask;
   13.47 -    struct hvm_virpic *pics_state;
   13.48 +    struct vpic *pics_state;
   13.49  } PicState;
   13.50  
   13.51 -struct hvm_virpic {
   13.52 +struct vpic {
   13.53      /* 0 is master pic, 1 is slave pic */
   13.54 -    /* XXX: better separation between the two pics */
   13.55      PicState pics[2];
   13.56      void (*irq_request)(void *opaque, int level);
   13.57      void *irq_request_opaque;
   13.58 @@ -63,13 +60,12 @@ struct hvm_virpic {
   13.59      spinlock_t lock;
   13.60  };
   13.61  
   13.62 -
   13.63  void pic_set_xen_irq(void *opaque, int irq, int level);
   13.64 -void pic_set_irq(struct hvm_virpic *s, int irq, int level);
   13.65 -void pic_init(struct hvm_virpic *s, 
   13.66 +void pic_set_irq(struct vpic *vpic, int irq, int level);
   13.67 +void pic_init(struct vpic *vpic,
   13.68                void (*irq_request)(void *, int),
   13.69                void *irq_request_opaque);
   13.70 -void pic_update_irq(struct hvm_virpic *s); /* Caller must hold s->lock */
   13.71 +void pic_update_irq(struct vpic *vpic); /* Caller must hold vpic->lock */
   13.72  void register_pic_io_hook(struct domain *d);
   13.73  int cpu_get_pic_interrupt(struct vcpu *v, int *type);
   13.74  int is_periodic_irq(struct vcpu *v, int irq, int type);