direct-io.hg

changeset 5462:cb924d6ba79d

bitkeeper revision 1.1709.1.9 (42b056day4oavPqdg1qWc4E5Lgw8Bw)

Merge djm@sportsman.fc.hp.com:/home/djm/xeno-unstable-ia64.bk
into kirby.fc.hp.com:/home/djm/src/xen/xeno-unstable-ia64.bk
author djm@kirby.fc.hp.com
date Wed Jun 15 16:27:06 2005 +0000 (2005-06-15)
parents fbb0e9caca09 5da30c7f9999
children 39bf99b109dd
files xen/arch/ia64/ivt.S xen/arch/ia64/process.c xen/arch/ia64/regionreg.c xen/arch/ia64/vcpu.c xen/arch/ia64/vhpt.c xen/include/asm-ia64/vhpt.h
line diff
     1.1 --- a/xen/arch/ia64/ivt.S	Tue Jun 14 18:49:01 2005 +0000
     1.2 +++ b/xen/arch/ia64/ivt.S	Wed Jun 15 16:27:06 2005 +0000
     1.3 @@ -348,12 +348,23 @@ ENTRY(alt_itlb_miss)
     1.4  //	;;
     1.5  //#endif
     1.6  #endif
     1.7 +#ifdef XEN
     1.8 +	mov r31=pr
     1.9 +	mov r16=cr.ifa		// get address that caused the TLB miss
    1.10 +	;;
    1.11 +late_alt_itlb_miss:
    1.12 +	movl r17=PAGE_KERNEL
    1.13 +	mov r21=cr.ipsr
    1.14 +	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
    1.15 +	;;
    1.16 +#else
    1.17  	mov r16=cr.ifa		// get address that caused the TLB miss
    1.18  	movl r17=PAGE_KERNEL
    1.19  	mov r21=cr.ipsr
    1.20  	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
    1.21  	mov r31=pr
    1.22  	;;
    1.23 +#endif
    1.24  #ifdef CONFIG_DISABLE_VHPT
    1.25  	shr.u r22=r16,61			// get the region number into r21
    1.26  	;;
    1.27 @@ -399,13 +410,18 @@ ENTRY(alt_dtlb_miss)
    1.28  //	;;
    1.29  //#endif
    1.30  #endif
    1.31 +#ifdef XEN
    1.32 +	mov r31=pr
    1.33  	mov r16=cr.ifa		// get address that caused the TLB miss
    1.34 +	;;
    1.35 +late_alt_dtlb_miss:
    1.36  	movl r17=PAGE_KERNEL
    1.37  	mov r20=cr.isr
    1.38  	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
    1.39  	mov r21=cr.ipsr
    1.40 -	mov r31=pr
    1.41  	;;
    1.42 +#else
    1.43 +#endif
    1.44  #ifdef CONFIG_DISABLE_VHPT
    1.45  	shr.u r22=r16,61			// get the region number into r21
    1.46  	;;
     2.1 --- a/xen/arch/ia64/process.c	Tue Jun 14 18:49:01 2005 +0000
     2.2 +++ b/xen/arch/ia64/process.c	Wed Jun 15 16:27:06 2005 +0000
     2.3 @@ -313,45 +313,31 @@ void xen_handle_domain_access(unsigned l
     2.4  	}
     2.5  if (address < 0x4000) printf("WARNING: page_fault @%p, iip=%p\n",address,iip);
     2.6  		
     2.7 +	if (trp = match_tr(current,address)) {
     2.8 +		// FIXME address had better be pre-validated on insert
     2.9 +		pteval = translate_domain_pte(trp->page_flags,address,trp->itir);
    2.10 +		vcpu_itc_no_srlz(current,6,address,pteval,-1UL,(trp->itir>>2)&0x3f);
    2.11 +		return;
    2.12 +	}
    2.13  	// if we are fortunate enough to have it in the 1-entry TLB...
    2.14  	if (pteval = match_dtlb(ed,address,&ps,NULL)) {
    2.15  		vcpu_itc_no_srlz(ed,6,address,pteval,-1UL,ps);
    2.16  		return;
    2.17  	}
    2.18 -	// look in the TRs
    2.19 -	fault = vcpu_tpa(ed,address,&mpaddr);
    2.20 -	if (fault != IA64_NO_FAULT) {
    2.21 -		static int uacnt = 0;
    2.22 -		// can't translate it, just fail (poor man's exception)
    2.23 -		// which results in retrying execution
    2.24 -//printk("*** xen_handle_domain_access: poor man's exception cnt=%i iip=%p, addr=%p...\n",uacnt++,iip,address);
    2.25 -		if (ia64_done_with_exception(regs)) {
    2.26 +	if (ia64_done_with_exception(regs)) {
    2.27  //if (!(uacnt++ & 0x3ff)) printk("*** xen_handle_domain_access: successfully handled cnt=%d iip=%p, addr=%p...\n",uacnt,iip,address);
    2.28  			return;
    2.29 -		}
    2.30 -		else {
    2.31 -			// should never happen.  If it does, region 0 addr may
    2.32 -			// indicate a bad xen pointer
    2.33 -			printk("*** xen_handle_domain_access: exception table"
    2.34 -                               " lookup failed, iip=%p, addr=%p, spinning...\n",
    2.35 -				iip,address);
    2.36 -			panic_domain(regs,"*** xen_handle_domain_access: exception table"
    2.37 -                               " lookup failed, iip=%p, addr=%p, spinning...\n",
    2.38 -				iip,address);
    2.39 -		}
    2.40  	}
    2.41 -	if (d == dom0) {
    2.42 -		if (mpaddr < dom0_start || mpaddr >= dom0_start + dom0_size) {
    2.43 -			printk("xen_handle_domain_access: vcpu_tpa returned out-of-bounds dom0 mpaddr %p! continuing...\n",mpaddr);
    2.44 -			tdpfoo();
    2.45 -		}
    2.46 +	else {
    2.47 +		// should never happen.  If it does, region 0 addr may
    2.48 +		// indicate a bad xen pointer
    2.49 +		printk("*** xen_handle_domain_access: exception table"
    2.50 +                       " lookup failed, iip=%p, addr=%p, spinning...\n",
    2.51 +			iip,address);
    2.52 +		panic_domain(regs,"*** xen_handle_domain_access: exception table"
    2.53 +                       " lookup failed, iip=%p, addr=%p, spinning...\n",
    2.54 +			iip,address);
    2.55  	}
    2.56 -//printk("*** xen_handle_domain_access: tpa resolved miss @%p...\n",address);
    2.57 -	pteval = lookup_domain_mpa(d,mpaddr);
    2.58 -	// would be nice to have a counter here
    2.59 -	//printf("Handling privop data TLB miss\n");
    2.60 -	// FIXME, must be inlined or potential for nested fault here!
    2.61 -	vcpu_itc_no_srlz(ed,2,address,pteval,-1UL,PAGE_SHIFT);
    2.62  }
    2.63  
    2.64  void ia64_do_page_fault (unsigned long address, unsigned long isr, struct pt_regs *regs, unsigned long itir)
    2.65 @@ -441,7 +427,7 @@ panic_domain(0,"ia64_do_page_fault: @%p?
    2.66  				if (pteval & _PAGE_P)
    2.67  				{
    2.68  					pteval = translate_domain_pte(pteval,address,itir);
    2.69 -					vcpu_itc_no_srlz(current,is_data?2:1,address,pteval,-1UL,(itir>>2)&0x3f);
    2.70 +					vcpu_itc_no_srlz(current,is_data?6:1,address,pteval,-1UL,(itir>>2)&0x3f);
    2.71  					return;
    2.72  				}
    2.73  				else vector = is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR;
     3.1 --- a/xen/arch/ia64/regionreg.c	Tue Jun 14 18:49:01 2005 +0000
     3.2 +++ b/xen/arch/ia64/regionreg.c	Wed Jun 15 16:27:06 2005 +0000
     3.3 @@ -274,6 +274,7 @@ int set_one_rr(unsigned long rr, unsigne
     3.4  		return 0;
     3.5  	}
     3.6  
     3.7 +#ifdef CONFIG_VTI
     3.8  	memrrv.rrval = rrv.rrval;
     3.9  	if (rreg == 7) {
    3.10  		newrrv.rid = newrid;
    3.11 @@ -290,6 +291,15 @@ int set_one_rr(unsigned long rr, unsigne
    3.12  		if (rreg == 0) v->arch.metaphysical_saved_rr0 = newrrv.rrval;
    3.13  		set_rr(rr,newrrv.rrval);
    3.14  	}
    3.15 +#else
    3.16 +	memrrv.rrval = rrv.rrval;
    3.17 +	newrrv.rid = newrid;
    3.18 +	newrrv.ve = 1;  // VHPT now enabled for region 7!!
    3.19 +	newrrv.ps = PAGE_SHIFT;
    3.20 +	if (rreg == 0) v->arch.metaphysical_saved_rr0 = newrrv.rrval;
    3.21 +	if (rreg == 7) ia64_new_rr7(vmMangleRID(newrrv.rrval),v->vcpu_info);
    3.22 +	else set_rr(rr,newrrv.rrval);
    3.23 +#endif
    3.24  	return 1;
    3.25  }
    3.26  
     4.1 --- a/xen/arch/ia64/vcpu.c	Tue Jun 14 18:49:01 2005 +0000
     4.2 +++ b/xen/arch/ia64/vcpu.c	Wed Jun 15 16:27:06 2005 +0000
     4.3 @@ -1589,7 +1589,8 @@ void vcpu_itc_no_srlz(VCPU *vcpu, UINT64
     4.4  		// addresses never get flushed.  More work needed if this
     4.5  		// ever happens.
     4.6  //printf("vhpt_insert(%p,%p,%p)\n",vaddr,pte,1L<<logps);
     4.7 -		vhpt_insert(vaddr,pte,logps<<2);
     4.8 +		if (logps > PAGE_SHIFT) vhpt_multiple_insert(vaddr,pte,logps);
     4.9 +		else vhpt_insert(vaddr,pte,logps<<2);
    4.10  	}
    4.11  	// even if domain pagesize is larger than PAGE_SIZE, just put
    4.12  	// PAGE_SIZE mapping in the vhpt for now, else purging is complicated
     5.1 --- a/xen/arch/ia64/vhpt.c	Tue Jun 14 18:49:01 2005 +0000
     5.2 +++ b/xen/arch/ia64/vhpt.c	Wed Jun 15 16:27:06 2005 +0000
     5.3 @@ -87,6 +87,37 @@ void vhpt_map(void)
     5.4  	ia64_srlz_i();
     5.5  }
     5.6  
     5.7 +void vhpt_multiple_insert(unsigned long vaddr, unsigned long pte, unsigned long logps)
     5.8 +{
     5.9 +	unsigned long mask = (1L << logps) - 1;
    5.10 +	int i;
    5.11 +
    5.12 +	if (logps-PAGE_SHIFT > 10) {
    5.13 +		// if this happens, we may want to revisit this algorithm
    5.14 +		printf("vhpt_multiple_insert:logps-PAGE_SHIFT>10,spinning..\n");
    5.15 +		while(1);
    5.16 +	}
    5.17 +	if (logps-PAGE_SHIFT > 2) {
    5.18 +		// FIXME: Should add counter here to see how often this
    5.19 +		//  happens (e.g. for 16MB pages!) and determine if it
    5.20 +		//  is a performance problem.  On a quick look, it takes
    5.21 +		//  about 39000 instrs for a 16MB page and it seems to occur
    5.22 +		//  only a few times/second, so OK for now.
    5.23 +		//  An alternate solution would be to just insert the one
    5.24 +		//  16KB in the vhpt (but with the full mapping)?
    5.25 +		//printf("vhpt_multiple_insert: logps-PAGE_SHIFT==%d,"
    5.26 +			//"va=%p, pa=%p, pa-masked=%p\n",
    5.27 +			//logps-PAGE_SHIFT,vaddr,pte&_PFN_MASK,
    5.28 +			//(pte&_PFN_MASK)&~mask);
    5.29 +	}
    5.30 +	vaddr &= ~mask;
    5.31 +	pte = ((pte & _PFN_MASK) & ~mask) | (pte & ~_PFN_MASK);
    5.32 +	for (i = 1L << (logps-PAGE_SHIFT); i > 0; i--) {
    5.33 +		vhpt_insert(vaddr,pte,logps<<2);
    5.34 +		vaddr += PAGE_SIZE;
    5.35 +	}
    5.36 +}
    5.37 +
    5.38  void vhpt_init(void)
    5.39  {
    5.40  	unsigned long vhpt_total_size, vhpt_alignment, vhpt_imva;
     6.1 --- a/xen/include/asm-ia64/vhpt.h	Tue Jun 14 18:49:01 2005 +0000
     6.2 +++ b/xen/include/asm-ia64/vhpt.h	Wed Jun 15 16:27:06 2005 +0000
     6.3 @@ -140,12 +140,20 @@ CC_##Name:;							\
     6.4  	mov r16 = cr.ifa;					\
     6.5  	movl r30 = int_counts;					\
     6.6  	;;							\
     6.7 +	extr.u r17=r16,59,5					\
     6.8 +	;;							\
     6.9 +	cmp.eq p6,p0=0x1e,r17;					\
    6.10 +(p6)	br.cond.spnt	.Alt_##Name				\
    6.11 +	;;							\
    6.12 +	cmp.eq p6,p0=0x1d,r17;					\
    6.13 +(p6)	br.cond.spnt	.Alt_##Name				\
    6.14 +	;;							\
    6.15  	thash r28 = r16;					\
    6.16  	adds  r30 = CAUSE_VHPT_CC_HANDLED << 3, r30;		\
    6.17  	;;							\
    6.18  	ttag r19 = r16;						\
    6.19 -	ld8 r27 = [r30];					\
    6.20 -	adds r17 = VLE_CCHAIN_OFFSET, r28;			\
    6.21 +ld8 r27 = [r30];					\
    6.22 +adds r17 = VLE_CCHAIN_OFFSET, r28;			\
    6.23  	;;							\
    6.24  	ld8 r17 = [r17];					\
    6.25  	;;							\
    6.26 @@ -192,6 +200,11 @@ CC_##Name:;							\
    6.27  	rfi;							\
    6.28  	;;							\
    6.29  								\
    6.30 +.Alt_##Name:;							\
    6.31 +	mov pr = r31, 0x1ffff;					\
    6.32 +	;;							\
    6.33 +	br.cond.sptk late_alt_##Name				\
    6.34 +	;;							\
    6.35  .Out_##Name:;							\
    6.36  	mov pr = r31, 0x1ffff;					\
    6.37  	;;							\