direct-io.hg

changeset 10606:bf396988059e

[IA64] Allow guest to set the address of shared_info.

Add a new hypercall: SET_SHARED_INFO_VA.
Cleanup of asm-xsi-offsets: do not define absolute address, use a new macro.
Cleanup of linux asm-offsets: use a macro for xen mapped regs.
xensetup.S: set the shared_info address (disabled if using compatibility).
privop.h: May redefined XSI_BASE (not yet enabled for compatibility).
Vocabulary coherence: use XMAPPEDREGS_ prefix.
Cleanup of xensystem.h

Signed-off-by: Tristan Gingold <tristan.gingold@bull.net>
author awilliam@xenbuild.aw
date Fri Jun 23 09:46:39 2006 -0600 (2006-06-23)
parents 0e5635d68de3
children cf4a70ab3f59
files linux-2.6-xen-sparse/arch/ia64/kernel/asm-offsets.c linux-2.6-xen-sparse/arch/ia64/xen/xensetup.S linux-2.6-xen-sparse/include/asm-ia64/xen/privop.h xen/arch/ia64/asm-xsi-offsets.c xen/arch/ia64/vmx/vmx_entry.S xen/arch/ia64/xen/domain.c xen/arch/ia64/xen/faults.c xen/arch/ia64/xen/hypercall.c xen/arch/ia64/xen/hyperprivop.S xen/arch/ia64/xen/ivt.S xen/arch/ia64/xen/vcpu.c xen/arch/ia64/xen/xenasm.S xen/include/asm-ia64/dom_fw.h xen/include/asm-ia64/domain.h xen/include/asm-ia64/xenkregs.h xen/include/asm-ia64/xensystem.h xen/include/public/arch-ia64.h
line diff
     1.1 --- a/linux-2.6-xen-sparse/arch/ia64/kernel/asm-offsets.c	Wed Jun 21 11:17:08 2006 -0600
     1.2 +++ b/linux-2.6-xen-sparse/arch/ia64/kernel/asm-offsets.c	Fri Jun 23 09:46:39 2006 -0600
     1.3 @@ -265,34 +265,25 @@ void foo(void)
     1.4  #ifdef CONFIG_XEN
     1.5  	BLANK();
     1.6  
     1.7 -	DEFINE(XSI_PSR_I_ADDR_OFS, (XSI_OFS + offsetof(mapped_regs_t, interrupt_mask_addr)));
     1.8 -	DEFINE(XSI_IPSR_OFS, (XSI_OFS + offsetof(mapped_regs_t, ipsr)));
     1.9 -	DEFINE(XSI_IIP_OFS, (XSI_OFS + offsetof(mapped_regs_t, iip)));
    1.10 -	DEFINE(XSI_IFS_OFS, (XSI_OFS + offsetof(mapped_regs_t, ifs)));
    1.11 -	DEFINE(XSI_PRECOVER_IFS_OFS, (XSI_OFS + offsetof(mapped_regs_t, precover_ifs)));
    1.12 -	DEFINE(XSI_ISR_OFS, (XSI_OFS + offsetof(mapped_regs_t, isr)));
    1.13 -	DEFINE(XSI_IFA_OFS, (XSI_OFS + offsetof(mapped_regs_t, ifa)));
    1.14 -	DEFINE(XSI_IIPA_OFS, (XSI_OFS + offsetof(mapped_regs_t, iipa)));
    1.15 -	DEFINE(XSI_IIM_OFS, (XSI_OFS + offsetof(mapped_regs_t, iim)));
    1.16 -	DEFINE(XSI_TPR_OFS, (XSI_OFS + offsetof(mapped_regs_t, tpr)));
    1.17 -	DEFINE(XSI_IHA_OFS, (XSI_OFS + offsetof(mapped_regs_t, iha)));
    1.18 -	DEFINE(XSI_ITIR_OFS, (XSI_OFS + offsetof(mapped_regs_t, itir)));
    1.19 -	DEFINE(XSI_ITV_OFS, (XSI_OFS + offsetof(mapped_regs_t, itv)));
    1.20 -	DEFINE(XSI_PTA_OFS, (XSI_OFS + offsetof(mapped_regs_t, pta)));
    1.21 -	DEFINE(XSI_PSR_IC_OFS, (XSI_OFS + offsetof(mapped_regs_t, interrupt_collection_enabled)));
    1.22 -	DEFINE(XSI_PEND_OFS, (XSI_OFS + offsetof(mapped_regs_t, pending_interruption)));
    1.23 -	DEFINE(XSI_INCOMPL_REGFR_OFS, (XSI_OFS + offsetof(mapped_regs_t, incomplete_regframe)));
    1.24 -	DEFINE(XSI_METAPHYS_OFS, (XSI_OFS + offsetof(mapped_regs_t, metaphysical_mode)));
    1.25 +#define DEFINE_MAPPED_REG_OFS(sym, field) \
    1.26 +	DEFINE(sym, (XMAPPEDREGS_OFS + offsetof(mapped_regs_t, field)))
    1.27  
    1.28 -	DEFINE(XSI_BANKNUM_OFS, (XSI_OFS + offsetof(mapped_regs_t, banknum)));
    1.29 -
    1.30 -	DEFINE(XSI_BANK0_R16_OFS, (XSI_OFS + offsetof(mapped_regs_t, bank0_regs[0])));
    1.31 -	DEFINE(XSI_BANK1_R16_OFS, (XSI_OFS + offsetof(mapped_regs_t, bank1_regs[0])));
    1.32 -	DEFINE(XSI_B0NATS_OFS, (XSI_OFS + offsetof(mapped_regs_t, vbnat)));
    1.33 -	DEFINE(XSI_B1NATS_OFS, (XSI_OFS + offsetof(mapped_regs_t, vnat)));
    1.34 -	DEFINE(XSI_RR0_OFS, (XSI_OFS + offsetof(mapped_regs_t, rrs[0])));
    1.35 -	DEFINE(XSI_KR0_OFS, (XSI_OFS + offsetof(mapped_regs_t, krs[0])));
    1.36 -	DEFINE(XSI_PKR0_OFS, (XSI_OFS + offsetof(mapped_regs_t, pkrs[0])));
    1.37 -	DEFINE(XSI_TMP0_OFS, (XSI_OFS + offsetof(mapped_regs_t, tmp[0])));
    1.38 +	DEFINE_MAPPED_REG_OFS(XSI_PSR_I_ADDR_OFS, interrupt_mask_addr);
    1.39 +	DEFINE_MAPPED_REG_OFS(XSI_IPSR_OFS, ipsr);
    1.40 +	DEFINE_MAPPED_REG_OFS(XSI_IIP_OFS, iip);
    1.41 +	DEFINE_MAPPED_REG_OFS(XSI_IFS_OFS, ifs);
    1.42 +	DEFINE_MAPPED_REG_OFS(XSI_PRECOVER_IFS_OFS, precover_ifs);
    1.43 +	DEFINE_MAPPED_REG_OFS(XSI_ISR_OFS, isr);
    1.44 +	DEFINE_MAPPED_REG_OFS(XSI_IFA_OFS, ifa);
    1.45 +	DEFINE_MAPPED_REG_OFS(XSI_IIPA_OFS, iipa);
    1.46 +	DEFINE_MAPPED_REG_OFS(XSI_IIM_OFS, iim);
    1.47 +	DEFINE_MAPPED_REG_OFS(XSI_IHA_OFS, iha);
    1.48 +	DEFINE_MAPPED_REG_OFS(XSI_ITIR_OFS, itir);
    1.49 +	DEFINE_MAPPED_REG_OFS(XSI_PSR_IC_OFS, interrupt_collection_enabled);
    1.50 +	DEFINE_MAPPED_REG_OFS(XSI_PEND_OFS, pending_interruption);
    1.51 +	DEFINE_MAPPED_REG_OFS(XSI_INCOMPL_REGFR_OFS, incomplete_regframe);
    1.52 +	DEFINE_MAPPED_REG_OFS(XSI_BANKNUM_OFS, banknum);
    1.53 +	DEFINE_MAPPED_REG_OFS(XSI_BANK0_R16_OFS, bank0_regs[0]);
    1.54 +	DEFINE_MAPPED_REG_OFS(XSI_BANK1_R16_OFS, bank1_regs[0]);
    1.55  #endif /* CONFIG_XEN */
    1.56  }
     2.1 --- a/linux-2.6-xen-sparse/arch/ia64/xen/xensetup.S	Wed Jun 21 11:17:08 2006 -0600
     2.2 +++ b/linux-2.6-xen-sparse/arch/ia64/xen/xensetup.S	Fri Jun 23 09:46:39 2006 -0600
     2.3 @@ -15,10 +15,21 @@ GLOBAL_ENTRY(early_xen_setup)
     2.4  	mov r8=ar.rsc		// Initialized in head.S
     2.5  (isBP)	movl r9=running_on_xen;;
     2.6  	extr.u r8=r8,2,2;;	// Extract pl fields
     2.7 -	cmp.ne p7,p0=r8,r0;;	// p7: running on xen 
     2.8 -(p7)	mov r8=1		// booleanize.
     2.9 -(p7)	movl r10=xen_ivt;;
    2.10 +	cmp.eq p7,p0=r8,r0	// p7: !running on xen
    2.11 +	mov r8=1		// booleanize.
    2.12 +(p7)	br.ret.sptk.many rp;;
    2.13  (isBP)	st4 [r9]=r8
    2.14 -(p7)	mov cr.iva=r10
    2.15 -	br.ret.sptk.many rp;;
    2.16 +	movl r10=xen_ivt;;
    2.17 +	
    2.18 +	mov cr.iva=r10
    2.19 +
    2.20 +#if XSI_BASE != 0xf100000000000000UL
    2.21 +	/* Backward compatibility.  */
    2.22 +(isBP)	mov r2=0x600
    2.23 +(isBP)	movl r28=XSI_BASE;;
    2.24 +(isBP)	break 0x1000;;
    2.25 +#endif
    2.26 +
    2.27 +	br.ret.sptk.many rp
    2.28 +	;;
    2.29  END(early_xen_setup)
     3.1 --- a/linux-2.6-xen-sparse/include/asm-ia64/xen/privop.h	Wed Jun 21 11:17:08 2006 -0600
     3.2 +++ b/linux-2.6-xen-sparse/include/asm-ia64/xen/privop.h	Fri Jun 23 09:46:39 2006 -0600
     3.3 @@ -14,8 +14,15 @@
     3.4  
     3.5  #define IA64_PARAVIRTUALIZED
     3.6  
     3.7 -#define XSI_OFS		XSI_SIZE
     3.8 -#define XPRIVREG_BASE	(XSI_BASE + XSI_SIZE)
     3.9 +#if 0
    3.10 +#undef XSI_BASE
    3.11 +/* At 1 MB, before per-cpu space but still addressable using addl instead
    3.12 +   of movl. */
    3.13 +#define XSI_BASE				0xfffffffffff00000
    3.14 +#endif
    3.15 +
    3.16 +/* Address of mapped regs.  */
    3.17 +#define XMAPPEDREGS_BASE		(XSI_BASE + XSI_SIZE)
    3.18  
    3.19  #ifdef __ASSEMBLY__
    3.20  #define	XEN_HYPER_RFI			break HYPERPRIVOP_RFI
    3.21 @@ -98,16 +105,16 @@ extern void xen_set_eflag(unsigned long)
    3.22   * Others, like "pend", are abstractions based on privileged registers.
    3.23   * "Pend" is guaranteed to be set if reading cr.ivr would return a
    3.24   * (non-spurious) interrupt. */
    3.25 -#define XEN_PRIVREGS ((struct mapped_regs *)XPRIVREG_BASE)
    3.26 +#define XEN_MAPPEDREGS ((struct mapped_regs *)XMAPPEDREGS_BASE)
    3.27  #define XSI_PSR_I			\
    3.28 -	(*XEN_PRIVREGS->interrupt_mask_addr)
    3.29 +	(*XEN_MAPPEDREGS->interrupt_mask_addr)
    3.30  #define xen_get_virtual_psr_i()		\
    3.31  	(!XSI_PSR_I)
    3.32  #define xen_set_virtual_psr_i(_val)	\
    3.33  	({ XSI_PSR_I = (uint8_t)(_val) ? 0 : 1; })
    3.34  #define xen_set_virtual_psr_ic(_val)	\
    3.35 -	({ XEN_PRIVREGS->interrupt_collection_enabled = _val ? 1 : 0; })
    3.36 -#define xen_get_virtual_pend()		(XEN_PRIVREGS->pending_interruption)
    3.37 +	({ XEN_MAPPEDREGS->interrupt_collection_enabled = _val ? 1 : 0; })
    3.38 +#define xen_get_virtual_pend()		(XEN_MAPPEDREGS->pending_interruption)
    3.39  
    3.40  /* Hyperprivops are "break" instructions with a well-defined API.
    3.41   * In particular, the virtual psr.ic bit must be off; in this way
     4.1 --- a/xen/arch/ia64/asm-xsi-offsets.c	Wed Jun 21 11:17:08 2006 -0600
     4.2 +++ b/xen/arch/ia64/asm-xsi-offsets.c	Fri Jun 23 09:46:39 2006 -0600
     4.3 @@ -42,66 +42,34 @@
     4.4  
     4.5  #define BLANK() asm volatile("\n->" : : )
     4.6  
     4.7 -#define OFFSET(_sym, _str, _mem) \
     4.8 -    DEFINE(_sym, offsetof(_str, _mem));
     4.9 +#define DEFINE_MAPPED_REG_OFS(sym, field) \
    4.10 +	DEFINE(sym, (XMAPPEDREGS_OFS + offsetof(mapped_regs_t, field)))
    4.11  
    4.12  void foo(void)
    4.13  {
    4.14 -	/* First is shared info page, and then arch specific vcpu context */
    4.15 -	//DEFINE(XSI_BASE, SHAREDINFO_ADDR);
    4.16 -
    4.17 -	DEFINE(XSI_PSR_I_ADDR_OFS, (XSI_OFS + offsetof(mapped_regs_t, interrupt_mask_addr)));
    4.18 -	DEFINE(XSI_PSR_I_ADDR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, interrupt_mask_addr)));
    4.19 -	DEFINE(XSI_IPSR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, ipsr)));
    4.20 -	DEFINE(XSI_IPSR_OFS, (XSI_OFS + offsetof(mapped_regs_t, ipsr)));
    4.21 -	DEFINE(XSI_IIP_OFS, (XSI_OFS + offsetof(mapped_regs_t, iip)));
    4.22 -	DEFINE(XSI_IIP, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, iip)));
    4.23 -	DEFINE(XSI_IFS_OFS, (XSI_OFS + offsetof(mapped_regs_t, ifs)));
    4.24 -	DEFINE(XSI_IFS, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, ifs)));
    4.25 -	DEFINE(XSI_PRECOVER_IFS_OFS, (XSI_OFS + offsetof(mapped_regs_t, precover_ifs)));
    4.26 -	DEFINE(XSI_PRECOVER_IFS, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, precover_ifs)));
    4.27 -	DEFINE(XSI_ISR_OFS, (XSI_OFS + offsetof(mapped_regs_t, isr)));
    4.28 -	DEFINE(XSI_ISR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, isr)));
    4.29 -	DEFINE(XSI_IFA_OFS, (XSI_OFS + offsetof(mapped_regs_t, ifa)));
    4.30 -	DEFINE(XSI_IFA, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, ifa)));
    4.31 -	DEFINE(XSI_IIPA_OFS, (XSI_OFS + offsetof(mapped_regs_t, iipa)));
    4.32 -	DEFINE(XSI_IIPA, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, iipa)));
    4.33 -	DEFINE(XSI_IIM_OFS, (XSI_OFS + offsetof(mapped_regs_t, iim)));
    4.34 -	DEFINE(XSI_IIM, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, iim)));
    4.35 -	DEFINE(XSI_TPR_OFS, (XSI_OFS + offsetof(mapped_regs_t, tpr)));
    4.36 -	DEFINE(XSI_TPR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, tpr)));
    4.37 -	DEFINE(XSI_IHA_OFS, (XSI_OFS + offsetof(mapped_regs_t, iha)));
    4.38 -	DEFINE(XSI_IHA, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, iha)));
    4.39 -	DEFINE(XSI_ITIR_OFS, (XSI_OFS + offsetof(mapped_regs_t, itir)));
    4.40 -	DEFINE(XSI_ITIR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, itir)));
    4.41 -	DEFINE(XSI_ITV_OFS, (XSI_OFS + offsetof(mapped_regs_t, itv)));
    4.42 -	DEFINE(XSI_ITV, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, itv)));
    4.43 -	DEFINE(XSI_PTA_OFS, (XSI_OFS + offsetof(mapped_regs_t, pta)));
    4.44 -	DEFINE(XSI_PTA, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, pta)));
    4.45 -	DEFINE(XSI_PSR_IC_OFS, (XSI_OFS + offsetof(mapped_regs_t, interrupt_collection_enabled)));
    4.46 -	DEFINE(XSI_PSR_IC, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, interrupt_collection_enabled)));
    4.47 -	DEFINE(XSI_PEND_OFS, (XSI_OFS + offsetof(mapped_regs_t, pending_interruption)));
    4.48 -	DEFINE(XSI_PEND, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, pending_interruption)));
    4.49 -	DEFINE(XSI_INCOMPL_REGFR_OFS, (XSI_OFS + offsetof(mapped_regs_t, incomplete_regframe)));
    4.50 -	DEFINE(XSI_INCOMPL_REGFR, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, incomplete_regframe)));
    4.51 -	DEFINE(XSI_METAPHYS_OFS, (XSI_OFS + offsetof(mapped_regs_t, metaphysical_mode)));
    4.52 -	DEFINE(XSI_METAPHYS, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, metaphysical_mode)));
    4.53 -
    4.54 -	DEFINE(XSI_BANKNUM_OFS, (XSI_OFS + offsetof(mapped_regs_t, banknum)));
    4.55 -	DEFINE(XSI_BANKNUM, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, banknum)));
    4.56 -
    4.57 -	DEFINE(XSI_BANK0_R16_OFS, (XSI_OFS + offsetof(mapped_regs_t, bank0_regs[0])));
    4.58 -	DEFINE(XSI_BANK0_R16, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, bank0_regs[0])));
    4.59 -	DEFINE(XSI_BANK1_R16_OFS, (XSI_OFS + offsetof(mapped_regs_t, bank1_regs[0])));
    4.60 -	DEFINE(XSI_BANK1_R16, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, bank1_regs[0])));
    4.61 -	DEFINE(XSI_B0NATS_OFS, (XSI_OFS + offsetof(mapped_regs_t, vbnat)));
    4.62 -	DEFINE(XSI_B1NATS_OFS, (XSI_OFS + offsetof(mapped_regs_t, vnat)));
    4.63 -	DEFINE(XSI_RR0_OFS, (XSI_OFS + offsetof(mapped_regs_t, rrs[0])));
    4.64 -	DEFINE(XSI_RR0, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, rrs[0])));
    4.65 -	DEFINE(XSI_KR0_OFS, (XSI_OFS + offsetof(mapped_regs_t, krs[0])));
    4.66 -	DEFINE(XSI_KR0, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, krs[0])));
    4.67 -	DEFINE(XSI_PKR0_OFS, (XSI_OFS + offsetof(mapped_regs_t, pkrs[0])));
    4.68 -	DEFINE(XSI_PKR0, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, pkrs[0])));
    4.69 -	DEFINE(XSI_TMP0_OFS, (XSI_OFS + offsetof(mapped_regs_t, tmp[0])));
    4.70 -	DEFINE(XSI_TMP0, (SHARED_ARCHINFO_ADDR+offsetof(mapped_regs_t, tmp[0])));
    4.71 +	DEFINE_MAPPED_REG_OFS(XSI_PSR_I_ADDR_OFS, interrupt_mask_addr);
    4.72 +	DEFINE_MAPPED_REG_OFS(XSI_IPSR_OFS, ipsr);
    4.73 +	DEFINE_MAPPED_REG_OFS(XSI_IIP_OFS, iip);
    4.74 +	DEFINE_MAPPED_REG_OFS(XSI_IFS_OFS, ifs);
    4.75 +	DEFINE_MAPPED_REG_OFS(XSI_PRECOVER_IFS_OFS, precover_ifs);
    4.76 +	DEFINE_MAPPED_REG_OFS(XSI_ISR_OFS, isr);
    4.77 +	DEFINE_MAPPED_REG_OFS(XSI_IFA_OFS, ifa);
    4.78 +	DEFINE_MAPPED_REG_OFS(XSI_IIPA_OFS, iipa);
    4.79 +	DEFINE_MAPPED_REG_OFS(XSI_IIM_OFS, iim);
    4.80 +	DEFINE_MAPPED_REG_OFS(XSI_TPR_OFS, tpr);
    4.81 +	DEFINE_MAPPED_REG_OFS(XSI_IHA_OFS, iha);
    4.82 +	DEFINE_MAPPED_REG_OFS(XSI_ITIR_OFS, itir);
    4.83 +	DEFINE_MAPPED_REG_OFS(XSI_ITV_OFS, itv);
    4.84 +	DEFINE_MAPPED_REG_OFS(XSI_PTA_OFS, pta);
    4.85 +	DEFINE_MAPPED_REG_OFS(XSI_PSR_IC_OFS, interrupt_collection_enabled);
    4.86 +	DEFINE_MAPPED_REG_OFS(XSI_PEND_OFS, pending_interruption);
    4.87 +	DEFINE_MAPPED_REG_OFS(XSI_INCOMPL_REGFR_OFS, incomplete_regframe);
    4.88 +	DEFINE_MAPPED_REG_OFS(XSI_METAPHYS_OFS, metaphysical_mode);
    4.89 +	DEFINE_MAPPED_REG_OFS(XSI_BANKNUM_OFS, banknum);
    4.90 +	DEFINE_MAPPED_REG_OFS(XSI_BANK0_R16_OFS, bank0_regs[0]);
    4.91 +	DEFINE_MAPPED_REG_OFS(XSI_BANK1_R16_OFS, bank1_regs[0]);
    4.92 +	DEFINE_MAPPED_REG_OFS(XSI_B0NATS_OFS, vbnat);
    4.93 +	DEFINE_MAPPED_REG_OFS(XSI_B1NATS_OFS, vnat);
    4.94 +	DEFINE_MAPPED_REG_OFS(XSI_RR0_OFS, rrs[0]);
    4.95 +	DEFINE_MAPPED_REG_OFS(XSI_KR0_OFS, krs[0]);
    4.96  }
     5.1 --- a/xen/arch/ia64/vmx/vmx_entry.S	Wed Jun 21 11:17:08 2006 -0600
     5.2 +++ b/xen/arch/ia64/vmx/vmx_entry.S	Fri Jun 23 09:46:39 2006 -0600
     5.3 @@ -675,39 +675,6 @@ 1:
     5.4     itr.d dtr[r24]=loc2     // wire in new mapping...
     5.5     ;;
     5.6  
     5.7 -
     5.8 -#if    0
     5.9 -   // re-pin mappings for shared_info
    5.10 -
    5.11 -   mov r24=IA64_TR_SHARED_INFO
    5.12 -   movl r25=__pgprot(__DIRTY_BITS | _PAGE_PL_2 | _PAGE_AR_RW)
    5.13 -   ;;
    5.14 -   or loc3 = r25,loc3          // construct PA | page properties
    5.15 -   mov r23 = PAGE_SHIFT<<2
    5.16 -   ;;
    5.17 -   ptr.d   in1,r23
    5.18 -   ;;
    5.19 -   mov cr.itir=r23
    5.20 -   mov cr.ifa=in1
    5.21 -   ;;
    5.22 -   itr.d dtr[r24]=loc3     // wire in new mapping...
    5.23 -   ;;
    5.24 -   // re-pin mappings for shared_arch_info
    5.25 -
    5.26 -   mov r24=IA64_TR_ARCH_INFO
    5.27 -   or loc4 = r25,loc4          // construct PA | page properties
    5.28 -   mov r23 = PAGE_SHIFT<<2
    5.29 -   ;;
    5.30 -   ptr.d   in2,r23
    5.31 -   ;;
    5.32 -   mov cr.itir=r23
    5.33 -   mov cr.ifa=in2
    5.34 -   ;;
    5.35 -   itr.d dtr[r24]=loc4     // wire in new mapping...
    5.36 -   ;;
    5.37 -#endif
    5.38 -
    5.39 -
    5.40     // re-pin mappings for guest_vhpt
    5.41  
    5.42     mov r24=IA64_TR_PERVP_VHPT
     6.1 --- a/xen/arch/ia64/xen/domain.c	Wed Jun 21 11:17:08 2006 -0600
     6.2 +++ b/xen/arch/ia64/xen/domain.c	Fri Jun 23 09:46:39 2006 -0600
     6.3 @@ -88,6 +88,7 @@ extern struct vcpu *ia64_switch_to (stru
     6.4  /* Address of vpsr.i (in fact evtchn_upcall_mask) of current vcpu.
     6.5     This is a Xen virtual address.  */
     6.6  DEFINE_PER_CPU(uint8_t *, current_psr_i_addr);
     6.7 +DEFINE_PER_CPU(int *, current_psr_ic_addr);
     6.8  
     6.9  #include <xen/sched-if.h>
    6.10  
    6.11 @@ -106,6 +107,8 @@ void schedule_tail(struct vcpu *prev)
    6.12  		vcpu_load_kernel_regs(current);
    6.13  		__ia64_per_cpu_var(current_psr_i_addr) = &current->domain->
    6.14  		  shared_info->vcpu_info[current->vcpu_id].evtchn_upcall_mask;
    6.15 +		__ia64_per_cpu_var(current_psr_ic_addr) = (int *)
    6.16 +		  (current->domain->arch.shared_info_va + XSI_PSR_IC_OFS);
    6.17  	}
    6.18  }
    6.19  
    6.20 @@ -159,6 +162,8 @@ if (!i--) { i = 1000000; printk("+"); }
    6.21  			vcpu_pend_timer(current);
    6.22  		__ia64_per_cpu_var(current_psr_i_addr) = &nd->shared_info->
    6.23  		  vcpu_info[current->vcpu_id].evtchn_upcall_mask;
    6.24 +		__ia64_per_cpu_var(current_psr_ic_addr) =
    6.25 +		  (int *)(nd->arch.shared_info_va + XSI_PSR_IC_OFS);
    6.26      	} else {
    6.27  		/* When switching to idle domain, only need to disable vhpt
    6.28  		 * walker. Then all accesses happen within idle context will
    6.29 @@ -167,6 +172,7 @@ if (!i--) { i = 1000000; printk("+"); }
    6.30  		pta = ia64_get_pta();
    6.31  		ia64_set_pta(pta & ~VHPT_ENABLED);
    6.32  		__ia64_per_cpu_var(current_psr_i_addr) = NULL;
    6.33 +		__ia64_per_cpu_var(current_psr_ic_addr) = NULL;
    6.34          }
    6.35      }
    6.36      local_irq_restore(spsr);
    6.37 @@ -304,7 +310,7 @@ static void init_switch_stack(struct vcp
    6.38  int arch_domain_create(struct domain *d)
    6.39  {
    6.40  	// the following will eventually need to be negotiated dynamically
    6.41 -	d->arch.shared_info_va = SHAREDINFO_ADDR;
    6.42 +	d->arch.shared_info_va = DEFAULT_SHAREDINFO_ADDR;
    6.43  	d->arch.breakimm = 0x1000;
    6.44  
    6.45  	if (is_idle_domain(d))
    6.46 @@ -514,6 +520,41 @@ void build_physmap_table(struct domain *
    6.47  	d->arch.physmap_built = 1;
    6.48  }
    6.49  
    6.50 +unsigned long
    6.51 +domain_set_shared_info_va (unsigned long va)
    6.52 +{
    6.53 +	struct vcpu *v = current;
    6.54 +	struct domain *d = v->domain;
    6.55 +	struct vcpu *v1;
    6.56 +
    6.57 +	/* Check virtual address:
    6.58 +	   must belong to region 7,
    6.59 +	   must be 64Kb aligned,
    6.60 +	   must not be within Xen virtual space.  */
    6.61 +	if ((va >> 61) != 7
    6.62 +	    || (va & 0xffffUL) != 0
    6.63 +	    || (va >= HYPERVISOR_VIRT_START && va < HYPERVISOR_VIRT_END))
    6.64 +		panic_domain (NULL, "%s: bad va (0x%016lx)\n", __func__, va);
    6.65 +
    6.66 +	/* Note: this doesn't work well if other cpus are already running.
    6.67 +	   However this is part of the spec :-)  */
    6.68 +	printf ("Domain set shared_info_va to 0x%016lx\n", va);
    6.69 +	d->arch.shared_info_va = va;
    6.70 +
    6.71 +	for_each_vcpu (d, v1) {
    6.72 +		VCPU(v1, interrupt_mask_addr) = 
    6.73 +			(unsigned char *)va + INT_ENABLE_OFFSET(v1);
    6.74 +	}
    6.75 +
    6.76 +	__ia64_per_cpu_var(current_psr_ic_addr) = (int *)(va + XSI_PSR_IC_OFS);
    6.77 +
    6.78 +	/* Remap the shared pages.  */
    6.79 +	set_one_rr (7UL << 61, PSCB(v,rrs[7]));
    6.80 +
    6.81 +	return 0;
    6.82 +}
    6.83 +
    6.84 +
    6.85  // remove following line if not privifying in memory
    6.86  //#define HAVE_PRIVIFY_MEMORY
    6.87  #ifndef HAVE_PRIVIFY_MEMORY
     7.1 --- a/xen/arch/ia64/xen/faults.c	Wed Jun 21 11:17:08 2006 -0600
     7.2 +++ b/xen/arch/ia64/xen/faults.c	Fri Jun 23 09:46:39 2006 -0600
     7.3 @@ -118,7 +118,7 @@ void reflect_interruption(unsigned long 
     7.4  
     7.5  	regs->cr_iip = ((unsigned long) PSCBX(v,iva) + vector) & ~0xffUL;
     7.6  	regs->cr_ipsr = (regs->cr_ipsr & ~DELIVER_PSR_CLR) | DELIVER_PSR_SET;
     7.7 -	regs->r31 = XSI_IPSR;
     7.8 +	regs->r31 = current->domain->arch.shared_info_va + XSI_IPSR_OFS;
     7.9  
    7.10  	v->vcpu_info->evtchn_upcall_mask = 1;
    7.11  	PSCB(v,interrupt_collection_enabled) = 0;
    7.12 @@ -172,7 +172,7 @@ void reflect_event(struct pt_regs *regs)
    7.13  
    7.14  	regs->cr_iip = v->arch.event_callback_ip;
    7.15  	regs->cr_ipsr = (regs->cr_ipsr & ~DELIVER_PSR_CLR) | DELIVER_PSR_SET;
    7.16 -	regs->r31 = XSI_IPSR;
    7.17 +	regs->r31 = current->domain->arch.shared_info_va + XSI_IPSR_OFS;
    7.18  
    7.19  	v->vcpu_info->evtchn_upcall_mask = 1;
    7.20  	PSCB(v,interrupt_collection_enabled) = 0;
     8.1 --- a/xen/arch/ia64/xen/hypercall.c	Wed Jun 21 11:17:08 2006 -0600
     8.2 +++ b/xen/arch/ia64/xen/hypercall.c	Fri Jun 23 09:46:39 2006 -0600
     8.3 @@ -267,6 +267,9 @@ fw_hypercall (struct pt_regs *regs)
     8.4  	    case FW_HYPERCALL_IPI:
     8.5  		fw_hypercall_ipi (regs);
     8.6  		break;
     8.7 +	    case FW_HYPERCALL_SET_SHARED_INFO_VA:
     8.8 +	        regs->r8 = domain_set_shared_info_va (regs->r28);
     8.9 +		break;
    8.10  	    case FW_HYPERCALL_FPSWA:
    8.11  		fpswa_ret = fw_hypercall_fpswa (v);
    8.12  		regs->r8  = fpswa_ret.status;
     9.1 --- a/xen/arch/ia64/xen/hyperprivop.S	Wed Jun 21 11:17:08 2006 -0600
     9.2 +++ b/xen/arch/ia64/xen/hyperprivop.S	Fri Jun 23 09:46:39 2006 -0600
     9.3 @@ -304,9 +304,13 @@ ENTRY(hyper_ssm_i)
     9.4  	add r24=r24,r23;;
     9.5  	mov cr.iip=r24;;
     9.6  	// OK, now all set to go except for switch to virtual bank0
     9.7 -	mov r30=r2; mov r29=r3;;
     9.8 +	mov r30=r2
     9.9 +	mov r29=r3
    9.10 +	mov r28=r4
    9.11 +	;;
    9.12  	adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18;
    9.13  	adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18;;
    9.14 +	adds r4=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18
    9.15  	bsw.1;;
    9.16  	// FIXME?: ar.unat is not really handled correctly,
    9.17  	// but may not matter if the OS is NaT-clean
    9.18 @@ -326,9 +330,11 @@ ENTRY(hyper_ssm_i)
    9.19  	.mem.offset 8,0; st8.spill [r3]=r29,16 ;;
    9.20  	.mem.offset 0,0; st8.spill [r2]=r30,16;
    9.21  	.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
    9.22 -	movl r31=XSI_IPSR;;
    9.23 +	mov r31=r4
    9.24  	bsw.0 ;;
    9.25 -	mov r2=r30; mov r3=r29;;
    9.26 +	mov r2=r30
    9.27 +	mov r3=r29
    9.28 +	mov r4=r28
    9.29  	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
    9.30  	st4 [r20]=r0 ;;
    9.31  	mov pr=r31,-1 ;;
    9.32 @@ -372,7 +378,10 @@ GLOBAL_ENTRY(fast_tick_reflect)
    9.33  	st8 [r20]=r21;;
    9.34  #endif
    9.35  	// vcpu_pend_timer(current)
    9.36 -	movl r18=XSI_PSR_IC;;
    9.37 +	movl r18=THIS_CPU(current_psr_ic_addr)
    9.38 +	;;
    9.39 +	ld8 r18=[r18]
    9.40 +	;;
    9.41  	adds r20=XSI_ITV_OFS-XSI_PSR_IC_OFS,r18 ;;
    9.42  	ld8 r20=[r20];;
    9.43  	cmp.eq p6,p0=r20,r0	// if cr.itv==0 done
    9.44 @@ -481,12 +490,17 @@ GLOBAL_ENTRY(fast_tick_reflect)
    9.45  	add r24=r24,r23;;
    9.46  	mov cr.iip=r24;;
    9.47  	// OK, now all set to go except for switch to virtual bank0
    9.48 -	mov r30=r2; mov r29=r3;;
    9.49 +	mov r30=r2
    9.50 +	mov r29=r3
    9.51 +	mov r27=r4
    9.52  #ifdef HANDLE_AR_UNAT
    9.53  	mov r28=ar.unat;
    9.54  #endif
    9.55 -	adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18;
    9.56 -	adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18;;
    9.57 +	;;
    9.58 +	adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18
    9.59 +	adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18
    9.60 +	adds r4=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18
    9.61 +	;;
    9.62  	bsw.1;;
    9.63  	.mem.offset 0,0; st8.spill [r2]=r16,16;
    9.64  	.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
    9.65 @@ -506,28 +520,32 @@ GLOBAL_ENTRY(fast_tick_reflect)
    9.66  	.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
    9.67  #ifdef HANDLE_AR_UNAT
    9.68   	// r16~r23 are preserved regsin bank0 regs, we need to restore them,
    9.69 -    // r24~r31 are scratch regs, we don't need to handle NaT bit,
    9.70 -    // because OS handler must assign it before access it
    9.71 -    ld8 r16=[r2],16;
    9.72 -    ld8 r17=[r3],16;;
    9.73 -    ld8 r18=[r2],16;
    9.74 -    ld8 r19=[r3],16;;
    9.75 -    ld8 r20=[r2],16;
    9.76 -    ld8 r21=[r3],16;;
    9.77 -    ld8 r22=[r2],16;
    9.78 -    ld8 r23=[r3],16;;
    9.79 +	// r24~r31 are scratch regs, we don't need to handle NaT bit,
    9.80 +	// because OS handler must assign it before access it
    9.81 +	ld8 r16=[r2],16;
    9.82 +	ld8 r17=[r3],16;;
    9.83 +	ld8 r18=[r2],16;
    9.84 +	ld8 r19=[r3],16;;
    9.85 +	ld8 r20=[r2],16;
    9.86 +	ld8 r21=[r3],16;;
    9.87 +	ld8 r22=[r2],16;
    9.88 +	ld8 r23=[r3],16;;
    9.89  #endif
    9.90 -    movl r31=XSI_IPSR;;
    9.91 -    bsw.0 ;;
    9.92 -    mov r24=ar.unat;
    9.93 -    mov r2=r30; mov r3=r29;;
    9.94 +	mov r31=r4
    9.95 +	;;
    9.96 +	bsw.0 ;;
    9.97 +	mov r24=ar.unat;
    9.98 +	mov r2=r30
    9.99 +	mov r3=r29
   9.100 +	mov r4=r27
   9.101  #ifdef HANDLE_AR_UNAT
   9.102 -    mov ar.unat=r28;
   9.103 +	mov ar.unat=r28;
   9.104  #endif
   9.105 -    adds r25=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18 ;
   9.106 -    adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
   9.107 -    st8 [r25]=r24;
   9.108 -    st4 [r20]=r0 ;;
   9.109 +	;;
   9.110 +	adds r25=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18 ;
   9.111 +	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
   9.112 +	st8 [r25]=r24;
   9.113 +	st4 [r20]=r0 ;;
   9.114  fast_tick_reflect_done:
   9.115  	mov pr=r31,-1 ;;
   9.116  	rfi
   9.117 @@ -659,12 +677,16 @@ ENTRY(fast_reflect)
   9.118  	add r20=r20,r23;;
   9.119  	mov cr.iip=r20;;
   9.120  	// OK, now all set to go except for switch to virtual bank0
   9.121 -	mov r30=r2; mov r29=r3;;
   9.122 +	mov r30=r2
   9.123 +	mov r29=r3
   9.124  #ifdef HANDLE_AR_UNAT
   9.125  	mov r28=ar.unat;
   9.126  #endif
   9.127 +	mov r27=r4
   9.128  	adds r2=XSI_BANK1_R16_OFS-XSI_PSR_IC_OFS,r18;
   9.129 -	adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18;;
   9.130 +	adds r3=(XSI_BANK1_R16_OFS+8)-XSI_PSR_IC_OFS,r18
   9.131 +	adds r4=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18
   9.132 +	;;
   9.133  	bsw.1;;
   9.134  	.mem.offset 0,0; st8.spill [r2]=r16,16;
   9.135  	.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
   9.136 @@ -687,24 +709,28 @@ ENTRY(fast_reflect)
   9.137      // r24~r31 are scratch regs, we don't need to handle NaT bit,
   9.138      // because OS handler must assign it before access it
   9.139  	ld8 r16=[r2],16;
   9.140 -    ld8 r17=[r3],16;;
   9.141 -    ld8 r18=[r2],16;
   9.142 -    ld8 r19=[r3],16;;
   9.143 +	ld8 r17=[r3],16;;
   9.144 +	ld8 r18=[r2],16;
   9.145 +	ld8 r19=[r3],16;;
   9.146  	ld8 r20=[r2],16;
   9.147 -    ld8 r21=[r3],16;;
   9.148 -    ld8 r22=[r2],16;
   9.149 -    ld8 r23=[r3],16;;
   9.150 +	ld8 r21=[r3],16;;
   9.151 +	ld8 r22=[r2],16;
   9.152 +	ld8 r23=[r3],16;;
   9.153  #endif
   9.154 -	movl r31=XSI_IPSR;;
   9.155 +	mov r31=r4
   9.156 +	;;
   9.157  	bsw.0 ;;
   9.158 -    mov r24=ar.unat;
   9.159 -	mov r2=r30; mov r3=r29;;
   9.160 +	mov r24=ar.unat;
   9.161 +	mov r2=r30
   9.162 +	mov r3=r29
   9.163  #ifdef HANDLE_AR_UNAT
   9.164  	mov ar.unat=r28;
   9.165  #endif
   9.166 -    adds r25=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18 ;
   9.167 +	mov r4=r27
   9.168 +	;;
   9.169 +	adds r25=XSI_B1NATS_OFS-XSI_PSR_IC_OFS,r18 ;
   9.170  	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
   9.171 -    st8 [r25]=r24;
   9.172 +	st8 [r25]=r24;
   9.173  	st4 [r20]=r0 ;;
   9.174  	mov pr=r31,-1 ;;
   9.175  	rfi
   9.176 @@ -732,7 +758,8 @@ GLOBAL_ENTRY(fast_access_reflect)
   9.177  	extr.u r21=r30,IA64_PSR_CPL0_BIT,2 ;;
   9.178  	cmp.eq p7,p0=r21,r0
   9.179  (p7)	br.spnt.few dispatch_reflection ;;
   9.180 -	movl r18=XSI_PSR_IC;;
   9.181 +	movl r18=THIS_CPU(current_psr_ic_addr);;
   9.182 +	ld8 r18=[r18];;
   9.183  	ld4 r21=[r18];;
   9.184  	cmp.eq p7,p0=r0,r21
   9.185  (p7)	br.spnt.few dispatch_reflection ;;
   9.186 @@ -1043,8 +1070,8 @@ 1:
   9.187  	// validate vcr.iip, if in Xen range, do it the slow way
   9.188  	adds r20=XSI_IIP_OFS-XSI_PSR_IC_OFS,r18 ;;
   9.189  	ld8 r22=[r20];;
   9.190 -	movl r23=XEN_VIRT_SPACE_LOW
   9.191 -	movl r24=XEN_VIRT_SPACE_HIGH ;;
   9.192 +	movl r23=HYPERVISOR_VIRT_START
   9.193 +	movl r24=HYPERVISOR_VIRT_END;;
   9.194  	cmp.ltu p0,p7=r22,r23 ;;	// if !(iip<low) &&
   9.195  (p7)	cmp.geu p0,p7=r22,r24 ;;	//    !(iip>=high)
   9.196  (p7)	br.spnt.few dispatch_break_fault ;;
    10.1 --- a/xen/arch/ia64/xen/ivt.S	Wed Jun 21 11:17:08 2006 -0600
    10.2 +++ b/xen/arch/ia64/xen/ivt.S	Fri Jun 23 09:46:39 2006 -0600
    10.3 @@ -508,10 +508,9 @@ late_alt_dtlb_miss:
    10.4  	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
    10.5  	mov r21=cr.ipsr
    10.6  	;;
    10.7 -#else
    10.8  #endif
    10.9  #ifdef CONFIG_DISABLE_VHPT
   10.10 -	shr.u r22=r16,61			// get the region number into r21
   10.11 +	shr.u r22=r16,61			// get the region into r22
   10.12  	;;
   10.13  	cmp.gt p8,p0=6,r22			// access to region 0-5
   10.14  	;;
   10.15 @@ -992,7 +991,9 @@ ENTRY(break_fault)
   10.16          cmp.eq p7,p0=r17,r18 ;; 
   10.17  (p7)    br.spnt.few dispatch_break_fault ;;
   10.18  #endif
   10.19 -	movl r18=XSI_PSR_IC
   10.20 +	movl r18=THIS_CPU(current_psr_ic_addr)
   10.21 +	;;
   10.22 +	ld8 r18=[r18]
   10.23  	;;
   10.24  	ld4 r19=[r18]
   10.25  	;;
    11.1 --- a/xen/arch/ia64/xen/vcpu.c	Wed Jun 21 11:17:08 2006 -0600
    11.2 +++ b/xen/arch/ia64/xen/vcpu.c	Fri Jun 23 09:46:39 2006 -0600
    11.3 @@ -1354,7 +1354,7 @@ check_xen_space_overlap (const char *fun
    11.4  	base &= ~(page_size - 1);
    11.5  
    11.6  	/* FIXME: ideally an MCA should be generated...  */
    11.7 -	if (range_overlap (XEN_VIRT_SPACE_LOW, XEN_VIRT_SPACE_HIGH,
    11.8 +	if (range_overlap (HYPERVISOR_VIRT_START, HYPERVISOR_VIRT_END,
    11.9  			   base, base + page_size))
   11.10  		panic_domain (NULL, "%s on Xen virtual space (%lx)\n",
   11.11  			      func, base);
    12.1 --- a/xen/arch/ia64/xen/xenasm.S	Wed Jun 21 11:17:08 2006 -0600
    12.2 +++ b/xen/arch/ia64/xen/xenasm.S	Fri Jun 23 09:46:39 2006 -0600
    12.3 @@ -10,7 +10,8 @@
    12.4  #include <asm/processor.h>
    12.5  #include <asm/pgtable.h>
    12.6  #include <asm/vhpt.h>
    12.7 -
    12.8 +#include <public/arch-ia64.h>
    12.9 +	
   12.10  // Change rr7 to the passed value while ensuring
   12.11  // Xen is mapped into the new region.
   12.12  #define PSR_BITS_TO_CLEAR						\
   12.13 @@ -140,8 +141,8 @@ 1:
   12.14  	;;
   12.15  	itr.d dtr[r21]=r23		// wire in new mapping...
   12.16  	
   12.17 -	// Map for arch_vcpu_info_t
   12.18 -	movl r22=XSI_OFS
   12.19 +	// Map mapped_regs
   12.20 +	mov r22=XMAPPEDREGS_OFS
   12.21  	mov r24=PAGE_SHIFT<<2
   12.22  	;; 
   12.23  	add r22=r22,in3
   12.24 @@ -150,7 +151,7 @@ 1:
   12.25  	or r23=loc7,r25			// construct PA | page properties
   12.26  	mov cr.itir=r24
   12.27  	mov cr.ifa=r22
   12.28 -	mov r21=IA64_TR_ARCH_INFO
   12.29 +	mov r21=IA64_TR_MAPPED_REGS
   12.30  	;;
   12.31  	itr.d dtr[r21]=r23		// wire in new mapping...
   12.32  
   12.33 @@ -239,19 +240,24 @@ GLOBAL_ENTRY(__get_domain_bundle)
   12.34  END(__get_domain_bundle)
   12.35  
   12.36  GLOBAL_ENTRY(dorfirfi)
   12.37 -        movl r16 = XSI_IIP
   12.38 -        movl r17 = XSI_IPSR
   12.39 -        movl r18 = XSI_IFS
   12.40 +	// Read current vcpu shared info
   12.41 +	movl r16=THIS_CPU(current_psr_ic_addr)
   12.42 +	;;
   12.43 +	ld8 r19 = [r16]
   12.44 +	;;
   12.45 +	add r16 = XSI_IIP_OFS - XSI_PSR_IC_OFS, r19
   12.46 +	add r17 = XSI_IPSR_OFS - XSI_PSR_IC_OFS, r19
   12.47 +	add r18 = XSI_IFS_OFS - XSI_PSR_IC_OFS, r19
   12.48  	;;
   12.49  	ld8 r16 = [r16]
   12.50  	ld8 r17 = [r17]
   12.51  	ld8 r18 = [r18]
   12.52  	;;
   12.53 -        mov cr.iip=r16
   12.54 -        mov cr.ipsr=r17
   12.55 -        mov cr.ifs=r18
   12.56 +	mov cr.iip=r16
   12.57 +	mov cr.ipsr=r17
   12.58 +	mov cr.ifs=r18
   12.59  	;;
   12.60 -        rfi
   12.61 +	rfi
   12.62  	;;
   12.63  END(dorfirfi)
   12.64  
    13.1 --- a/xen/include/asm-ia64/dom_fw.h	Wed Jun 21 11:17:08 2006 -0600
    13.2 +++ b/xen/include/asm-ia64/dom_fw.h	Fri Jun 23 09:46:39 2006 -0600
    13.3 @@ -145,6 +145,9 @@
    13.4  #define FW_HYPERCALL_FPSWA_PATCH_PADDR			FW_HYPERCALL_PADDR(FW_HYPERCALL_FPSWA_PATCH_INDEX)
    13.5  #define FW_HYPERCALL_FPSWA				0x500UL
    13.6  
    13.7 +/* Set the shared_info base virtual address.  */
    13.8 +#define FW_HYPERCALL_SET_SHARED_INFO_VA			0x600UL
    13.9 +
   13.10  /* Hypercalls index bellow _FIRST_ARCH are reserved by Xen, while those above
   13.11     are for the architecture.
   13.12     Note: this limit was defined by Xen/ia64 (and not by Xen).²
    14.1 --- a/xen/include/asm-ia64/domain.h	Wed Jun 21 11:17:08 2006 -0600
    14.2 +++ b/xen/include/asm-ia64/domain.h	Fri Jun 23 09:46:39 2006 -0600
    14.3 @@ -27,7 +27,7 @@ p2m_entry_set(struct p2m_entry* entry, v
    14.4  static inline int
    14.5  p2m_entry_retry(struct p2m_entry* entry)
    14.6  {
    14.7 -    //XXX see lookup_domian_pte().
    14.8 +    //XXX see lookup_domain_pte().
    14.9      //    NULL is set for invalid gpaddr for the time being.
   14.10      if (entry->pte == NULL)
   14.11          return 0;
   14.12 @@ -41,6 +41,9 @@ extern void domain_relinquish_resources(
   14.13  extern unsigned long translate_domain_mpaddr(unsigned long mpaddr,
   14.14                                               struct p2m_entry* entry);
   14.15  
   14.16 +/* Set shared_info virtual address.  */
   14.17 +extern unsigned long domain_set_shared_info_va (unsigned long va);
   14.18 +
   14.19  /* Flush cache of domain d.
   14.20     If sync_only is true, only synchronize I&D caches,
   14.21     if false, flush and invalidate caches.  */
    15.1 --- a/xen/include/asm-ia64/xenkregs.h	Wed Jun 21 11:17:08 2006 -0600
    15.2 +++ b/xen/include/asm-ia64/xenkregs.h	Fri Jun 23 09:46:39 2006 -0600
    15.3 @@ -6,7 +6,7 @@
    15.4   */
    15.5  #define IA64_TR_SHARED_INFO	3	/* dtr3: page shared with domain */
    15.6  #define	IA64_TR_VHPT		4	/* dtr4: vhpt */
    15.7 -#define IA64_TR_ARCH_INFO	5
    15.8 +#define IA64_TR_MAPPED_REGS	5	/* dtr5: vcpu mapped regs */
    15.9  #define IA64_TR_PERVP_VHPT	6
   15.10  #define IA64_DTR_GUEST_KERNEL   7
   15.11  #define IA64_ITR_GUEST_KERNEL   2
    16.1 --- a/xen/include/asm-ia64/xensystem.h	Wed Jun 21 11:17:08 2006 -0600
    16.2 +++ b/xen/include/asm-ia64/xensystem.h	Fri Jun 23 09:46:39 2006 -0600
    16.3 @@ -16,26 +16,20 @@
    16.4  /* Define HV space hierarchy.
    16.5     VMM memory space is protected by CPL for paravirtualized domains and
    16.6     by VA for VTi domains.  VTi imposes VA bit 60 != VA bit 59 for VMM.  */
    16.7 -#define XEN_VIRT_SPACE_LOW	 0xe800000000000000
    16.8 -#define XEN_VIRT_SPACE_HIGH	 0xf800000000000000	
    16.9  
   16.10 -#define __IA64_UNCACHED_OFFSET	 0xe800000000000000UL
   16.11 -
   16.12 -#define XEN_START_ADDR		 0xf000000000000000
   16.13 -#define HYPERVISOR_VIRT_START	 0xf000000000000000
   16.14 +#define HYPERVISOR_VIRT_START	 0xe800000000000000
   16.15  #define KERNEL_START		 0xf000000004000000
   16.16 -#define SHAREDINFO_ADDR		 0xf100000000000000
   16.17 -#define XSI_OFS 		 PAGE_SIZE
   16.18 -#define SHARED_ARCHINFO_ADDR	 (SHAREDINFO_ADDR + XSI_OFS)
   16.19 -#define PERCPU_ADDR		 (SHAREDINFO_ADDR - PERCPU_PAGE_SIZE)
   16.20 +#define DEFAULT_SHAREDINFO_ADDR	 0xf100000000000000
   16.21 +#define PERCPU_ADDR		 (DEFAULT_SHAREDINFO_ADDR - PERCPU_PAGE_SIZE)
   16.22  #define VHPT_ADDR		 0xf200000000000000
   16.23  #ifdef CONFIG_VIRTUAL_FRAME_TABLE
   16.24  #define VIRT_FRAME_TABLE_ADDR	 0xf300000000000000
   16.25  #define VIRT_FRAME_TABLE_END	 0xf400000000000000
   16.26  #endif
   16.27 -#define XEN_END_ADDR		 0xf400000000000000
   16.28 +#define HYPERVISOR_VIRT_END	 0xf800000000000000
   16.29  
   16.30 -#define PAGE_OFFSET	__IA64_UL_CONST(0xf000000000000000)
   16.31 +#define PAGE_OFFSET		 __IA64_UL_CONST(0xf000000000000000)
   16.32 +#define __IA64_UNCACHED_OFFSET	 0xe800000000000000UL
   16.33  
   16.34  #define IS_VMM_ADDRESS(addr) ((((addr) >> 60) ^ ((addr) >> 59)) & 1)
   16.35  
    17.1 --- a/xen/include/public/arch-ia64.h	Wed Jun 21 11:17:08 2006 -0600
    17.2 +++ b/xen/include/public/arch-ia64.h	Fri Jun 23 09:46:39 2006 -0600
    17.3 @@ -380,13 +380,17 @@ DEFINE_XEN_GUEST_HANDLE(vcpu_guest_conte
    17.4  
    17.5  #endif /* !__ASSEMBLY__ */
    17.6  
    17.7 -/* Address of shared_info in domain virtual space.  */
    17.8 -#define XSI_BASE	0xf100000000000000
    17.9 +/* Address of shared_info in domain virtual space.
   17.10 +   This is the default address, for compatibility only.  */
   17.11 +#define XSI_BASE				0xf100000000000000
   17.12 +
   17.13  /* Size of the shared_info area (this is not related to page size).  */
   17.14 -#define XSI_LOG_SIZE	14
   17.15 -#define XSI_SIZE	(1 << XSI_LOG_SIZE)
   17.16 +#define XSI_LOG_SIZE			14
   17.17 +#define XSI_SIZE				(1 << XSI_LOG_SIZE)
   17.18  /* Log size of mapped_regs area (64 KB - only 4KB is used).  */
   17.19 -#define XASI_LOG_SIZE	16
   17.20 +#define XMAPPEDREGS_LOG_SIZE	16
   17.21 +/* Offset of XASI (Xen arch shared info) wrt XSI_BASE.  */
   17.22 +#define XMAPPEDREGS_OFS			XSI_SIZE
   17.23  
   17.24  /* Hyperprivops.  */
   17.25  #define HYPERPRIVOP_RFI			0x1