direct-io.hg

changeset 10387:b87ff075dab9

[IA64] Put guest physical translation into VHPT

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author awilliam@xenbuild.aw
date Thu Jun 08 11:08:35 2006 -0600 (2006-06-08)
parents b20733e82ab6
children 1c9bdbc5e27b
files xen/arch/ia64/vmx/vmx_phy_mode.c xen/arch/ia64/vmx/vmx_process.c xen/include/asm-ia64/vmx_phy_mode.h
line diff
     1.1 --- a/xen/arch/ia64/vmx/vmx_phy_mode.c	Thu Jun 08 11:00:09 2006 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vmx_phy_mode.c	Thu Jun 08 11:08:35 2006 -0600
     1.3 @@ -105,54 +105,19 @@ physical_mode_init(VCPU *vcpu)
     1.4  }
     1.5  
     1.6  extern void vmx_switch_rr7(unsigned long ,shared_info_t*,void *,void *,void *);
     1.7 -/*void
     1.8 -physical_itlb_miss(VCPU *vcpu, u64 vadr)
     1.9 +
    1.10 +void
    1.11 +physical_tlb_miss(VCPU *vcpu, u64 vadr)
    1.12  {
    1.13 -    u64 psr;
    1.14 +    u64 pte;
    1.15      IA64_PSR vpsr;
    1.16 -    u64 xen_mppn,xen_gppn;
    1.17      vpsr.val=vmx_vcpu_get_psr(vcpu);
    1.18 -    xen_gppn=(vadr<<1)>>(PAGE_SHIFT+1);
    1.19 -    xen_mppn = gmfn_to_mfn(vcpu->domain, xen_gppn);
    1.20 -    xen_mppn=(xen_mppn<<PAGE_SHIFT)|(vpsr.cpl<<7);
    1.21 -    if(vadr>>63)
    1.22 -        xen_mppn |= PHY_PAGE_UC;
    1.23 -    else
    1.24 -        xen_mppn |= PHY_PAGE_WB;
    1.25 -
    1.26 -    psr=ia64_clear_ic();
    1.27 -    ia64_itc(1,vadr&PAGE_MASK,xen_mppn,PAGE_SHIFT);
    1.28 -    ia64_set_psr(psr);
    1.29 -    ia64_srlz_i();
    1.30 +    pte =  vadr& _PAGE_PPN_MASK;
    1.31 +    pte = pte|(vpsr.cpl<<7)|PHY_PAGE_WB;
    1.32 +    thash_purge_and_insert(vcpu, pte, (PAGE_SHIFT<<2), vadr);
    1.33      return;
    1.34  }
    1.35  
    1.36 -*/
    1.37 -/* 
    1.38 - *      vec=1, itlb miss
    1.39 - *      vec=2, dtlb miss
    1.40 - */
    1.41 -void
    1.42 -physical_tlb_miss(VCPU *vcpu, u64 vadr, u64 vec)
    1.43 -{
    1.44 -    u64 psr;
    1.45 -    IA64_PSR vpsr;
    1.46 -    u64 xen_mppn,xen_gppn;
    1.47 -    vpsr.val=vmx_vcpu_get_psr(vcpu);
    1.48 -    xen_gppn=(vadr<<1)>>(PAGE_SHIFT+1);
    1.49 -    xen_mppn = gmfn_to_mfn(vcpu->domain, xen_gppn);
    1.50 -    xen_mppn=(xen_mppn<<PAGE_SHIFT)|(vpsr.cpl<<7);
    1.51 -    if(vadr>>63)
    1.52 -        xen_mppn |= PHY_PAGE_UC;
    1.53 -    else
    1.54 -        xen_mppn |= PHY_PAGE_WB;
    1.55 -
    1.56 -    psr=ia64_clear_ic();
    1.57 -    ia64_itc(vec,vadr&PAGE_MASK,xen_mppn,PAGE_SHIFT);
    1.58 -    ia64_set_psr(psr);
    1.59 -    ia64_srlz_i();
    1.60 -    return;
    1.61 -}
    1.62  
    1.63  void
    1.64  vmx_init_all_rr(VCPU *vcpu)
     2.1 --- a/xen/arch/ia64/vmx/vmx_process.c	Thu Jun 08 11:00:09 2006 -0600
     2.2 +++ b/xen/arch/ia64/vmx/vmx_process.c	Thu Jun 08 11:08:35 2006 -0600
     2.3 @@ -259,7 +259,7 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
     2.4                  return IA64_FAULT;
     2.5              }
     2.6          }
     2.7 -        physical_tlb_miss(v, vadr, vec);
     2.8 +        physical_tlb_miss(v, vadr);
     2.9          return IA64_FAULT;
    2.10      }
    2.11      if(vec == 1) type = ISIDE_TLB;
     3.1 --- a/xen/include/asm-ia64/vmx_phy_mode.h	Thu Jun 08 11:00:09 2006 -0600
     3.2 +++ b/xen/include/asm-ia64/vmx_phy_mode.h	Thu Jun 08 11:08:35 2006 -0600
     3.3 @@ -96,7 +96,7 @@ extern void prepare_if_physical_mode(VCP
     3.4  extern void recover_if_physical_mode(VCPU *vcpu);
     3.5  extern void vmx_init_all_rr(VCPU *vcpu);
     3.6  extern void vmx_load_all_rr(VCPU *vcpu);
     3.7 -extern void physical_tlb_miss(VCPU *vcpu, u64 vadr, u64 vec);
     3.8 +extern void physical_tlb_miss(VCPU *vcpu, u64 vadr);
     3.9  /*
    3.10   * No sanity check here, since all psr changes have been
    3.11   * checked in switch_mm_mode().