direct-io.hg

changeset 814:b487e696e814

bitkeeper revision 1.498.1.2 (3f870808Dvsdzic2p7uQgZ0pTQzx7w)

add a handy tool for reading the P4 performance counters: xen_perfctr
author iap10@labyrinth.cl.cam.ac.uk
date Fri Oct 10 19:27:04 2003 +0000 (2003-10-10)
parents 0247e417838a
children 399bb8faf92a
files .rootkeys tools/misc/Makefile tools/misc/p4perf.h tools/misc/xen_cpuperf.c
line diff
     1.1 --- a/.rootkeys	Fri Oct 10 19:26:34 2003 +0000
     1.2 +++ b/.rootkeys	Fri Oct 10 19:27:04 2003 +0000
     1.3 @@ -177,9 +177,11 @@ 3f776bd2Xd-dUcPKlPN2vG89VGtfvQ tools/mis
     1.4  3f6dc136ZKOjd8PIqLbFBl_v-rnkGg tools/misc/miniterm/Makefile
     1.5  3f6dc140C8tAeBfroAF24VrmCS4v_w tools/misc/miniterm/README
     1.6  3f6dc142IHaf6XIcAYGmhV9nNSIHFQ tools/misc/miniterm/miniterm.c
     1.7 +3f870808_8aFBAcZbWiWGdgrGQyIEw tools/misc/p4perf.h
     1.8  3f5ef5a2ir1kVAthS14Dc5QIRCEFWg tools/misc/xen-clone
     1.9  3f5ef5a2dTZP0nnsFoeq2jRf3mWDDg tools/misc/xen-clone.README
    1.10  3f1668d4-FUY6Enc7MB3GcwUtfJ5HA tools/misc/xen-mkdevnodes
    1.11 +3f870808zS6T6iFhqYPGelroZlVfGQ tools/misc/xen_cpuperf.c
    1.12  3f13d81eQ9Vz-h-6RDGFkNR9CRP95g tools/misc/xen_nat_enable
    1.13  3f13d81e6Z6806ihYYUw8GVKNkYnuw tools/misc/xen_nat_enable.README
    1.14  3f1668d4F29Jsw0aC0bJEIkOBiagiQ tools/misc/xen_read_console.c
     2.1 --- a/tools/misc/Makefile	Fri Oct 10 19:26:34 2003 +0000
     2.2 +++ b/tools/misc/Makefile	Fri Oct 10 19:27:04 2003 +0000
     2.3 @@ -1,13 +1,13 @@
     2.4  
     2.5  CC       = gcc
     2.6  CFLAGS   = -Wall -O3 
     2.7 -CFLAGS  += -I../../xen/include -I../../xenolinux-sparse/include
     2.8 +CFLAGS  += -I../../xen/include -I../../xenolinux-sparse/include -I../internal
     2.9  
    2.10  HDRS     = $(wildcard *.h)
    2.11  SRCS     = $(wildcard *.c)
    2.12  OBJS     = $(patsubst %.c,%.o,$(SRCS))
    2.13  
    2.14 -TARGETS  = xen_read_console 
    2.15 +TARGETS  = xen_read_console xen_cpuperf
    2.16  
    2.17  INSTALL  = $(TARGETS) xen-mkdevnodes xen-clone
    2.18  
     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/tools/misc/p4perf.h	Fri Oct 10 19:27:04 2003 +0000
     3.3 @@ -0,0 +1,559 @@
     3.4 +/*
     3.5 + * For P6 use PERFCTR1 (0 used for APIC NMI watchdog). Must setup after
     3.6 + * APIC NMI watchdog setup. Note that if this previous setup doesn't happen
     3.7 + * we still must enable both counters.
     3.8 + *
     3.9 + * P4 Xeon with Hyperthreading has counters per physical package which can
    3.10 + * count events from either logical CPU. However, in many cases more than
    3.11 + * ECSR and CCCR/counter can be used to count the same event. For instr or
    3.12 + * uops retired, use either ESCR0/IQ_CCCR0 ESCR1/IQ_CCCR2.
    3.13 + *
    3.14 + * USE CONFIG_MPENTIUM4_HT for a P4 Xeon with hyperthreading.
    3.15 + *
    3.16 + * Note that the counters may be initialised on each logical processor
    3.17 + * which will cause each physical processor to be initialised twice. This
    3.18 + * should not cause a problem.
    3.19 + */
    3.20 +
    3.21 +#ifndef P4PERF_H
    3.22 +#define P4PERF_H
    3.23 +
    3.24 +#ifdef __KERNEL__
    3.25 +#include <asm/msr.h>
    3.26 +#endif
    3.27 +
    3.28 +/*****************************************************************************
    3.29 + * Performance counter configuration.                                        *
    3.30 + *****************************************************************************/
    3.31 +
    3.32 +#ifndef P6_EVNTSEL_OS
    3.33 +# define P6_EVNTSEL_OS     (1 << 17)
    3.34 +# define P6_EVNTSEL_USR    (1 << 16)
    3.35 +# define P6_EVNTSEL_E      (1 << 18)
    3.36 +# define P6_EVNTSEL_EN     (1 << 22)
    3.37 +#endif
    3.38 +#define P6_PERF_INST_RETIRED 0xc0
    3.39 +#define P6_PERF_UOPS_RETIRED 0xc2
    3.40 +
    3.41 +#define P4_ESCR_USR                    (1 << 2)
    3.42 +#define P4_ESCR_OS                     (1 << 3)
    3.43 +#define P4_ESCR_T0_USR                 (1 << 2) /* First logical CPU  */
    3.44 +#define P4_ESCR_T0_OS                  (1 << 3)
    3.45 +#define P4_ESCR_T1_USR                 (1 << 0) /* Second logical CPU */
    3.46 +#define P4_ESCR_T1_OS                  (1 << 1)
    3.47 +#define P4_ESCR_TE                     (1 << 4)
    3.48 +#define P4_ESCR_THREADS(t)             (t)
    3.49 +#define P4_ESCR_TV(tag)                (tag << 5)
    3.50 +#define P4_ESCR_EVNTSEL(e)             (e << 25)
    3.51 +#define P4_ESCR_EVNTMASK(e)            (e << 9)
    3.52 +
    3.53 +#define P4_ESCR_EVNTSEL_FRONT_END      0x08
    3.54 +#define P4_ESCR_EVNTSEL_EXECUTION      0x0c
    3.55 +#define P4_ESCR_EVNTSEL_REPLAY         0x09
    3.56 +#define P4_ESCR_EVNTSEL_INSTR_RETIRED  0x02
    3.57 +#define P4_ESCR_EVNTSEL_UOPS_RETIRED   0x01
    3.58 +#define P4_ESCR_EVNTSEL_UOP_TYPE       0x02
    3.59 +#define P4_ESCR_EVNTSEL_RET_MBR_TYPE   0x05
    3.60 +//#define P4_ESCR_EVNTSEL_RET_MBR_TYPE   0x04
    3.61 +
    3.62 +#define P4_ESCR_EVNTMASK_FE_NBOGUS     0x01
    3.63 +#define P4_ESCR_EVNTMASK_FE_BOGUS      0x02
    3.64 +
    3.65 +#define P4_ESCR_EVNTMASK_EXEC_NBOGUS0  0x01
    3.66 +#define P4_ESCR_EVNTMASK_EXEC_NBOGUS1  0x02
    3.67 +#define P4_ESCR_EVNTMASK_EXEC_NBOGUS2  0x04
    3.68 +#define P4_ESCR_EVNTMASK_EXEC_NBOGUS3  0x08
    3.69 +#define P4_ESCR_EVNTMASK_EXEC_BOGUS0   0x10
    3.70 +#define P4_ESCR_EVNTMASK_EXEC_BOGUS1   0x20
    3.71 +#define P4_ESCR_EVNTMASK_EXEC_BOGUS2   0x40
    3.72 +#define P4_ESCR_EVNTMASK_EXEC_BOGUS3   0x80
    3.73 +
    3.74 +#define P4_ESCR_EVNTMASK_REPLAY_NBOGUS 0x01
    3.75 +#define P4_ESCR_EVNTMASK_REPLAY_BOGUS  0x02
    3.76 +
    3.77 +#define P4_ESCR_EVNTMASK_IRET_NB_NTAG  0x01
    3.78 +#define P4_ESCR_EVNTMASK_IRET_NB_TAG   0x02
    3.79 +#define P4_ESCR_EVNTMASK_IRET_B_NTAG   0x04
    3.80 +#define P4_ESCR_EVNTMASK_IRET_B_TAG    0x08
    3.81 +
    3.82 +#define P4_ESCR_EVNTMASK_URET_NBOGUS   0x01
    3.83 +#define P4_ESCR_EVNTMASK_URET_BOGUS    0x02
    3.84 +
    3.85 +#define P4_ESCR_EVNTMASK_UOP_LOADS     0x02
    3.86 +#define P4_ESCR_EVNTMASK_UOP_STORES    0x04
    3.87 +
    3.88 +#define P4_ESCR_EVNTMASK_RMBRT_COND    0x02
    3.89 +#define P4_ESCR_EVNTMASK_RMBRT_CALL    0x04
    3.90 +#define P4_ESCR_EVNTMASK_RMBRT_RETURN  0x08
    3.91 +#define P4_ESCR_EVNTMASK_RMBRT_INDIR   0x10
    3.92 +
    3.93 +#define P4_ESCR_EVNTMASK_RBRT_COND     0x02
    3.94 +#define P4_ESCR_EVNTMASK_RBRT_CALL     0x04
    3.95 +#define P4_ESCR_EVNTMASK_RBRT_RETURN   0x08
    3.96 +#define P4_ESCR_EVNTMASK_RBRT_INDIR    0x10
    3.97 +
    3.98 +//#define P4_ESCR_EVNTMASK_INSTR_RETIRED 0x01  /* Non bogus, not tagged */
    3.99 +//#define P4_ESCR_EVNTMASK_UOPS_RETIRED  0x01  /* Non bogus             */
   3.100 +
   3.101 +#define P4_CCCR_OVF                    (1 << 31)
   3.102 +#define P4_CCCR_CASCADE                (1 << 30)
   3.103 +#define P4_CCCR_FORCE_OVF              (1 << 25)
   3.104 +#define P4_CCCR_EDGE                   (1 << 24)
   3.105 +#define P4_CCCR_COMPLEMENT             (1 << 19)
   3.106 +#define P4_CCCR_COMPARE                (1 << 18)
   3.107 +#define P4_CCCR_THRESHOLD(t)           (t << 20)
   3.108 +#define P4_CCCR_ENABLE                 (1 << 12)
   3.109 +#define P4_CCCR_ESCR(escr)             (escr << 13)
   3.110 +#define P4_CCCR_ACTIVE_THREAD(t)       (t << 16)   /* Set to 11 */
   3.111 +#define P4_CCCR_OVF_PMI_T0             (1 << 26)
   3.112 +#define P4_CCCR_OVF_PMI_T1             (1 << 27)
   3.113 +#define P4_CCCR_RESERVED               (3 << 16)
   3.114 +#define P4_CCCR_OVF_PMI                (1 << 26)
   3.115 +
   3.116 +// BPU
   3.117 +#define MSR_P4_BPU_COUNTER0            0x300
   3.118 +#define MSR_P4_BPU_COUNTER1            0x301
   3.119 +#define MSR_P4_BPU_CCCR0               0x360
   3.120 +#define MSR_P4_BPU_CCCR1               0x361
   3.121 +
   3.122 +#define MSR_P4_BPU_COUNTER2            0x302
   3.123 +#define MSR_P4_BPU_COUNTER3            0x303
   3.124 +#define MSR_P4_BPU_CCCR2               0x362
   3.125 +#define MSR_P4_BPU_CCCR3               0x363
   3.126 +
   3.127 +#define MSR_P4_BSU_ESCR0               0x3a0
   3.128 +#define MSR_P4_FSB_ESCR0               0x3a2
   3.129 +#define MSR_P4_MOB_ESCR0               0x3aa
   3.130 +#define MSR_P4_PMH_ESCR0               0x3ac
   3.131 +#define MSR_P4_BPU_ESCR0               0x3b2
   3.132 +#define MSR_P4_IS_ESCR0                0x3b4
   3.133 +#define MSR_P4_ITLB_ESCR0              0x3b6
   3.134 +#define MSR_P4_IX_ESCR0                0x3c8
   3.135 +
   3.136 +#define P4_BSU_ESCR0_NUMBER            7
   3.137 +#define P4_FSB_ESCR0_NUMBER            6
   3.138 +#define P4_MOB_ESCR0_NUMBER            2
   3.139 +#define P4_PMH_ESCR0_NUMBER            4
   3.140 +#define P4_BPU_ESCR0_NUMBER            0
   3.141 +#define P4_IS_ESCR0_NUMBER             1
   3.142 +#define P4_ITLB_ESCR0_NUMBER           3
   3.143 +#define P4_IX_ESCR0_NUMBER             5
   3.144 +
   3.145 +#define MSR_P4_BSU_ESCR1               0x3a1
   3.146 +#define MSR_P4_FSB_ESCR1               0x3a3
   3.147 +#define MSR_P4_MOB_ESCR1               0x3ab
   3.148 +#define MSR_P4_PMH_ESCR1               0x3ad
   3.149 +#define MSR_P4_BPU_ESCR1               0x3b3
   3.150 +#define MSR_P4_IS_ESCR1                0x3b5
   3.151 +#define MSR_P4_ITLB_ESCR1              0x3b7
   3.152 +#define MSR_P4_IX_ESCR1                0x3c9
   3.153 +
   3.154 +#define P4_BSU_ESCR1_NUMBER            7
   3.155 +#define P4_FSB_ESCR1_NUMBER            6
   3.156 +#define P4_MOB_ESCR1_NUMBER            2
   3.157 +#define P4_PMH_ESCR1_NUMBER            4
   3.158 +#define P4_BPU_ESCR1_NUMBER            0
   3.159 +#define P4_IS_ESCR1_NUMBER             1
   3.160 +#define P4_ITLB_ESCR1_NUMBER           3
   3.161 +#define P4_IX_ESCR1_NUMBER             5
   3.162 +
   3.163 +// MS
   3.164 +#define MSR_P4_MS_COUNTER0             0x304
   3.165 +#define MSR_P4_MS_COUNTER1             0x305
   3.166 +#define MSR_P4_MS_CCCR0                0x364
   3.167 +#define MSR_P4_MS_CCCR1                0x365
   3.168 +
   3.169 +#define MSR_P4_MS_COUNTER2             0x306
   3.170 +#define MSR_P4_MS_COUNTER3             0x307
   3.171 +#define MSR_P4_MS_CCCR2                0x366
   3.172 +#define MSR_P4_MS_CCCR3                0x367
   3.173 +
   3.174 +#define MSR_P4_MS_ESCR0                0x3c0
   3.175 +#define MSR_P4_TBPU_ESCR0              0x3c2
   3.176 +#define MSR_P4_TC_ESCR0                0x3c4
   3.177 +
   3.178 +#define P4_MS_ESCR0_NUMBER             0
   3.179 +#define P4_TBPU_ESCR0_NUMBER           2
   3.180 +#define P4_TC_ESCR0_NUMBER             1
   3.181 +
   3.182 +#define MSR_P4_MS_ESCR1                0x3c1
   3.183 +#define MSR_P4_TBPU_ESCR1              0x3c3
   3.184 +#define MSR_P4_TC_ESCR1                0x3c5
   3.185 +
   3.186 +#define P4_MS_ESCR1_NUMBER             0
   3.187 +#define P4_TBPU_ESCR1_NUMBER           2
   3.188 +#define P4_TC_ESCR1_NUMBER             1
   3.189 +
   3.190 +// FLAME
   3.191 +#define MSR_P4_FLAME_COUNTER0          0x308
   3.192 +#define MSR_P4_FLAME_COUNTER1          0x309
   3.193 +#define MSR_P4_FLAME_CCCR0             0x368
   3.194 +#define MSR_P4_FLAME_CCCR1             0x369
   3.195 +
   3.196 +#define MSR_P4_FLAME_COUNTER2          0x30a
   3.197 +#define MSR_P4_FLAME_COUNTER3          0x30b
   3.198 +#define MSR_P4_FLAME_CCCR2             0x36a
   3.199 +#define MSR_P4_FLAME_CCCR3             0x36b
   3.200 +
   3.201 +#define MSR_P4_FIRM_ESCR0              0x3a4
   3.202 +#define MSR_P4_FLAME_ESCR0             0x3a6
   3.203 +#define MSR_P4_DAC_ESCR0               0x3a8
   3.204 +#define MSR_P4_SAAT_ESCR0              0x3ae
   3.205 +#define MSR_P4_U2L_ESCR0               0x3b0
   3.206 +
   3.207 +#define P4_FIRM_ESCR0_NUMBER           1
   3.208 +#define P4_FLAME_ESCR0_NUMBER          0
   3.209 +#define P4_DAC_ESCR0_NUMBER            5
   3.210 +#define P4_SAAT_ESCR0_NUMBER           2
   3.211 +#define P4_U2L_ESCR0_NUMBER            3
   3.212 +
   3.213 +#define MSR_P4_FIRM_ESCR1              0x3a5
   3.214 +#define MSR_P4_FLAME_ESCR1             0x3a7
   3.215 +#define MSR_P4_DAC_ESCR1               0x3a9
   3.216 +#define MSR_P4_SAAT_ESCR1              0x3af
   3.217 +#define MSR_P4_U2L_ESCR1               0x3b1
   3.218 +
   3.219 +#define P4_FIRM_ESCR1_NUMBER           1
   3.220 +#define P4_FLAME_ESCR1_NUMBER          0
   3.221 +#define P4_DAC_ESCR1_NUMBER            5
   3.222 +#define P4_SAAT_ESCR1_NUMBER           2
   3.223 +#define P4_U2L_ESCR1_NUMBER            3
   3.224 +
   3.225 +// IQ
   3.226 +#define MSR_P4_IQ_COUNTER0             0x30c
   3.227 +#define MSR_P4_IQ_COUNTER1             0x30d
   3.228 +#define MSR_P4_IQ_CCCR0                0x36c
   3.229 +#define MSR_P4_IQ_CCCR1                0x36d
   3.230 +
   3.231 +#define MSR_P4_IQ_COUNTER2             0x30e
   3.232 +#define MSR_P4_IQ_COUNTER3             0x30f
   3.233 +#define MSR_P4_IQ_CCCR2                0x36e
   3.234 +#define MSR_P4_IQ_CCCR3                0x36f
   3.235 +
   3.236 +#define MSR_P4_IQ_COUNTER4             0x310
   3.237 +#define MSR_P4_IQ_COUNTER5             0x311
   3.238 +#define MSR_P4_IQ_CCCR4                0x370
   3.239 +#define MSR_P4_IQ_CCCR5                0x371
   3.240 +
   3.241 +#define MSR_P4_CRU_ESCR0               0x3b8
   3.242 +#define MSR_P4_CRU_ESCR2               0x3cc
   3.243 +#define MSR_P4_CRU_ESCR4               0x3e0
   3.244 +#define MSR_P4_IQ_ESCR0                0x3ba
   3.245 +#define MSR_P4_RAT_ESCR0               0x3bc
   3.246 +#define MSR_P4_SSU_ESCR0               0x3be
   3.247 +#define MSR_P4_ALF_ESCR0               0x3ca
   3.248 +
   3.249 +#define P4_CRU_ESCR0_NUMBER            4
   3.250 +#define P4_CRU_ESCR2_NUMBER            5
   3.251 +#define P4_CRU_ESCR4_NUMBER            6
   3.252 +#define P4_IQ_ESCR0_NUMBER             0
   3.253 +#define P4_RAT_ESCR0_NUMBER            2
   3.254 +#define P4_SSU_ESCR0_NUMBER            3
   3.255 +#define P4_ALF_ESCR0_NUMBER            1
   3.256 +
   3.257 +#define MSR_P4_CRU_ESCR1               0x3b9
   3.258 +#define MSR_P4_CRU_ESCR3               0x3cd
   3.259 +#define MSR_P4_CRU_ESCR5               0x3e1
   3.260 +#define MSR_P4_IQ_ESCR1                0x3bb
   3.261 +#define MSR_P4_RAT_ESCR1               0x3bd
   3.262 +#define MSR_P4_ALF_ESCR1               0x3cb
   3.263 +
   3.264 +#define P4_CRU_ESCR1_NUMBER            4
   3.265 +#define P4_CRU_ESCR3_NUMBER            5
   3.266 +#define P4_CRU_ESCR5_NUMBER            6
   3.267 +#define P4_IQ_ESCR1_NUMBER             0
   3.268 +#define P4_RAT_ESCR1_NUMBER            2
   3.269 +#define P4_ALF_ESCR1_NUMBER            1
   3.270 +
   3.271 +#define P4_BPU_COUNTER0_NUMBER         0
   3.272 +#define P4_BPU_COUNTER1_NUMBER         1
   3.273 +#define P4_BPU_COUNTER2_NUMBER         2
   3.274 +#define P4_BPU_COUNTER3_NUMBER         3
   3.275 +
   3.276 +#define P4_MS_COUNTER0_NUMBER          4
   3.277 +#define P4_MS_COUNTER1_NUMBER          5
   3.278 +#define P4_MS_COUNTER2_NUMBER          6
   3.279 +#define P4_MS_COUNTER3_NUMBER          7
   3.280 +
   3.281 +#define P4_FLAME_COUNTER0_NUMBER       8
   3.282 +#define P4_FLAME_COUNTER1_NUMBER       9
   3.283 +#define P4_FLAME_COUNTER2_NUMBER       10
   3.284 +#define P4_FLAME_COUNTER3_NUMBER       11
   3.285 +
   3.286 +#define P4_IQ_COUNTER0_NUMBER          12
   3.287 +#define P4_IQ_COUNTER1_NUMBER          13
   3.288 +#define P4_IQ_COUNTER2_NUMBER          14
   3.289 +#define P4_IQ_COUNTER3_NUMBER          15
   3.290 +#define P4_IQ_COUNTER4_NUMBER          16
   3.291 +#define P4_IQ_COUNTER5_NUMBER          17
   3.292 +
   3.293 +/* PEBS
   3.294 + */
   3.295 +#define MSR_P4_PEBS_ENABLE             0x3F1
   3.296 +#define MSR_P4_PEBS_MATRIX_VERT        0x3F2
   3.297 +
   3.298 +#define P4_PEBS_ENABLE_MY_THR          (1 << 25)
   3.299 +#define P4_PEBS_ENABLE_OTH_THR         (1 << 26)
   3.300 +#define P4_PEBS_ENABLE                 (1 << 24)
   3.301 +#define P4_PEBS_BIT0                   (1 << 0)
   3.302 +#define P4_PEBS_BIT1                   (1 << 1)
   3.303 +#define P4_PEBS_BIT2                   (1 << 2)
   3.304 +
   3.305 +#define P4_PEBS_MATRIX_VERT_BIT0       (1 << 0)
   3.306 +#define P4_PEBS_MATRIX_VERT_BIT1       (1 << 1)
   3.307 +#define P4_PEBS_MATRIX_VERT_BIT2       (1 << 2)
   3.308 +
   3.309 +/* Replay tagging.
   3.310 + */
   3.311 +#define P4_REPLAY_TAGGING_PEBS_L1LMR   P4_PEBS_BIT0
   3.312 +#define P4_REPLAY_TAGGING_PEBS_L2LMR   P4_PEBS_BIT1
   3.313 +#define P4_REPLAY_TAGGING_PEBS_DTLMR   P4_PEBS_BIT2
   3.314 +#define P4_REPLAY_TAGGING_PEBS_DTSMR   P4_PEBS_BIT2
   3.315 +#define P4_REPLAY_TAGGING_PEBS_DTAMR   P4_PEBS_BIT2
   3.316 +
   3.317 +#define P4_REPLAY_TAGGING_VERT_L1LMR   P4_PEBS_MATRIX_VERT_BIT0
   3.318 +#define P4_REPLAY_TAGGING_VERT_L2LMR   P4_PEBS_MATRIX_VERT_BIT0
   3.319 +#define P4_REPLAY_TAGGING_VERT_DTLMR   P4_PEBS_MATRIX_VERT_BIT0
   3.320 +#define P4_REPLAY_TAGGING_VERT_DTSMR   P4_PEBS_MATRIX_VERT_BIT1
   3.321 +#define P4_REPLAY_TAGGING_VERT_DTAMR   P4_PEBS_MATRIX_VERT_BIT0 | P4_PEBS_MATRIX_VERT_BIT1
   3.322 +
   3.323 +
   3.324 +
   3.325 +
   3.326 +/*****************************************************************************
   3.327 + *                                                                           *
   3.328 + *****************************************************************************/
   3.329 +
   3.330 +// x87_FP_uop
   3.331 +#define EVENT_SEL_x87_FP_uop                0x04
   3.332 +#define EVENT_MASK_x87_FP_uop_ALL           (1 << 15)
   3.333 +
   3.334 +// execution event (at retirement)
   3.335 +#define EVENT_SEL_execution_event           0x0C
   3.336 +
   3.337 +// scalar_SP_uop
   3.338 +#define EVENT_SEL_scalar_SP_uop             0x0a
   3.339 +#define EVENT_MASK_scalar_SP_uop_ALL        (1 << 15)
   3.340 +
   3.341 +// scalar_DP_uop
   3.342 +#define EVENT_SEL_scalar_DP_uop             0x0e
   3.343 +#define EVENT_MASK_scalar_DP_uop_ALL        (1 << 15)
   3.344 +
   3.345 +// Instruction retired
   3.346 +#define EVENT_SEL_instr_retired             0x02
   3.347 +#define EVENT_MASK_instr_retired_ALL        0x0f
   3.348 +
   3.349 +// uOps retired
   3.350 +#define EVENT_SEL_uops_retired              0x01
   3.351 +#define EVENT_MASK_uops_retired_ALL         0x03
   3.352 +
   3.353 +// L1 misses retired
   3.354 +#define EVENT_SEL_replay_event              0x09
   3.355 +#define EVENT_MASK_replay_event_ALL         0x03
   3.356 +
   3.357 +// Trace cache
   3.358 +#define EVENT_SEL_BPU_fetch_request         0x03
   3.359 +#define EVENT_MASK_BPU_fetch_request_TCMISS 0x01
   3.360 +
   3.361 +// Bus activity
   3.362 +#define EVENT_SEL_FSB_data_activity               0x17
   3.363 +#define EVENT_MASK_FSB_data_activity_DRDY_DRV     0x01
   3.364 +#define EVENT_MASK_FSB_data_activity_DRDY_OWN     0x02
   3.365 +#define EVENT_MASK_FSB_data_activity_DRDY_OOTHER  0x04
   3.366 +#define EVENT_MASK_FSB_data_activity_DBSY_DRV     0x08
   3.367 +#define EVENT_MASK_FSB_data_activity_DBSY_OWN     0x10
   3.368 +#define EVENT_MASK_FSB_data_activity_DBSY_OOTHER  0x20
   3.369 +
   3.370 +// Cache L2
   3.371 +#define EVENT_SEL_BSQ_cache_reference             0x0c
   3.372 +#define EVENT_MASK_BSQ_cache_reference_RD_L2_HITS 0x001
   3.373 +#define EVENT_MASK_BSQ_cache_reference_RD_L2_HITE 0x002
   3.374 +#define EVENT_MASK_BSQ_cache_reference_RD_L2_HITM 0x004
   3.375 +
   3.376 +#define EVENT_MASK_BSQ_cache_reference_RD_L3_HITS 0x008
   3.377 +#define EVENT_MASK_BSQ_cache_reference_RD_L3_HITE 0x010
   3.378 +#define EVENT_MASK_BSQ_cache_reference_RD_L3_HITM 0x020
   3.379 +
   3.380 +#define EVENT_MASK_BSQ_cache_reference_RD_L2_MISS 0x100
   3.381 +#define EVENT_MASK_BSQ_cache_reference_RD_L3_MISS 0x200
   3.382 +#define EVENT_MASK_BSQ_cache_reference_WR_L2_MISS 0x400
   3.383 +
   3.384 +/*****************************************************************************
   3.385 + *                                                                           *
   3.386 + *****************************************************************************/
   3.387 +
   3.388 +
   3.389 +/* The following turn configuration macros into 1/0 to allow code to be
   3.390 + * selected using if(MPENTIUM4_HT) rather then #ifdef (to avoid stale code).
   3.391 + * We rely on the compiler to optimise out unreachable code,
   3.392 + */
   3.393 +#ifdef CONFIG_MPENTIUM4_HT
   3.394 +# define MPENTIUM4_HT 1
   3.395 +#else
   3.396 +# define MPENTIUM4_HT 0
   3.397 +#endif
   3.398 +
   3.399 +#ifdef CONFIG_MPENTIUMIII
   3.400 +# define MPENTIUMIII 1
   3.401 +#else
   3.402 +# define MPENTIUMIII 0
   3.403 +#endif
   3.404 +
   3.405 +#ifdef CONFIG_MPENTIUM4
   3.406 +# define MPENTIUM4 1
   3.407 +#else
   3.408 +# define MPENTIUM4 0
   3.409 +#endif
   3.410 +
   3.411 +/*****************************************************************************
   3.412 + * MSR access macros                                                         *
   3.413 + *****************************************************************************/
   3.414 +
   3.415 +/* rpcc: get full 64-bit Pentium TSC value
   3.416 + */
   3.417 +static __inline__ unsigned long long int rpcc(void) 
   3.418 +{
   3.419 +    unsigned int __h, __l;
   3.420 +    __asm__ __volatile__ ("rdtsc" :"=a" (__l), "=d" (__h));
   3.421 +    return (((unsigned long long)__h) << 32) + __l;
   3.422 +}
   3.423 +
   3.424 +/*****************************************************************************
   3.425 + * Functions.                                                                *
   3.426 + *****************************************************************************/
   3.427 +
   3.428 +#ifdef __KERNEL__
   3.429 +static inline void smt_sched_setup(void)
   3.430 +{
   3.431 +    if (MPENTIUMIII) {
   3.432 +        unsigned int evntsel, x;
   3.433 +        
   3.434 +        /* Make sure counters enabled. */
   3.435 +        rdmsr(MSR_P6_EVNTSEL0, evntsel, x);
   3.436 +        evntsel |= P6_EVNTSEL_EN;
   3.437 +        wrmsr(MSR_P6_EVNTSEL0, evntsel, 0);
   3.438 +        
   3.439 +        evntsel =
   3.440 +            P6_PERF_INST_RETIRED | 
   3.441 +            P6_EVNTSEL_OS        | 
   3.442 +            P6_EVNTSEL_USR       | 
   3.443 +            P6_EVNTSEL_E;
   3.444 +        wrmsr(MSR_P6_EVNTSEL1, evntsel, 0);
   3.445 +    }
   3.446 +
   3.447 +    if(MPENTIUM4) {
   3.448 +        unsigned int x;
   3.449 +        
   3.450 +        /* Program the ESCR */
   3.451 +        x = P4_ESCR_USR                                    |
   3.452 +            P4_ESCR_OS                                     | 
   3.453 +            P4_ESCR_EVNTSEL(P4_ESCR_EVNTSEL_INSTR_RETIRED) | 
   3.454 +            P4_ESCR_EVNTMASK(P4_ESCR_EVNTMASK_IRET_NB_NTAG);
   3.455 +        wrmsr(MSR_P4_CRU_ESCR0, x, 0);
   3.456 +        
   3.457 +        /* Program the CCCR */
   3.458 +        if (MPENTIUM4_HT) {
   3.459 +            x = P4_CCCR_ENABLE                    | 
   3.460 +                P4_CCCR_ESCR(P4_CRU_ESCR0_NUMBER) |
   3.461 +                P4_CCCR_ACTIVE_THREAD(3);
   3.462 +        }
   3.463 +        else {
   3.464 +            x = P4_CCCR_ENABLE                    | 
   3.465 +                P4_CCCR_ESCR(P4_CRU_ESCR0_NUMBER) |
   3.466 +                P4_CCCR_RESERVED;
   3.467 +        }
   3.468 +        wrmsr(MSR_P4_IQ_CCCR0, x, 0);
   3.469 +
   3.470 +        if (MPENTIUM4_HT) {
   3.471 +
   3.472 +            /* Program the second ESCR */
   3.473 +            x = P4_ESCR_T1_USR                                 |
   3.474 +                P4_ESCR_T1_OS                                  | 
   3.475 +                P4_ESCR_EVNTSEL(P4_ESCR_EVNTSEL_INSTR_RETIRED) | 
   3.476 +                P4_ESCR_EVNTMASK(P4_ESCR_EVNTMASK_IRET_NB_NTAG);
   3.477 +            wrmsr(MSR_P4_CRU_ESCR1, x, 0);
   3.478 +            
   3.479 +            /* Program the second CCCR */
   3.480 +            x = P4_CCCR_ENABLE                    |
   3.481 +                P4_CCCR_ESCR(P4_CRU_ESCR1_NUMBER) |
   3.482 +                P4_CCCR_ACTIVE_THREAD(3);
   3.483 +            wrmsr(MSR_P4_IQ_CCCR2, x, 0);
   3.484 +        }
   3.485 +    }
   3.486 +
   3.487 +    if (!MPENTIUMIII && !MPENTIUM4) {
   3.488 +        printk("WARNING: Not setting up IPC performance counters.\n");
   3.489 +    } else {
   3.490 +        printk("Setting up IPC performance counters.\n");
   3.491 +    }
   3.492 +}
   3.493 +
   3.494 +#ifdef CONFIG_MPENTIUMIII
   3.495 +# define MY_MSR_COUNTER MSR_P6_PERFCTR1
   3.496 +#endif
   3.497 +#ifdef CONFIG_MPENTIUM4
   3.498 +# define MY_MSR_COUNTER MSR_P4_IQ_COUNTER0
   3.499 +#endif
   3.500 +#ifndef MY_MSR_COUNTER
   3.501 +# define MY_MSR_COUNTER 0 /* Never used but ensures compilation */
   3.502 +#endif
   3.503 +#define MY_MSR_COUNTER0 MSR_P4_IQ_COUNTER0
   3.504 +#define MY_MSR_COUNTER1 MSR_P4_IQ_COUNTER2
   3.505 +
   3.506 +# define smt_sched_start_sample(task)                                        \
   3.507 +{                                                                            \
   3.508 +    unsigned int l, h;                                                       \
   3.509 +                                                                             \
   3.510 +    if (MPENTIUM4_HT) {                                                      \
   3.511 +        unsigned int msr =                                                   \
   3.512 +            (task->processor & 1)?MY_MSR_COUNTER1:MY_MSR_COUNTER0;           \
   3.513 +        rdmsr(msr, l, h);                                                    \
   3.514 +    }                                                                        \
   3.515 +    else {                                                                   \
   3.516 +        rdmsr(MY_MSR_COUNTER, l, h);                                         \
   3.517 +    }                                                                        \
   3.518 +    task->ipc_sample_start_count_lo = l;                                     \
   3.519 +    task->ipc_sample_start_count_hi = h;                                     \
   3.520 +    rdtsc(l, h);                                                             \
   3.521 +    task->ipc_sample_start_cycle_lo = l;                                     \
   3.522 +    task->ipc_sample_start_cycle_hi = h;                                     \
   3.523 +}
   3.524 +
   3.525 +# define smt_sched_stop_sample(task)                                         \
   3.526 +{                                                                            \
   3.527 +    if (task->ipc_sample_start_cycle_hi != 0)                                \
   3.528 +    {                                                                        \
   3.529 +        unsigned int cl, ch, tl, th;                                         \
   3.530 +        unsigned int c, t;                                                   \
   3.531 +                                                                             \
   3.532 +        if (MPENTIUM4_HT) {                                                  \
   3.533 +            unsigned int msr =                                               \
   3.534 +                (task->processor & 1)?MY_MSR_COUNTER1:MY_MSR_COUNTER0;       \
   3.535 +            rdmsr(msr, cl, ch);                                              \
   3.536 +        }                                                                    \
   3.537 +        else {                                                               \
   3.538 +            rdmsr(MY_MSR_COUNTER, cl, ch);                                   \
   3.539 +        }                                                                    \
   3.540 +                                                                             \
   3.541 +        rdtsc(tl, th);                                                       \
   3.542 +                                                                             \
   3.543 +        c = cl - task->ipc_sample_start_count_lo;                            \
   3.544 +        t = tl - task->ipc_sample_start_cycle_lo;                            \
   3.545 +        task->ipc_average = IPC_AVERAGE(task->ipc_average,                   \
   3.546 +                                        ((double)c)/((double)t));            \
   3.547 +        task->ipc_sample_start_cycle_hi = 0;                                 \
   3.548 +                                                                             \
   3.549 +    }                                                                        \
   3.550 +    else                                                                     \
   3.551 +        task->ipc_average = 0.0;                                             \
   3.552 +                                                                             \
   3.553 +}
   3.554 +
   3.555 +//        task->ipc_sample_latest =                                            
   3.556 +//            (unsigned int)(1000.0*((double)c)/((double)t));                  
   3.557 +#endif /* __KERNEL__ */
   3.558 +
   3.559 +
   3.560 +#endif /* P4PERF_H */
   3.561 +
   3.562 +/* End of $RCSfile$ */
     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/tools/misc/xen_cpuperf.c	Fri Oct 10 19:27:04 2003 +0000
     4.3 @@ -0,0 +1,265 @@
     4.4 +/*
     4.5 + * User mode program to prod MSR values through /proc/perfcntr
     4.6 + *
     4.7 + *
     4.8 + * $Id$
     4.9 + *
    4.10 + * $Log$
    4.11 + */
    4.12 +
    4.13 +#include <sys/types.h>
    4.14 +#include <sched.h>
    4.15 +#include <error.h>
    4.16 +#include <stdio.h>
    4.17 +#include <unistd.h>
    4.18 +#include <stdlib.h>
    4.19 +#include <string.h>
    4.20 +
    4.21 +#include "p4perf.h"
    4.22 +#include "hypervisor-ifs/dom0_ops.h"
    4.23 +#include "dom0_defs.h"
    4.24 +
    4.25 +void dom0_wrmsr( int cpu_mask, int msr, unsigned int low, unsigned int high )
    4.26 +{
    4.27 +  dom0_op_t op;
    4.28 +  op.cmd = DOM0_MSR;
    4.29 +  op.u.msr.write = 1;
    4.30 +  op.u.msr.msr = msr;
    4.31 +  op.u.msr.cpu_mask = cpu_mask;
    4.32 +  op.u.msr.in1 = low;
    4.33 +  op.u.msr.in2 = high;
    4.34 +  do_dom0_op(&op);
    4.35 +}
    4.36 +
    4.37 +unsigned long long dom0_rdmsr( int cpu_mask, int msr )
    4.38 +{
    4.39 +  dom0_op_t op;
    4.40 +  op.cmd = DOM0_MSR;
    4.41 +  op.u.msr.write = 0;
    4.42 +  op.u.msr.msr = msr;
    4.43 +  op.u.msr.cpu_mask = cpu_mask;
    4.44 +  do_dom0_op(&op);
    4.45 +  return (((unsigned long long)op.u.msr.out2)<<32) | op.u.msr.out1 ;
    4.46 +} 
    4.47 +
    4.48 +struct macros {
    4.49 +    char         *name;
    4.50 +    unsigned long msr_addr;
    4.51 +    int           number;
    4.52 +};
    4.53 +
    4.54 +struct macros msr[] = {
    4.55 +    {"BPU_COUNTER0", 0x300, 0},
    4.56 +    {"BPU_COUNTER1", 0x301, 1},
    4.57 +    {"BPU_COUNTER2", 0x302, 2},
    4.58 +    {"BPU_COUNTER3", 0x303, 3},
    4.59 +    {"MS_COUNTER0", 0x304, 4},
    4.60 +    {"MS_COUNTER1", 0x305, 5},
    4.61 +    {"MS_COUNTER2", 0x306, 6},
    4.62 +    {"MS_COUNTER3", 0x307, 7},
    4.63 +    {"FLAME_COUNTER0", 0x308, 8},
    4.64 +    {"FLAME_COUNTER1", 0x309, 9},
    4.65 +    {"FLAME_COUNTER2", 0x30a, 10},
    4.66 +    {"FLAME_COUNTER3", 0x30b, 11},
    4.67 +    {"IQ_COUNTER0", 0x30c, 12},
    4.68 +    {"IQ_COUNTER1", 0x30d, 13},
    4.69 +    {"IQ_COUNTER2", 0x30e, 14},
    4.70 +    {"IQ_COUNTER3", 0x30f, 15},
    4.71 +    {"IQ_COUNTER4", 0x310, 16},
    4.72 +    {"IQ_COUNTER5", 0x311, 17},
    4.73 +    {"BPU_CCCR0", 0x360, 0},
    4.74 +    {"BPU_CCCR1", 0x361, 1},
    4.75 +    {"BPU_CCCR2", 0x362, 2},
    4.76 +    {"BPU_CCCR3", 0x363, 3},
    4.77 +    {"MS_CCCR0", 0x364, 4},
    4.78 +    {"MS_CCCR1", 0x365, 5},
    4.79 +    {"MS_CCCR2", 0x366, 6},
    4.80 +    {"MS_CCCR3", 0x367, 7},
    4.81 +    {"FLAME_CCCR0", 0x368, 8},
    4.82 +    {"FLAME_CCCR1", 0x369, 9},
    4.83 +    {"FLAME_CCCR2", 0x36a, 10},
    4.84 +    {"FLAME_CCCR3", 0x36b, 11},
    4.85 +    {"IQ_CCCR0", 0x36c, 12},
    4.86 +    {"IQ_CCCR1", 0x36d, 13},
    4.87 +    {"IQ_CCCR2", 0x36e, 14},
    4.88 +    {"IQ_CCCR3", 0x36f, 15},
    4.89 +    {"IQ_CCCR4", 0x370, 16},
    4.90 +    {"IQ_CCCR5", 0x371, 17},
    4.91 +    {"BSU_ESCR0", 0x3a0, 7},
    4.92 +    {"BSU_ESCR1", 0x3a1, 7},
    4.93 +    {"FSB_ESCR0", 0x3a2, 6},
    4.94 +    {"FSB_ESCR1", 0x3a3, 6},
    4.95 +    {"MOB_ESCR0", 0x3aa, 2},
    4.96 +    {"MOB_ESCR1", 0x3ab, 2},
    4.97 +    {"PMH_ESCR0", 0x3ac, 4},
    4.98 +    {"PMH_ESCR1", 0x3ad, 4},
    4.99 +    {"BPU_ESCR0", 0x3b2, 0},
   4.100 +    {"BPU_ESCR1", 0x3b3, 0},
   4.101 +    {"IS_ESCR0", 0x3b4, 1},
   4.102 +    {"IS_ESCR1", 0x3b5, 1},
   4.103 +    {"ITLB_ESCR0", 0x3b6, 3},
   4.104 +    {"ITLB_ESCR1", 0x3b7, 3},
   4.105 +    {"IX_ESCR0", 0x3c8, 5},
   4.106 +    {"IX_ESCR1", 0x3c9, 5},
   4.107 +    {"MS_ESCR0", 0x3c0, 0},
   4.108 +    {"MS_ESCR1", 0x3c1, 0},
   4.109 +    {"TBPU_ESCR0", 0x3c2, 2},
   4.110 +    {"TBPU_ESCR1", 0x3c3, 2},
   4.111 +    {"TC_ESCR0", 0x3c4, 1},
   4.112 +    {"TC_ESCR1", 0x3c5, 1},
   4.113 +    {"FIRM_ESCR0", 0x3a4, 1},
   4.114 +    {"FIRM_ESCR1", 0x3a5, 1},
   4.115 +    {"FLAME_ESCR0", 0x3a6, 0},
   4.116 +    {"FLAME_ESCR1", 0x3a7, 0},
   4.117 +    {"DAC_ESCR0", 0x3a8, 5},
   4.118 +    {"DAC_ESCR1", 0x3a9, 5},
   4.119 +    {"SAAT_ESCR0", 0x3ae, 2},
   4.120 +    {"SAAT_ESCR1", 0x3af, 2},
   4.121 +    {"U2L_ESCR0", 0x3b0, 3},
   4.122 +    {"U2L_ESCR1", 0x3b1, 3},
   4.123 +    {"CRU_ESCR0", 0x3b8, 4},
   4.124 +    {"CRU_ESCR1", 0x3b9, 4},
   4.125 +    {"CRU_ESCR2", 0x3cc, 5},
   4.126 +    {"CRU_ESCR3", 0x3cd, 5},
   4.127 +    {"CRU_ESCR4", 0x3e0, 6},
   4.128 +    {"CRU_ESCR5", 0x3e1, 6},
   4.129 +    {"IQ_ESCR0", 0x3ba, 0},
   4.130 +    {"IQ_ESCR1", 0x3bb, 0},
   4.131 +    {"RAT_ESCR0", 0x3bc, 2},
   4.132 +    {"RAT_ESCR1", 0x3bd, 2},
   4.133 +    {"SSU_ESCR0", 0x3be, 3},
   4.134 +    {"SSU_ESCR1", 0x3bf, 3},
   4.135 +    {"ALF_ESCR0", 0x3ca, 1},
   4.136 +    {"ALF_ESCR1", 0x3cb, 1},
   4.137 +    {"PEBS_ENABLE", 0x3f1, 0},
   4.138 +    {"PEBS_MATRIX_VERT", 0x3f2, 0},
   4.139 +    {NULL, 0, 0}
   4.140 +};
   4.141 +
   4.142 +struct macros *lookup_macro(char *str)
   4.143 +{
   4.144 +    struct macros *m;
   4.145 +
   4.146 +    m = msr;
   4.147 +    while (m->name) {
   4.148 +        if (strcmp(m->name, str) == 0)
   4.149 +            return m;
   4.150 +        m++;
   4.151 +    }
   4.152 +    return NULL;
   4.153 +}
   4.154 +
   4.155 +int main(int argc, char **argv)
   4.156 +{
   4.157 +    int c, t = 0xc, es = 0, em = 0, tv = 0, te = 0;
   4.158 +    unsigned int cpu_mask = 1; 
   4.159 +    struct macros *escr = NULL, *cccr = NULL;
   4.160 +    unsigned long escr_val, cccr_val;
   4.161 +    int debug = 0;
   4.162 +    unsigned long pebs = 0, pebs_vert = 0;
   4.163 +    int pebs_x = 0, pebs_vert_x = 0;
   4.164 +    int read = 0;
   4.165 + 
   4.166 +    while ((c = getopt(argc, argv, "dc:t:e:m:T:E:C:P:V:r")) != -1) {
   4.167 +        switch((char)c) {
   4.168 +        case 'P':
   4.169 +            pebs |= 1 << atoi(optarg);
   4.170 +            pebs_x = 1;
   4.171 +            break;
   4.172 +        case 'V':
   4.173 +            pebs_vert |= 1 << atoi(optarg);
   4.174 +            pebs_vert_x = 1;
   4.175 +            break;
   4.176 +        case 'd':
   4.177 +            debug = 1;
   4.178 +            break;
   4.179 +        case 'c':
   4.180 +	    {
   4.181 +            int cpu = atoi(optarg);
   4.182 +            cpu_mask  = (cpu == -1)?(~0):(1<<cpu);
   4.183 +            break;
   4.184 +            }
   4.185 +        case 't': // ESCR thread bits
   4.186 +            t = atoi(optarg);
   4.187 +            break;
   4.188 +        case 'e': // eventsel
   4.189 +            es = atoi(optarg);
   4.190 +            break;
   4.191 +        case 'm': // eventmask
   4.192 +            em = atoi(optarg);
   4.193 +            break;
   4.194 +        case 'T': // tag value
   4.195 +            tv = atoi(optarg);
   4.196 +            te = 1;
   4.197 +            break;
   4.198 +        case 'E':
   4.199 +            escr = lookup_macro(optarg);
   4.200 +            if (!escr) {
   4.201 +                fprintf(stderr, "Macro '%s' not found.\n", optarg);
   4.202 +                exit(1);
   4.203 +            }
   4.204 +            break;
   4.205 +        case 'C':
   4.206 +            cccr = lookup_macro(optarg);
   4.207 +            if (!cccr) {
   4.208 +                fprintf(stderr, "Macro '%s' not found.\n", optarg);
   4.209 +                exit(1);
   4.210 +            }
   4.211 +            break;
   4.212 +	case 'r':
   4.213 +	    read = 1;
   4.214 +	    break;
   4.215 +        }
   4.216 +    }
   4.217 +
   4.218 +    if (read) {
   4.219 +	while((cpu_mask&1)) {
   4.220 +	int i;
   4.221 +	for (i=0x300;i<0x312;i++)
   4.222 +	  {
   4.223 +	    printf("%010llx ",dom0_rdmsr( cpu_mask, i ) );
   4.224 +	  }
   4.225 +        printf("\n");
   4.226 +	cpu_mask>>=1;
   4.227 +	}
   4.228 +	exit(1);
   4.229 +    }
   4.230 +
   4.231 +    if (!escr) {
   4.232 +        fprintf(stderr, "Need an ESCR.\n");
   4.233 +        exit(1);
   4.234 +    }
   4.235 +    if (!cccr) {
   4.236 +        fprintf(stderr, "Need a counter number.\n");
   4.237 +        exit(1);
   4.238 +    }
   4.239 +
   4.240 +    escr_val = P4_ESCR_THREADS(t) | P4_ESCR_EVNTSEL(es) |
   4.241 +        P4_ESCR_EVNTMASK(em) | P4_ESCR_TV(tv) | ((te)?P4_ESCR_TE:0);
   4.242 +    cccr_val = P4_CCCR_ENABLE | P4_CCCR_ESCR(escr->number) |
   4.243 +        P4_CCCR_ACTIVE_THREAD(3)/*reserved*/;
   4.244 +
   4.245 +    if (debug) {
   4.246 +        fprintf(stderr, "ESCR 0x%lx <= 0x%08lx\n", escr->msr_addr, escr_val);
   4.247 +        fprintf(stderr, "CCCR 0x%lx <= 0x%08lx (%u)\n",
   4.248 +                cccr->msr_addr, cccr_val, cccr->number);
   4.249 +        if (pebs_x)
   4.250 +            fprintf(stderr, "PEBS 0x%x <= 0x%08lx\n",
   4.251 +                    MSR_P4_PEBS_ENABLE, pebs);
   4.252 +        if (pebs_vert_x)
   4.253 +            fprintf(stderr, "PMV  0x%x <= 0x%08lx\n",
   4.254 +                    MSR_P4_PEBS_MATRIX_VERT, pebs_vert);
   4.255 +    }
   4.256 +
   4.257 +    dom0_wrmsr( cpu_mask, escr->msr_addr, escr_val, 0 );
   4.258 +    dom0_wrmsr( cpu_mask, cccr->msr_addr, cccr_val, 0 );
   4.259 +
   4.260 +    if (pebs_x)
   4.261 +      dom0_wrmsr( cpu_mask, MSR_P4_PEBS_ENABLE, pebs, 0 );
   4.262 +
   4.263 +    if (pebs_vert_x)
   4.264 +      dom0_wrmsr( cpu_mask, MSR_P4_PEBS_MATRIX_VERT, pebs_vert, 0 );
   4.265 +
   4.266 +    return 0;
   4.267 +}
   4.268 +