direct-io.hg

changeset 8340:b438b8cb38f8

Support VMX guest accesses to IA32_TIME_STAMP_COUNTER MSR.

Signed-off-by: Haifeng Xue <haifeng.xue@intel.com>
author kaf24@firebug.cl.cam.ac.uk
date Tue Dec 13 17:08:05 2005 +0100 (2005-12-13)
parents 494243ba43b8
children 269abc1e4fa5
files xen/arch/x86/vmx.c xen/arch/x86/vmx_io.c xen/include/asm-x86/msr.h xen/include/asm-x86/vmx_vpit.h
line diff
     1.1 --- a/xen/arch/x86/vmx.c	Tue Dec 13 17:02:55 2005 +0100
     1.2 +++ b/xen/arch/x86/vmx.c	Tue Dec 13 17:08:05 2005 +0100
     1.3 @@ -1476,6 +1476,15 @@ static inline void vmx_do_msr_read(struc
     1.4                  (unsigned long)regs->ecx, (unsigned long)regs->eax,
     1.5                  (unsigned long)regs->edx);
     1.6      switch (regs->ecx) {
     1.7 +    case MSR_IA32_TIME_STAMP_COUNTER:
     1.8 +    {
     1.9 +        struct vmx_virpit *vpit;
    1.10 +
    1.11 +        rdtscll(msr_content);
    1.12 +        vpit = &(v->domain->arch.vmx_platform.vmx_pit);
    1.13 +        msr_content += vpit->shift;
    1.14 +        break;
    1.15 +    }
    1.16      case MSR_IA32_SYSENTER_CS:
    1.17          __vmread(GUEST_SYSENTER_CS, (u32 *)&msr_content);
    1.18          break;
    1.19 @@ -1516,6 +1525,23 @@ static inline void vmx_do_msr_write(stru
    1.20      msr_content = (regs->eax & 0xFFFFFFFF) | ((u64)regs->edx << 32);
    1.21  
    1.22      switch (regs->ecx) {
    1.23 +    case MSR_IA32_TIME_STAMP_COUNTER:
    1.24 +    {
    1.25 +        struct vmx_virpit *vpit;
    1.26 +        u64 host_tsc, drift;
    1.27 +
    1.28 +        rdtscll(host_tsc);
    1.29 +        vpit = &(v->domain->arch.vmx_platform.vmx_pit);
    1.30 +        drift = v->arch.arch_vmx.tsc_offset - vpit->shift;
    1.31 +        vpit->shift = msr_content - host_tsc;
    1.32 +        v->arch.arch_vmx.tsc_offset = vpit->shift + drift;
    1.33 +        __vmwrite(TSC_OFFSET, vpit->shift);
    1.34 +
    1.35 +#if defined (__i386__)
    1.36 +        __vmwrite(TSC_OFFSET_HIGH, ((vpit->shift)>>32));
    1.37 +#endif
    1.38 +        break;
    1.39 +    }
    1.40      case MSR_IA32_SYSENTER_CS:
    1.41          __vmwrite(GUEST_SYSENTER_CS, msr_content);
    1.42          break;
     2.1 --- a/xen/arch/x86/vmx_io.c	Tue Dec 13 17:02:55 2005 +0100
     2.2 +++ b/xen/arch/x86/vmx_io.c	Tue Dec 13 17:08:05 2005 +0100
     2.3 @@ -801,11 +801,11 @@ void set_tsc_shift(struct vcpu *v,struct
     2.4          drift = vpit->period_cycles * vpit->pending_intr_nr;
     2.5      else 
     2.6          drift = 0;
     2.7 -    drift = v->arch.arch_vmx.tsc_offset - drift;
     2.8 -    __vmwrite(TSC_OFFSET, drift);
     2.9 +    vpit->shift = v->arch.arch_vmx.tsc_offset - drift;
    2.10 +    __vmwrite(TSC_OFFSET, vpit->shift);
    2.11  
    2.12  #if defined (__i386__)
    2.13 -    __vmwrite(TSC_OFFSET_HIGH, (drift >> 32));
    2.14 +    __vmwrite(TSC_OFFSET_HIGH, ((vpit->shift)>> 32));
    2.15  #endif
    2.16  }
    2.17  
     3.1 --- a/xen/include/asm-x86/msr.h	Tue Dec 13 17:02:55 2005 +0100
     3.2 +++ b/xen/include/asm-x86/msr.h	Tue Dec 13 17:08:05 2005 +0100
     3.3 @@ -88,6 +88,7 @@ static inline void wrmsrl(unsigned int m
     3.4  /* Intel defined MSRs. */
     3.5  #define MSR_IA32_P5_MC_ADDR		0
     3.6  #define MSR_IA32_P5_MC_TYPE		1
     3.7 +#define MSR_IA32_TIME_STAMP_COUNTER	0x10
     3.8  #define MSR_IA32_PLATFORM_ID		0x17
     3.9  #define MSR_IA32_EBL_CR_POWERON		0x2a
    3.10  
     4.1 --- a/xen/include/asm-x86/vmx_vpit.h	Tue Dec 13 17:02:55 2005 +0100
     4.2 +++ b/xen/include/asm-x86/vmx_vpit.h	Tue Dec 13 17:08:05 2005 +0100
     4.3 @@ -21,6 +21,7 @@ struct vmx_virpit {
     4.4      /* for simulation of counter 0 in mode 2*/
     4.5      u64 period_cycles;	                /* pit frequency in cpu cycles */
     4.6      u64 inject_point; /* the time inject virt intr */
     4.7 +    u64 shift;  /* save the value of offset - drift */
     4.8      s_time_t scheduled;                 /* scheduled timer interrupt */
     4.9      struct ac_timer pit_timer;  /* periodic timer for mode 2*/
    4.10      unsigned int channel;  /* the pit channel, counter 0~2 */