direct-io.hg

changeset 15277:912f7e312ec2

hvm svm: Fix for BSOD when "migrating" from Intel to AMD.

The Intel processor driver for Windows (XP and later at least) reads
an MSR that AMD doesn't have. This causes GP-fault in kernel mode,
which causes blue-screen-of-death on Windows. This prevents a
disk-image that was installed on Intel from starting on an AMD
processor.

This patch "fixes" the problem by allowing reads from the msr,
returning all zero's (which is a valid, if not particulary
meaningful, value for this register).

Signed-off-by: Mats Petersson <mats.petersson@amd.com>
author kfraser@localhost.localdomain
date Thu Jun 14 15:54:57 2007 +0100 (2007-06-14)
parents 4d8381679606
children a0c0c7efffca
files xen/arch/x86/hvm/svm/svm.c xen/include/asm-x86/msr.h
line diff
     1.1 --- a/xen/arch/x86/hvm/svm/svm.c	Wed Jun 13 22:24:28 2007 +0100
     1.2 +++ b/xen/arch/x86/hvm/svm/svm.c	Thu Jun 14 15:54:57 2007 +0100
     1.3 @@ -2089,6 +2089,15 @@ static inline void svm_do_msr_access(
     1.4              msr_content = 1ULL << 61; /* MC4_MISC.Locked */
     1.5              break;
     1.6  
     1.7 +        case MSR_IA32_EBC_FREQUENCY_ID:
     1.8 +            /*
     1.9 +             * This Intel-only register may be accessed if this HVM guest
    1.10 +             * has been migrated from an Intel host. The value zero is not
    1.11 +             * particularly meaningful, but at least avoids the guest crashing!
    1.12 +             */
    1.13 +            msr_content = 0;
    1.14 +            break;
    1.15 +
    1.16          default:
    1.17              if ( rdmsr_hypervisor_regs(ecx, &eax, &edx) ||
    1.18                   rdmsr_safe(ecx, eax, edx) == 0 )
     2.1 --- a/xen/include/asm-x86/msr.h	Wed Jun 13 22:24:28 2007 +0100
     2.2 +++ b/xen/include/asm-x86/msr.h	Thu Jun 14 15:54:57 2007 +0100
     2.3 @@ -96,6 +96,7 @@ static inline void wrmsrl(unsigned int m
     2.4  #define MSR_IA32_TIME_STAMP_COUNTER     0x10
     2.5  #define MSR_IA32_PLATFORM_ID		0x17
     2.6  #define MSR_IA32_EBL_CR_POWERON		0x2a
     2.7 +#define MSR_IA32_EBC_FREQUENCY_ID	0x2c
     2.8  
     2.9  #define MSR_IA32_APICBASE		0x1b
    2.10  #define MSR_IA32_APICBASE_BSP		(1<<8)