1.1 --- a/xen/arch/powerpc/powerpc64/Makefile	Thu Sep 14 10:17:23 2006 -0400
     1.2 +++ b/xen/arch/powerpc/powerpc64/Makefile	Thu Sep 14 10:20:16 2006 -0400
     1.3 @@ -6,6 +6,9 @@ obj-y += hypercall_table.o
     1.4  obj-y += io.o
     1.5  obj-y += memcpy.o
     1.6  obj-y += ppc970.o
     1.7 +obj-y += ppc970_machinecheck.o
     1.8 +obj-y += ppc970_scom.o
     1.9  obj-y += prom_call.o
    1.10  obj-y += string.o
    1.11  obj-y += traps.o
    1.12 +

     2.1 --- a/xen/arch/powerpc/powerpc64/ppc970.c	Thu Sep 14 10:17:23 2006 -0400
     2.2 +++ b/xen/arch/powerpc/powerpc64/ppc970.c	Thu Sep 14 10:20:16 2006 -0400
     2.3 @@ -112,19 +112,6 @@ int cpu_io_mfn(ulong mfn)
     2.4      return 0;
     2.5  }
     2.6  
     2.7 -#ifdef DEBUG
     2.8 -static void scom_init(void)
     2.9 -{
    2.10 -    write_scom(SCOM_AMCS_AND_MASK, 0);
    2.11 -    
    2.12 -    printk("scom MCKE: 0x%016lx\n", read_scom(SCOM_CMCE));
    2.13 -    write_scom(SCOM_CMCE, ~0UL);
    2.14 -    printk("scom MCKE: 0x%016lx\n", read_scom(SCOM_CMCE));
    2.15 -}
    2.16 -#else
    2.17 -#define scom_init()
    2.18 -#endif
    2.19 -
    2.20  static u64 cpu0_hids[6];
    2.21  static u64 cpu0_hior;
    2.22  
    2.23 @@ -243,7 +230,7 @@ void cpu_initialize(int cpuid)
    2.24                "to be larger that NR_CPUS(%u)\n",
    2.25                mfpir(), NR_CPUS);
    2.26  
    2.27 -    scom_init();
    2.28 +    cpu_scom_init();
    2.29  
    2.30      /* initialize the SLB */
    2.31  #ifdef DEBUG
    2.32 @@ -287,76 +274,3 @@ void load_cpu_sprs(struct vcpu *v)
    2.33  {
    2.34      mthid4(v->arch.cpu.hid4.word);
    2.35  }
    2.36 -
    2.37 -int cpu_machinecheck(struct cpu_user_regs *regs)
    2.38 -{
    2.39 -    int recover = 0;
    2.40 -    u32 dsisr = mfdsisr();
    2.41 -
    2.42 -    if (regs->msr & MCK_SRR1_RI)
    2.43 -        recover = 1;
    2.44 -
    2.45 -    printk("MACHINE CHECK: %s Recoverable\n", recover ? "IS": "NOT");
    2.46 -    if (mck_cpu_stats[mfpir()] != 0)
    2.47 -        printk("While in CI IO\n");
    2.48 -
    2.49 -    printk("SRR1: 0x%016lx\n", regs->msr);
    2.50 -    if (regs->msr & MCK_SRR1_INSN_FETCH_UNIT)
    2.51 -        printk("42: Exception caused by Instruction Fetch Unit (IFU) "
    2.52 -               "detection of a hardware uncorrectable error (UE).\n");
    2.53 -
    2.54 -    if (regs->msr & MCK_SRR1_LOAD_STORE)
    2.55 -        printk("43: Exception caused by load/store detection of error "
    2.56 -               "(see DSISR)\n");
    2.57 -
    2.58 -    switch (regs->msr & MCK_SRR1_CAUSE_MASK) {
    2.59 -    case MCK_SRR1_CAUSE_SLB_PAR:
    2.60 -        printk("0b01: Exception caused by an SLB parity error detected "
    2.61 -               "while translating an instruction fetch address.\n");
    2.62 -        break;
    2.63 -    case MCK_SRR1_CAUSE_TLB_PAR:
    2.64 -        printk("0b10: Exception caused by a TLB parity error detected "
    2.65 -               "while translating an instruction fetch address.\n");
    2.66 -        break;
    2.67 -    case MCK_SRR1_CAUSE_UE:
    2.68 -        printk("0b11: Exception caused by a hardware uncorrectable "
    2.69 -               "error (UE) detected while doing a reload of an "
    2.70 -               "instruction-fetch TLB tablewalk.\n");
    2.71 -        break;
    2.72 -    default:
    2.73 -        break;
    2.74 -    }
    2.75 -
    2.76 -    printk("\nDSIDR: 0x%08x\n", dsisr);
    2.77 -    if (dsisr & MCK_DSISR_UE)
    2.78 -        printk("16: Exception caused by a UE deferred error "
    2.79 -               "(DAR is undefined).\n");
    2.80 -    
    2.81 -    if (dsisr & MCK_DSISR_UE_TABLE_WALK)
    2.82 -        printk("17: Exception caused by a UE deferred error "
    2.83 -               "during a tablewalk (D-side).\n"); 
    2.84 -
    2.85 -    if (dsisr & MCK_DSISR_L1_DCACHE_PAR)
    2.86 -        printk("18: Exception was caused by a software recoverable "
    2.87 -               "parity error in the L1 D-cache.\n");
    2.88 -
    2.89 -    if (dsisr & MCK_DSISR_L1_DCACHE_TAG_PAR)
    2.90 -        printk("19: Exception was caused by a software recoverable "
    2.91 -               "parity error in the L1 D-cache tag.\n");
    2.92 -
    2.93 -    if (dsisr & MCK_DSISR_D_ERAT_PAR)
    2.94 -        printk("20: Exception was caused by a software recoverable parity "
    2.95 -               "error in the D-ERAT.\n");
    2.96 -        
    2.97 -    if (dsisr & MCK_DSISR_TLB_PAR)
    2.98 -        printk("21: Exception was caused by a software recoverable parity "
    2.99 -               "error in the TLB.\n");
   2.100 -
   2.101 -    if (dsisr & MCK_DSISR_SLB_PAR)
   2.102 -        printk("23: Exception was caused by an SLB parity error (may not be "
   2.103 -               "recoverable). This condition could occur if the "
   2.104 -               "effective segment ID (ESID) fields of two or more SLB "
   2.105 -               "entries contain the same value.");
   2.106 -
   2.107 -    return 0; /* for now lets not recover; */
   2.108 -}

     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/xen/arch/powerpc/powerpc64/ppc970_machinecheck.c	Thu Sep 14 10:20:16 2006 -0400
     3.3 @@ -0,0 +1,116 @@
     3.4 +/*
     3.5 + * This program is free software; you can redistribute it and/or modify
     3.6 + * it under the terms of the GNU General Public License as published by
     3.7 + * the Free Software Foundation; either version 2 of the License, or
     3.8 + * (at your option) any later version.
     3.9 + *
    3.10 + * This program is distributed in the hope that it will be useful,
    3.11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
    3.12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    3.13 + * GNU General Public License for more details.
    3.14 + *
    3.15 + * You should have received a copy of the GNU General Public License
    3.16 + * along with this program; if not, write to the Free Software
    3.17 + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
    3.18 + *
    3.19 + * Copyright (C) IBM Corp. 2006
    3.20 + *
    3.21 + * Authors: Jimi Xenidis <jimix@watson.ibm.com>
    3.22 + */
    3.23 +
    3.24 +#include <xen/config.h>
    3.25 +#include <xen/types.h>
    3.26 +#include <xen/lib.h>
    3.27 +#include <public/xen.h>
    3.28 +#include <asm/processor.h>
    3.29 +#include <asm/percpu.h>
    3.30 +
    3.31 +#define MCK_SRR1_INSN_FETCH_UNIT    0x0000000000200000 /* 42 */
    3.32 +#define MCK_SRR1_LOAD_STORE         0x0000000000100000 /* 43 */
    3.33 +#define MCK_SRR1_CAUSE_MASK         0x00000000000c0000 /* 44:45 */
    3.34 +#define MCK_SRR1_CAUSE_NONE         0x0000000000000000 /* 0b00 */
    3.35 +#define MCK_SRR1_CAUSE_SLB_PAR      0x0000000000040000 /* 0b01 */
    3.36 +#define MCK_SRR1_CAUSE_TLB_PAR      0x0000000000080000 /* 0b10 */
    3.37 +#define MCK_SRR1_CAUSE_UE           0x00000000000c0000 /* 0b11 */
    3.38 +#define MCK_SRR1_RI                 MSR_RI
    3.39 +
    3.40 +#define MCK_DSISR_UE                0x00008000 /* 16 */
    3.41 +#define MCK_DSISR_UE_TABLE_WALK     0x00004000 /* 17 */
    3.42 +#define MCK_DSISR_L1_DCACHE_PAR     0x00002000 /* 18 */
    3.43 +#define MCK_DSISR_L1_DCACHE_TAG_PAR 0x00001000 /* 19 */
    3.44 +#define MCK_DSISR_D_ERAT_PAR        0x00000800 /* 20 */
    3.45 +#define MCK_DSISR_TLB_PAR           0x00000400 /* 21 */
    3.46 +#define MCK_DSISR_SLB_PAR           0x00000100 /* 23 */
    3.47 +
    3.48 +int cpu_machinecheck(struct cpu_user_regs *regs)
    3.49 +{
    3.50 +    int recover = 0;
    3.51 +    u32 dsisr = mfdsisr();
    3.52 +
    3.53 +    if (regs->msr & MCK_SRR1_RI)
    3.54 +        recover = 1;
    3.55 +
    3.56 +    printk("MACHINE CHECK: %s Recoverable\n", recover ? "IS": "NOT");
    3.57 +    if (mck_cpu_stats[mfpir()] != 0)
    3.58 +        printk("While in CI IO\n");
    3.59 +
    3.60 +    printk("SRR1: 0x%016lx\n", regs->msr);
    3.61 +    if (regs->msr & MCK_SRR1_INSN_FETCH_UNIT)
    3.62 +        printk("42: Exception caused by Instruction Fetch Unit (IFU) "
    3.63 +               "detection of a hardware uncorrectable error (UE).\n");
    3.64 +
    3.65 +    if (regs->msr & MCK_SRR1_LOAD_STORE)
    3.66 +        printk("43: Exception caused by load/store detection of error "
    3.67 +               "(see DSISR)\n");
    3.68 +
    3.69 +    switch (regs->msr & MCK_SRR1_CAUSE_MASK) {
    3.70 +    case MCK_SRR1_CAUSE_SLB_PAR:
    3.71 +        printk("0b01: Exception caused by an SLB parity error detected "
    3.72 +               "while translating an instruction fetch address.\n");
    3.73 +        break;
    3.74 +    case MCK_SRR1_CAUSE_TLB_PAR:
    3.75 +        printk("0b10: Exception caused by a TLB parity error detected "
    3.76 +               "while translating an instruction fetch address.\n");
    3.77 +        break;
    3.78 +    case MCK_SRR1_CAUSE_UE:
    3.79 +        printk("0b11: Exception caused by a hardware uncorrectable "
    3.80 +               "error (UE) detected while doing a reload of an "
    3.81 +               "instruction-fetch TLB tablewalk.\n");
    3.82 +        break;
    3.83 +    default:
    3.84 +        break;
    3.85 +    }
    3.86 +
    3.87 +    printk("\nDSIDR: 0x%08x\n", dsisr);
    3.88 +    if (dsisr & MCK_DSISR_UE)
    3.89 +        printk("16: Exception caused by a UE deferred error "
    3.90 +               "(DAR is undefined).\n");
    3.91 +    
    3.92 +    if (dsisr & MCK_DSISR_UE_TABLE_WALK)
    3.93 +        printk("17: Exception caused by a UE deferred error "
    3.94 +               "during a tablewalk (D-side).\n"); 
    3.95 +
    3.96 +    if (dsisr & MCK_DSISR_L1_DCACHE_PAR)
    3.97 +        printk("18: Exception was caused by a software recoverable "
    3.98 +               "parity error in the L1 D-cache.\n");
    3.99 +
   3.100 +    if (dsisr & MCK_DSISR_L1_DCACHE_TAG_PAR)
   3.101 +        printk("19: Exception was caused by a software recoverable "
   3.102 +               "parity error in the L1 D-cache tag.\n");
   3.103 +
   3.104 +    if (dsisr & MCK_DSISR_D_ERAT_PAR)
   3.105 +        printk("20: Exception was caused by a software recoverable parity "
   3.106 +               "error in the D-ERAT.\n");
   3.107 +        
   3.108 +    if (dsisr & MCK_DSISR_TLB_PAR)
   3.109 +        printk("21: Exception was caused by a software recoverable parity "
   3.110 +               "error in the TLB.\n");
   3.111 +
   3.112 +    if (dsisr & MCK_DSISR_SLB_PAR)
   3.113 +        printk("23: Exception was caused by an SLB parity error (may not be "
   3.114 +               "recoverable). This condition could occur if the "
   3.115 +               "effective segment ID (ESID) fields of two or more SLB "
   3.116 +               "entries contain the same value.");
   3.117 +
   3.118 +    return 0; /* for now lets not recover; */
   3.119 +}

     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/xen/arch/powerpc/powerpc64/ppc970_scom.c	Thu Sep 14 10:20:16 2006 -0400
     4.3 @@ -0,0 +1,116 @@
     4.4 +/*
     4.5 + * This program is free software; you can redistribute it and/or modify
     4.6 + * it under the terms of the GNU General Public License as published by
     4.7 + * the Free Software Foundation; either version 2 of the License, or
     4.8 + * (at your option) any later version.
     4.9 + *
    4.10 + * This program is distributed in the hope that it will be useful,
    4.11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
    4.12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    4.13 + * GNU General Public License for more details.
    4.14 + *
    4.15 + * You should have received a copy of the GNU General Public License
    4.16 + * along with this program; if not, write to the Free Software
    4.17 + * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
    4.18 + *
    4.19 + * Copyright (C) IBM Corp. 2006
    4.20 + *
    4.21 + * Authors: Jimi Xenidis <jimix@watson.ibm.com>
    4.22 + */
    4.23 +
    4.24 +#include <xen/config.h>
    4.25 +#include <xen/types.h>
    4.26 +#include <xen/lib.h>
    4.27 +
    4.28 +#define SPRN_SCOMC 276
    4.29 +#define SPRN_SCOMD 277
    4.30 +
    4.31 +static inline void mtscomc(ulong scomc)
    4.32 +{
    4.33 +    __asm__ __volatile__ ("mtspr %1, %0" : : "r" (scomc), "i"(SPRN_SCOMC));
    4.34 +}
    4.35 +
    4.36 +static inline ulong mfscomc(void)
    4.37 +{
    4.38 +    ulong scomc;
    4.39 +    __asm__ __volatile__ ("mfspr %0, %1" : "=r" (scomc): "i"(SPRN_SCOMC));
    4.40 +    return scomc;
    4.41 +}
    4.42 +
    4.43 +static inline void mtscomd(ulong scomd)
    4.44 +{
    4.45 +    __asm__ __volatile__ ("mtspr %1, %0" : : "r" (scomd), "i"(SPRN_SCOMD));
    4.46 +}
    4.47 +
    4.48 +static inline ulong mfscomd(void)
    4.49 +{
    4.50 +    ulong scomd;
    4.51 +    __asm__ __volatile__ ("mfspr %0, %1" : "=r" (scomd): "i"(SPRN_SCOMD));
    4.52 +    return scomd;
    4.53 +}
    4.54 +
    4.55 +union scomc {
    4.56 +    struct scomc_bits {
    4.57 +        ulong _reserved_0_31: 32;
    4.58 +        ulong addr:           16;
    4.59 +        ulong RW:              1;
    4.60 +        ulong _reserved_49_55: 7;
    4.61 +        ulong _reserved_56_57: 2;
    4.62 +        ulong addr_error:      1;
    4.63 +        ulong iface_error:     1;
    4.64 +        ulong disabled:        1;
    4.65 +        ulong _reserved_61_62: 2;
    4.66 +        ulong failure:         1;
    4.67 +    } bits;
    4.68 +    ulong word;
    4.69 +};
    4.70 +
    4.71 +
    4.72 +static inline ulong read_scom(ulong addr)
    4.73 +{
    4.74 +    union scomc c;
    4.75 +    ulong d;
    4.76 +
    4.77 +    c.word = 0;
    4.78 +    c.bits.addr = addr;
    4.79 +    c.bits.RW = 0;
    4.80 +
    4.81 +    mtscomc(c.word);
    4.82 +    d = mfscomd();
    4.83 +    c.word = mfscomc();
    4.84 +    if (c.bits.failure)
    4.85 +        panic("scom status: 0x%016lx\n", c.word);
    4.86 +
    4.87 +    return d;
    4.88 +}
    4.89 +
    4.90 +static inline void write_scom(ulong addr, ulong val)
    4.91 +{
    4.92 +    union scomc c;
    4.93 +
    4.94 +    c.word = 0;
    4.95 +    c.bits.addr = addr;
    4.96 +    c.bits.RW = 0;
    4.97 +
    4.98 +    mtscomd(val);
    4.99 +    mtscomc(c.word);
   4.100 +    c.word = mfscomc();
   4.101 +    if (c.bits.failure)
   4.102 +        panic("scom status: 0x%016lx\n", c.word);
   4.103 +}
   4.104 +
   4.105 +#define SCOM_AMCS_REG      0x022601
   4.106 +#define SCOM_AMCS_AND_MASK 0x022700
   4.107 +#define SCOM_AMCS_OR_MASK  0x022800
   4.108 +#define SCOM_CMCE          0x030901
   4.109 +
   4.110 +void cpu_scom_init(void)
   4.111 +{
   4.112 +#ifdef not_yet    
   4.113 +    write_scom(SCOM_AMCS_AND_MASK, 0);
   4.114 +    
   4.115 +    printk("scom MCKE: 0x%016lx\n", read_scom(SCOM_CMCE));
   4.116 +    write_scom(SCOM_CMCE, ~0UL);
   4.117 +    printk("scom MCKE: 0x%016lx\n", read_scom(SCOM_CMCE));
   4.118 +#endif
   4.119 +}

     5.1 --- a/xen/include/asm-powerpc/powerpc64/ppc970-hid.h	Thu Sep 14 10:17:23 2006 -0400
     5.2 +++ b/xen/include/asm-powerpc/powerpc64/ppc970-hid.h	Thu Sep 14 10:20:16 2006 -0400
     5.3 @@ -141,102 +141,4 @@ union hid5 {
     5.4      ulong word;
     5.5  };
     5.6  
     5.7 -#define MCK_SRR1_INSN_FETCH_UNIT    0x0000000000200000 /* 42 */
     5.8 -#define MCK_SRR1_LOAD_STORE         0x0000000000100000 /* 43 */
     5.9 -#define MCK_SRR1_CAUSE_MASK         0x00000000000c0000 /* 44:45 */
    5.10 -#define MCK_SRR1_CAUSE_NONE         0x0000000000000000 /* 0b00 */
    5.11 -#define MCK_SRR1_CAUSE_SLB_PAR      0x0000000000040000 /* 0b01 */
    5.12 -#define MCK_SRR1_CAUSE_TLB_PAR      0x0000000000080000 /* 0b10 */
    5.13 -#define MCK_SRR1_CAUSE_UE           0x00000000000c0000 /* 0b11 */
    5.14 -#define MCK_SRR1_RI                 MSR_RI
    5.15 -
    5.16 -#define MCK_DSISR_UE                0x00008000 /* 16 */
    5.17 -#define MCK_DSISR_UE_TABLE_WALK     0x00004000 /* 17 */
    5.18 -#define MCK_DSISR_L1_DCACHE_PAR     0x00002000 /* 18 */
    5.19 -#define MCK_DSISR_L1_DCACHE_TAG_PAR 0x00001000 /* 19 */
    5.20 -#define MCK_DSISR_D_ERAT_PAR        0x00000800 /* 20 */
    5.21 -#define MCK_DSISR_TLB_PAR           0x00000400 /* 21 */
    5.22 -#define MCK_DSISR_SLB_PAR           0x00000100 /* 23 */
    5.23 -
    5.24 -#define SPRN_SCOMC 276
    5.25 -#define SPRN_SCOMD 277
    5.26 -
    5.27 -static inline void mtscomc(ulong scomc)
    5.28 -{
    5.29 -    __asm__ __volatile__ ("mtspr %1, %0" : : "r" (scomc), "i"(SPRN_SCOMC));
    5.30 -}
    5.31 -
    5.32 -static inline ulong mfscomc(void)
    5.33 -{
    5.34 -    ulong scomc;
    5.35 -    __asm__ __volatile__ ("mfspr %0, %1" : "=r" (scomc): "i"(SPRN_SCOMC));
    5.36 -    return scomc;
    5.37 -}
    5.38 -
    5.39 -static inline void mtscomd(ulong scomd)
    5.40 -{
    5.41 -    __asm__ __volatile__ ("mtspr %1, %0" : : "r" (scomd), "i"(SPRN_SCOMD));
    5.42 -}
    5.43 -
    5.44 -static inline ulong mfscomd(void)
    5.45 -{
    5.46 -    ulong scomd;
    5.47 -    __asm__ __volatile__ ("mfspr %0, %1" : "=r" (scomd): "i"(SPRN_SCOMD));
    5.48 -    return scomd;
    5.49 -}
    5.50 -
    5.51 -union scomc {
    5.52 -    struct scomc_bits {
    5.53 -        ulong _reserved_0_31: 32;
    5.54 -        ulong addr:           16;
    5.55 -        ulong RW:              1;
    5.56 -        ulong _reserved_49_55: 7;
    5.57 -        ulong _reserved_56_57: 2;
    5.58 -        ulong addr_error:      1;
    5.59 -        ulong iface_error:     1;
    5.60 -        ulong disabled:        1;
    5.61 -        ulong _reserved_61_62: 2;
    5.62 -        ulong failure:         1;
    5.63 -    } bits;
    5.64 -    ulong word;
    5.65 -};
    5.66 -
    5.67 -
    5.68 -static inline ulong read_scom(ulong addr)
    5.69 -{
    5.70 -    union scomc c;
    5.71 -    ulong d;
    5.72 -
    5.73 -    c.word = 0;
    5.74 -    c.bits.addr = addr;
    5.75 -    c.bits.RW = 0;
    5.76 -
    5.77 -    mtscomc(c.word);
    5.78 -    d = mfscomd();
    5.79 -    c.word = mfscomc();
    5.80 -    if (c.bits.failure)
    5.81 -        panic("scom status: 0x%016lx\n", c.word);
    5.82 -
    5.83 -    return d;
    5.84 -}
    5.85 -
    5.86 -static inline void write_scom(ulong addr, ulong val)
    5.87 -{
    5.88 -    union scomc c;
    5.89 -
    5.90 -    c.word = 0;
    5.91 -    c.bits.addr = addr;
    5.92 -    c.bits.RW = 0;
    5.93 -
    5.94 -    mtscomd(val);
    5.95 -    mtscomc(c.word);
    5.96 -    c.word = mfscomc();
    5.97 -    if (c.bits.failure)
    5.98 -        panic("scom status: 0x%016lx\n", c.word);
    5.99 -}
   5.100 -
   5.101 -#define SCOM_AMCS_REG      0x022601
   5.102 -#define SCOM_AMCS_AND_MASK 0x022700
   5.103 -#define SCOM_AMCS_OR_MASK  0x022800
   5.104 -#define SCOM_CMCE          0x030901
   5.105  #endif

     6.1 --- a/xen/include/asm-powerpc/processor.h	Thu Sep 14 10:17:23 2006 -0400
     6.2 +++ b/xen/include/asm-powerpc/processor.h	Thu Sep 14 10:20:16 2006 -0400
     6.3 @@ -38,6 +38,7 @@ struct domain;
     6.4  struct vcpu;
     6.5  struct cpu_user_regs;
     6.6  extern int cpu_machinecheck(struct cpu_user_regs *);
     6.7 +extern int cpu_scom_init(void);
     6.8  extern void show_registers(struct cpu_user_regs *);
     6.9  extern void show_execution_state(struct cpu_user_regs *);
    6.10  extern void show_backtrace(ulong sp, ulong lr, ulong pc);