direct-io.hg

changeset 8016:8952af4fc166

Shootdown TLB entries across all VCPUs for SMP shadow mode.

Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Thu Nov 24 16:47:44 2005 +0100 (2005-11-24)
parents 8392d3955ed4
children 64d919032001
files xen/arch/x86/shadow.c xen/arch/x86/shadow32.c xen/include/asm-x86/shadow.h
line diff
     1.1 --- a/xen/arch/x86/shadow.c	Thu Nov 24 16:32:38 2005 +0100
     1.2 +++ b/xen/arch/x86/shadow.c	Thu Nov 24 16:47:44 2005 +0100
     1.3 @@ -1757,6 +1757,7 @@ static void sync_all(struct domain *d)
     1.4      struct out_of_sync_entry *entry;
     1.5      int need_flush = 0;
     1.6      l1_pgentry_t *ppte, opte, npte;
     1.7 +    cpumask_t other_vcpus_mask;
     1.8  
     1.9      perfc_incrc(shadow_sync_all);
    1.10  
    1.11 @@ -1789,23 +1790,15 @@ static void sync_all(struct domain *d)
    1.12          unmap_domain_page(ppte);
    1.13      }
    1.14  
    1.15 -    // XXX mafetter: SMP
    1.16 -    //
    1.17 -    // With the current algorithm, we've gotta flush all the TLBs
    1.18 -    // before we can safely continue.  I don't think we want to
    1.19 -    // do it this way, so I think we should consider making
    1.20 -    // entirely private copies of the shadow for each vcpu, and/or
    1.21 -    // possibly having a mix of private and shared shadow state
    1.22 -    // (any path from a PTE that grants write access to an out-of-sync
    1.23 -    // page table page needs to be vcpu private).
    1.24 -    //
    1.25 -#if 0 // this should be enabled for SMP guests...
    1.26 -    flush_tlb_mask(cpu_online_map);
    1.27 -#endif
    1.28 +    /* Other VCPUs mustn't use the revoked writable mappings. */
    1.29 +    other_vcpus_mask = d->cpumask;
    1.30 +    cpu_clear(smp_processor_id(), other_vcpus_mask);
    1.31 +    flush_tlb_mask(other_vcpus_mask);
    1.32 +
    1.33 +    /* Flush ourself later. */
    1.34      need_flush = 1;
    1.35  
    1.36 -    // Second, resync all L1 pages, then L2 pages, etc...
    1.37 -    //
    1.38 +    /* Second, resync all L1 pages, then L2 pages, etc... */
    1.39      need_flush |= resync_all(d, PGT_l1_shadow);
    1.40  
    1.41  #if CONFIG_PAGING_LEVELS == 2
     2.1 --- a/xen/arch/x86/shadow32.c	Thu Nov 24 16:32:38 2005 +0100
     2.2 +++ b/xen/arch/x86/shadow32.c	Thu Nov 24 16:47:44 2005 +0100
     2.3 @@ -2554,6 +2554,7 @@ void __shadow_sync_all(struct domain *d)
     2.4      struct out_of_sync_entry *entry;
     2.5      int need_flush = 0;
     2.6      l1_pgentry_t *ppte, opte, npte;
     2.7 +    cpumask_t other_vcpus_mask;
     2.8  
     2.9      perfc_incrc(shadow_sync_all);
    2.10  
    2.11 @@ -2586,23 +2587,15 @@ void __shadow_sync_all(struct domain *d)
    2.12          unmap_domain_page(ppte);
    2.13      }
    2.14  
    2.15 -    // XXX mafetter: SMP
    2.16 -    //
    2.17 -    // With the current algorithm, we've gotta flush all the TLBs
    2.18 -    // before we can safely continue.  I don't think we want to
    2.19 -    // do it this way, so I think we should consider making
    2.20 -    // entirely private copies of the shadow for each vcpu, and/or
    2.21 -    // possibly having a mix of private and shared shadow state
    2.22 -    // (any path from a PTE that grants write access to an out-of-sync
    2.23 -    // page table page needs to be vcpu private).
    2.24 -    //
    2.25 -#if 0 // this should be enabled for SMP guests...
    2.26 -    flush_tlb_mask(cpu_online_map);
    2.27 -#endif
    2.28 +    /* Other VCPUs mustn't use the revoked writable mappings. */
    2.29 +    other_vcpus_mask = d->cpumask;
    2.30 +    cpu_clear(smp_processor_id(), other_vcpus_mask);
    2.31 +    flush_tlb_mask(other_vcpus_mask);
    2.32 +
    2.33 +    /* Flush ourself later. */
    2.34      need_flush = 1;
    2.35  
    2.36 -    // Second, resync all L1 pages, then L2 pages, etc...
    2.37 -    //
    2.38 +    /* Second, resync all L1 pages, then L2 pages, etc... */
    2.39      need_flush |= resync_all(d, PGT_l1_shadow);
    2.40      if ( shadow_mode_translate(d) )
    2.41          need_flush |= resync_all(d, PGT_hl2_shadow);
     3.1 --- a/xen/include/asm-x86/shadow.h	Thu Nov 24 16:32:38 2005 +0100
     3.2 +++ b/xen/include/asm-x86/shadow.h	Thu Nov 24 16:47:44 2005 +0100
     3.3 @@ -596,8 +596,8 @@ update_hl2e(struct vcpu *v, unsigned lon
     3.4          if ( need_flush )
     3.5          {
     3.6              perfc_incrc(update_hl2e_invlpg);
     3.7 -            // SMP BUG???
     3.8 -            local_flush_tlb_one(&linear_pg_table[l1_linear_offset(va)]);
     3.9 +            flush_tlb_one_mask(v->domain->cpumask,
    3.10 +                               &linear_pg_table[l1_linear_offset(va)]);
    3.11          }
    3.12      }
    3.13  }