direct-io.hg

changeset 11531:7c6aaa106f15

[HVM][SVM] This patch cleans up the SVM CPUID logic a bit, adds proper clearing
of MCA/MCE bits, and also ties clearing the PAE bit with the NX bit. We
have seen issues with Solaris if the NX bit is set but the PAE bit is
not.

Signed-off-by: Tom Woller <thomas.woller@amd.com>=20
author kfraser@localhost.localdomain
date Tue Sep 19 11:03:12 2006 +0100 (2006-09-19)
parents 7877e25e2b23
children 33955ca54ec1
files xen/arch/x86/hvm/svm/svm.c
line diff
     1.1 --- a/xen/arch/x86/hvm/svm/svm.c	Tue Sep 19 11:01:05 2006 +0100
     1.2 +++ b/xen/arch/x86/hvm/svm/svm.c	Tue Sep 19 11:03:12 2006 +0100
     1.3 @@ -1041,95 +1041,76 @@ static void svm_vmexit_do_cpuid(struct v
     1.4                  (unsigned long)regs->ecx, (unsigned long)regs->edx,
     1.5                  (unsigned long)regs->esi, (unsigned long)regs->edi);
     1.6  
     1.7 -    cpuid(input, &eax, &ebx, &ecx, &edx);
     1.8 -
     1.9 -    if (input == 0x00000001)
    1.10 -    {
    1.11 -        if ( !hvm_apic_support(v->domain) ||
    1.12 -             !vlapic_global_enabled((VLAPIC(v))) )
    1.13 -        {
    1.14 -            /* Since the apic is disabled, avoid any confusion 
    1.15 -               about SMP cpus being available */
    1.16 -            clear_bit(X86_FEATURE_APIC, &edx);
    1.17 -        }
    1.18 -
    1.19 -#if CONFIG_PAGING_LEVELS >= 3
    1.20 -        if ( !v->domain->arch.hvm_domain.params[HVM_PARAM_PAE_ENABLED] )
    1.21 -#endif
    1.22 -            clear_bit(X86_FEATURE_PAE, &edx);
    1.23 -        clear_bit(X86_FEATURE_PSE36, &edx);
    1.24 -
    1.25 -        /* Clear out reserved bits. */
    1.26 -        ecx &= ~SVM_VCPU_CPUID_L1_ECX_RESERVED;
    1.27 -        edx &= ~SVM_VCPU_CPUID_L1_EDX_RESERVED;
    1.28 -
    1.29 -        clear_bit(X86_FEATURE_MWAIT & 31, &ecx);
    1.30 -
    1.31 -        /* Guest should only see one logical processor.
    1.32 -         * See details on page 23 of AMD CPUID Specification. 
    1.33 -         */
    1.34 -        clear_bit(X86_FEATURE_HT, &edx);  /* clear the hyperthread bit */
    1.35 -        ebx &= 0xFF00FFFF;  /* clear the logical processor count when HTT=0 */
    1.36 -        ebx |= 0x00010000;  /* set to 1 just for precaution */
    1.37 -
    1.38 -        /* Disable machine check architecture */
    1.39 -        clear_bit(X86_FEATURE_MCA, &edx);
    1.40 -        clear_bit(X86_FEATURE_MCE, &edx);
    1.41 -    }
    1.42 -    else if ( (input > 0x00000005) && (input < 0x80000000) )
    1.43 -    {
    1.44 -        if ( !cpuid_hypervisor_leaves(input, &eax, &ebx, &ecx, &edx) )
    1.45 -            eax = ebx = ecx = edx = 0;
    1.46 -    }
    1.47 -    else if ( input == 0x80000001 )
    1.48 +    if ( !cpuid_hypervisor_leaves(input, &eax, &ebx, &ecx, &edx) )
    1.49      {
    1.50 -        /* We duplicate some CPUID_00000001 code because many bits of 
    1.51 -           CPUID_80000001_EDX overlaps with CPUID_00000001_EDX. */
    1.52 -
    1.53 -        if ( !hvm_apic_support(v->domain) ||
    1.54 -             !vlapic_global_enabled((VLAPIC(v))) )
    1.55 +        cpuid(input, &eax, &ebx, &ecx, &edx);       
    1.56 +        if (input == 0x00000001 || input == 0x80000001 )
    1.57          {
    1.58 -            /* Since the apic is disabled, avoid any confusion 
    1.59 -               about SMP cpus being available */
    1.60 -            clear_bit(X86_FEATURE_APIC, &edx);
    1.61 -        }
    1.62 -
    1.63 -        /* Clear the Cmp_Legacy bit 
    1.64 -         * This bit is supposed to be zero when HTT = 0.
    1.65 -         * See details on page 23 of AMD CPUID Specification. 
    1.66 -         */
    1.67 -        clear_bit(X86_FEATURE_CMP_LEGACY & 31, &ecx);
    1.68 -
    1.69 -#ifdef __i386__
    1.70 -        /* Mask feature for Intel ia32e or AMD long mode. */
    1.71 -        clear_bit(X86_FEATURE_LAHF_LM & 31, &ecx);
    1.72 -
    1.73 -        clear_bit(X86_FEATURE_LM & 31, &edx);
    1.74 -        clear_bit(X86_FEATURE_SYSCALL & 31, &edx);
    1.75 +            if ( !hvm_apic_support(v->domain) ||
    1.76 +                 !vlapic_global_enabled((VLAPIC(v))) )
    1.77 +            {
    1.78 +                /* Since the apic is disabled, avoid any confusion 
    1.79 +                   about SMP cpus being available */
    1.80 +                clear_bit(X86_FEATURE_APIC, &edx);
    1.81 +            }
    1.82 +#if CONFIG_PAGING_LEVELS >= 3
    1.83 +            if ( !v->domain->arch.hvm_domain.params[HVM_PARAM_PAE_ENABLED] )
    1.84  #endif
    1.85 -
    1.86 -
    1.87 -#if CONFIG_PAGING_LEVELS >= 3
    1.88 -        if ( !v->domain->arch.hvm_domain.params[HVM_PARAM_PAE_ENABLED] )
    1.89 +            {
    1.90 +                clear_bit(X86_FEATURE_PAE, &edx);
    1.91 +                if (input == 0x80000001 )
    1.92 +                   clear_bit(X86_FEATURE_NX & 31, &edx);
    1.93 +            }
    1.94 +            clear_bit(X86_FEATURE_PSE36, &edx);
    1.95 +            /* Disable machine check architecture */
    1.96 +            clear_bit(X86_FEATURE_MCA, &edx);
    1.97 +            clear_bit(X86_FEATURE_MCE, &edx);
    1.98 +            if (input == 0x00000001 )
    1.99 +            {
   1.100 +                /* Clear out reserved bits. */
   1.101 +                ecx &= ~SVM_VCPU_CPUID_L1_ECX_RESERVED;
   1.102 +                edx &= ~SVM_VCPU_CPUID_L1_EDX_RESERVED;
   1.103 +
   1.104 +                clear_bit(X86_FEATURE_MWAIT & 31, &ecx);
   1.105 +
   1.106 +                /* Guest should only see one logical processor.
   1.107 +                 * See details on page 23 of AMD CPUID Specification. 
   1.108 +                 */
   1.109 +                clear_bit(X86_FEATURE_HT, &edx);  /* clear the hyperthread bit */
   1.110 +                ebx &= 0xFF00FFFF;  /* clear the logical processor count when HTT=0 */
   1.111 +                ebx |= 0x00010000;  /* set to 1 just for precaution */
   1.112 +            }
   1.113 +            else
   1.114 +            {
   1.115 +                /* Clear the Cmp_Legacy bit 
   1.116 +                 * This bit is supposed to be zero when HTT = 0.
   1.117 +                 * See details on page 23 of AMD CPUID Specification. 
   1.118 +                 */
   1.119 +                clear_bit(X86_FEATURE_CMP_LEGACY & 31, &ecx);
   1.120 +                /* Make SVM feature invisible to the guest. */
   1.121 +                clear_bit(X86_FEATURE_SVME & 31, &ecx);
   1.122 +#ifdef __i386__
   1.123 +                /* Mask feature for Intel ia32e or AMD long mode. */
   1.124 +                clear_bit(X86_FEATURE_LAHF_LM & 31, &ecx);
   1.125 +
   1.126 +                clear_bit(X86_FEATURE_LM & 31, &edx);
   1.127 +                clear_bit(X86_FEATURE_SYSCALL & 31, &edx);
   1.128  #endif
   1.129 -            clear_bit(X86_FEATURE_PAE, &edx);
   1.130 -        clear_bit(X86_FEATURE_PSE36, &edx);
   1.131 -
   1.132 -        /* Make SVM feature invisible to the guest. */
   1.133 -        clear_bit(X86_FEATURE_SVME & 31, &ecx);
   1.134 -
   1.135 -        /* So far, we do not support 3DNow for the guest. */
   1.136 -        clear_bit(X86_FEATURE_3DNOW & 31, &edx);
   1.137 -        clear_bit(X86_FEATURE_3DNOWEXT & 31, &edx);
   1.138 -    }
   1.139 -    else if ( ( input == 0x80000007 ) || ( input == 0x8000000A  ) )
   1.140 -    {
   1.141 -        /* Mask out features of power management and SVM extension. */
   1.142 -        eax = ebx = ecx = edx = 0;
   1.143 -    }
   1.144 -    else if ( input == 0x80000008 )
   1.145 -    {
   1.146 -        ecx &= 0xFFFFFF00; /* Make sure Number of CPU core is 1 when HTT=0 */
   1.147 +                /* So far, we do not support 3DNow for the guest. */
   1.148 +                clear_bit(X86_FEATURE_3DNOW & 31, &edx);
   1.149 +                clear_bit(X86_FEATURE_3DNOWEXT & 31, &edx);
   1.150 +            }
   1.151 +        }
   1.152 +        else if ( ( input == 0x80000007 ) || ( input == 0x8000000A  ) )
   1.153 +        {
   1.154 +            /* Mask out features of power management and SVM extension. */
   1.155 +            eax = ebx = ecx = edx = 0;
   1.156 +        }
   1.157 +        else if ( input == 0x80000008 )
   1.158 +        {
   1.159 +            /* Make sure Number of CPU core is 1 when HTT=0 */
   1.160 +            ecx &= 0xFFFFFF00; 
   1.161 +        }
   1.162      }
   1.163  
   1.164      regs->eax = (unsigned long)eax;