direct-io.hg

changeset 15102:7c176473786b

[IA64] Rewrite ia64 vcpu_guest_context_regs structure

All registers and the rbs are now declared in the structure.
Minimal updates to other parts.

Signed-off-by: Tristan Gingold <tgingold@free.fr>
author Alex Williamson <alex.williamson@hp.com>
date Mon May 07 10:37:16 2007 -0600 (2007-05-07)
parents 423055a4c972
children 1a010d9444ba
files tools/libxc/ia64/xc_ia64_hvm_build.c tools/libxc/ia64/xc_ia64_linux_restore.c tools/libxc/ia64/xc_ia64_linux_save.c tools/libxc/xc_dom_ia64.c tools/xentrace/xenctx.c xen/arch/ia64/xen/domain.c xen/include/public/arch-ia64.h xen/include/public/foreign/reference.size
line diff
     1.1 --- a/tools/libxc/ia64/xc_ia64_hvm_build.c	Mon May 07 08:56:28 2007 -0600
     1.2 +++ b/tools/libxc/ia64/xc_ia64_hvm_build.c	Mon May 07 10:37:16 2007 -0600
     1.3 @@ -738,7 +738,7 @@ xc_hvm_build(int xc_handle, uint32_t dom
     1.4  
     1.5      free(image);
     1.6  
     1.7 -    ctxt->user_regs.cr_iip = 0x80000000ffffffb0UL;
     1.8 +    ctxt->regs.ip = 0x80000000ffffffb0UL;
     1.9  
    1.10      memset(&launch_domctl, 0, sizeof(launch_domctl));
    1.11  
     2.1 --- a/tools/libxc/ia64/xc_ia64_linux_restore.c	Mon May 07 08:56:28 2007 -0600
     2.2 +++ b/tools/libxc/ia64/xc_ia64_linux_restore.c	Mon May 07 10:37:16 2007 -0600
     2.3 @@ -226,8 +226,7 @@ xc_domain_restore(int xc_handle, int io_
     2.4          goto out;
     2.5      }
     2.6  
     2.7 -    fprintf(stderr, "ip=%016lx, b0=%016lx\n", ctxt.user_regs.cr_iip,
     2.8 -            ctxt.user_regs.b0);
     2.9 +    fprintf(stderr, "ip=%016lx, b0=%016lx\n", ctxt.regs.ip, ctxt.regs.b[0]);
    2.10  
    2.11      /* First to initialize.  */
    2.12      domctl.cmd = XEN_DOMCTL_setvcpucontext;
     3.1 --- a/tools/libxc/ia64/xc_ia64_linux_save.c	Mon May 07 08:56:28 2007 -0600
     3.2 +++ b/tools/libxc/ia64/xc_ia64_linux_save.c	Mon May 07 10:37:16 2007 -0600
     3.3 @@ -460,8 +460,7 @@ xc_domain_save(int xc_handle, int io_fd,
     3.4          goto out;
     3.5      }
     3.6  
     3.7 -    fprintf(stderr, "ip=%016lx, b0=%016lx\n", ctxt.user_regs.cr_iip,
     3.8 -            ctxt.user_regs.b0);
     3.9 +    fprintf(stderr, "ip=%016lx, b0=%016lx\n", ctxt.regs.ip, ctxt.regs.b[0]);
    3.10  
    3.11      mem = xc_map_foreign_range(xc_handle, dom, PAGE_SIZE,
    3.12                                 PROT_READ|PROT_WRITE, ctxt.privregs_pfn);
     4.1 --- a/tools/libxc/xc_dom_ia64.c	Mon May 07 08:56:28 2007 -0600
     4.2 +++ b/tools/libxc/xc_dom_ia64.c	Mon May 07 10:37:16 2007 -0600
     4.3 @@ -92,13 +92,13 @@ static int vcpu_ia64(struct xc_dom_image
     4.4      memset(ctxt, 0, sizeof(*ctxt));
     4.5  
     4.6      ctxt->flags = 0;
     4.7 -    ctxt->user_regs.cr_ipsr = 0; /* all necessary bits filled by hypervisor */
     4.8 -    ctxt->user_regs.cr_iip = dom->parms.virt_entry;
     4.9 -    ctxt->user_regs.cr_ifs = (uint64_t) 1 << 63;
    4.10 -#ifdef __ia64__   /* FIXME */
    4.11 -    ctxt->user_regs.ar_fpsr = xc_ia64_fpsr_default();
    4.12 +    ctxt->regs.psr = 0;	/* all necessary bits filled by hypervisor */
    4.13 +    ctxt->regs.ip = dom->parms.virt_entry;
    4.14 +    ctxt->regs.cfm = (uint64_t) 1 << 63;
    4.15 +#ifdef __ia64__			/* FIXME */
    4.16 +    ctxt->regs.ar.fpsr = xc_ia64_fpsr_default();
    4.17  #endif
    4.18 -    ctxt->user_regs.r28 = (dom->start_info_pfn << PAGE_SHIFT_IA64)
    4.19 +    ctxt->regs.r[28] = (dom->start_info_pfn << PAGE_SHIFT_IA64)
    4.20          + sizeof(start_info_ia64_t);
    4.21      return 0;
    4.22  }
     5.1 --- a/tools/xentrace/xenctx.c	Mon May 07 08:56:28 2007 -0600
     5.2 +++ b/tools/xentrace/xenctx.c	Mon May 07 10:37:16 2007 -0600
     5.3 @@ -45,12 +45,6 @@ int stack_trace = 0;
     5.4  #define STACK_ROWS		4
     5.5  #define STACK_COLS		4
     5.6  #elif defined (__ia64__)
     5.7 -#define FMT_SIZE_T		"%016lx"
     5.8 -#define STACK_POINTER(regs)	(regs->r12)
     5.9 -#define FRAME_POINTER(regs)	0
    5.10 -#define INSTR_POINTER(regs)	(regs->cr_iip)
    5.11 -#define STACK_ROWS		4
    5.12 -#define STACK_COLS		4
    5.13  /* On ia64, we can't translate virtual address to physical address.  */
    5.14  #define NO_TRANSLATION
    5.15  #endif
    5.16 @@ -296,117 +290,117 @@ void print_ctx(vcpu_guest_context_t *ctx
    5.17  
    5.18  void print_ctx(vcpu_guest_context_t *ctx1)
    5.19  {
    5.20 -    struct cpu_user_regs *regs = &ctx1->user_regs;
    5.21 -    struct vcpu_extra_regs *er = &ctx1->extra_regs;
    5.22 +    struct vcpu_guest_context_regs *regs = &ctx1->regs;
    5.23 +    struct vcpu_tr_regs *tr = &ctx1->regs.tr;
    5.24      int i, ps_val, ma_val;
    5.25      unsigned long pa;
    5.26  
    5.27 -    const char ps[][5] = {"  4K", "  8K", " 16K", "    ",
    5.28 -                          " 64K", "    ", "256K", "    ",
    5.29 -                          "  1M", "    ", "  4M", "    ",
    5.30 -                          " 16M", "    ", " 64M", "    ",
    5.31 -                          "256M"};
    5.32 -    const char ma[][4] = {"WB ", "   ", "   ", "   ",
    5.33 -                          "UC ", "UCE", "WC ", "Nat"};
    5.34 +    static const char ps[][5] = {"  4K", "  8K", " 16K", "    ",
    5.35 +                                 " 64K", "    ", "256K", "    ",
    5.36 +                                 "  1M", "    ", "  4M", "    ",
    5.37 +                                 " 16M", "    ", " 64M", "    ",
    5.38 +                                 "256M"};
    5.39 +    static const char ma[][4] = {"WB ", "   ", "   ", "   ",
    5.40 +                                 "UC ", "UCE", "WC ", "Nat"};
    5.41  
    5.42 -    printf(" iip:               %016lx  ", regs->cr_iip);
    5.43 -    print_symbol(regs->cr_iip);
    5.44 +    printf(" ip:                %016lx  ", regs->ip);
    5.45 +    print_symbol(regs->ip);
    5.46      printf("\n");
    5.47 -    printf(" ipsr:              %016lx  ", regs->cr_ipsr);
    5.48 -    printf(" b0:                %016lx\n", regs->b0);
    5.49 -    printf(" b6:                %016lx  ", regs->b6);
    5.50 -    printf(" b7:                %016lx\n", regs->b7);
    5.51 -    printf(" cr_ifs:            %016lx  ", regs->cr_ifs);
    5.52 -    printf(" ar_unat:           %016lx\n", regs->ar_unat);
    5.53 -    printf(" ar_pfs:            %016lx  ", regs->ar_pfs);
    5.54 -    printf(" ar_rsc:            %016lx\n", regs->ar_rsc);
    5.55 -    printf(" ar_rnat:           %016lx  ", regs->ar_rnat);
    5.56 -    printf(" ar_bspstore:       %016lx\n", regs->ar_bspstore);
    5.57 -    printf(" ar_fpsr:           %016lx  ", regs->ar_fpsr);
    5.58 -    printf(" event_callback_ip: %016lx\n", er->event_callback_ip);
    5.59 +    printf(" psr:               %016lx  ", regs->psr);
    5.60 +    printf(" b0:                %016lx\n", regs->b[0]);
    5.61 +    printf(" b6:                %016lx  ", regs->b[6]);
    5.62 +    printf(" b7:                %016lx\n", regs->b[7]);
    5.63 +    printf(" cfm:               %016lx  ", regs->cfm);
    5.64 +    printf(" ar.unat:           %016lx\n", regs->ar.unat);
    5.65 +    printf(" ar.pfs:            %016lx  ", regs->ar.pfs);
    5.66 +    printf(" ar.rsc:            %016lx\n", regs->ar.rsc);
    5.67 +    printf(" ar.rnat:           %016lx  ", regs->ar.rnat);
    5.68 +    printf(" ar.bspstore:       %016lx\n", regs->ar.bspstore);
    5.69 +    printf(" ar.fpsr:           %016lx  ", regs->ar.fpsr);
    5.70 +    printf(" event_callback_ip: %016lx\n", ctx1->event_callback_ip);
    5.71      printf(" pr:                %016lx  ", regs->pr);
    5.72 -    printf(" loadrs:            %016lx\n", regs->loadrs);
    5.73 -    printf(" iva:               %016lx  ", er->iva);
    5.74 -    printf(" dcr:               %016lx\n", er->dcr);
    5.75 +    /*    printf(" loadrs:            %016lx\n", regs->loadrs); */
    5.76 +    printf(" iva:               %016lx\n", regs->cr.iva);
    5.77 +    printf(" dcr:               %016lx\n", regs->cr.dcr);
    5.78  
    5.79      printf("\n");
    5.80 -    printf(" r1:  %016lx\n", regs->r1);
    5.81 -    printf(" r2:  %016lx  ", regs->r2);
    5.82 -    printf(" r3:  %016lx\n", regs->r3);
    5.83 -    printf(" r4:  %016lx  ", regs->r4);
    5.84 -    printf(" r5:  %016lx\n", regs->r5);
    5.85 -    printf(" r6:  %016lx  ", regs->r6);
    5.86 -    printf(" r7:  %016lx\n", regs->r7);
    5.87 -    printf(" r8:  %016lx  ", regs->r8);
    5.88 -    printf(" r9:  %016lx\n", regs->r9);
    5.89 -    printf(" r10: %016lx  ", regs->r10);
    5.90 -    printf(" r11: %016lx\n", regs->r11);
    5.91 -    printf(" sp:  %016lx  ", regs->r12);
    5.92 -    printf(" tp:  %016lx\n", regs->r13);
    5.93 -    printf(" r14: %016lx  ", regs->r14);
    5.94 -    printf(" r15: %016lx\n", regs->r15);
    5.95 -    printf(" r16: %016lx  ", regs->r16);
    5.96 -    printf(" r17: %016lx\n", regs->r17);
    5.97 -    printf(" r18: %016lx  ", regs->r18);
    5.98 -    printf(" r19: %016lx\n", regs->r19);
    5.99 -    printf(" r20: %016lx  ", regs->r20);
   5.100 -    printf(" r21: %016lx\n", regs->r21);
   5.101 -    printf(" r22: %016lx  ", regs->r22);
   5.102 -    printf(" r23: %016lx\n", regs->r23);
   5.103 -    printf(" r24: %016lx  ", regs->r24);
   5.104 -    printf(" r25: %016lx\n", regs->r25);
   5.105 -    printf(" r26: %016lx  ", regs->r26);
   5.106 -    printf(" r27: %016lx\n", regs->r27);
   5.107 -    printf(" r28: %016lx  ", regs->r28);
   5.108 -    printf(" r29: %016lx\n", regs->r29);
   5.109 -    printf(" r30: %016lx  ", regs->r30);
   5.110 -    printf(" r31: %016lx\n", regs->r31);
   5.111 +    printf(" r1:  %016lx\n", regs->r[1]);
   5.112 +    printf(" r2:  %016lx  ", regs->r[2]);
   5.113 +    printf(" r3:  %016lx\n", regs->r[3]);
   5.114 +    printf(" r4:  %016lx  ", regs->r[4]);
   5.115 +    printf(" r5:  %016lx\n", regs->r[5]);
   5.116 +    printf(" r6:  %016lx  ", regs->r[6]);
   5.117 +    printf(" r7:  %016lx\n", regs->r[7]);
   5.118 +    printf(" r8:  %016lx  ", regs->r[8]);
   5.119 +    printf(" r9:  %016lx\n", regs->r[9]);
   5.120 +    printf(" r10: %016lx  ", regs->r[10]);
   5.121 +    printf(" r11: %016lx\n", regs->r[11]);
   5.122 +    printf(" sp:  %016lx  ", regs->r[12]);
   5.123 +    printf(" tp:  %016lx\n", regs->r[13]);
   5.124 +    printf(" r14: %016lx  ", regs->r[14]);
   5.125 +    printf(" r15: %016lx\n", regs->r[15]);
   5.126 +    printf(" r16: %016lx  ", regs->r[16]);
   5.127 +    printf(" r17: %016lx\n", regs->r[17]);
   5.128 +    printf(" r18: %016lx  ", regs->r[18]);
   5.129 +    printf(" r19: %016lx\n", regs->r[19]);
   5.130 +    printf(" r20: %016lx  ", regs->r[20]);
   5.131 +    printf(" r21: %016lx\n", regs->r[21]);
   5.132 +    printf(" r22: %016lx  ", regs->r[22]);
   5.133 +    printf(" r23: %016lx\n", regs->r[23]);
   5.134 +    printf(" r24: %016lx  ", regs->r[24]);
   5.135 +    printf(" r25: %016lx\n", regs->r[25]);
   5.136 +    printf(" r26: %016lx  ", regs->r[26]);
   5.137 +    printf(" r27: %016lx\n", regs->r[27]);
   5.138 +    printf(" r28: %016lx  ", regs->r[28]);
   5.139 +    printf(" r29: %016lx\n", regs->r[29]);
   5.140 +    printf(" r30: %016lx  ", regs->r[30]);
   5.141 +    printf(" r31: %016lx\n", regs->r[31]);
   5.142      
   5.143      printf("\n itr: P rid    va               pa            ps      ed pl "
   5.144             "ar a d ma    key\n");
   5.145      for (i = 0; i < 8; i++) {
   5.146 -        ps_val =  er->itrs[i].itir >> ITIR_PS_SHIFT & ITIR_PS_MASK;
   5.147 -        ma_val =  er->itrs[i].pte  >> PTE_MA_SHIFT  & PTE_MA_MASK;
   5.148 -        pa     = (er->itrs[i].pte  >> PTE_PPN_SHIFT & PTE_PPN_MASK) <<
   5.149 +        ps_val =  tr->itrs[i].itir >> ITIR_PS_SHIFT & ITIR_PS_MASK;
   5.150 +        ma_val =  tr->itrs[i].pte  >> PTE_MA_SHIFT  & PTE_MA_MASK;
   5.151 +        pa     = (tr->itrs[i].pte  >> PTE_PPN_SHIFT & PTE_PPN_MASK) <<
   5.152                   PTE_PPN_SHIFT;
   5.153          pa     = (pa >> ps_val) << ps_val;
   5.154          printf(" [%d]  %ld %06lx %016lx %013lx %02x %s %ld  %ld  %ld  %ld "
   5.155                 "%ld %d %s %06lx\n", i,
   5.156 -               er->itrs[i].pte  >> PTE_P_SHIFT    & PTE_P_MASK,
   5.157 -               er->itrs[i].rid  >> RR_RID_SHIFT   & RR_RID_MASK,
   5.158 -               er->itrs[i].vadr, pa, ps_val,
   5.159 +               tr->itrs[i].pte  >> PTE_P_SHIFT    & PTE_P_MASK,
   5.160 +               tr->itrs[i].rid  >> RR_RID_SHIFT   & RR_RID_MASK,
   5.161 +               tr->itrs[i].vadr, pa, ps_val,
   5.162                 ((ps_val >= ITIR_PS_MIN && ps_val <= ITIR_PS_MAX) ?
   5.163                  ps[ps_val - ITIR_PS_MIN] : "    "),
   5.164 -               er->itrs[i].pte  >> PTE_ED_SHIFT   & PTE_ED_MASK,
   5.165 -               er->itrs[i].pte  >> PTE_PL_SHIFT   & PTE_PL_MASK,
   5.166 -               er->itrs[i].pte  >> PTE_AR_SHIFT   & PTE_AR_MASK,
   5.167 -               er->itrs[i].pte  >> PTE_A_SHIFT    & PTE_A_MASK,
   5.168 -               er->itrs[i].pte  >> PTE_D_SHIFT    & PTE_D_MASK,
   5.169 +               tr->itrs[i].pte  >> PTE_ED_SHIFT   & PTE_ED_MASK,
   5.170 +               tr->itrs[i].pte  >> PTE_PL_SHIFT   & PTE_PL_MASK,
   5.171 +               tr->itrs[i].pte  >> PTE_AR_SHIFT   & PTE_AR_MASK,
   5.172 +               tr->itrs[i].pte  >> PTE_A_SHIFT    & PTE_A_MASK,
   5.173 +               tr->itrs[i].pte  >> PTE_D_SHIFT    & PTE_D_MASK,
   5.174                 ma_val, ma[ma_val],
   5.175 -               er->itrs[i].itir >> ITIR_KEY_SHIFT & ITIR_KEY_MASK);
   5.176 +               tr->itrs[i].itir >> ITIR_KEY_SHIFT & ITIR_KEY_MASK);
   5.177      }
   5.178      printf("\n dtr: P rid    va               pa            ps      ed pl "
   5.179             "ar a d ma    key\n");
   5.180      for (i = 0; i < 8; i++) {
   5.181 -        ps_val =  er->dtrs[i].itir >> ITIR_PS_SHIFT & ITIR_PS_MASK;
   5.182 -        ma_val =  er->dtrs[i].pte  >> PTE_MA_SHIFT  & PTE_MA_MASK;
   5.183 -        pa     = (er->dtrs[i].pte  >> PTE_PPN_SHIFT & PTE_PPN_MASK) <<
   5.184 +        ps_val =  tr->dtrs[i].itir >> ITIR_PS_SHIFT & ITIR_PS_MASK;
   5.185 +        ma_val =  tr->dtrs[i].pte  >> PTE_MA_SHIFT  & PTE_MA_MASK;
   5.186 +        pa     = (tr->dtrs[i].pte  >> PTE_PPN_SHIFT & PTE_PPN_MASK) <<
   5.187                   PTE_PPN_SHIFT;
   5.188          pa     = (pa >> ps_val) << ps_val;
   5.189          printf(" [%d]  %ld %06lx %016lx %013lx %02x %s %ld  %ld  %ld  %ld "
   5.190                 "%ld %d %s %06lx\n", i,
   5.191 -               er->dtrs[i].pte  >> PTE_P_SHIFT    & PTE_P_MASK,
   5.192 -               er->dtrs[i].rid  >> RR_RID_SHIFT   & RR_RID_MASK,
   5.193 -               er->dtrs[i].vadr, pa, ps_val,
   5.194 +               tr->dtrs[i].pte  >> PTE_P_SHIFT    & PTE_P_MASK,
   5.195 +               tr->dtrs[i].rid  >> RR_RID_SHIFT   & RR_RID_MASK,
   5.196 +               tr->dtrs[i].vadr, pa, ps_val,
   5.197                 ((ps_val >= ITIR_PS_MIN && ps_val <= ITIR_PS_MAX) ?
   5.198                  ps[ps_val - ITIR_PS_MIN] : "    "),
   5.199 -               er->dtrs[i].pte  >> PTE_ED_SHIFT   & PTE_ED_MASK,
   5.200 -               er->dtrs[i].pte  >> PTE_PL_SHIFT   & PTE_PL_MASK,
   5.201 -               er->dtrs[i].pte  >> PTE_AR_SHIFT   & PTE_AR_MASK,
   5.202 -               er->dtrs[i].pte  >> PTE_A_SHIFT    & PTE_A_MASK,
   5.203 -               er->dtrs[i].pte  >> PTE_D_SHIFT    & PTE_D_MASK,
   5.204 +               tr->dtrs[i].pte  >> PTE_ED_SHIFT   & PTE_ED_MASK,
   5.205 +               tr->dtrs[i].pte  >> PTE_PL_SHIFT   & PTE_PL_MASK,
   5.206 +               tr->dtrs[i].pte  >> PTE_AR_SHIFT   & PTE_AR_MASK,
   5.207 +               tr->dtrs[i].pte  >> PTE_A_SHIFT    & PTE_A_MASK,
   5.208 +               tr->dtrs[i].pte  >> PTE_D_SHIFT    & PTE_D_MASK,
   5.209                 ma_val, ma[ma_val],
   5.210 -               er->dtrs[i].itir >> ITIR_KEY_SHIFT & ITIR_KEY_MASK);
   5.211 +               tr->dtrs[i].itir >> ITIR_KEY_SHIFT & ITIR_KEY_MASK);
   5.212      }
   5.213  }
   5.214  #endif
   5.215 @@ -526,8 +520,6 @@ void print_stack(vcpu_guest_context_t *c
   5.216          }
   5.217      }
   5.218  }
   5.219 -#else
   5.220 -#define print_stack(ctx, vcpu)
   5.221  #endif
   5.222  
   5.223  void dump_ctx(int vcpu)
   5.224 @@ -551,8 +543,10 @@ void dump_ctx(int vcpu)
   5.225      }
   5.226  
   5.227      print_ctx(&ctx);
   5.228 +#ifndef NO_TRANSLATION
   5.229      if (is_kernel_text(INSTR_POINTER((&ctx.user_regs))))
   5.230          print_stack(&ctx, vcpu);
   5.231 +#endif
   5.232  
   5.233      ret = xc_domain_unpause(xc_handle, domid);
   5.234      if (ret < 0) {
     6.1 --- a/xen/arch/ia64/xen/domain.c	Mon May 07 08:56:28 2007 -0600
     6.2 +++ b/xen/arch/ia64/xen/domain.c	Mon May 07 10:37:16 2007 -0600
     6.3 @@ -607,63 +607,210 @@ int arch_vcpu_reset(struct vcpu *v)
     6.4  void arch_get_info_guest(struct vcpu *v, vcpu_guest_context_u c)
     6.5  {
     6.6  	int i;
     6.7 -	struct vcpu_extra_regs *er = &c.nat->extra_regs;
     6.8 +	struct vcpu_tr_regs *tr = &c.nat->regs.tr;
     6.9 +	struct cpu_user_regs *uregs = vcpu_regs(v);
    6.10 +	int is_hvm = VMX_DOMAIN(v);
    6.11 +
    6.12 +	c.nat->regs.b[6] = uregs->b6;
    6.13 +	c.nat->regs.b[7] = uregs->b7;
    6.14 +
    6.15 +	c.nat->regs.ar.csd = uregs->ar_csd;
    6.16 +	c.nat->regs.ar.ssd = uregs->ar_ssd;
    6.17 +
    6.18 +	c.nat->regs.r[8] = uregs->r8;
    6.19 +	c.nat->regs.r[9] = uregs->r9;
    6.20 +	c.nat->regs.r[10] = uregs->r10;
    6.21 +	c.nat->regs.r[11] = uregs->r11;
    6.22 +
    6.23 +	if (is_hvm) {
    6.24 +		c.nat->regs.psr = vmx_vcpu_get_psr (v);
    6.25 +	} else {
    6.26 +		/* FIXME: get the vpsr.  */
    6.27 +		c.nat->regs.psr = uregs->cr_ipsr;
    6.28 +	}
    6.29 +
    6.30 +	c.nat->regs.ip = uregs->cr_iip;
    6.31 +	c.nat->regs.cfm = uregs->cr_ifs;
    6.32 +
    6.33 +	c.nat->regs.ar.unat = uregs->ar_unat;
    6.34 +	c.nat->regs.ar.pfs = uregs->ar_pfs;
    6.35 +	c.nat->regs.ar.rsc = uregs->ar_rsc;
    6.36 +	c.nat->regs.ar.rnat = uregs->ar_rnat;
    6.37 +	c.nat->regs.ar.bspstore = uregs->ar_bspstore;
    6.38 +
    6.39 +	c.nat->regs.pr = uregs->pr;
    6.40 +	c.nat->regs.b[0] = uregs->b0;
    6.41 +	c.nat->regs.ar.bsp = uregs->ar_bspstore + (uregs->loadrs >> 16);
    6.42  
    6.43 -	c.nat->user_regs = *vcpu_regs(v);
    6.44 - 	c.nat->privregs_pfn = get_gpfn_from_mfn(virt_to_maddr(v->arch.privregs) >>
    6.45 -                                                PAGE_SHIFT);
    6.46 +	c.nat->regs.r[1] = uregs->r1;
    6.47 +	c.nat->regs.r[12] = uregs->r12;
    6.48 +	c.nat->regs.r[13] = uregs->r13;
    6.49 +	c.nat->regs.ar.fpsr = uregs->ar_fpsr;
    6.50 +	c.nat->regs.r[15] = uregs->r15;
    6.51 +
    6.52 +	c.nat->regs.r[14] = uregs->r14;
    6.53 +	c.nat->regs.r[2] = uregs->r2;
    6.54 +	c.nat->regs.r[3] = uregs->r3;
    6.55 +	c.nat->regs.r[16] = uregs->r16;
    6.56 +	c.nat->regs.r[17] = uregs->r17;
    6.57 +	c.nat->regs.r[18] = uregs->r18;
    6.58 +	c.nat->regs.r[19] = uregs->r19;
    6.59 +	c.nat->regs.r[20] = uregs->r20;
    6.60 +	c.nat->regs.r[21] = uregs->r21;
    6.61 +	c.nat->regs.r[22] = uregs->r22;
    6.62 +	c.nat->regs.r[23] = uregs->r23;
    6.63 +	c.nat->regs.r[24] = uregs->r24;
    6.64 +	c.nat->regs.r[25] = uregs->r25;
    6.65 +	c.nat->regs.r[26] = uregs->r26;
    6.66 +	c.nat->regs.r[27] = uregs->r27;
    6.67 +	c.nat->regs.r[28] = uregs->r28;
    6.68 +	c.nat->regs.r[29] = uregs->r29;
    6.69 +	c.nat->regs.r[30] = uregs->r30;
    6.70 +	c.nat->regs.r[31] = uregs->r31;
    6.71 +
    6.72 +	c.nat->regs.ar.ccv = uregs->ar_ccv;
    6.73 +
    6.74 +	c.nat->regs.f[6] = uregs->f6;
    6.75 +	c.nat->regs.f[7] = uregs->f7;
    6.76 +	c.nat->regs.f[8] = uregs->f8;
    6.77 +	c.nat->regs.f[9] = uregs->f9;
    6.78 +	c.nat->regs.f[10] = uregs->f10;
    6.79 +	c.nat->regs.f[11] = uregs->f11;
    6.80 +
    6.81 +	c.nat->regs.r[4] = uregs->r4;
    6.82 +	c.nat->regs.r[5] = uregs->r5;
    6.83 +	c.nat->regs.r[6] = uregs->r6;
    6.84 +	c.nat->regs.r[7] = uregs->r7;
    6.85 +
    6.86 +	/* FIXME: to be reordered.  */
    6.87 +	c.nat->regs.nats = uregs->eml_unat;
    6.88 +
    6.89 + 	c.nat->privregs_pfn = get_gpfn_from_mfn
    6.90 +		(virt_to_maddr(v->arch.privregs) >> PAGE_SHIFT);
    6.91  
    6.92  	/* Fill extra regs.  */
    6.93  	for (i = 0; i < 8; i++) {
    6.94 -		er->itrs[i].pte = v->arch.itrs[i].pte.val;
    6.95 -		er->itrs[i].itir = v->arch.itrs[i].itir;
    6.96 -		er->itrs[i].vadr = v->arch.itrs[i].vadr;
    6.97 -		er->itrs[i].rid = v->arch.itrs[i].rid;
    6.98 +		tr->itrs[i].pte = v->arch.itrs[i].pte.val;
    6.99 +		tr->itrs[i].itir = v->arch.itrs[i].itir;
   6.100 +		tr->itrs[i].vadr = v->arch.itrs[i].vadr;
   6.101 +		tr->itrs[i].rid = v->arch.itrs[i].rid;
   6.102  	}
   6.103  	for (i = 0; i < 8; i++) {
   6.104 -		er->dtrs[i].pte = v->arch.dtrs[i].pte.val;
   6.105 -		er->dtrs[i].itir = v->arch.dtrs[i].itir;
   6.106 -		er->dtrs[i].vadr = v->arch.dtrs[i].vadr;
   6.107 -		er->dtrs[i].rid = v->arch.dtrs[i].rid;
   6.108 +		tr->dtrs[i].pte = v->arch.dtrs[i].pte.val;
   6.109 +		tr->dtrs[i].itir = v->arch.dtrs[i].itir;
   6.110 +		tr->dtrs[i].vadr = v->arch.dtrs[i].vadr;
   6.111 +		tr->dtrs[i].rid = v->arch.dtrs[i].rid;
   6.112  	}
   6.113 -	er->event_callback_ip = v->arch.event_callback_ip;
   6.114 -	er->dcr = v->arch.privregs ? PSCB(v,dcr) : 0;
   6.115 -	er->iva = v->arch.iva;
   6.116 +	c.nat->event_callback_ip = v->arch.event_callback_ip;
   6.117 +
   6.118 +	/* If PV and privregs is not set, we can't read mapped registers.  */
   6.119 + 	if (!v->domain->arch.is_vti && v->arch.privregs == NULL)
   6.120 +		return;
   6.121 +
   6.122 +	vcpu_get_dcr (v, &c.nat->regs.cr.dcr);
   6.123 +	vcpu_get_iva (v, &c.nat->regs.cr.iva);
   6.124  }
   6.125  
   6.126  int arch_set_info_guest(struct vcpu *v, vcpu_guest_context_u c)
   6.127  {
   6.128 -	struct pt_regs *regs = vcpu_regs (v);
   6.129 +	struct cpu_user_regs *uregs = vcpu_regs(v);
   6.130  	struct domain *d = v->domain;
   6.131  	int rc;
   6.132 +
   6.133 +	uregs->b6 = c.nat->regs.b[6];
   6.134 +	uregs->b7 = c.nat->regs.b[7];
   6.135  	
   6.136 -	*regs = c.nat->user_regs;
   6.137 - 	
   6.138 +	uregs->ar_csd = c.nat->regs.ar.csd;
   6.139 +	uregs->ar_ssd = c.nat->regs.ar.ssd;
   6.140 +	
   6.141 +	uregs->r8 = c.nat->regs.r[8];
   6.142 +	uregs->r9 = c.nat->regs.r[9];
   6.143 +	uregs->r10 = c.nat->regs.r[10];
   6.144 +	uregs->r11 = c.nat->regs.r[11];
   6.145 +	
   6.146 +	uregs->cr_ipsr = c.nat->regs.psr;
   6.147 +	uregs->cr_iip = c.nat->regs.ip;
   6.148 +	uregs->cr_ifs = c.nat->regs.cfm;
   6.149 +	
   6.150 +	uregs->ar_unat = c.nat->regs.ar.unat;
   6.151 +	uregs->ar_pfs = c.nat->regs.ar.pfs;
   6.152 +	uregs->ar_rsc = c.nat->regs.ar.rsc;
   6.153 +	uregs->ar_rnat = c.nat->regs.ar.rnat;
   6.154 +	uregs->ar_bspstore = c.nat->regs.ar.bspstore;
   6.155 +	
   6.156 +	uregs->pr = c.nat->regs.pr;
   6.157 +	uregs->b0 = c.nat->regs.b[0];
   6.158 +	uregs->loadrs = (c.nat->regs.ar.bsp - c.nat->regs.ar.bspstore) << 16;
   6.159 +
   6.160 +	uregs->r1 = c.nat->regs.r[1];
   6.161 +	uregs->r12 = c.nat->regs.r[12];
   6.162 +	uregs->r13 = c.nat->regs.r[13];
   6.163 +	uregs->ar_fpsr = c.nat->regs.ar.fpsr;
   6.164 +	uregs->r15 = c.nat->regs.r[15];
   6.165 +
   6.166 +	uregs->r14 = c.nat->regs.r[14];
   6.167 +	uregs->r2 = c.nat->regs.r[2];
   6.168 +	uregs->r3 = c.nat->regs.r[3];
   6.169 +	uregs->r16 = c.nat->regs.r[16];
   6.170 +	uregs->r17 = c.nat->regs.r[17];
   6.171 +	uregs->r18 = c.nat->regs.r[18];
   6.172 +	uregs->r19 = c.nat->regs.r[19];
   6.173 +	uregs->r20 = c.nat->regs.r[20];
   6.174 +	uregs->r21 = c.nat->regs.r[21];
   6.175 +	uregs->r22 = c.nat->regs.r[22];
   6.176 +	uregs->r23 = c.nat->regs.r[23];
   6.177 +	uregs->r24 = c.nat->regs.r[24];
   6.178 +	uregs->r25 = c.nat->regs.r[25];
   6.179 +	uregs->r26 = c.nat->regs.r[26];
   6.180 +	uregs->r27 = c.nat->regs.r[27];
   6.181 +	uregs->r28 = c.nat->regs.r[28];
   6.182 +	uregs->r29 = c.nat->regs.r[29];
   6.183 +	uregs->r30 = c.nat->regs.r[30];
   6.184 +	uregs->r31 = c.nat->regs.r[31];
   6.185 +	
   6.186 +	uregs->ar_ccv = c.nat->regs.ar.ccv;
   6.187 +	
   6.188 +	uregs->f6 = c.nat->regs.f[6];
   6.189 +	uregs->f7 = c.nat->regs.f[7];
   6.190 +	uregs->f8 = c.nat->regs.f[8];
   6.191 +	uregs->f9 = c.nat->regs.f[9];
   6.192 +	uregs->f10 = c.nat->regs.f[10];
   6.193 +	uregs->f11 = c.nat->regs.f[11];
   6.194 +	
   6.195 +	uregs->r4 = c.nat->regs.r[4];
   6.196 +	uregs->r5 = c.nat->regs.r[5];
   6.197 +	uregs->r6 = c.nat->regs.r[6];
   6.198 +	uregs->r7 = c.nat->regs.r[7];
   6.199 +	
   6.200 +	/* FIXME: to be reordered and restored.  */
   6.201 +	/* uregs->eml_unat = c.nat->regs.nat; */
   6.202 +	uregs->eml_unat = 0;
   6.203 +	
   6.204   	if (!d->arch.is_vti) {
   6.205   		/* domain runs at PL2/3 */
   6.206 - 		regs->cr_ipsr |= 2UL << IA64_PSR_CPL0_BIT;
   6.207 - 		regs->ar_rsc |= (2 << 2); /* force PL2/3 */
   6.208 + 		uregs->cr_ipsr |= 2UL << IA64_PSR_CPL0_BIT;
   6.209 + 		uregs->ar_rsc |= (2 << 2); /* force PL2/3 */
   6.210   	}
   6.211  
   6.212  	if (c.nat->flags & VGCF_EXTRA_REGS) {
   6.213  		int i;
   6.214 -		struct vcpu_extra_regs *er = &c.nat->extra_regs;
   6.215 +		struct vcpu_tr_regs *tr = &c.nat->regs.tr;
   6.216  
   6.217  		for (i = 0; i < 8; i++) {
   6.218 -			vcpu_set_itr(v, i, er->itrs[i].pte,
   6.219 -			             er->itrs[i].itir,
   6.220 -			             er->itrs[i].vadr,
   6.221 -			             er->itrs[i].rid);
   6.222 +			vcpu_set_itr(v, i, tr->itrs[i].pte,
   6.223 +			             tr->itrs[i].itir,
   6.224 +			             tr->itrs[i].vadr,
   6.225 +			             tr->itrs[i].rid);
   6.226  		}
   6.227  		for (i = 0; i < 8; i++) {
   6.228  			vcpu_set_dtr(v, i,
   6.229 -			             er->dtrs[i].pte,
   6.230 -			             er->dtrs[i].itir,
   6.231 -			             er->dtrs[i].vadr,
   6.232 -			             er->dtrs[i].rid);
   6.233 +			             tr->dtrs[i].pte,
   6.234 +			             tr->dtrs[i].itir,
   6.235 +			             tr->dtrs[i].vadr,
   6.236 +			             tr->dtrs[i].rid);
   6.237  		}
   6.238 -		v->arch.event_callback_ip = er->event_callback_ip;
   6.239 -		v->arch.iva = er->iva;
   6.240 +		v->arch.event_callback_ip = c.nat->event_callback_ip;
   6.241 +		v->arch.iva = c.nat->regs.cr.iva;
   6.242  	}
   6.243  
   6.244  	if (v->is_initialised)
     7.1 --- a/xen/include/public/arch-ia64.h	Mon May 07 08:56:28 2007 -0600
     7.2 +++ b/xen/include/public/arch-ia64.h	Mon May 07 10:37:16 2007 -0600
     7.3 @@ -337,20 +337,120 @@ struct ia64_tr_entry {
     7.4      unsigned long rid;
     7.5  };
     7.6  
     7.7 -struct vcpu_extra_regs {
     7.8 +struct vcpu_tr_regs {
     7.9      struct ia64_tr_entry itrs[8];
    7.10      struct ia64_tr_entry dtrs[8];
    7.11 -    unsigned long iva;
    7.12 -    unsigned long dcr;
    7.13 -    unsigned long event_callback_ip;
    7.14 +};
    7.15 +
    7.16 +union vcpu_ar_regs {
    7.17 +    unsigned long ar[128];
    7.18 +    struct {
    7.19 +        unsigned long kr[8];
    7.20 +        unsigned long rsv1[8];
    7.21 +        unsigned long rsc;
    7.22 +        unsigned long bsp;
    7.23 +        unsigned long bspstore;
    7.24 +        unsigned long rnat;
    7.25 +        unsigned long rsv2;
    7.26 +        unsigned long fcr;
    7.27 +        unsigned long rsv3[2];
    7.28 +        unsigned long eflag;
    7.29 +        unsigned long csd;
    7.30 +        unsigned long ssd;
    7.31 +        unsigned long cflg;
    7.32 +        unsigned long fsr;
    7.33 +        unsigned long fir;
    7.34 +        unsigned long fdr;
    7.35 +        unsigned long rsv4;
    7.36 +        unsigned long ccv; /* 32 */
    7.37 +        unsigned long rsv5[3];
    7.38 +        unsigned long unat;
    7.39 +        unsigned long rsv6[3];
    7.40 +        unsigned long fpsr;
    7.41 +        unsigned long rsv7[3];
    7.42 +        unsigned long itc;
    7.43 +        unsigned long rsv8[3];
    7.44 +        unsigned long ign1[16];
    7.45 +        unsigned long pfs; /* 64 */
    7.46 +        unsigned long lc;
    7.47 +        unsigned long ec;
    7.48 +        unsigned long rsv9[45];
    7.49 +        unsigned long ign2[16];
    7.50 +    };
    7.51 +};
    7.52 +
    7.53 +union vcpu_cr_regs {
    7.54 +    unsigned long cr[128];
    7.55 +    struct {
    7.56 +        unsigned long dcr;  // CR0
    7.57 +        unsigned long itm;
    7.58 +        unsigned long iva;
    7.59 +        unsigned long rsv1[5];
    7.60 +        unsigned long pta;  // CR8
    7.61 +        unsigned long rsv2[7];
    7.62 +        unsigned long ipsr;  // CR16
    7.63 +        unsigned long isr;
    7.64 +        unsigned long rsv3;
    7.65 +        unsigned long iip;
    7.66 +        unsigned long ifa;
    7.67 +        unsigned long itir;
    7.68 +        unsigned long iipa;
    7.69 +        unsigned long ifs;
    7.70 +        unsigned long iim;  // CR24
    7.71 +        unsigned long iha;
    7.72 +        unsigned long rsv4[38];
    7.73 +        unsigned long lid;  // CR64
    7.74 +        unsigned long ivr;
    7.75 +        unsigned long tpr;
    7.76 +        unsigned long eoi;
    7.77 +        unsigned long irr[4];
    7.78 +        unsigned long itv;  // CR72
    7.79 +        unsigned long pmv;
    7.80 +        unsigned long cmcv;
    7.81 +        unsigned long rsv5[5];
    7.82 +        unsigned long lrr0;  // CR80
    7.83 +        unsigned long lrr1;
    7.84 +        unsigned long rsv6[46];
    7.85 +    };
    7.86 +};
    7.87 +
    7.88 +struct vcpu_guest_context_regs {
    7.89 +        unsigned long r[32];
    7.90 +        unsigned long b[8];
    7.91 +        unsigned long bank[16];
    7.92 +        unsigned long ip;
    7.93 +        unsigned long psr;
    7.94 +        unsigned long cfm;
    7.95 +        unsigned long pr;
    7.96 +        unsigned long nats; /* NaT bits for r1-r31.  */
    7.97 +        union vcpu_ar_regs ar;
    7.98 +        union vcpu_cr_regs cr;
    7.99 +        struct pt_fpreg f[128];
   7.100 +        unsigned long dbr[8];
   7.101 +        unsigned long ibr[8];
   7.102 +        unsigned long rr[8];
   7.103 +        unsigned long pkr[16];
   7.104 +
   7.105 +        /* FIXME: cpuid,pmd,pmc */
   7.106 +
   7.107 +        unsigned long xip;
   7.108 +        unsigned long xpsr;
   7.109 +        unsigned long xfs;
   7.110 +        unsigned long xr[4];
   7.111 +
   7.112 +        struct vcpu_tr_regs tr;
   7.113 +
   7.114 +        /* Note: loadrs is 2**14 bytes == 2**11 slots.  */
   7.115 +        unsigned long rbs[2048];
   7.116  };
   7.117  
   7.118  struct vcpu_guest_context {
   7.119  #define VGCF_EXTRA_REGS (1<<1)	/* Get/Set extra regs.  */
   7.120      unsigned long flags;       /* VGCF_* flags */
   7.121  
   7.122 -    struct cpu_user_regs user_regs;
   7.123 -    struct vcpu_extra_regs extra_regs;
   7.124 +    struct vcpu_guest_context_regs regs;
   7.125 +
   7.126 +    unsigned long event_callback_ip;
   7.127      unsigned long privregs_pfn;
   7.128  };
   7.129  typedef struct vcpu_guest_context vcpu_guest_context_t;
     8.1 --- a/xen/include/public/foreign/reference.size	Mon May 07 08:56:28 2007 -0600
     8.2 +++ b/xen/include/public/foreign/reference.size	Mon May 07 10:37:16 2007 -0600
     8.3 @@ -7,8 +7,8 @@ pt_fpreg             |       -       -  
     8.4  cpu_user_regs        |      68     200     496
     8.5  xen_ia64_boot_param  |       -       -      96
     8.6  ia64_tr_entry        |       -       -      32
     8.7 -vcpu_extra_regs      |       -       -     536
     8.8 -vcpu_guest_context   |    2800    5168    1056
     8.9 +vcpu_extra_regs      |       -       -       -
    8.10 +vcpu_guest_context   |    2800    5168   21904
    8.11  arch_vcpu_info       |      24      16       0
    8.12  vcpu_time_info       |      32      32      32
    8.13  vcpu_info            |      64      64      48