direct-io.hg

changeset 15530:69ec2ef3d132

Reverted ioemu directory back to rev 15522
author Guy Zana <guy@neocleus.com>
date Wed Aug 29 00:48:01 2007 +0300 (2007-08-29)
parents 9ce39dc1425f
children b4d5751e8783
files tools/ioemu/Makefile tools/ioemu/Makefile.target tools/ioemu/hw/passthrough/dm-access.c tools/ioemu/hw/passthrough/dpciarg.c tools/ioemu/hw/passthrough/legacy.c tools/ioemu/hw/passthrough/pass-through.c tools/ioemu/hw/passthrough/pass-through.h tools/ioemu/hw/pc.c tools/ioemu/pt-libpci/Makefile tools/ioemu/pt-libpci/lib2.2.6/.gitignore tools/ioemu/pt-libpci/lib2.2.6/Makefile tools/ioemu/pt-libpci/lib2.2.6/access.c tools/ioemu/pt-libpci/lib2.2.6/aix-device.c tools/ioemu/pt-libpci/lib2.2.6/config.h tools/ioemu/pt-libpci/lib2.2.6/config.mk tools/ioemu/pt-libpci/lib2.2.6/configure tools/ioemu/pt-libpci/lib2.2.6/dump.c tools/ioemu/pt-libpci/lib2.2.6/example.c tools/ioemu/pt-libpci/lib2.2.6/fbsd-device.c tools/ioemu/pt-libpci/lib2.2.6/filter.c tools/ioemu/pt-libpci/lib2.2.6/generic.c tools/ioemu/pt-libpci/lib2.2.6/header.h tools/ioemu/pt-libpci/lib2.2.6/i386-io-hurd.h tools/ioemu/pt-libpci/lib2.2.6/i386-io-linux.h tools/ioemu/pt-libpci/lib2.2.6/i386-io-sunos.h tools/ioemu/pt-libpci/lib2.2.6/i386-io-windows.h tools/ioemu/pt-libpci/lib2.2.6/i386-ports.c tools/ioemu/pt-libpci/lib2.2.6/internal.h tools/ioemu/pt-libpci/lib2.2.6/libpci.pc.in tools/ioemu/pt-libpci/lib2.2.6/names.c tools/ioemu/pt-libpci/lib2.2.6/nbsd-libpci.c tools/ioemu/pt-libpci/lib2.2.6/obsd-device.c tools/ioemu/pt-libpci/lib2.2.6/pci.h tools/ioemu/pt-libpci/lib2.2.6/pread.h tools/ioemu/pt-libpci/lib2.2.6/proc.c tools/ioemu/pt-libpci/lib2.2.6/sysdep.h tools/ioemu/pt-libpci/lib2.2.6/sysfs.c tools/ioemu/pt-libpci/lib2.2.6/types.h tools/ioemu/pt-libpci/lspci.c tools/ioemu/pt-libpci/pt_libpci.c tools/ioemu/pt-libpci/pt_libpci.h tools/ioemu/pt-libpci/pt_pci_access.c tools/ioemu/pt-libpci/pt_pci_access.h tools/ioemu/pt-libpci/pt_pci_probe.c tools/ioemu/pt-libpci/pt_pci_probe.h tools/ioemu/pt-libpci/pt_pci_tree.c tools/ioemu/pt-libpci/pt_pci_tree.h tools/ioemu/pt-libpci/pt_util.c tools/ioemu/target-i386-dm/exec-dm.c tools/ioemu/target-i386-dm/helper2.c tools/ioemu/target-i386-dm/piix_pci-dm.c tools/ioemu/vl.c tools/ioemu/vl.h
line diff
     1.1 --- a/tools/ioemu/Makefile	Thu Aug 23 13:42:03 2007 -0700
     1.2 +++ b/tools/ioemu/Makefile	Wed Aug 29 00:48:01 2007 +0300
     1.3 @@ -37,10 +37,7 @@ endif
     1.4  
     1.5  TOOLS=
     1.6  
     1.7 -all: pt_libpci $(TOOLS) $(DOCS) recurse-all
     1.8 -
     1.9 -pt_libpci:
    1.10 -	$(MAKE) -C pt-libpci
    1.11 +all: $(TOOLS) $(DOCS) recurse-all
    1.12  
    1.13  subdir-%:
    1.14  	$(MAKE) -C $(subst subdir-,,$@) all
    1.15 @@ -58,7 +55,6 @@ clean:
    1.16  	rm -f config.mak config.h op-i386.h opc-i386.h gen-op-i386.h op-arm.h opc-arm.h gen-op-arm.h 
    1.17  	rm -f *.o *.a $(TOOLS) dyngen$(EXESUF) TAGS *.pod *~ */*~
    1.18  	$(MAKE) -C tests clean
    1.19 -	$(MAKE) -C pt-libpci clean
    1.20  	for d in $(TARGET_DIRS); do \
    1.21  	[ -d $$d ] && $(MAKE) -C $$d $@ || exit 0 ; \
    1.22          done
    1.23 @@ -106,7 +102,7 @@ test speed test2: all
    1.24  	$(MAKE) -C tests $@
    1.25  
    1.26  TAGS: 
    1.27 -	etags *.[ch] target-i386-dm/*.[ch] hw/*.[ch] hw/pass-through/*.[ch]
    1.28 +	etags *.[ch] target-i386-dm/*.[ch] hw/*.[ch]
    1.29  
    1.30  cscope:
    1.31  	rm -f ./cscope.*
     2.1 --- a/tools/ioemu/Makefile.target	Thu Aug 23 13:42:03 2007 -0700
     2.2 +++ b/tools/ioemu/Makefile.target	Wed Aug 29 00:48:01 2007 +0300
     2.3 @@ -14,12 +14,10 @@ ifeq ($(TARGET_ARCH), sparc64)
     2.4  TARGET_BASE_ARCH:=sparc
     2.5  endif
     2.6  TARGET_PATH=$(SRC_PATH)/target-$(TARGET_BASE_ARCH)$(TARGET_SUB)
     2.7 -VPATH=$(SRC_PATH):$(TARGET_PATH):$(SRC_PATH)/hw:$(SRC_PATH)/audio:$(SRC_PATH)/hw/passthrough
     2.8 +VPATH=$(SRC_PATH):$(TARGET_PATH):$(SRC_PATH)/hw:$(SRC_PATH)/audio
     2.9  CPPFLAGS=-I. -I.. -I$(TARGET_PATH) -I$(SRC_PATH)
    2.10  CPPFLAGS+= -I$(XEN_ROOT)/tools/libxc
    2.11  CPPFLAGS+= -I$(XEN_ROOT)/tools/xenstore
    2.12 -# pt-libpci
    2.13 -CPPFLAGS+= -I$(SRC_PATH)/pt-libpci -DPT_LIBPCI
    2.14  ifdef CONFIG_DARWIN_USER
    2.15  VPATH+=:$(SRC_PATH)/darwin-user
    2.16  CPPFLAGS+=-I$(SRC_PATH)/darwin-user -I$(SRC_PATH)/darwin-user/$(TARGET_ARCH)
    2.17 @@ -242,7 +240,6 @@ endif
    2.18  
    2.19  SRCS:= $(OBJS:.o=.c)
    2.20  OBJS+= libqemu.a
    2.21 -OBJS+= ../pt-libpci/pt_libpci.a
    2.22  
    2.23  # cpu emulator library
    2.24  LIBOBJS=exec.o kqemu.o translate-op.o translate-all.o cpu-exec.o\
    2.25 @@ -398,7 +395,6 @@ VL_OBJS+= fdc.o mc146818rtc.o serial.o p
    2.26  else
    2.27  VL_OBJS+= fdc.o serial.o pc.o
    2.28  endif
    2.29 -VL_OBJS+= pass-through.o legacy.o dm-access.o dpciarg.o
    2.30  VL_OBJS+= cirrus_vga.o mixeng.o parallel.o acpi.o
    2.31  VL_OBJS+= usb-uhci.o smbus_eeprom.o
    2.32  VL_OBJS+= piix4acpi.o
    2.33 @@ -497,7 +493,7 @@ ifdef CONFIG_WIN32
    2.34  SDL_LIBS := $(filter-out -mwindows, $(SDL_LIBS)) -mconsole
    2.35  endif
    2.36  
    2.37 -$(QEMU_SYSTEM): $(VL_OBJS) libqemu.a ../pt-libpci/pt_libpci.a
    2.38 +$(QEMU_SYSTEM): $(VL_OBJS) libqemu.a
    2.39  	$(CC) $(VL_LDFLAGS) -o $@ $^ $(LIBS) $(SDL_LIBS) $(COCOA_LIBS) $(VL_LIBS)
    2.40  
    2.41  cocoa.o: cocoa.m
     3.1 --- a/tools/ioemu/hw/passthrough/dm-access.c	Thu Aug 23 13:42:03 2007 -0700
     3.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.3 @@ -1,402 +0,0 @@
     3.4 -/* Copyright (c) 2007, Neocleus */
     3.5 -#include <sys/mman.h>
     3.6 -#include <sys/io.h>
     3.7 -
     3.8 -#include "pass-through.h"
     3.9 -#include "pt_pci_access.h"
    3.10 -#include "vl.h"
    3.11 -
    3.12 -extern FILE * logfile;
    3.13 -
    3.14 -/* mmap handle */
    3.15 -int pt_phys_ram_fd;
    3.16 -
    3.17 -CPUReadMemoryFunc * pt_mmio_read_cb[3] = {
    3.18 -    pt_mmio_readb,
    3.19 -    pt_mmio_readw,
    3.20 -    pt_mmio_readl
    3.21 -};
    3.22 -
    3.23 -CPUWriteMemoryFunc * pt_mmio_write_cb[3] = {
    3.24 -    pt_mmio_writeb,
    3.25 -    pt_mmio_writew,
    3.26 -    pt_mmio_writel
    3.27 -};
    3.28 -
    3.29 -void pt_mmio_writeb(void * opaque, target_phys_addr_t e_phys, uint32_t value)
    3.30 -{
    3.31 -    uint32_t r_virt = 0;
    3.32 -    pt_region_t * r_access = (pt_region_t  *)opaque;
    3.33 -
    3.34 -    r_virt = r_access->access.virtual_address + ((uint32_t)e_phys - r_access->e_physbase);
    3.35 -
    3.36 -    if ( r_access->do_logging )
    3.37 -    {
    3.38 -        fprintf(logfile,"pt_mmio_writeb: e_physbase=%08x e_phys=%08x r_virt=%08x value=%08x\n",
    3.39 -            r_access->e_physbase, (uint32_t)e_phys, r_virt, value);
    3.40 -    }
    3.41 -    
    3.42 -    pt_mmio_write(r_virt, value, 1);
    3.43 -}
    3.44 -
    3.45 -void pt_mmio_writew(void * opaque, target_phys_addr_t e_phys, uint32_t value)
    3.46 -{
    3.47 -    uint32_t r_virt = 0;
    3.48 -    pt_region_t * r_access = (pt_region_t  *)opaque;
    3.49 -
    3.50 -    r_virt = r_access->access.virtual_address + ((uint32_t)e_phys - r_access->e_physbase);
    3.51 -
    3.52 -    if ( r_access->do_logging )
    3.53 -    {
    3.54 -        fprintf(logfile,"pt_mmio_writew: e_physbase=%08x e_phys=%08x r_virt=%08x value=%08x\n",
    3.55 -            r_access->e_physbase, (uint32_t)e_phys, r_virt, value);
    3.56 -    }
    3.57 -    
    3.58 -    pt_mmio_write(r_virt, value, 2);			
    3.59 -}
    3.60 -
    3.61 -void pt_mmio_writel(void *opaque, target_phys_addr_t e_phys, uint32_t value)
    3.62 -{
    3.63 -    uint32_t r_virt = 0;
    3.64 -    pt_region_t * r_access = (pt_region_t  *)opaque;
    3.65 -
    3.66 -    r_virt = r_access->access.virtual_address + ((uint32_t)e_phys - r_access->e_physbase);
    3.67 -
    3.68 -    if ( r_access->do_logging )
    3.69 -    {
    3.70 -        fprintf(logfile,"pt_mmio_writel: e_physbase=%08x e_phys=%08x r_virt=%08x value=%08x\n",
    3.71 -        r_access->e_physbase, (uint32_t)e_phys, r_virt, value);
    3.72 -    }
    3.73 -    
    3.74 -    pt_mmio_write(r_virt, value, 4);		
    3.75 -}
    3.76 -
    3.77 -uint32_t pt_mmio_readb(void * opaque, target_phys_addr_t e_phys)
    3.78 -{
    3.79 -    uint32_t r_virt = 0;
    3.80 -    uint32_t value = 0;
    3.81 -    pt_region_t * r_access = (pt_region_t  *)opaque;
    3.82 -
    3.83 -    r_virt = r_access->access.virtual_address + ((uint32_t)e_phys - r_access->e_physbase);
    3.84 -    value = pt_mmio_read(r_virt, 1);
    3.85 -
    3.86 -    if ( r_access->do_logging )
    3.87 -    {
    3.88 -        fprintf(logfile,"pt_mmio_readb:  e_physbase=%08x e_phys=%08x r_virt=%08x value=%08x\n", 
    3.89 -            r_access->e_physbase, (uint32_t)e_phys, r_virt, value);
    3.90 -    }
    3.91 -    
    3.92 -    return (value);
    3.93 -}
    3.94 -
    3.95 -uint32_t pt_mmio_readw(void * opaque, target_phys_addr_t e_phys)
    3.96 -{
    3.97 -    uint32_t r_virt = 0;
    3.98 -    uint32_t value = 0;
    3.99 -    pt_region_t * r_access = (pt_region_t  *)opaque;
   3.100 -
   3.101 -    r_virt = r_access->access.virtual_address + ((uint32_t)e_phys - r_access->e_physbase);
   3.102 -    value = pt_mmio_read(r_virt, 2);
   3.103 -
   3.104 -    if ( r_access->do_logging )
   3.105 -    {
   3.106 -        fprintf(logfile,"pt_mmio_readw:  e_physbase=%08x e_phys=%08x r_virt=%08x value=%08x\n",
   3.107 -            r_access->e_physbase, (uint32_t)e_phys, r_virt, value);
   3.108 -    }
   3.109 -    
   3.110 -    return (value);
   3.111 -}
   3.112 -
   3.113 -uint32_t pt_mmio_readl(void * opaque, target_phys_addr_t e_phys)
   3.114 -{
   3.115 -    uint32_t r_virt = 0;
   3.116 -    uint32_t value = 0;
   3.117 -    pt_region_t * r_access = (pt_region_t  *)opaque;
   3.118 -
   3.119 -    r_virt = r_access->access.virtual_address + ((uint32_t)e_phys - r_access->e_physbase);
   3.120 -    value = pt_mmio_read(r_virt, 4);
   3.121 -
   3.122 -    if ( r_access->do_logging )
   3.123 -    {
   3.124 -        fprintf(logfile,"pt_mmio_readl:  e_physbase=%08x e_phys=%08x r_virt=%08x value=%08x\n",
   3.125 -            r_access->e_physbase, (uint32_t)e_phys, r_virt, value);
   3.126 -    }
   3.127 -    
   3.128 -    return (value);
   3.129 -}
   3.130 -
   3.131 -void pt_ioport_writeb(void *opaque, uint32_t addr, uint32_t value)
   3.132 -{
   3.133 -    uint32_t r_pio = 0;
   3.134 -    pt_region_t * r_access = (pt_region_t  *)opaque;
   3.135 -
   3.136 -    r_pio = (addr - r_access->e_physbase) + r_access->access.ioport_base;
   3.137 -
   3.138 -    if ( r_access->do_logging )
   3.139 -    {
   3.140 -        fprintf(logfile,"pt_ioport_writeb: r_pio=%08x e_physbase=%08x access.ioport_base=%08x value=%08x\n",
   3.141 -            r_pio,  r_access->e_physbase, r_access->access.ioport_base, value);
   3.142 -    }
   3.143 -    
   3.144 -    pt_pio_write(r_pio, value, 1);
   3.145 -}
   3.146 -
   3.147 -void pt_ioport_writew(void *opaque, uint32_t addr, uint32_t value)
   3.148 -{
   3.149 -    uint32_t r_pio = 0;
   3.150 -    pt_region_t * r_access = (pt_region_t  *)opaque;
   3.151 -
   3.152 -    r_pio = (addr - r_access->e_physbase) + r_access->access.ioport_base;
   3.153 -
   3.154 -    if ( r_access->do_logging )
   3.155 -    {
   3.156 -        fprintf(logfile,"pt_ioport_writew: r_pio=%08x e_physbase=%08x access.ioport_base=%08x value=%08x\n",
   3.157 -            r_pio,  r_access->e_physbase, r_access->access.ioport_base, value);
   3.158 -    }
   3.159 -    
   3.160 -    pt_pio_write(r_pio, value, 2);
   3.161 -}
   3.162 -
   3.163 -void pt_ioport_writel(void *opaque, uint32_t addr, uint32_t value)
   3.164 -{
   3.165 -    uint32_t r_pio = 0;
   3.166 -    pt_region_t * r_access = (pt_region_t  *)opaque;
   3.167 -
   3.168 -    r_pio = (addr - r_access->e_physbase) + r_access->access.ioport_base;
   3.169 -
   3.170 -    if ( r_access->do_logging )
   3.171 -    {
   3.172 -        fprintf(logfile,"pt_ioport_writel: r_pio=%08x e_physbase=%08x access.ioport_base=%08x value=%08x\n",
   3.173 -            r_pio,  r_access->e_physbase, r_access->access.ioport_base, value);
   3.174 -    }
   3.175 -    
   3.176 -    pt_pio_write(r_pio, value, 4);
   3.177 -}
   3.178 -
   3.179 -uint32_t pt_ioport_readb(void *opaque, uint32_t addr)
   3.180 -{
   3.181 -
   3.182 -    uint32_t r_pio = 0;
   3.183 -    uint32_t value = 0;
   3.184 -    pt_region_t * r_access = (pt_region_t  *)opaque;
   3.185 -    
   3.186 -    r_pio = (addr - r_access->e_physbase) + r_access->access.ioport_base;
   3.187 -
   3.188 -    value = pt_pio_read(r_pio, 1);
   3.189 -
   3.190 -    if ( r_access->do_logging )
   3.191 -    {
   3.192 -        fprintf(logfile,"pt_ioport_readb:  r_pio=%08x e_physbase=%08x access.ioport_base=%08x value=%08x\n",
   3.193 -            r_pio,  r_access->e_physbase, r_access->access.ioport_base, value);
   3.194 -    }
   3.195 -    
   3.196 -    return (value);
   3.197 -}
   3.198 -
   3.199 -uint32_t pt_ioport_readw(void *opaque, uint32_t addr)
   3.200 -{
   3.201 -
   3.202 -    uint32_t r_pio = 0;
   3.203 -    uint32_t value = 0;
   3.204 -    pt_region_t * r_access = (pt_region_t  *)opaque;
   3.205 -    
   3.206 -    r_pio = (addr - r_access->e_physbase) + r_access->access.ioport_base;
   3.207 -
   3.208 -    value = pt_pio_read(r_pio, 2);
   3.209 -
   3.210 -    if ( r_access->do_logging )
   3.211 -    {
   3.212 -        fprintf(logfile,"pt_ioport_readw:  r_pio=%08x e_physbase=%08x access.ioport_base=%08x value=%08x\n",
   3.213 -            r_pio,  r_access->e_physbase, r_access->access.ioport_base, value);
   3.214 -    }
   3.215 -    
   3.216 -    return (value);	
   3.217 -}
   3.218 -
   3.219 -uint32_t pt_ioport_readl(void *opaque, uint32_t addr)
   3.220 -{
   3.221 -
   3.222 -    uint32_t r_pio = 0;
   3.223 -    uint32_t value = 0;
   3.224 -    pt_region_t * r_access = (pt_region_t  *)opaque;
   3.225 -    
   3.226 -    r_pio = (addr - r_access->e_physbase) + r_access->access.ioport_base;
   3.227 -
   3.228 -    value = pt_pio_read(r_pio, 4);
   3.229 -
   3.230 -    if ( r_access->do_logging )
   3.231 -    {
   3.232 -        fprintf(logfile,"pt_ioport_readl:  r_pio=%08x e_physbase=%08x access.ioport_base=%08x value=%08x\n",
   3.233 -            r_pio,  r_access->e_physbase, r_access->access.ioport_base, value);
   3.234 -    }
   3.235 -    
   3.236 -    return (value);
   3.237 -}
   3.238 -
   3.239 -
   3.240 -void pt_ioport_map_dm(PCIDevice *pci_dev, int i, 
   3.241 -                       uint32_t addr, uint32_t size, int type)
   3.242 -{
   3.243 -    pt_dev_t * r_dev = (pt_dev_t *)pci_dev;
   3.244 -    uint32_t old_ebase = r_dev->bases[i].e_physbase;
   3.245 -    uint8_t first_map = !(r_dev->bases[i].e_size != 0);
   3.246 -    int ret = 0;
   3.247 -    
   3.248 -    fprintf(logfile,"pt_ioport_map: e_addr=0x%x access.ioport_base=0x%x type=0x%x len=%d region_num=%d \n", 
   3.249 -        addr, r_dev->bases[i].access.ioport_base, type, size, i);
   3.250 -
   3.251 -    /* Update access */
   3.252 -    r_dev->bases[i].e_physbase = addr;
   3.253 -    r_dev->bases[i].e_size= size;
   3.254 -
   3.255 -    if ( size == 0 ) 
   3.256 -    {
   3.257 -        fprintf(logfile, "pt_ioport_map failed: size = 0!\n"); 
   3.258 -        return;
   3.259 -    }
   3.260 -    
   3.261 -    if ( !first_map )
   3.262 -        isa_unassign_ioport(old_ebase, r_dev->bases[i].e_size);
   3.263 -
   3.264 -    /* Create new mapping */
   3.265 -    ret |= register_ioport_write(addr, size, 1, pt_ioport_writeb, (void*)&(r_dev->bases[i]));
   3.266 -    ret |= register_ioport_read( addr, size, 1, pt_ioport_readb,  (void*)&(r_dev->bases[i]));
   3.267 -
   3.268 -    ret |= register_ioport_write(addr, size, 2, pt_ioport_writew, (void*)&(r_dev->bases[i]));
   3.269 -    ret |= register_ioport_read( addr, size, 2, pt_ioport_readw,  (void*)&(r_dev->bases[i]));
   3.270 -
   3.271 -    ret |= register_ioport_write(addr, size, 4, pt_ioport_writel, (void*)&(r_dev->bases[i]));
   3.272 -    ret |= register_ioport_read( addr, size, 4, pt_ioport_readl,  (void*)&(r_dev->bases[i]));
   3.273 -
   3.274 -    if ( 0 != ret )
   3.275 -        fprintf(logfile, "pt_ioport_map: failed!\n");
   3.276 -        
   3.277 -}
   3.278 -
   3.279 -void pt_iomem_map_dm(PCIDevice *d, int i,
   3.280 -			       uint32_t e_phys, uint32_t e_size, int type)
   3.281 -{
   3.282 -    pt_dev_t * r_dev  = (pt_dev_t *)d; 
   3.283 -
   3.284 -    r_dev->bases[i].e_physbase = e_phys;
   3.285 -    r_dev->bases[i].e_size= e_size;
   3.286 -
   3.287 -    fprintf(logfile, "pt_iomem_map: e_phys=%08x r_virt=%08x type=%d len=%08x region_number=%d \n",
   3.288 -    	e_phys, r_dev->bases[i].access.virtual_address, type, e_size, i);
   3.289 -
   3.290 -    if ( e_size == 0 ) 
   3.291 -    {
   3.292 -        fprintf(logfile, "pt_iomem_map failed: e_size = 0!\n");
   3.293 -        return;
   3.294 -    }
   3.295 -
   3.296 -    cpu_register_physical_memory(e_phys, e_size, r_dev->bases[i].memory_index);
   3.297 -}
   3.298 -
   3.299 -int pt_register_region_dm(pci_phys_dev_t * phys_dev, pt_dev_t * pci_dev, int i)
   3.300 -{
   3.301 -    pci_region_t * r;
   3.302 -
   3.303 -    if ( i >= PCI_NUM_REGIONS)
   3.304 -        return -1;
   3.305 -
   3.306 -    /* PCI ROM Region */
   3.307 -    if ( i == PCI_ROM_SLOT ) 
   3.308 -    {
   3.309 -        /* Check if ROM found */
   3.310 -        if ( (phys_dev->rom_size == 0) || (phys_dev->rom_base_addr == 0) )
   3.311 -            return -1;
   3.312 -
   3.313 -        /* MMAP BAR address */
   3.314 -        pci_dev->bases[i].e_physbase = phys_dev->rom_base_addr;
   3.315 -        pci_dev->bases[i].access.virtual_address = (uint32_t) mmap(NULL, 
   3.316 -            (phys_dev->rom_size + 0xFFF) & 0xFFFFF000, 
   3.317 -            PROT_WRITE | PROT_READ, MAP_SHARED,  
   3.318 -            pt_phys_ram_fd,
   3.319 -            (off_t) (phys_dev->rom_base_addr & 0xFFFFF000));
   3.320 -
   3.321 -        if ( (uint32_t)-1 == pci_dev->bases[i].access.virtual_address ) 
   3.322 -        {
   3.323 -            fprintf(logfile,"pt_register_region_dm: Couldn't mmap expansion ROM 0x%x!\n", (uint32_t)(phys_dev->rom_base_addr));
   3.324 -            return -1;
   3.325 -        }
   3.326 -
   3.327 -        /* Add offset (in case the region is not page aligned) */
   3.328 -        pci_dev->bases[i].access.virtual_address += (phys_dev->rom_base_addr & 0xFFF);
   3.329 -
   3.330 -        pci_dev->bases[i].do_logging = PT_LOG_ACCESS_MMIO;
   3.331 -
   3.332 -        pci_dev->bases[i].memory_index = cpu_register_io_memory(0, 
   3.333 -                pt_mmio_read_cb, pt_mmio_write_cb, (void *)&(pci_dev->bases[i]));
   3.334 -                
   3.335 -        pci_register_io_region((PCIDevice *)pci_dev, PCI_ROM_SLOT, phys_dev->rom_size, 
   3.336 -                       PCI_ADDRESS_SPACE_MEM_PREFETCH, pt_iomem_map);
   3.337 -
   3.338 -        fprintf(logfile,"pt_register_region_dm: Expansion ROM registered (size=0x%08x base_addr=0x%08x)\n",
   3.339 -            phys_dev->rom_size, phys_dev->rom_base_addr);
   3.340 -            
   3.341 -    }
   3.342 -    else /* PIO/MMIO Region */
   3.343 -    {
   3.344 -        r = &phys_dev->regions[i];
   3.345 -
   3.346 -        if ( !IS_VALID_REGION(r) )
   3.347 -            return -1;
   3.348 -
   3.349 -        if ( (r->type == PT_PCI_ADDRESS_SPACE_MEM) ||
   3.350 -             (r->type == PT_PCI_ADDRESS_SPACE_MEM_PREFETCH) )
   3.351 -        {
   3.352 -            /* MMAP BAR address */
   3.353 -            pci_dev->bases[i].e_physbase = r->base_addr;
   3.354 -            pci_dev->bases[i].access.virtual_address = (uint32_t) mmap(NULL, 
   3.355 -                (r->size + 0xFFF) & 0xFFFFF000, 
   3.356 -                PROT_WRITE | PROT_READ, MAP_SHARED,  
   3.357 -                pt_phys_ram_fd,
   3.358 -                (off_t) (r->base_addr & 0xFFFFF000));
   3.359 -
   3.360 -            if ( (uint32_t)-1 == pci_dev->bases[i].access.virtual_address )
   3.361 -            {
   3.362 -                fprintf(logfile,"pt_register_region_dm: Couldn't mmap 0x%x!\n", (uint32_t)(r->base_addr));
   3.363 -                return -1;	
   3.364 -            }
   3.365 -
   3.366 -            /* Add offset (in case the region is not page aligned) */
   3.367 -            pci_dev->bases[i].access.virtual_address += (r->base_addr & 0xFFF);
   3.368 -            
   3.369 -            pci_dev->bases[i].do_logging = PT_LOG_ACCESS_MMIO;
   3.370 -                        
   3.371 -            pci_dev->bases[i].memory_index = cpu_register_io_memory(0, 
   3.372 -                    pt_mmio_read_cb, pt_mmio_write_cb,(void *)&(pci_dev->bases[i]));
   3.373 -
   3.374 -            pci_register_io_region((PCIDevice *) pci_dev, i, r->size, r->type, pt_iomem_map);
   3.375 -
   3.376 -        }
   3.377 -        else if ( r->type == PT_PCI_ADDRESS_SPACE_IO )
   3.378 -        {
   3.379 -            pci_dev->bases[i].e_physbase = r->base_addr;
   3.380 -            pci_dev->bases[i].access.ioport_base = r->base_addr;
   3.381 -            pci_dev->bases[i].memory_index = 0; // not relevant for port io
   3.382 -            pci_dev->bases[i].do_logging = PT_LOG_ACCESS_PIO;
   3.383 -            pci_register_io_region((PCIDevice *) pci_dev, i, r->size, r->type, pt_ioport_map);
   3.384 -        }
   3.385 -
   3.386 -        fprintf(logfile,"pt_register_region_dm: IO region registered (size=0x%08x type=%-34s index=%d base_addr=0x%08x)\n",
   3.387 -            r->size, PT_GET_TYPE_STR(r->type), i, r->base_addr);
   3.388 -    }
   3.389 -
   3.390 -    return 0;
   3.391 -}
   3.392 -
   3.393 -int pt_init_mmio_access_dm(void)
   3.394 -{
   3.395 -    /* open /dev/mem for mapping mmio */
   3.396 -    if ( (pt_phys_ram_fd = open("/dev/mem", O_RDWR | O_SYNC)) < 0 ) 
   3.397 -    {
   3.398 -        fprintf(logfile,"pt_init_mmio_access_dm: couldn't open /dev/mem!\n");
   3.399 -        return -1;
   3.400 -    }
   3.401 -
   3.402 -    return 0;
   3.403 -}
   3.404 -
   3.405 -
     4.1 --- a/tools/ioemu/hw/passthrough/dpciarg.c	Thu Aug 23 13:42:03 2007 -0700
     4.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.3 @@ -1,39 +0,0 @@
     4.4 -#include "vl.h"
     4.5 -#include "pass-through.h"
     4.6 -
     4.7 -char * token;
     4.8 -
     4.9 -int pci_devs(const char *direct_pci)
    4.10 -{
    4.11 -    int count = 0;
    4.12 -    const char *c;
    4.13 -
    4.14 -    /* skip first "[" character */
    4.15 -    c = direct_pci + 1;
    4.16 -    while ((c = strchr(c, '[')) != NULL) {
    4.17 -        c++;
    4.18 -        count++;
    4.19 -    }
    4.20 -    return (count);
    4.21 -}
    4.22 -
    4.23 -int next_token(char *direct_pci)
    4.24 -{
    4.25 -    if (token == NULL)
    4.26 -        token = strtok(direct_pci, ",");
    4.27 -    else 
    4.28 -        token = strtok(NULL, ",");
    4.29 -    token = strchr(token, 'x');
    4.30 -    token = token + 1;
    4.31 -    return ((int) strtol(token, NULL, 16));
    4.32 -}
    4.33 -
    4.34 -void next_bdf(char *direct_pci, int *seg,
    4.35 -              int *bus, int *dev, int *func)
    4.36 -{
    4.37 -    *seg  = next_token(direct_pci);
    4.38 -    *bus  = next_token(direct_pci);
    4.39 -    *dev  = next_token(direct_pci);
    4.40 -    *func = next_token(direct_pci);
    4.41 -}
    4.42 -
     5.1 --- a/tools/ioemu/hw/passthrough/legacy.c	Thu Aug 23 13:42:03 2007 -0700
     5.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.3 @@ -1,126 +0,0 @@
     5.4 -/*
     5.5 - * Copyright (c) 2007, Neocleus / Intel
     5.6 - *
     5.7 - * Alex Novik <alex@neocleus.com>
     5.8 - * Allen Kay <allen.m.kay@intel.com>
     5.9 - * Guy Zana <guy@neocleus.com>
    5.10 - *
    5.11 - */
    5.12 -#include <sys/mman.h>
    5.13 -#include <sys/io.h>
    5.14 -#include "pass-through.h"
    5.15 -#include "pt_libpci.h"
    5.16 -
    5.17 -extern CPUReadMemoryFunc * pt_mmio_read_cb[3];
    5.18 -extern CPUReadMemoryFunc * pt_mmio_write_cb[3];
    5.19 -extern int pt_phys_ram_fd;
    5.20 -
    5.21 -int register_pt_legacy_mmio_region_dm(uint32_t mmio_addr, uint32_t length, uint8_t do_logging)
    5.22 -{
    5.23 -    pt_region_t * r_access;
    5.24 -
    5.25 -    /* TBD: free! */
    5.26 -    r_access = qemu_mallocz(sizeof(pt_region_t));
    5.27 -    r_access->e_physbase = mmio_addr;
    5.28 -    r_access->e_size = length;
    5.29 -    r_access->access.virtual_address = (uint32_t) mmap(NULL, 
    5.30 -        (length + 0xFFF) & 0xFFFFF000, 
    5.31 -        PROT_WRITE | PROT_READ, MAP_SHARED,  
    5.32 -        pt_phys_ram_fd,
    5.33 -        (off_t) (mmio_addr & 0xFFFFF000));
    5.34 -
    5.35 -    if ( (uint32_t)-1 == r_access->access.virtual_address ) 
    5.36 -    {
    5.37 -        fprintf(logfile,"Error: Couldn't mmap 0x%x!\n", (uint32_t)(mmio_addr & 0xFFFFF000));
    5.38 -        return -1;
    5.39 -    }
    5.40 -
    5.41 -    /* Add offset */
    5.42 -    r_access->access.virtual_address += mmio_addr & 0xFFF;
    5.43 -
    5.44 -    /* Logging */
    5.45 -    r_access->do_logging = do_logging;
    5.46 -    
    5.47 -    /* Register memory access callbacks */
    5.48 -    r_access->memory_index = cpu_register_io_memory(0, pt_mmio_read_cb, pt_mmio_write_cb, (void *)r_access);
    5.49 -    if ( (uint32_t)-1 == r_access->memory_index )
    5.50 -    {
    5.51 -        fprintf(logfile,"Error: Couldn't register legacy mmio region 0x%08x!\n", mmio_addr);
    5.52 -        return -1;
    5.53 -    }
    5.54 -
    5.55 -    cpu_register_physical_memory(mmio_addr, length, r_access->memory_index);
    5.56 -
    5.57 -    fprintf(logfile,"MMIO 0x%08x-0x%08x mapped successfuly!\n", mmio_addr, mmio_addr+length);
    5.58 -    return 0;
    5.59 -}
    5.60 -
    5.61 -int register_pt_legacy_pio_region_dm(uint32_t pio_start, uint32_t length, uint8_t do_logging) 
    5.62 -{
    5.63 -    pt_region_t * r_access;
    5.64 -    int rc = 0;
    5.65 -
    5.66 -    /* TODO: free! */
    5.67 -    r_access = qemu_mallocz(sizeof(pt_region_t));
    5.68 -    r_access->e_physbase = pio_start;
    5.69 -    r_access->access.ioport_base = pio_start;
    5.70 -    r_access->e_size = length;    
    5.71 -
    5.72 -    /* Logging */
    5.73 -    r_access->do_logging = do_logging;
    5.74 -
    5.75 -    /* Register callbacks */
    5.76 -    rc |= register_ioport_write(pio_start, length, 1, pt_ioport_writeb, (void *)r_access);
    5.77 -    rc |= register_ioport_read( pio_start, length, 1, pt_ioport_readb, (void *)r_access);
    5.78 -
    5.79 -    if ( length >=2 ) 
    5.80 -    {
    5.81 -        rc |= register_ioport_write(pio_start, length, 2, pt_ioport_writew, (void*)r_access);    
    5.82 -        rc |= register_ioport_read( pio_start, length, 2, pt_ioport_readw, (void*)r_access);
    5.83 -    }
    5.84 -
    5.85 -    if ( length >= 4 ) 
    5.86 -    {
    5.87 -        rc |= register_ioport_write(pio_start, length, 4, pt_ioport_writel, (void*)r_access);
    5.88 -        rc |= register_ioport_read( pio_start, length, 4, pt_ioport_readl, (void*)r_access);
    5.89 -    }
    5.90 - 
    5.91 -    fprintf(logfile,"PIO 0x%04x-0x%04x mapped successfuly!\n", pio_start, pio_start+length);
    5.92 -    return rc;
    5.93 -}
    5.94 -
    5.95 -
    5.96 -int register_pt_legacy_mmio_region_hypervisor(uint32_t mmio_addr, uint32_t length, uint8_t do_logging)
    5.97 -{
    5.98 -
    5.99 -    int ret;
   5.100 -    ret = xc_domain_memory_mapping(xc_handle,
   5.101 -                           domid,
   5.102 -                           mmio_addr >> 12,
   5.103 -                           mmio_addr >> 12,
   5.104 -                           length >> 12,
   5.105 -                           DPCI_ADD_MAPPING);
   5.106 -
   5.107 -    if ( 0 == ret )
   5.108 -        fprintf(logfile,"MMIO 0x%08x-0x%08x mapped successfuly!\n", mmio_addr, mmio_addr+length);
   5.109 -        
   5.110 -    return ret;
   5.111 -}
   5.112 -
   5.113 -int register_pt_legacy_pio_region_hypervisor(uint32_t pio_start, uint32_t length, uint8_t do_logging) 
   5.114 -{
   5.115 -
   5.116 -    int ret;
   5.117 -    ret = xc_domain_ioport_mapping(xc_handle,
   5.118 -                                   domid,
   5.119 -                                   pio_start,
   5.120 -                                   pio_start,
   5.121 -                                   length,
   5.122 -                                   DPCI_ADD_MAPPING);
   5.123 -
   5.124 -    if ( 0 == ret )
   5.125 -        fprintf(logfile,"PIO 0x%04x-0x%04x mapped successfuly!\n", pio_start, pio_start+length);
   5.126 -        
   5.127 -    return ret;
   5.128 -}
   5.129 -
     6.1 --- a/tools/ioemu/hw/passthrough/pass-through.c	Thu Aug 23 13:42:03 2007 -0700
     6.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.3 @@ -1,418 +0,0 @@
     6.4 -/*
     6.5 - * Copyright (c) 2007, Neocleus / Intel
     6.6 - *
     6.7 - * Alex Novik <alex@neocleus.com>
     6.8 - * Allen Kay <allen.m.kay@intel.com>
     6.9 - * Guy Zana <guy@neocleus.com>
    6.10 - *
    6.11 - * This file implements direct PCI assignment to a HVM guest domain.
    6.12 - *
    6.13 - */
    6.14 -#include "vl.h"
    6.15 -#include "pass-through.h"
    6.16 -
    6.17 -#include "pt_libpci.h"
    6.18 -#include "pt_pci_probe.h"
    6.19 -#include "pt_pci_access.h"
    6.20 -#include "pt_pci_tree.h"
    6.21 -
    6.22 -extern FILE * logfile;
    6.23 -
    6.24 -/* Being called anytime a mmio region has been updated */
    6.25 -void pt_iomem_map_hypervisor(PCIDevice *d, int i,
    6.26 -			                 uint32_t e_phys, uint32_t e_size, int type)
    6.27 -{
    6.28 -    pt_dev_t * r_dev  = (pt_dev_t *)d; 
    6.29 -    uint32_t old_ebase = r_dev->bases[i].e_physbase;
    6.30 -    uint8_t first_map = (r_dev->bases[i].e_size == 0);
    6.31 -    int ret = 0;
    6.32 -
    6.33 -    r_dev->bases[i].e_physbase = e_phys;
    6.34 -    r_dev->bases[i].e_size= e_size;
    6.35 -
    6.36 -    fprintf(logfile, "pt_iomem_map: e_phys=%08x access.machine_address=%08x type=%d len=%08x region_number=%d \n",
    6.37 -    	e_phys, r_dev->bases[i].access.machine_address, type, e_size, i);
    6.38 -
    6.39 -    if ( e_size == 0 ) 
    6.40 -    {
    6.41 -        fprintf(logfile, "pt_iomem_map failed: e_size = 0!\n");
    6.42 -        return ;
    6.43 -    }
    6.44 -
    6.45 -    if ( !first_map ) 
    6.46 -    {    
    6.47 -        /* Remove old mapping */
    6.48 -        ret = xc_domain_memory_mapping(xc_handle,
    6.49 -                                   domid,
    6.50 -                                   old_ebase >> 12,
    6.51 -                                   r_dev->bases[i].access.machine_address >> 12,
    6.52 -                                   (e_size+0xFFF) >> 12,
    6.53 -                                   DPCI_REMOVE_MAPPING);
    6.54 -
    6.55 -        if ( 0 != ret ) 
    6.56 -        {
    6.57 -            fprintf(logfile, "pt_iomem_map: remove old mapping failed!\n");
    6.58 -            return;
    6.59 -        }
    6.60 -                               
    6.61 -    }
    6.62 -
    6.63 -    /* Create new mapping */
    6.64 -    ret = xc_domain_memory_mapping(xc_handle,
    6.65 -                               domid,
    6.66 -                               r_dev->bases[i].e_physbase >> 12,
    6.67 -                               r_dev->bases[i].access.machine_address >> 12,
    6.68 -                               (e_size+0xFFF) >> 12,
    6.69 -                               DPCI_ADD_MAPPING);
    6.70 -
    6.71 -    if ( 0 != ret )
    6.72 -        fprintf(logfile, "pt_iomem_map: create new mapping failed!\n");
    6.73 -
    6.74 -}
    6.75 -
    6.76 -                       
    6.77 -void pt_ioport_map_hypervisor(PCIDevice *pci_dev, int i, 
    6.78 -                       uint32_t addr, uint32_t size, int type)
    6.79 -{
    6.80 -    pt_dev_t * r_dev = (pt_dev_t *)pci_dev;
    6.81 -    uint32_t old_ebase = r_dev->bases[i].e_physbase;
    6.82 -    uint8_t first_map = !(r_dev->bases[i].e_size != 0);
    6.83 -    int ret = 0;
    6.84 -    
    6.85 -    fprintf(logfile,"pt_ioport_map: e_addr=0x%x access.ioport_base=0x%x type=0x%x len=%d region_number=%d\n", 
    6.86 -        addr, r_dev->bases[i].access.ioport_base, type, size, i);
    6.87 -
    6.88 -    /* update access */
    6.89 -    r_dev->bases[i].e_physbase = addr;
    6.90 -    r_dev->bases[i].e_size= size;
    6.91 -
    6.92 -    if ( size == 0 )
    6.93 -    {
    6.94 -        fprintf(logfile, "pt_ioport_map failed: size = 0!\n");
    6.95 -        return;
    6.96 -    }
    6.97 -
    6.98 -    if ( !first_map )
    6.99 -    {
   6.100 -        /* Remove old mapping */
   6.101 -        ret = xc_domain_ioport_mapping(xc_handle,
   6.102 -                                       domid,
   6.103 -                                       old_ebase,
   6.104 -                                       r_dev->bases[i].access.ioport_base,
   6.105 -                                       size,
   6.106 -                                       DPCI_REMOVE_MAPPING);
   6.107 -
   6.108 -        if ( 0 != ret ) 
   6.109 -        {
   6.110 -            fprintf(logfile, "pt_ioport_map: remove old mapping failed!\n");
   6.111 -            return;
   6.112 -        }
   6.113 -    }
   6.114 -                                   
   6.115 -    /* Add new mapping */
   6.116 -    ret = xc_domain_ioport_mapping(xc_handle,
   6.117 -                                   domid,
   6.118 -                                   addr,
   6.119 -                                   r_dev->bases[i].access.ioport_base,
   6.120 -                                   size,
   6.121 -                                   DPCI_ADD_MAPPING);
   6.122 -                                   
   6.123 -    if ( 0 != ret )
   6.124 -        fprintf(logfile, "pt_ioport_map: create new mapping failed!\n");    
   6.125 -
   6.126 -}
   6.127 -
   6.128 -static void update_rom_enable_bit(  uint8_t b, uint8_t d, uint8_t f, 
   6.129 -                                    uint32_t rom_address, uint32_t new_val)
   6.130 -{
   6.131 -    uint32_t bar_data = 0;
   6.132 -
   6.133 -    bar_data = pci_read_long(b, d, f, rom_address);
   6.134 -    bar_data &= ~1UL;
   6.135 -    bar_data |= (new_val & 1);
   6.136 -    pci_write_long(b, d, f, rom_address, bar_data);
   6.137 -}
   6.138 -
   6.139 -static void pt_pci_write_config(PCIDevice * d, uint32_t address, uint32_t val, 
   6.140 -                                int len)
   6.141 -{
   6.142 -    pt_dev_t * r_dev = (pt_dev_t *)d;
   6.143 -
   6.144 -#ifdef PT_DEBUG_PCI_CONFIG    
   6.145 -    fprintf(logfile, "pt_pci_write_config (%x.%x): address=%04x val=0x%08x len=%d\n",
   6.146 -       ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), (uint16_t) address, val, len);
   6.147 -#endif 
   6.148 -
   6.149 -    /* Pre-write hooking */
   6.150 -    switch (address) {
   6.151 -    case 0x30:                  /* ROM base */
   6.152 -        update_rom_enable_bit(r_dev->b, r_dev->d, r_dev->f, address, val);
   6.153 -    case 0x34:                  /* Capabilities pointer */
   6.154 -    case 0x3C:                  /* Interrupt Line */
   6.155 -    case 0x10 ... 0x27:          /* BARs */
   6.156 -        pci_default_write_config(d, address, val, len);
   6.157 -        return;
   6.158 -    }
   6.159 -
   6.160 -    /* PCI config pass-through */
   6.161 -    switch (len){
   6.162 -    case 1:
   6.163 -        pci_write_byte(r_dev->b, r_dev->d, r_dev->f, address, val);						
   6.164 -        break;
   6.165 -    case 2:
   6.166 -        pci_write_word(r_dev->b, r_dev->d, r_dev->f, address, val);					
   6.167 -        break;
   6.168 -    case 4:	
   6.169 -        pci_write_long(r_dev->b, r_dev->d, r_dev->f, address, val);						
   6.170 -        break;
   6.171 -    }
   6.172 -
   6.173 -    /* Post-write hooking */
   6.174 -    switch (address) {
   6.175 -    case 0x04:                  /* CMD register (enable IO access trap) */
   6.176 -        pci_default_write_config(d, address, val, len);
   6.177 -        break;  
   6.178 -    }
   6.179 -    
   6.180 -}
   6.181 -
   6.182 -static uint32_t pt_pci_read_config(PCIDevice * d, uint32_t address, int len)
   6.183 -{
   6.184 -
   6.185 -    pt_dev_t * r_dev = (pt_dev_t *)d;
   6.186 -    uint32_t val=0;                               
   6.187 -
   6.188 -    /* Pre-hooking */
   6.189 -    switch (address) {
   6.190 -    case 0x10 ... 0x27:          /* BARs */
   6.191 -    case 0x30:                  /* ROM base */
   6.192 -    case 0x34:                  /* Capabilities pointer */
   6.193 -    case 0x3C:                  /* Interrupt Line */    
   6.194 -        val = pci_default_read_config(d, address, len);
   6.195 -        goto exit;
   6.196 -    }
   6.197 -    
   6.198 -    switch (len) {
   6.199 -    case 1:
   6.200 -        val = pci_read_byte(r_dev->b, r_dev->d, r_dev->f, address);
   6.201 -        break;
   6.202 -    case 2:
   6.203 -        val = pci_read_word(r_dev->b, r_dev->d, r_dev->f, address);
   6.204 -        break;
   6.205 -    case 4:
   6.206 -        val = pci_read_long(r_dev->b, r_dev->d, r_dev->f, address);
   6.207 -        break;
   6.208 -    }
   6.209 -
   6.210 -exit:
   6.211 -       
   6.212 -#ifdef PCI_KILL_NEW_CAPABILITIES
   6.213 -    /* kill the special capabilities */
   6.214 -    if ((address ==0x4) && (len == 4)) {
   6.215 -        val &= ~0x100000;
   6.216 -    } else if (address ==0x6) {
   6.217 -        val &= ~0x10;
   6.218 -    }
   6.219 -#endif
   6.220 -
   6.221 -#ifdef PT_DEBUG_PCI_CONFIG
   6.222 -    fprintf(logfile, "pt_pci_read_config  (%x.%x): address=%04x val=0x%08x len=%d\n",
   6.223 -       (d->devfn >> 3) & 0x1F, (d->devfn & 0x7), address, val, len);
   6.224 -#endif
   6.225 -
   6.226 -    return (val);
   6.227 -}
   6.228 -
   6.229 -int pt_register_region_hypervisor(pci_phys_dev_t * phys_dev, pt_dev_t * pci_dev, int i)
   6.230 -{
   6.231 -    pci_region_t * r;
   6.232 -
   6.233 -    if ( i >= PCI_NUM_REGIONS)
   6.234 -        return -1;
   6.235 -
   6.236 -    /* PCI ROM Region */
   6.237 -    if ( i == PCI_ROM_SLOT ) 
   6.238 -    {
   6.239 -        /* Check if ROM found */
   6.240 -        if ( (phys_dev->rom_size == 0) || (phys_dev->rom_base_addr == 0) )
   6.241 -            return -1;
   6.242 -            
   6.243 -        pci_dev->bases[PCI_ROM_SLOT].e_physbase = phys_dev->rom_base_addr;
   6.244 -        pci_dev->bases[PCI_ROM_SLOT].access.machine_address = phys_dev->rom_base_addr;
   6.245 -        
   6.246 -        pci_register_io_region((PCIDevice *)pci_dev, PCI_ROM_SLOT, phys_dev->rom_size, 
   6.247 -                       PCI_ADDRESS_SPACE_MEM_PREFETCH, pt_iomem_map);
   6.248 -
   6.249 -        fprintf(logfile,"pt_register_region_hypervisor: Expansion ROM registered (size=0x%08x base_addr=0x%016x)\n",
   6.250 -            (uint32_t)(phys_dev->rom_size), (uint64_t)(phys_dev->rom_base_addr));
   6.251 -    }
   6.252 -    else /* Regular PIO/MMIO Region */
   6.253 -    {
   6.254 -        r = &phys_dev->regions[i];
   6.255 -
   6.256 -        if ( !IS_VALID_REGION(r) )
   6.257 -            return -1;
   6.258 -
   6.259 -        if ( (r->type == PT_PCI_ADDRESS_SPACE_MEM) ||
   6.260 -             (r->type == PT_PCI_ADDRESS_SPACE_MEM_PREFETCH) )
   6.261 -        {
   6.262 -            pci_dev->bases[i].e_physbase = r->base_addr;
   6.263 -            pci_dev->bases[i].access.machine_address = r->base_addr;
   6.264 -            pci_register_io_region((PCIDevice *) pci_dev, i, r->size, r->type, pt_iomem_map);
   6.265 -        }
   6.266 -        else if ( r->type == PT_PCI_ADDRESS_SPACE_IO )
   6.267 -        {
   6.268 -            pci_dev->bases[i].e_physbase = r->base_addr;
   6.269 -            pci_dev->bases[i].access.ioport_base = r->base_addr;
   6.270 -            pci_dev->bases[i].memory_index = 0; // not relevant for port io
   6.271 -            pci_register_io_region((PCIDevice *) pci_dev, i, r->size,  r->type, pt_ioport_map);
   6.272 -        }
   6.273 -
   6.274 -        fprintf(logfile,"pt_register_region: IO region registered (size=0x%08x type=%-34s index=%d base_addr=0x%016x)\n",
   6.275 -            (uint32_t)(r->size), PT_GET_TYPE_STR(r->type), i, (uint64_t)(r->base_addr));
   6.276 -    }
   6.277 -
   6.278 -    return 0;
   6.279 -}
   6.280 -
   6.281 -
   6.282 -int pt_register_regions(pci_phys_dev_t * real_device, pt_dev_t * pci_dev)
   6.283 -{
   6.284 -    int i=0;
   6.285 -       
   6.286 -    for (i=0; i < real_device->region_number; i++)
   6.287 -        pt_register_region(real_device, pci_dev, i);
   6.288 -
   6.289 -    /* Register Expansion ROM */    
   6.290 -    if ( (real_device->rom_size != 0) && (real_device->rom_base_addr != 0) )
   6.291 -        pt_register_region(real_device, pci_dev, PCI_ROM_SLOT);
   6.292 -
   6.293 -    return 0;
   6.294 -}
   6.295 -
   6.296 -pt_dev_t * register_real_device(PCIBus * e_bus, const char * e_dev_name, int e_devfn, 
   6.297 -                                            uint8_t r_bus, uint8_t r_dev, uint8_t r_func, uint32_t machine_irq,
   6.298 -                                            uint8_t * config, uint32_t config_len)
   6.299 -{
   6.300 -    pt_dev_t * pci_dev = NULL;
   6.301 -    pci_phys_dev_t * real_device = NULL;
   6.302 -    uint8_t e_device, e_intx;
   6.303 -    struct pci_config_cf8 machine_bdf;
   6.304 -    int rc;
   6.305 -
   6.306 -    fprintf(logfile,"Registering real physical device %s (devfn=0x%x)...\n", e_dev_name, e_devfn);
   6.307 -    
   6.308 -    real_device = pt_devfn_probe(r_bus, r_dev, r_func, PT_PCI_SCAN_FORCE_AUTO);
   6.309 -    if ( NULL == real_device ) 
   6.310 -    {
   6.311 -        fprintf(logfile,"Error: Couldn't lookup real device (%s) in tree!\n", e_dev_name);
   6.312 -        return NULL;	
   6.313 -    }
   6.314 -
   6.315 -    pt_print_device(logfile, real_device);
   6.316 -
   6.317 -    pci_dev = (pt_dev_t *) pci_register_device(e_bus, e_dev_name, sizeof(pt_dev_t),
   6.318 -                        e_devfn, pt_pci_read_config, pt_pci_write_config);
   6.319 -    
   6.320 -    if ( NULL == pci_dev )
   6.321 -    {
   6.322 -        fprintf(logfile,"Error: Couldn't register real device %s\n", e_dev_name);
   6.323 -        return NULL;
   6.324 -    }
   6.325 -
   6.326 -    /* issue PCIe FLR */
   6.327 -    pdev_flr(pci_dev);    
   6.328 -
   6.329 -    pci_dev->b = r_bus;
   6.330 -    pci_dev->d = r_dev;
   6.331 -    pci_dev->f = r_func;
   6.332 -    
   6.333 -    /* tell XEN vmm to change iommu settings */
   6.334 -    machine_bdf.reg = 0;
   6.335 -    machine_bdf.bus = pci_dev->b;
   6.336 -    machine_bdf.dev = pci_dev->d;
   6.337 -    machine_bdf.func = pci_dev->f;
   6.338 -    rc = xc_assign_device(xc_handle, domid, machine_bdf.value);
   6.339 -    if ( rc < 0 )
   6.340 -        fprintf(logfile, "Error: xc_domain_assign_device error %d\n", rc);
   6.341 -
   6.342 -    /* handle real device's MMIO/PIO BARs */
   6.343 -    rc = pt_register_regions(real_device, pci_dev);
   6.344 -    if ( rc != 0 )
   6.345 -        return NULL;
   6.346 -
   6.347 -    /* Initialize PCI configuration */
   6.348 -    if ( NULL != config ) 
   6.349 -    {
   6.350 -        memset(pci_dev->dev.config, 0, PCI_CONFIG_SIZE);
   6.351 -        memcpy(pci_dev->dev.config, config, config_len);
   6.352 -    }
   6.353 -    else 
   6.354 -        pci_read_data(r_bus, r_dev, r_func, pci_dev->dev.config, 0, PCI_CONFIG_SIZE);
   6.355 -    
   6.356 -    /* Handle interrupt */
   6.357 -    e_device = (pci_dev->dev.devfn >> 3) & 0x1f;
   6.358 -    e_intx = pci_dev->dev.config[0x3d]-1;
   6.359 -
   6.360 -    if ( PT_MACHINE_IRQ_AUTO == machine_irq )
   6.361 -        machine_irq = real_device->irq;
   6.362 -
   6.363 -    /* bind machine_irq to device */
   6.364 -    if ( 0 != machine_irq ) 
   6.365 -    {
   6.366 -        rc = xc_domain_bind_pt_pci_irq(xc_handle, (uint32_t) domid, machine_irq, 0, e_device, e_intx);
   6.367 -        if ( rc < 0 )
   6.368 -        {
   6.369 -            /* TBD: unregister device in case of an error */
   6.370 -            fprintf(logfile,"register_real_device: Binding of interrupt failed! rc=%d\n", rc);
   6.371 -        }
   6.372 -    } 
   6.373 -    else {
   6.374 -        /* Disable PCI intx assertion (turn on bit10 of devctl) */
   6.375 -        pci_dev->dev.config[0x05] |= 0x04;
   6.376 -        pci_write_word(r_bus, r_dev, r_func, 
   6.377 -                       0x04, *(uint16_t *)(&pci_dev->dev.config[0x04]));
   6.378 -    }
   6.379 -
   6.380 -    fprintf(logfile,"Real physical device (%02x:%02x.%x) \"%s\" registered successfuly!\n", 
   6.381 -        r_bus, r_dev, r_func, e_dev_name);
   6.382 -
   6.383 -    return pci_dev;
   6.384 -}
   6.385 -
   6.386 -int pt_init(PCIBus * e_bus, char *direct_pci)
   6.387 -{
   6.388 -    int rc, i;
   6.389 -    int seg, b, d, f;
   6.390 -    pt_libpci_rc_t res;
   6.391 -    pt_dev_t * pt_dev;
   6.392 -
   6.393 -    res = pt_libpci_init(logfile);
   6.394 -    if ( res != PT_RC_SUCCESS ) 
   6.395 -    {
   6.396 -        fprintf(logfile,"pt_init: pt_libpci_init failed!\n");			
   6.397 -        return -1;
   6.398 -    }
   6.399 -    
   6.400 -    if ( pt_init_mmio_access() < 0 )
   6.401 -        return -1;
   6.402 -
   6.403 -    for (i=0; i < pci_devs(direct_pci); i++)
   6.404 -    {
   6.405 -        /* Get next dpci device bdf (bus, device, function) */
   6.406 -        next_bdf(direct_pci, &seg, &b, &d, &f);
   6.407 -
   6.408 -        /* Register real device on emulated bus */
   6.409 -        pt_dev = register_real_device(e_bus, "Passthru", PT_VIRT_DEVFN_AUTO,
   6.410 -            b, d, f, PT_MACHINE_IRQ_AUTO, NULL, 0);
   6.411 -
   6.412 -        if ( NULL == pt_dev ) 
   6.413 -        {
   6.414 -            fprintf(logfile,"pt_init: Registration failed (%02x:%02x.%x)\n", b, d, f);
   6.415 -            return -1;
   6.416 -        }
   6.417 -    }
   6.418 -    
   6.419 -    /* Success */
   6.420 -    return 0;
   6.421 -}
     7.1 --- a/tools/ioemu/hw/passthrough/pass-through.h	Thu Aug 23 13:42:03 2007 -0700
     7.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.3 @@ -1,146 +0,0 @@
     7.4 -/*
     7.5 - * Copyright (c) 2007, Neocleus / Intel
     7.6 - *
     7.7 - * Alex Novik <alex@neocleus.com>
     7.8 - * Allen Kay <allen.m.kay@intel.com>
     7.9 - * Guy Zana <guy@neocleus.com>
    7.10 - *
    7.11 - */
    7.12 -#ifndef __PASSTHROUGH_H__
    7.13 -#define __PASSTHROUGH_H__
    7.14 -
    7.15 -#include <sys/mman.h>
    7.16 -
    7.17 -#include "vl.h"
    7.18 -#include "pt_libpci.h"
    7.19 -#include "pt_pci_probe.h"
    7.20 -#include "pt_pci_access.h"
    7.21 -#include "pt_pci_tree.h"
    7.22 -
    7.23 -/* Log acesss */
    7.24 -#define PT_LOG_ACCESS_PIO        (0)
    7.25 -#define PT_LOG_ACCESS_MMIO       (0)
    7.26 -
    7.27 -/* Some compilation flags */
    7.28 -// #define PT_DEBUG_PCI_CONFIG
    7.29 -// #define PCI_KILL_NEW_CAPABILITIES
    7.30 -
    7.31 -/* 
    7.32 -    PT_USE_DM_ACCESS Tells whether to access the hardware from dom0,
    7.33 -    or from the hypervisor using hypercalls.
    7.34 -
    7.35 -    Accessing MMIO regions from dom0 is done by mmaping the real 
    7.36 -    physical address
    7.37 -*/
    7.38 -//#define PT_USE_DM_ACCESS
    7.39 -
    7.40 -#define PT_MACHINE_IRQ_AUTO (0xFFFFFFFF)
    7.41 -#define PT_VIRT_DEVFN_AUTO  (-1)
    7.42 -
    7.43 -typedef struct pt_region_s {
    7.44 -    /* Virtual phys base & size */
    7.45 -    uint32_t e_physbase;
    7.46 -    uint32_t e_size;
    7.47 -    /* Index of region in qemu */
    7.48 -    uint32_t memory_index;
    7.49 -    /* Log access to this region? */
    7.50 -    uint8_t do_logging;
    7.51 -    /* Translation of the emulated address */
    7.52 -    union {
    7.53 -        uint32_t machine_address;
    7.54 -        uint32_t virtual_address;
    7.55 -        uint32_t ioport_base;
    7.56 -    } access;
    7.57 -} pt_region_t;
    7.58 -
    7.59 -/*
    7.60 -    This structure holds the context of the mapping functions 
    7.61 -    and data that is relevant for qemu device management
    7.62 -*/
    7.63 -typedef struct pt_dev_s {
    7.64 -    PCIDevice dev;
    7.65 -    uint8_t b, d, f;
    7.66 -    pt_region_t bases[PCI_NUM_REGIONS];
    7.67 -} pt_dev_t;
    7.68 -
    7.69 -/* Used for formatting PCI BDF into cf8 format */
    7.70 -struct pci_config_cf8 {
    7.71 -    union {
    7.72 -        unsigned int value;
    7.73 -        struct {
    7.74 -            unsigned int reserved1:2;
    7.75 -            unsigned int reg:6;
    7.76 -            unsigned int func:3;
    7.77 -            unsigned int dev:5;
    7.78 -            unsigned int bus:8;
    7.79 -            unsigned int reserved2:7;
    7.80 -            unsigned int enable:1;
    7.81 -        };
    7.82 -    };
    7.83 -};
    7.84 -
    7.85 -/* Argument parsing */
    7.86 -int pci_devs(const char *direct_pci);
    7.87 -int next_token(char *direct_pci);
    7.88 -void next_bdf(char *direct_pci, int *seg,
    7.89 -              int *bus, int *dev, int *func);
    7.90 -
    7.91 -/* MMIO/PIO access functions (through dom0) */
    7.92 -uint32_t pt_mmio_readb(void * opaque, target_phys_addr_t e_phys);
    7.93 -uint32_t pt_mmio_readw(void * opaque, target_phys_addr_t e_phys);
    7.94 -uint32_t pt_mmio_readl(void * opaque, target_phys_addr_t e_phys);
    7.95 -void pt_mmio_writeb(void * opaque, target_phys_addr_t e_phys, uint32_t value);
    7.96 -void pt_mmio_writew(void * opaque, target_phys_addr_t e_phys, uint32_t value);
    7.97 -void pt_mmio_writel(void * opaque, target_phys_addr_t e_phys, uint32_t value);
    7.98 -uint32_t pt_ioport_readb(void *opaque, uint32_t addr);
    7.99 -uint32_t pt_ioport_readw(void *opaque, uint32_t addr);
   7.100 -uint32_t pt_ioport_readl(void *opaque, uint32_t addr);
   7.101 -void  pt_ioport_writeb(void *opaque, uint32_t addr, uint32_t value);
   7.102 -void  pt_ioport_writew(void *opaque, uint32_t addr, uint32_t value);
   7.103 -void  pt_ioport_writel(void *opaque, uint32_t addr, uint32_t value);
   7.104 -
   7.105 -/* PIO/MMIO mapping functions (access resources through the hypervisor) */
   7.106 -void pt_ioport_map_hypervisor(PCIDevice *pci_dev, int i, 
   7.107 -                              uint32_t addr, uint32_t size, int type);
   7.108 -void pt_iomem_map_hypervisor(PCIDevice *d, int i,
   7.109 -                             uint32_t e_phys, uint32_t e_size, int type);
   7.110 -/* PIO/MMIO mapping functions (access resources through the device model) */
   7.111 -void pt_ioport_map_dm(PCIDevice *pci_dev, int i, 
   7.112 -                      uint32_t addr, uint32_t size, int type);
   7.113 -void pt_iomem_map_dm(PCIDevice *d, int i,
   7.114 -                     uint32_t e_phys, uint32_t e_size, int type);
   7.115 -
   7.116 -/* Legacy registration functions */
   7.117 -int register_pt_legacy_pio_region_hypervisor(uint32_t pio_start, uint32_t length, uint8_t do_logging);
   7.118 -int register_pt_legacy_mmio_region_hypervisor(uint32_t mmio_addr, uint32_t length, uint8_t do_logging);
   7.119 -int register_pt_legacy_pio_region_dm(uint32_t pio_start, uint32_t length, uint8_t do_logging);
   7.120 -int register_pt_legacy_mmio_region_dm(uint32_t mmio_addr, uint32_t length, uint8_t do_logging);
   7.121 -int pt_init_mmio_access_dm(void);
   7.122 -
   7.123 -/* Pass-through PCI device registration on the e_bus */
   7.124 -int pt_register_region_hypervisor(pci_phys_dev_t * phys_dev, pt_dev_t * pci_dev, int i);
   7.125 -int pt_register_region_dm(pci_phys_dev_t * phys_dev, pt_dev_t * pci_dev, int i);
   7.126 -pt_dev_t * register_real_device(PCIBus * e_bus, const char * e_dev_name, int e_devfn, 
   7.127 -                                            uint8_t r_bus, uint8_t r_dev, uint8_t r_func, uint32_t machine_irq,
   7.128 -                                            uint8_t * config, uint32_t config_len);
   7.129 -
   7.130 -#if defined ( PT_USE_DM_ACCESS )
   7.131 -#define pt_init_mmio_access pt_init_mmio_access_dm
   7.132 -#define pt_ioport_map pt_ioport_map_dm
   7.133 -#define pt_iomem_map pt_iomem_map_dm
   7.134 -#define pt_register_region pt_register_region_dm
   7.135 -#define register_pt_legacy_pio_region register_pt_legacy_pio_region_dm
   7.136 -#define register_pt_legacy_mmio_region register_pt_legacy_mmio_region_dm
   7.137 -#else
   7.138 -#define pt_init_mmio_access(args...) (0)
   7.139 -#define pt_ioport_map pt_ioport_map_hypervisor
   7.140 -#define pt_iomem_map pt_iomem_map_hypervisor
   7.141 -#define pt_register_region pt_register_region_hypervisor
   7.142 -#define register_pt_legacy_pio_region register_pt_legacy_pio_region_hypervisor
   7.143 -#define register_pt_legacy_mmio_region register_pt_legacy_mmio_region_hypervisor
   7.144 -#endif
   7.145 -
   7.146 -int pt_init(PCIBus * e_bus, char * direct_pci);
   7.147 -
   7.148 -#endif /* __PASSTHROUGH_H__ */
   7.149 -
     8.1 --- a/tools/ioemu/hw/pc.c	Thu Aug 23 13:42:03 2007 -0700
     8.2 +++ b/tools/ioemu/hw/pc.c	Wed Aug 29 00:48:01 2007 +0300
     8.3 @@ -465,7 +465,7 @@ static void pc_init1(uint64_t ram_size, 
     8.4                       DisplayState *ds, const char **fd_filename, int snapshot,
     8.5                       const char *kernel_filename, const char *kernel_cmdline,
     8.6                       const char *initrd_filename,
     8.7 -                     int pci_enabled, const char *direct_pci)
     8.8 +                     int pci_enabled)
     8.9  {
    8.10  #ifndef NOBIOS
    8.11      char buf[1024];
    8.12 @@ -480,7 +480,6 @@ static void pc_init1(uint64_t ram_size, 
    8.13      int piix3_devfn = -1;
    8.14      CPUState *env;
    8.15      NICInfo *nd;
    8.16 -    int rc;
    8.17  
    8.18      linux_boot = (kernel_filename != NULL);
    8.19  
    8.20 @@ -666,17 +665,6 @@ static void pc_init1(uint64_t ram_size, 
    8.21          }
    8.22      }
    8.23  
    8.24 -    /* Pass-through Initialization */
    8.25 -    if ( pci_enabled && direct_pci )
    8.26 -    {
    8.27 -        rc = pt_init(pci_bus, direct_pci); 
    8.28 -        if ( rc < 0 )
    8.29 -        {
    8.30 -            fprintf(logfile, "Error: Initialization failed for pass-through devices\n");
    8.31 -            exit(1);
    8.32 -        }
    8.33 -    }
    8.34 -
    8.35      rtc_state = rtc_init(0x70, 8);
    8.36  
    8.37      register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
    8.38 @@ -813,14 +801,12 @@ static void pc_init_pci(uint64_t ram_siz
    8.39                          int snapshot, 
    8.40                          const char *kernel_filename, 
    8.41                          const char *kernel_cmdline,
    8.42 -                        const char *initrd_filename,
    8.43 -                        const char *direct_pci)
    8.44 +                        const char *initrd_filename)
    8.45  {
    8.46      pc_init1(ram_size, vga_ram_size, boot_device,
    8.47               ds, fd_filename, snapshot,
    8.48               kernel_filename, kernel_cmdline,
    8.49 -             initrd_filename, 1,
    8.50 -             direct_pci);
    8.51 +             initrd_filename, 1);
    8.52  }
    8.53  
    8.54  static void pc_init_isa(uint64_t ram_size, int vga_ram_size, char *boot_device,
    8.55 @@ -828,13 +814,12 @@ static void pc_init_isa(uint64_t ram_siz
    8.56                          int snapshot, 
    8.57                          const char *kernel_filename, 
    8.58                          const char *kernel_cmdline,
    8.59 -                        const char *initrd_filename,
    8.60 -                        const char *unused)
    8.61 +                        const char *initrd_filename)
    8.62  {
    8.63      pc_init1(ram_size, vga_ram_size, boot_device,
    8.64               ds, fd_filename, snapshot,
    8.65               kernel_filename, kernel_cmdline,
    8.66 -             initrd_filename, 0, NULL);
    8.67 +             initrd_filename, 0);
    8.68  }
    8.69  
    8.70  QEMUMachine pc_machine = {
     9.1 --- a/tools/ioemu/pt-libpci/Makefile	Thu Aug 23 13:42:03 2007 -0700
     9.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     9.3 @@ -1,32 +0,0 @@
     9.4 -# source files.
     9.5 -SRC = pt_libpci.c pt_pci_access.c pt_pci_probe.c pt_pci_tree.c pt_util.c access.c sysfs.c
     9.6 -VPATH += lib2.2.6/
     9.7 -
     9.8 -OBJ = $(SRC:.c=.o)
     9.9 -
    9.10 -OUT = pt_libpci.a
    9.11 -
    9.12 -# include directories
    9.13 -INCLUDES = -I.
    9.14 -
    9.15 -#defines
    9.16 -DEFINES = -DPT_LIBPCI
    9.17 -
    9.18 -# C compiler flags 
    9.19 -CCFLAGS = -O2 
    9.20 -
    9.21 -# compiler
    9.22 -CCC = gcc
    9.23 -
    9.24 -$(OUT): $(OBJ)
    9.25 -	ar rcs $(OUT) $(OBJ)
    9.26 -	ranlib $@
    9.27 -
    9.28 -%.o : %.c
    9.29 -	$(CCC) $(CCFLAGS) $(INCLUDES) $(DEFINES) -c $< -o $@
    9.30 -
    9.31 -lspci: $(OUT)
    9.32 -	$(CCC) $(INCLUDES) $(CCFLAGS) $(DEFINES) lspci.c pt_libpci.a -o lspci
    9.33 -
    9.34 -.PHONY clean:
    9.35 -	rm -f $(OBJ) $(OUT) lspci
    10.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/.gitignore	Thu Aug 23 13:42:03 2007 -0700
    10.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    10.3 @@ -1,3 +0,0 @@
    10.4 -config.h
    10.5 -config.mk
    10.6 -libpci.pc
    11.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/Makefile	Thu Aug 23 13:42:03 2007 -0700
    11.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.3 @@ -1,85 +0,0 @@
    11.4 -# Makefile for The PCI Library
    11.5 -# (c) 1999 Martin Mares <mj@ucw.cz>
    11.6 -
    11.7 -include config.mk
    11.8 -
    11.9 -OBJS=access.o generic.o dump.o names.o filter.o
   11.10 -INCL=internal.h pci.h config.h header.h sysdep.h types.h
   11.11 -
   11.12 -PCILIB=libpci.a
   11.13 -PCILIBPC=libpci.pc
   11.14 -
   11.15 -ifdef PCI_HAVE_PM_LINUX_SYSFS
   11.16 -OBJS += sysfs.o
   11.17 -endif
   11.18 -
   11.19 -ifdef PCI_HAVE_PM_LINUX_PROC
   11.20 -OBJS += proc.o
   11.21 -endif
   11.22 -
   11.23 -ifdef PCI_HAVE_PM_INTEL_CONF
   11.24 -OBJS += i386-ports.o
   11.25 -endif
   11.26 -
   11.27 -ifdef PCI_HAVE_PM_DUMP
   11.28 -OBJS += dump.o
   11.29 -endif
   11.30 -
   11.31 -ifdef PCI_HAVE_PM_SYSCALLS
   11.32 -OBJS += syscalls.o
   11.33 -endif
   11.34 -
   11.35 -ifdef PCI_HAVE_PM_FBSD_DEVICE
   11.36 -OBJS += fbsd-device.o
   11.37 -CFLAGS += -I/usr/src/sys
   11.38 -ifdef FREEBSD_SYS
   11.39 -CFLAGS += -I${FREEBSD_SYS}
   11.40 -endif
   11.41 -endif
   11.42 -
   11.43 -ifdef PCI_HAVE_PM_OBSD_DEVICE
   11.44 -OBJS += obsd-device.o
   11.45 -endif
   11.46 -
   11.47 -ifdef PCI_HAVE_PM_AIX_DEVICE
   11.48 -OBJS += aix-device.o
   11.49 -endif
   11.50 -
   11.51 -ifdef PCI_HAVE_PM_NBSD_LIBPCI
   11.52 -OBJS += nbsd-libpci.o
   11.53 -PCILIB=libpciutils.a
   11.54 -endif
   11.55 -
   11.56 -all: $(PCILIB) $(PCILIBPC)
   11.57 -
   11.58 -$(PCILIB): $(OBJS)
   11.59 -	rm -f $@
   11.60 -	ar rcs $@ $^
   11.61 -	ranlib $@
   11.62 -
   11.63 -$(PCILIBPC): $(PCILIBPC).in
   11.64 -	sed <$< >$@ -e 's,@PREFIX@,$(PREFIX),' \
   11.65 -		-e 's,@INCDIR@,$(INCDIR),' \
   11.66 -		-e 's,@LIBDIR@,$(LIBDIR),' \
   11.67 -		-e 's,@IDSDIR@,$(IDSDIR),' \
   11.68 -		-e 's,@VERSION@,$(VERSION),' \
   11.69 -		-e 's,@LIBZ@,$(LIBZ),'
   11.70 -
   11.71 -access.o: access.c $(INCL)
   11.72 -i386-ports.o: i386-ports.c $(INCL) i386-io-hurd.h i386-io-linux.h i386-io-sunos.h
   11.73 -proc.o: proc.c $(INCL) pread.h
   11.74 -sysfs.o: sysfs.c $(INCL) pread.h
   11.75 -generic.o: generic.c $(INCL)
   11.76 -syscalls.o: syscalls.c $(INCL)
   11.77 -obsd-device.o: obsd-device.c $(INCL)
   11.78 -fbsd-device.o: fbsd-device.c $(INCL)
   11.79 -aix-device.o: aix-device.c $(INCL)
   11.80 -dump.o: dump.c $(INCL)
   11.81 -names.o: names.c $(INCL)
   11.82 -filter.o: filter.c $(INCL)
   11.83 -nbsd-libpci.o: nbsd-libpci.c $(INCL)
   11.84 -
   11.85 -example: example.c $(PCILIB)
   11.86 -
   11.87 -clean:
   11.88 -	rm -f $(PCILIB) $(PCILIBPC) $(OBJS) example config.h config.mk
    12.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/access.c	Thu Aug 23 13:42:03 2007 -0700
    12.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    12.3 @@ -1,345 +0,0 @@
    12.4 -/*
    12.5 - *	The PCI Library -- User Access
    12.6 - *
    12.7 - *	Copyright (c) 1997--2003 Martin Mares <mj@ucw.cz>
    12.8 - *
    12.9 - *	Can be freely distributed and used under the terms of the GNU GPL.
   12.10 - */
   12.11 -
   12.12 -#include <stdio.h>
   12.13 -#include <stdlib.h>
   12.14 -#include <stdarg.h>
   12.15 -#include <string.h>
   12.16 -
   12.17 -#include "internal.h"
   12.18 -
   12.19 -static struct pci_methods *pci_methods[PCI_ACCESS_MAX] = {
   12.20 -  NULL,
   12.21 -#ifdef PCI_HAVE_PM_LINUX_SYSFS
   12.22 -  &pm_linux_sysfs,
   12.23 -#else
   12.24 -  NULL,
   12.25 -#endif
   12.26 -#ifdef PCI_HAVE_PM_LINUX_PROC
   12.27 -  &pm_linux_proc,
   12.28 -#else
   12.29 -  NULL,
   12.30 -#endif
   12.31 -#ifdef PCI_HAVE_PM_INTEL_CONF
   12.32 -  &pm_intel_conf1,
   12.33 -  &pm_intel_conf2,
   12.34 -#else
   12.35 -  NULL,
   12.36 -  NULL,
   12.37 -#endif
   12.38 -#ifdef PCI_HAVE_PM_FBSD_DEVICE
   12.39 -  &pm_fbsd_device,
   12.40 -#else
   12.41 -  NULL,
   12.42 -#endif
   12.43 -#ifdef PCI_HAVE_PM_AIX_DEVICE
   12.44 -  &pm_aix_device,
   12.45 -#else
   12.46 -  NULL,
   12.47 -#endif
   12.48 -#ifdef PCI_HAVE_PM_NBSD_LIBPCI
   12.49 -  &pm_nbsd_libpci,
   12.50 -#else
   12.51 -  NULL,
   12.52 -#endif
   12.53 -#ifdef PCI_HAVE_PM_OBSD_DEVICE
   12.54 -  &pm_obsd_device,
   12.55 -#else
   12.56 -  NULL,
   12.57 -#endif
   12.58 -#ifdef PCI_HAVE_PM_DUMP
   12.59 -  &pm_dump,
   12.60 -#else
   12.61 -  NULL,
   12.62 -#endif
   12.63 -};
   12.64 -
   12.65 -struct pci_access *
   12.66 -pci_alloc(void)
   12.67 -{
   12.68 -  struct pci_access *a = malloc(sizeof(struct pci_access));
   12.69 -  int i;
   12.70 -
   12.71 -  memset(a, 0, sizeof(*a));
   12.72 -#ifndef PT_LIBPCI  
   12.73 -  pci_set_name_list_path(a, PCI_PATH_IDS_DIR "/" PCI_IDS, 0);
   12.74 -  for(i=0; i<PCI_ACCESS_MAX; i++)
   12.75 -    if (pci_methods[i] && pci_methods[i]->config)
   12.76 -      pci_methods[i]->config(a);
   12.77 -#endif
   12.78 -
   12.79 -  return a;
   12.80 -}
   12.81 -
   12.82 -void *
   12.83 -pci_malloc(struct pci_access *a, int size)
   12.84 -{
   12.85 -  void *x = malloc(size);
   12.86 -
   12.87 -  if (!x)
   12.88 -    a->error("Out of memory (allocation of %d bytes failed)", size);
   12.89 -  return x;
   12.90 -}
   12.91 -
   12.92 -void
   12.93 -pci_mfree(void *x)
   12.94 -{
   12.95 -  if (x)
   12.96 -    free(x);
   12.97 -}
   12.98 -
   12.99 -static void
  12.100 -pci_generic_error(char *msg, ...)
  12.101 -{
  12.102 -  va_list args;
  12.103 -
  12.104 -  va_start(args, msg);
  12.105 -  fputs("pcilib: ", stderr);
  12.106 -  vfprintf(stderr, msg, args);
  12.107 -  fputc('\n', stderr);
  12.108 -  exit(1);
  12.109 -}
  12.110 -
  12.111 -static void
  12.112 -pci_generic_warn(char *msg, ...)
  12.113 -{
  12.114 -  va_list args;
  12.115 -
  12.116 -  va_start(args, msg);
  12.117 -  fputs("pcilib: ", stderr);
  12.118 -  vfprintf(stderr, msg, args);
  12.119 -  fputc('\n', stderr);
  12.120 -}
  12.121 -
  12.122 -static void
  12.123 -pci_generic_debug(char *msg, ...)
  12.124 -{
  12.125 -  va_list args;
  12.126 -
  12.127 -  va_start(args, msg);
  12.128 -  vfprintf(stdout, msg, args);
  12.129 -  va_end(args);
  12.130 -}
  12.131 -
  12.132 -static void
  12.133 -pci_null_debug(char *msg UNUSED, ...)
  12.134 -{
  12.135 -}
  12.136 -
  12.137 -void
  12.138 -pci_init(struct pci_access *a)
  12.139 -{
  12.140 -  if (!a->error)
  12.141 -    a->error = pci_generic_error;
  12.142 -  if (!a->warning)
  12.143 -    a->warning = pci_generic_warn;
  12.144 -  if (!a->debug)
  12.145 -    a->debug = pci_generic_debug;
  12.146 -  if (!a->debugging)
  12.147 -    a->debug = pci_null_debug;
  12.148 -
  12.149 -  if (a->method)
  12.150 -    {
  12.151 -      if (a->method >= PCI_ACCESS_MAX || !pci_methods[a->method])
  12.152 -	a->error("This access method is not supported.");
  12.153 -      a->methods = pci_methods[a->method];
  12.154 -    }
  12.155 -  else
  12.156 -    {
  12.157 -      unsigned int i;
  12.158 -      for(i=0; i<PCI_ACCESS_MAX; i++)
  12.159 -	if (pci_methods[i])
  12.160 -	  {
  12.161 -	    a->debug("Trying method %d...", i);
  12.162 -	    if (pci_methods[i]->detect(a))
  12.163 -	      {
  12.164 -		a->debug("...OK\n");
  12.165 -		a->methods = pci_methods[i];
  12.166 -		a->method = i;
  12.167 -		break;
  12.168 -	      }
  12.169 -	    a->debug("...No.\n");
  12.170 -	  }
  12.171 -      if (!a->methods)
  12.172 -	a->error("Cannot find any working access method.");
  12.173 -    }
  12.174 -  a->debug("Decided to use %s\n", a->methods->name);
  12.175 -  a->methods->init(a);
  12.176 -}
  12.177 -
  12.178 -void
  12.179 -pci_cleanup(struct pci_access *a)
  12.180 -{
  12.181 -  struct pci_dev *d, *e;
  12.182 -
  12.183 -  for(d=a->devices; d; d=e)
  12.184 -    {
  12.185 -      e = d->next;
  12.186 -      pci_free_dev(d);
  12.187 -    }
  12.188 -  if (a->methods)
  12.189 -    a->methods->cleanup(a);
  12.190 -#ifndef PT_LIBPCI
  12.191 -  pci_free_name_list(a);
  12.192 -  pci_set_name_list_path(a, NULL, 0);
  12.193 -#endif
  12.194 -  pci_mfree(a);
  12.195 -}
  12.196 -
  12.197 -void
  12.198 -pci_scan_bus(struct pci_access *a)
  12.199 -{
  12.200 -  a->methods->scan(a);
  12.201 -}
  12.202 -
  12.203 -struct pci_dev *
  12.204 -pci_alloc_dev(struct pci_access *a)
  12.205 -{
  12.206 -  struct pci_dev *d = pci_malloc(a, sizeof(struct pci_dev));
  12.207 -
  12.208 -  memset(d, 0, sizeof(*d));
  12.209 -  d->access = a;
  12.210 -  d->methods = a->methods;
  12.211 -  d->hdrtype = -1;
  12.212 -  if (d->methods->init_dev)
  12.213 -    d->methods->init_dev(d);
  12.214 -  return d;
  12.215 -}
  12.216 -
  12.217 -int
  12.218 -pci_link_dev(struct pci_access *a, struct pci_dev *d)
  12.219 -{
  12.220 -  d->next = a->devices;
  12.221 -  a->devices = d;
  12.222 -
  12.223 -  return 1;
  12.224 -}
  12.225 -
  12.226 -struct pci_dev *
  12.227 -pci_get_dev(struct pci_access *a, int domain, int bus, int dev, int func)
  12.228 -{
  12.229 -  struct pci_dev *d = pci_alloc_dev(a);
  12.230 -
  12.231 -  d->domain = domain;
  12.232 -  d->bus = bus;
  12.233 -  d->dev = dev;
  12.234 -  d->func = func;
  12.235 -  return d;
  12.236 -}
  12.237 -
  12.238 -void pci_free_dev(struct pci_dev *d)
  12.239 -{
  12.240 -  if (d->methods->cleanup_dev)
  12.241 -    d->methods->cleanup_dev(d);
  12.242 -  pci_mfree(d);
  12.243 -}
  12.244 -
  12.245 -#ifndef PT_LIBPCI
  12.246 -static inline void
  12.247 -pci_read_data(struct pci_dev *d, void *buf, int pos, int len)
  12.248 -{
  12.249 -  if (pos & (len-1))
  12.250 -    d->access->error("Unaligned read: pos=%02x, len=%d", pos, len);
  12.251 -  if (pos + len <= d->cache_len)
  12.252 -    memcpy(buf, d->cache + pos, len);
  12.253 -  else if (!d->methods->read(d, pos, buf, len))
  12.254 -    memset(buf, 0xff, len);
  12.255 -}
  12.256 -
  12.257 -byte
  12.258 -pci_read_byte(struct pci_dev *d, int pos)
  12.259 -{
  12.260 -  byte buf;
  12.261 -  pci_read_data(d, &buf, pos, 1);
  12.262 -  return buf;
  12.263 -}
  12.264 -
  12.265 -word
  12.266 -pci_read_word(struct pci_dev *d, int pos)
  12.267 -{
  12.268 -  word buf;
  12.269 -  pci_read_data(d, &buf, pos, 2);
  12.270 -  return le16_to_cpu(buf);
  12.271 -}
  12.272 -
  12.273 -u32
  12.274 -pci_read_long(struct pci_dev *d, int pos)
  12.275 -{
  12.276 -  u32 buf;
  12.277 -  pci_read_data(d, &buf, pos, 4);
  12.278 -  return le32_to_cpu(buf);
  12.279 -}
  12.280 -
  12.281 -int
  12.282 -pci_read_block(struct pci_dev *d, int pos, byte *buf, int len)
  12.283 -{
  12.284 -  return d->methods->read(d, pos, buf, len);
  12.285 -}
  12.286 -
  12.287 -static inline int
  12.288 -pci_write_data(struct pci_dev *d, void *buf, int pos, int len)
  12.289 -{
  12.290 -  if (pos & (len-1))
  12.291 -    d->access->error("Unaligned write: pos=%02x,len=%d", pos, len);
  12.292 -  if (pos + len <= d->cache_len)
  12.293 -    memcpy(d->cache + pos, buf, len);
  12.294 -  return d->methods->write(d, pos, buf, len);
  12.295 -}
  12.296 -
  12.297 -int
  12.298 -pci_write_byte(struct pci_dev *d, int pos, byte data)
  12.299 -{
  12.300 -  return pci_write_data(d, &data, pos, 1);
  12.301 -}
  12.302 -
  12.303 -int
  12.304 -pci_write_word(struct pci_dev *d, int pos, word data)
  12.305 -{
  12.306 -  word buf = cpu_to_le16(data);
  12.307 -  return pci_write_data(d, &buf, pos, 2);
  12.308 -}
  12.309 -
  12.310 -int
  12.311 -pci_write_long(struct pci_dev *d, int pos, u32 data)
  12.312 -{
  12.313 -  u32 buf = cpu_to_le32(data);
  12.314 -  return pci_write_data(d, &buf, pos, 4);
  12.315 -}
  12.316 -
  12.317 -int
  12.318 -pci_write_block(struct pci_dev *d, int pos, byte *buf, int len)
  12.319 -{
  12.320 -  if (pos < d->cache_len)
  12.321 -    {
  12.322 -      int l = (pos + len >= d->cache_len) ? (d->cache_len - pos) : len;
  12.323 -      memcpy(d->cache + pos, buf, l);
  12.324 -    }
  12.325 -  return d->methods->write(d, pos, buf, len);
  12.326 -}
  12.327 -
  12.328 -#endif /* !PT_LIBPCI */
  12.329 -
  12.330 -int
  12.331 -pci_fill_info(struct pci_dev *d, int flags)
  12.332 -{
  12.333 -  if (flags & PCI_FILL_RESCAN)
  12.334 -    {
  12.335 -      flags &= ~PCI_FILL_RESCAN;
  12.336 -      d->known_fields = 0;
  12.337 -    }
  12.338 -  if (flags & ~d->known_fields)
  12.339 -    d->known_fields |= d->methods->fill_info(d, flags & ~d->known_fields);
  12.340 -  return d->known_fields;
  12.341 -}
  12.342 -
  12.343 -void
  12.344 -pci_setup_cache(struct pci_dev *d, byte *cache, int len)
  12.345 -{
  12.346 -  d->cache = cache;
  12.347 -  d->cache_len = len;
  12.348 -}
    13.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/aix-device.c	Thu Aug 23 13:42:03 2007 -0700
    13.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    13.3 @@ -1,279 +0,0 @@
    13.4 -/*
    13.5 - *	The PCI Library -- AIX /dev/pci[0-n] access
    13.6 - *
    13.7 - *	Copyright (c) 1999 Jari Kirma <kirma@cs.hut.fi>
    13.8 - *
    13.9 - *	Can be freely distributed and used under the terms of the GNU GPL.
   13.10 - */
   13.11 -
   13.12 -/*
   13.13 - *      Read functionality of this driver is briefly tested, and seems
   13.14 - *      to supply basic information correctly, but I promise no more.
   13.15 - */
   13.16 -
   13.17 -#include <stdio.h>
   13.18 -#include <stdlib.h>
   13.19 -#include <string.h>
   13.20 -#include <unistd.h>
   13.21 -#include <fcntl.h>
   13.22 -
   13.23 -#include <sys/types.h>
   13.24 -#include <sys/mdio.h>
   13.25 -
   13.26 -#include "internal.h"
   13.27 -
   13.28 -#define AIX_LSDEV_CMD "/usr/sbin/lsdev -C -c bus -t pci\\* -S available -F name"
   13.29 -#define AIX_ODMGET_CMD \
   13.30 -  "/usr/bin/odmget -q 'name=%s and attribute=bus_number' CuAt | \
   13.31 -   /usr/bin/awk '$1 == \"value\" { print $3 }'"
   13.32 -
   13.33 -
   13.34 -/* AIX PCI bus device information */
   13.35 -
   13.36 -typedef struct aix_pci_bus {
   13.37 -    char *bus_name;
   13.38 -    int   bus_number;
   13.39 -    int   bus_fd;
   13.40 -} aix_pci_bus;
   13.41 -
   13.42 -#define PCI_BUS_MAX 16		/* arbitrary choice */
   13.43 -static aix_pci_bus pci_buses[PCI_BUS_MAX];
   13.44 -static int pci_bus_count = 0;
   13.45 -
   13.46 -
   13.47 -/* Utility Routines */
   13.48 -
   13.49 -static aix_pci_bus *
   13.50 -aix_find_bus(struct pci_access *a, int bus_number)
   13.51 -{
   13.52 -  int i;
   13.53 -
   13.54 -  for (i = 0; i < pci_bus_count; i++)
   13.55 -    {
   13.56 -      if (pci_buses[i].bus_number == bus_number)
   13.57 -        {
   13.58 -          return &pci_buses[i];
   13.59 -        }
   13.60 -    }
   13.61 -
   13.62 -  a->error("aix_find_bus: bus number %d not found", bus_number);
   13.63 -}
   13.64 -
   13.65 -static int
   13.66 -aix_bus_open(struct pci_access *a, int bus_number)
   13.67 -{
   13.68 -  aix_pci_bus *bp = aix_find_bus(a, bus_number);
   13.69 -
   13.70 -  if (bp->bus_fd < 0)
   13.71 -    {
   13.72 -      char devbuf[256];
   13.73 -      int mode = a->writeable ? O_RDWR : O_RDONLY;
   13.74 -
   13.75 -      snprintf(devbuf, sizeof (devbuf), "/dev/%s", bp->bus_name);
   13.76 -      bp->bus_fd = open(devbuf, mode, 0);
   13.77 -      if (bp->bus_fd < 0)
   13.78 -        {
   13.79 -          a->error("aix_open_bus: %s open failed", devbuf);
   13.80 -        }
   13.81 -    }
   13.82 -
   13.83 -  return bp->bus_fd;
   13.84 -}
   13.85 -
   13.86 -static int
   13.87 -aix_bus_number(char *name)
   13.88 -{
   13.89 -  int bus_number;
   13.90 -  FILE *odmget_pipe;
   13.91 -  char command[256];
   13.92 -  char buf[256];
   13.93 -  char *bp;
   13.94 -  char *ep;
   13.95 -
   13.96 -  snprintf(command, sizeof (command), AIX_ODMGET_CMD, name);
   13.97 -  odmget_pipe = popen(command, "r");
   13.98 -  if (odmget_pipe == NULL)
   13.99 -    {
  13.100 -      /* popen failed */
  13.101 -      return -1;
  13.102 -    }
  13.103 -
  13.104 -  if (fgets(buf, sizeof (buf) - 1, odmget_pipe) != NULL)
  13.105 -    {
  13.106 -      bp = buf + 1;	/* skip leading double quote */
  13.107 -      bus_number = strtol(bp, &ep, 0);
  13.108 -      if (bp == ep)
  13.109 -        {
  13.110 -          /* strtol failed */
  13.111 -          bus_number = -1;
  13.112 -        }
  13.113 -    }
  13.114 -  else
  13.115 -    {
  13.116 -      /* first PCI bus_number is not recorded in ODM CuAt; default to 0 */
  13.117 -      bus_number = 0;
  13.118 -    }
  13.119 -
  13.120 -  (void) pclose(odmget_pipe);
  13.121 -
  13.122 -  return bus_number;
  13.123 -}
  13.124 -
  13.125 -
  13.126 -/* Method entries */
  13.127 -
  13.128 -static void
  13.129 -aix_config(struct pci_access *a)
  13.130 -{
  13.131 -  a->method_params[PCI_ACCESS_AIX_DEVICE] = NULL;
  13.132 -}
  13.133 -
  13.134 -static int
  13.135 -aix_detect(struct pci_access *a)
  13.136 -{
  13.137 -  int len;
  13.138 -  int mode = a->writeable ? W_OK : R_OK;
  13.139 -  char *command = AIX_LSDEV_CMD;
  13.140 -  FILE *lsdev_pipe;
  13.141 -  char buf[256];
  13.142 -  char *name;
  13.143 -
  13.144 -  lsdev_pipe = popen(command, "r");
  13.145 -  if (lsdev_pipe == NULL)
  13.146 -    {
  13.147 -      a->error("aix_config: popen(\"%s\") failed", command);
  13.148 -    }
  13.149 -
  13.150 -  while (fgets(buf, sizeof (buf) - 1, lsdev_pipe) != NULL)
  13.151 -    {
  13.152 -      len = strlen(buf);
  13.153 -      while (buf[len-1] == '\n' || buf[len-1] == '\r')
  13.154 -          len--;
  13.155 -      buf[len] = '\0';				/* clobber the newline */
  13.156 -
  13.157 -      name = (char *) pci_malloc(a, len + 1);
  13.158 -      strcpy(name, buf);
  13.159 -      pci_buses[pci_bus_count].bus_name = name;
  13.160 -      pci_buses[pci_bus_count].bus_number = 0;
  13.161 -      pci_buses[pci_bus_count].bus_fd = -1;
  13.162 -      if (!pci_bus_count)
  13.163 -          a->debug("...using %s", name);
  13.164 -      else
  13.165 -          a->debug(", %s", name);
  13.166 -      pci_bus_count++;
  13.167 -      if (pci_bus_count >= PCI_BUS_MAX)
  13.168 -          break;
  13.169 -    }
  13.170 -
  13.171 -  (void) pclose(lsdev_pipe);
  13.172 -
  13.173 -  return pci_bus_count;
  13.174 -}
  13.175 -
  13.176 -static void
  13.177 -aix_init(struct pci_access *a)
  13.178 -{
  13.179 -  char *name;
  13.180 -  int i;
  13.181 -
  13.182 -  for (i = 0; i < pci_bus_count; i++)
  13.183 -    {
  13.184 -      name = pci_buses[i].bus_name;
  13.185 -      pci_buses[i].bus_number = aix_bus_number(name);
  13.186 -    }
  13.187 -}
  13.188 -
  13.189 -static void
  13.190 -aix_cleanup(struct pci_access *a)
  13.191 -{
  13.192 -  aix_pci_bus *bp;
  13.193 -
  13.194 -  while (pci_bus_count-- > 0)
  13.195 -    {
  13.196 -      bp = &pci_buses[pci_bus_count];
  13.197 -      (void) free(bp->bus_name);
  13.198 -      if (bp->bus_fd >= 0)
  13.199 -        {
  13.200 -          (void) close(bp->bus_fd);
  13.201 -          bp->bus_fd = -1;
  13.202 -        }
  13.203 -    }
  13.204 -}
  13.205 -
  13.206 -void
  13.207 -aix_scan(struct pci_access *a)
  13.208 -{
  13.209 -  int i;
  13.210 -  int bus_number;
  13.211 -  byte busmap[256];
  13.212 -
  13.213 -  memset(busmap, 0, sizeof(busmap));
  13.214 -  for (i = 0; i < pci_bus_count; i++)
  13.215 -    {
  13.216 -      bus_number = pci_buses[i].bus_number;
  13.217 -      if (!busmap[bus_number])
  13.218 -        {
  13.219 -          pci_generic_scan_bus(a, busmap, bus_number);
  13.220 -        }
  13.221 -    }
  13.222 -}
  13.223 -
  13.224 -static int
  13.225 -aix_read(struct pci_dev *d, int pos, byte *buf, int len)
  13.226 -{
  13.227 -  struct mdio mdio;
  13.228 -  int fd;
  13.229 -
  13.230 -  if (pos + len > 256)
  13.231 -    return 0;
  13.232 -
  13.233 -  fd = aix_bus_open(d->access, d->bus);
  13.234 -  mdio.md_addr = (ulong) pos;
  13.235 -  mdio.md_size = len;
  13.236 -  mdio.md_incr = MV_BYTE;
  13.237 -  mdio.md_data = (char *) buf;
  13.238 -  mdio.md_sla = PCI_DEVFN(d->dev, d->func);
  13.239 -
  13.240 -  if (ioctl(fd, MIOPCFGET, &mdio) < 0)
  13.241 -    d->access->error("aix_read: ioctl(MIOPCFGET) failed");
  13.242 -
  13.243 -  return 1;
  13.244 -}
  13.245 -
  13.246 -static int
  13.247 -aix_write(struct pci_dev *d, int pos, byte *buf, int len)
  13.248 -{
  13.249 -  struct mdio mdio;
  13.250 -  int fd;
  13.251 -
  13.252 -  if (pos + len > 256)
  13.253 -    return 0;
  13.254 -
  13.255 -  fd = aix_bus_open(d->access, d->bus);
  13.256 -  mdio.md_addr = (ulong) pos;
  13.257 -  mdio.md_size = len;
  13.258 -  mdio.md_incr = MV_BYTE;
  13.259 -  mdio.md_data = (char *) buf;
  13.260 -  mdio.md_sla = PCI_DEVFN(d->dev, d->func);
  13.261 -
  13.262 -  if (ioctl(fd, MIOPCFPUT, &mdio) < 0)
  13.263 -    {
  13.264 -      d->access->error("aix_write: ioctl(MIOPCFPUT) failed");
  13.265 -    }
  13.266 -
  13.267 -  return 1;
  13.268 -}
  13.269 -
  13.270 -struct pci_methods pm_aix_device = {
  13.271 -  "AIX-device",
  13.272 -  aix_config,
  13.273 -  aix_detect,
  13.274 -  aix_init,
  13.275 -  aix_cleanup,
  13.276 -  aix_scan,
  13.277 -  pci_generic_fill_info,
  13.278 -  aix_read,
  13.279 -  aix_write,
  13.280 -  NULL,                                 /* dev_init */
  13.281 -  NULL                                  /* dev_cleanup */
  13.282 -};
    14.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/config.h	Thu Aug 23 13:42:03 2007 -0700
    14.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    14.3 @@ -1,14 +0,0 @@
    14.4 -#define PCI_ARCH_I386
    14.5 -#define PCI_OS_LINUX
    14.6 -#define PCI_HAVE_PM_LINUX_SYSFS
    14.7 -//#define PCI_HAVE_PM_LINUX_PROC
    14.8 -#define PCI_HAVE_LINUX_BYTEORDER_H
    14.9 -//#define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci"
   14.10 -#define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci"
   14.11 -//#define PCI_HAVE_PM_INTEL_CONF
   14.12 -#define PCI_HAVE_64BIT_ADDRESS
   14.13 -//#define PCI_HAVE_PM_DUMP
   14.14 -#define PCI_COMPRESSED_IDS
   14.15 -#define PCI_IDS "pci.ids.gz"
   14.16 -#define PCI_PATH_IDS_DIR "/usr/share"
   14.17 -#define PCILIB_VERSION "0.0"
    15.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/config.mk	Thu Aug 23 13:42:03 2007 -0700
    15.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    15.3 @@ -1,16 +0,0 @@
    15.4 -LIBZ=-lz
    15.5 -LDFLAGS+=$(LIBZ)
    15.6 -PCI_ARCH_I386=1
    15.7 -PCI_OS_LINUX=1
    15.8 -PCI_HAVE_PM_LINUX_SYSFS=1
    15.9 -PCI_HAVE_PM_LINUX_PROC=1
   15.10 -PCI_HAVE_LINUX_BYTEORDER_H=1
   15.11 -PCI_PATH_PROC_BUS_PCI=/proc/bus/pci
   15.12 -PCI_PATH_SYS_BUS_PCI=/sys/bus/pci
   15.13 -PCI_HAVE_PM_INTEL_CONF=1
   15.14 -PCI_HAVE_64BIT_ADDRESS=1
   15.15 -PCI_HAVE_PM_DUMP=1
   15.16 -PCI_COMPRESSED_IDS=1
   15.17 -PCI_IDS=pci.ids.gz
   15.18 -PCI_PATH_IDS_DIR=/usr/share
   15.19 -PCILIB_VERSION=0.0
    16.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/configure	Thu Aug 23 13:42:03 2007 -0700
    16.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    16.3 @@ -1,132 +0,0 @@
    16.4 -#!/bin/sh
    16.5 -
    16.6 -echo_n() {
    16.7 -	if [ -n "$BASH" ]
    16.8 -	then
    16.9 -		echo -n "$*"
   16.10 -	else
   16.11 -		echo "$*\c"
   16.12 -	fi
   16.13 -}
   16.14 -
   16.15 -echo_n "Configuring libpci for your system..."
   16.16 -idsdir=${1:-/usr/share}
   16.17 -version=${2:-0.0}
   16.18 -sys=`uname -s`
   16.19 -rel=`uname -r`
   16.20 -if [ "$sys" = "AIX" -a -x /usr/bin/oslevel -a -x /usr/sbin/lsattr ]
   16.21 -then
   16.22 -	rel=`/usr/bin/oslevel`
   16.23 -	proc=`/usr/sbin/lsdev -C -c processor -S available -F name | head -1`
   16.24 -	cpu=`/usr/sbin/lsattr -F value -l $proc -a type | sed 's/_.*//'`
   16.25 -else
   16.26 -	cpu=`uname -m | sed 's/^i.86$/i386/;s/^sun4u$/sparc64/;s/^i86pc$/i386/'`
   16.27 -fi
   16.28 -if [ "$sys" = "GNU/kFreeBSD" ]
   16.29 -then
   16.30 -	sys=freebsd
   16.31 -fi
   16.32 -host=${3:-$cpu-$sys}
   16.33 -# CAVEAT: tr on Solaris is a bit weird and the extra [] is otherwise harmless.
   16.34 -host=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)$/\1--\2/' | tr '[A-Z]' '[a-z]'`
   16.35 -cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
   16.36 -sys=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
   16.37 -rel=${4:-$rel}
   16.38 -echo " $host $rel"
   16.39 -zlib=$5
   16.40 -
   16.41 -c=config.h
   16.42 -m=config.mk
   16.43 -echo >$c "#define PCI_ARCH_`echo $cpu | tr '[a-z]' '[A-Z]'`"
   16.44 -echo >>$c "#define PCI_OS_`echo $sys | tr '[a-z]' '[A-Z]'`"
   16.45 -rm -f $m
   16.46 -
   16.47 -echo_n "Looking for access methods..."
   16.48 -
   16.49 -case $sys in
   16.50 -	linux*)
   16.51 -		echo_n " sysfs proc"
   16.52 -		echo >>$c '#define PCI_HAVE_PM_LINUX_SYSFS'
   16.53 -		echo >>$c '#define PCI_HAVE_PM_LINUX_PROC'
   16.54 -		echo >>$c '#define PCI_HAVE_LINUX_BYTEORDER_H'
   16.55 -		echo >>$c '#define PCI_PATH_PROC_BUS_PCI "/proc/bus/pci"'
   16.56 -		echo >>$c '#define PCI_PATH_SYS_BUS_PCI "/sys/bus/pci"'
   16.57 -		case $cpu in
   16.58 -				i386)		echo_n " i386-ports"
   16.59 -						echo >>$c '#define PCI_HAVE_PM_INTEL_CONF'
   16.60 -						;;
   16.61 -		esac
   16.62 -		echo >>$c '#define PCI_HAVE_64BIT_ADDRESS'
   16.63 -		;;
   16.64 -	sunos)
   16.65 -		case $cpu in
   16.66 -				i386)		echo_n " i386-ports"
   16.67 -						echo >>$c "#define PCI_HAVE_PM_INTEL_CONF"
   16.68 -						;;
   16.69 -				*)
   16.70 -						echo " The PCI library is does not support Solaris for this architecture: $cpu"
   16.71 -						exit 1
   16.72 -						;;
   16.73 -		esac
   16.74 -		echo >>$c '#define PCI_HAVE_STDINT_H'
   16.75 -		;;
   16.76 -	freebsd)
   16.77 -		echo_n " fbsd-device"
   16.78 -		echo >>$c '#define PCI_HAVE_PM_FBSD_DEVICE'
   16.79 -		echo >>$c '#define PCI_PATH_FBSD_DEVICE "/dev/pci"'
   16.80 -		;;
   16.81 -        openbsd)
   16.82 -	        echo_n " obsd-device"
   16.83 -		echo >>$c '#define PCI_HAVE_PM_OBSD_DEVICE'
   16.84 -		echo >>$c '#define PCI_PATH_OBSD_DEVICE "/dev/pci"'
   16.85 -		;;
   16.86 -	aix)
   16.87 -		echo_n " aix-device"
   16.88 -		echo >>$c '#define PCI_HAVE_PM_AIX_DEVICE'
   16.89 -		echo >>$m 'CFLAGS=-g'
   16.90 -		echo >>$m 'INSTALL=installbsd'
   16.91 -		echo >>$m 'DIRINSTALL=mkdir -p'
   16.92 -		;;
   16.93 -	netbsd)
   16.94 -		echo_n " nbsd-libpci"
   16.95 -		echo >>$c '#define PCI_HAVE_PM_NBSD_LIBPCI'
   16.96 -		echo >>$c '#define PCI_PATH_NBSD_DEVICE "/dev/pci0"'
   16.97 -		echo >>$m 'PCILIB=lib/libpciutils.a'
   16.98 -		echo >>$m 'LDFLAGS+=-lpci'
   16.99 -		;;
  16.100 -    	gnu)
  16.101 -		echo_n " i386-ports"
  16.102 -		echo >>$c '#define PCI_HAVE_PM_INTEL_CONF'
  16.103 -		;;
  16.104 -        *)
  16.105 -		echo " Unfortunately, your OS is not supported by the PCI Library"
  16.106 -		exit 1
  16.107 -		;;
  16.108 -esac
  16.109 -
  16.110 -echo >>$c '#define PCI_HAVE_PM_DUMP'
  16.111 -echo " dump"
  16.112 -
  16.113 -echo_n "Checking for zlib support... "
  16.114 -if [ "$zlib" = yes -o "$zlib" = no ] ; then
  16.115 -	echo "$zlib (set manually)"
  16.116 -else
  16.117 -	if [ -f /usr/include/zlib.h ] ; then
  16.118 -		zlib=yes
  16.119 -	else
  16.120 -		zlib=no
  16.121 -	fi
  16.122 -	echo "$zlib (auto-detected)"
  16.123 -fi
  16.124 -if [ "$zlib" = yes ] ; then
  16.125 -	echo >>$c '#define PCI_COMPRESSED_IDS'
  16.126 -	echo >>$c '#define PCI_IDS "pci.ids.gz"'
  16.127 -	echo >>$m 'LIBZ=-lz'
  16.128 -	echo >>$m 'LDFLAGS+=$(LIBZ)'
  16.129 -else
  16.130 -	echo >>$c '#define PCI_IDS "pci.ids"'
  16.131 -fi
  16.132 -echo >>$c "#define PCI_PATH_IDS_DIR \"$idsdir\""
  16.133 -
  16.134 -echo >>$c "#define PCILIB_VERSION \"$version\""
  16.135 -sed '/"/{s/^#define \([^ ]*\) "\(.*\)"$/\1=\2/;p;d;};s/^#define \(.*\)/\1=1/' <$c >>$m
    17.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/dump.c	Thu Aug 23 13:42:03 2007 -0700
    17.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    17.3 @@ -1,170 +0,0 @@
    17.4 -/*
    17.5 - *	The PCI Library -- Reading of Bus Dumps
    17.6 - *
    17.7 - *	Copyright (c) 1997--2005 Martin Mares <mj@ucw.cz>
    17.8 - *
    17.9 - *	Can be freely distributed and used under the terms of the GNU GPL.
   17.10 - */
   17.11 -
   17.12 -#include <stdio.h>
   17.13 -#include <ctype.h>
   17.14 -#include <string.h>
   17.15 -#include <errno.h>
   17.16 -
   17.17 -#include "internal.h"
   17.18 -
   17.19 -struct dump_data {
   17.20 -  int len, allocated;
   17.21 -  byte data[1];
   17.22 -};
   17.23 -
   17.24 -static int
   17.25 -dump_detect(struct pci_access *a)
   17.26 -{
   17.27 -  return !!a->method_params[PCI_ACCESS_DUMP];
   17.28 -}
   17.29 -
   17.30 -static void
   17.31 -dump_alloc_data(struct pci_dev *dev, int len)
   17.32 -{
   17.33 -  struct dump_data *dd = pci_malloc(dev->access, sizeof(struct dump_data) + len - 1);
   17.34 -  dd->allocated = len;
   17.35 -  dd->len = 0;
   17.36 -  memset(dd->data, 0xff, len);
   17.37 -  dev->aux = dd;
   17.38 -}
   17.39 -
   17.40 -static int
   17.41 -dump_validate(char *s, char *fmt)
   17.42 -{
   17.43 -  while (*fmt)
   17.44 -    {
   17.45 -      if (*fmt == '#' ? !isxdigit(*s) : *fmt != *s)
   17.46 -	return 0;
   17.47 -      *fmt++, *s++;
   17.48 -    }
   17.49 -  return 1;
   17.50 -}
   17.51 -
   17.52 -static void
   17.53 -dump_init(struct pci_access *a)
   17.54 -{
   17.55 -  char *name = a->method_params[PCI_ACCESS_DUMP];
   17.56 -  FILE *f;
   17.57 -  char buf[256];
   17.58 -  struct pci_dev *dev = NULL;
   17.59 -  int len, mn, bn, dn, fn, i, j;
   17.60 -
   17.61 -  if (!a)
   17.62 -    a->error("dump: File name not given.");
   17.63 -  if (!(f = fopen(name, "r")))
   17.64 -    a->error("dump: Cannot open %s: %s", name, strerror(errno));
   17.65 -  while (fgets(buf, sizeof(buf)-1, f))
   17.66 -    {
   17.67 -      char *z = strchr(buf, '\n');
   17.68 -      if (!z)
   17.69 -	a->error("dump: line too long or unterminated");
   17.70 -      *z-- = 0;
   17.71 -      if (z >= buf && *z == '\r')
   17.72 -	*z-- = 0;
   17.73 -      len = z - buf + 1;
   17.74 -      mn = 0;
   17.75 -      if (dump_validate(buf, "##:##.# ") && sscanf(buf, "%x:%x.%d", &bn, &dn, &fn) == 3 ||
   17.76 -	  dump_validate(buf, "####:##:##.# ") && sscanf(buf, "%x:%x:%x.%d", &mn, &bn, &dn, &fn) == 4)
   17.77 -	{
   17.78 -	  dev = pci_get_dev(a, mn, bn, dn, fn);
   17.79 -	  dump_alloc_data(dev, 256);
   17.80 -	  pci_link_dev(a, dev);
   17.81 -	}
   17.82 -      else if (!len)
   17.83 -	dev = NULL;
   17.84 -      else if (dev &&
   17.85 -	       (dump_validate(buf, "##: ") || dump_validate(buf, "###: ")) &&
   17.86 -	       sscanf(buf, "%x: ", &i) == 1)
   17.87 -	{
   17.88 -	  struct dump_data *dd = dev->aux;
   17.89 -	  z = strchr(buf, ' ') + 1;
   17.90 -	  while (isxdigit(z[0]) && isxdigit(z[1]) && (!z[2] || z[2] == ' ') &&
   17.91 -		 sscanf(z, "%x", &j) == 1 && j < 256)
   17.92 -	    {
   17.93 -	      if (i >= 4096)
   17.94 -		a->error("dump: At most 4096 bytes of config space are supported");
   17.95 -	      if (i >= dd->allocated)	/* Need to re-allocate the buffer */
   17.96 -		{
   17.97 -		  dump_alloc_data(dev, 4096);
   17.98 -		  memcpy(((struct dump_data *) dev->aux)->data, dd->data, 256);
   17.99 -		  pci_mfree(dd);
  17.100 -		  dd = dev->aux;
  17.101 -		}
  17.102 -	      dd->data[i++] = j;
  17.103 -	      if (i > dd->len)
  17.104 -		dd->len = i;
  17.105 -	      z += 2;
  17.106 -	      if (*z)
  17.107 -		z++;
  17.108 -	    }
  17.109 -	  if (*z)
  17.110 -	    a->error("dump: Malformed line");
  17.111 -	}
  17.112 -    }
  17.113 -}
  17.114 -
  17.115 -static void
  17.116 -dump_cleanup(struct pci_access *a UNUSED)
  17.117 -{
  17.118 -}
  17.119 -
  17.120 -static void
  17.121 -dump_scan(struct pci_access *a UNUSED)
  17.122 -{
  17.123 -}
  17.124 -
  17.125 -static int
  17.126 -dump_read(struct pci_dev *d, int pos, byte *buf, int len)
  17.127 -{
  17.128 -  struct dump_data *dd;
  17.129 -  if (!(dd = d->aux))
  17.130 -    {
  17.131 -      struct pci_dev *e = d->access->devices;
  17.132 -      while (e && (e->domain != d->domain || e->bus != d->bus || e->dev != d->dev || e->func != d->func))
  17.133 -	e = e->next;
  17.134 -      if (!e)
  17.135 -	return 0;
  17.136 -      dd = e->aux;
  17.137 -    }
  17.138 -  if (pos + len > dd->len)
  17.139 -    return 0;
  17.140 -  memcpy(buf, dd->data + pos, len);
  17.141 -  return 1;
  17.142 -}
  17.143 -
  17.144 -static int
  17.145 -dump_write(struct pci_dev *d UNUSED, int pos UNUSED, byte *buf UNUSED, int len UNUSED)
  17.146 -{
  17.147 -  d->access->error("Writing to dump files is not supported.");
  17.148 -  return 0;
  17.149 -}
  17.150 -
  17.151 -static void
  17.152 -dump_cleanup_dev(struct pci_dev *d)
  17.153 -{
  17.154 -  if (d->aux)
  17.155 -    {
  17.156 -      pci_mfree(d->aux);
  17.157 -      d->aux = NULL;
  17.158 -    }
  17.159 -}
  17.160 -
  17.161 -struct pci_methods pm_dump = {
  17.162 -  "dump",
  17.163 -  NULL,					/* config */
  17.164 -  dump_detect,
  17.165 -  dump_init,
  17.166 -  dump_cleanup,
  17.167 -  dump_scan,
  17.168 -  pci_generic_fill_info,
  17.169 -  dump_read,
  17.170 -  dump_write,
  17.171 -  NULL,					/* init_dev */
  17.172 -  dump_cleanup_dev
  17.173 -};
    18.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/example.c	Thu Aug 23 13:42:03 2007 -0700
    18.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    18.3 @@ -1,32 +0,0 @@
    18.4 -/*
    18.5 - *	The PCI Library -- Example of use (simplistic lister of PCI devices)
    18.6 - *
    18.7 - *	Written by Martin Mares and put to public domain. You can do
    18.8 - *	with it anything you want, but I don't give you any warranty.
    18.9 - */
   18.10 -
   18.11 -#include <stdio.h>
   18.12 -
   18.13 -#include "pci.h"
   18.14 -
   18.15 -int main(void)
   18.16 -{
   18.17 -  struct pci_access *pacc;
   18.18 -  struct pci_dev *dev;
   18.19 -  unsigned int c;
   18.20 -
   18.21 -  pacc = pci_alloc();		/* Get the pci_access structure */
   18.22 -  /* Set all options you want -- here we stick with the defaults */
   18.23 -  pci_init(pacc);		/* Initialize the PCI library */
   18.24 -  pci_scan_bus(pacc);		/* We want to get the list of devices */
   18.25 -  for(dev=pacc->devices; dev; dev=dev->next)	/* Iterate over all devices */
   18.26 -    {
   18.27 -      pci_fill_info(dev, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_CLASS);	/* Fill in header info we need */
   18.28 -      c = pci_read_byte(dev, PCI_INTERRUPT_PIN);				/* Read config register directly */
   18.29 -      printf("%02x:%02x.%d vendor=%04x device=%04x class=%04x irq=%d (pin %d) base0=%lx\n",
   18.30 -	     dev->bus, dev->dev, dev->func, dev->vendor_id, dev->device_id,
   18.31 -	     dev->device_class, dev->irq, c, dev->base_addr[0]);
   18.32 -    }
   18.33 -  pci_cleanup(pacc);		/* Close everything */
   18.34 -  return 0;
   18.35 -}
    19.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/fbsd-device.c	Thu Aug 23 13:42:03 2007 -0700
    19.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    19.3 @@ -1,165 +0,0 @@
    19.4 -/*
    19.5 - *	The PCI Library -- FreeBSD /dev/pci access
    19.6 - *
    19.7 - *	Copyright (c) 1999 Jari Kirma <kirma@cs.hut.fi>
    19.8 - *	Updated in 2003 by Samy Al Bahra <samy@kerneled.com>
    19.9 - *
   19.10 - *	Can be freely distributed and used under the terms of the GNU GPL.
   19.11 - */
   19.12 -
   19.13 -#include <fcntl.h>
   19.14 -#include <string.h>
   19.15 -#include <unistd.h>
   19.16 -#include <osreldate.h>
   19.17 -#include <stdint.h>
   19.18 -
   19.19 -#ifdef __FreeBSD_kernel_version
   19.20 -#  ifndef __FreeBSD_version
   19.21 -#    define __FreeBSD_version __FreeBSD_kernel_version
   19.22 -#  endif
   19.23 -#endif
   19.24 -
   19.25 -#if __FreeBSD_version < 500000
   19.26 -#  include <pci/pcivar.h>
   19.27 -#else
   19.28 -#  include <dev/pci/pcivar.h>
   19.29 -#endif
   19.30 -
   19.31 -#if __FreeBSD_version < 430000
   19.32 -#  include <pci/pci_ioctl.h>
   19.33 -#else
   19.34 -#  include <sys/pciio.h>
   19.35 -#endif
   19.36 -
   19.37 -#include "internal.h"
   19.38 -
   19.39 -static void
   19.40 -fbsd_config(struct pci_access *a)
   19.41 -{
   19.42 -  a->method_params[PCI_ACCESS_FBSD_DEVICE] = PCI_PATH_FBSD_DEVICE;
   19.43 -}
   19.44 -
   19.45 -static int
   19.46 -fbsd_detect(struct pci_access *a)
   19.47 -{
   19.48 -  char *name = a->method_params[PCI_ACCESS_FBSD_DEVICE];
   19.49 -
   19.50 -  if (access(name, R_OK))
   19.51 -    {
   19.52 -      a->warning("Cannot open %s", name);
   19.53 -      return 0;
   19.54 -    }
   19.55 -  a->debug("...using %s", name);
   19.56 -  return 1;
   19.57 -}
   19.58 -
   19.59 -static void
   19.60 -fbsd_init(struct pci_access *a)
   19.61 -{
   19.62 -  char *name = a->method_params[PCI_ACCESS_FBSD_DEVICE];
   19.63 -
   19.64 -  a->fd = open(name, O_RDWR, 0);
   19.65 -  if (a->fd < 0)
   19.66 -    {
   19.67 -      a->error("fbsd_init: %s open failed", name);
   19.68 -    }
   19.69 -}
   19.70 -
   19.71 -static void
   19.72 -fbsd_cleanup(struct pci_access *a)
   19.73 -{
   19.74 -  close(a->fd);
   19.75 -}
   19.76 -
   19.77 -static int
   19.78 -fbsd_read(struct pci_dev *d, int pos, byte *buf, int len)
   19.79 -{
   19.80 -  struct pci_io pi;
   19.81 -
   19.82 -  if (!(len == 1 || len == 2 || len == 4))
   19.83 -    {
   19.84 -      return pci_generic_block_read(d, pos, buf, len);
   19.85 -    }
   19.86 -
   19.87 -  if (pos >= 256)
   19.88 -    return 0;
   19.89 -
   19.90 -  pi.pi_sel.pc_bus = d->bus;
   19.91 -  pi.pi_sel.pc_dev = d->dev;
   19.92 -  pi.pi_sel.pc_func = d->func;
   19.93 -
   19.94 -  pi.pi_reg = pos;
   19.95 -  pi.pi_width = len;
   19.96 -
   19.97 -  if (ioctl(d->access->fd, PCIOCREAD, &pi) < 0)
   19.98 -    d->access->error("fbsd_read: ioctl(PCIOCREAD) failed");
   19.99 -
  19.100 -  switch (len)
  19.101 -    {
  19.102 -    case 1:
  19.103 -      buf[0] = (u8) pi.pi_data;
  19.104 -      break;
  19.105 -    case 2:
  19.106 -      ((u16 *) buf)[0] = (u16) pi.pi_data;
  19.107 -      break;
  19.108 -    case 4:
  19.109 -      ((u32 *) buf)[0] = (u32) pi.pi_data;
  19.110 -      break;
  19.111 -    }
  19.112 -  return 1;
  19.113 -}
  19.114 -
  19.115 -static int
  19.116 -fbsd_write(struct pci_dev *d, int pos, byte *buf, int len)
  19.117 -{
  19.118 -  struct pci_io pi;
  19.119 -
  19.120 -  if (!(len == 1 || len == 2 || len == 4))
  19.121 -    {
  19.122 -      return pci_generic_block_write(d, pos, buf, len);
  19.123 -    }
  19.124 -
  19.125 -  if (pos >= 256)
  19.126 -    return 0;
  19.127 -
  19.128 -  pi.pi_sel.pc_bus = d->bus;
  19.129 -  pi.pi_sel.pc_dev = d->dev;
  19.130 -  pi.pi_sel.pc_func = d->func;
  19.131 -
  19.132 -  pi.pi_reg = pos;
  19.133 -  pi.pi_width = len;
  19.134 -
  19.135 -  switch (len)
  19.136 -    {
  19.137 -    case 1:
  19.138 -      pi.pi_data = buf[0];
  19.139 -      break;
  19.140 -    case 2:
  19.141 -      pi.pi_data = ((u16 *) buf)[0];
  19.142 -      break;
  19.143 -    case 4:
  19.144 -      pi.pi_data = ((u32 *) buf)[0];
  19.145 -      break;
  19.146 -    }
  19.147 -
  19.148 -  if (ioctl(d->access->fd, PCIOCWRITE, &pi) < 0)
  19.149 -    {
  19.150 -      d->access->error("fbsd_write: ioctl(PCIOCWRITE) failed");
  19.151 -    }
  19.152 -
  19.153 -  return 1;
  19.154 -}
  19.155 -
  19.156 -struct pci_methods pm_fbsd_device = {
  19.157 -  "FreeBSD-device",
  19.158 -  fbsd_config,
  19.159 -  fbsd_detect,
  19.160 -  fbsd_init,
  19.161 -  fbsd_cleanup,
  19.162 -  pci_generic_scan,
  19.163 -  pci_generic_fill_info,
  19.164 -  fbsd_read,
  19.165 -  fbsd_write,
  19.166 -  NULL,                                 /* dev_init */
  19.167 -  NULL                                  /* dev_cleanup */
  19.168 -};
    20.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/filter.c	Thu Aug 23 13:42:03 2007 -0700
    20.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    20.3 @@ -1,123 +0,0 @@
    20.4 -/*
    20.5 - *	The PCI Library -- Device Filtering
    20.6 - *
    20.7 - *	Copyright (c) 1998--2003 Martin Mares <mj@ucw.cz>
    20.8 - *
    20.9 - *	Can be freely distributed and used under the terms of the GNU GPL.
   20.10 - */
   20.11 -
   20.12 -#include <stdlib.h>
   20.13 -#include <string.h>
   20.14 -
   20.15 -#include "internal.h"
   20.16 -
   20.17 -void
   20.18 -pci_filter_init(struct pci_access *a UNUSED, struct pci_filter *f)
   20.19 -{
   20.20 -  f->domain = f->bus = f->slot = f->func = -1;
   20.21 -  f->vendor = f->device = -1;
   20.22 -}
   20.23 -
   20.24 -/* Slot filter syntax: [[[domain]:][bus]:][slot][.[func]] */
   20.25 -
   20.26 -char *
   20.27 -pci_filter_parse_slot(struct pci_filter *f, char *str)
   20.28 -{
   20.29 -  char *colon = strrchr(str, ':');
   20.30 -  char *dot = strchr((colon ? colon + 1 : str), '.');
   20.31 -  char *mid = str;
   20.32 -  char *e, *bus, *colon2;
   20.33 -
   20.34 -  if (colon)
   20.35 -    {
   20.36 -      *colon++ = 0;
   20.37 -      mid = colon;
   20.38 -      colon2 = strchr(str, ':');
   20.39 -      if (colon2)
   20.40 -	{
   20.41 -	  *colon2++ = 0;
   20.42 -	  bus = colon2;
   20.43 -	  if (str[0] && strcmp(str, "*"))
   20.44 -	    {
   20.45 -	      long int x = strtol(str, &e, 16);
   20.46 -	      if ((e && *e) || (x < 0 || x > 0xffff))
   20.47 -		return "Invalid domain number";
   20.48 -	      f->domain = x;
   20.49 -	    }
   20.50 -	}
   20.51 -      else
   20.52 -	bus = str;
   20.53 -      if (bus[0] && strcmp(bus, "*"))
   20.54 -	{
   20.55 -	  long int x = strtol(bus, &e, 16);
   20.56 -	  if ((e && *e) || (x < 0 || x > 0xff))
   20.57 -	    return "Invalid bus number";
   20.58 -	  f->bus = x;
   20.59 -	}
   20.60 -    }
   20.61 -  if (dot)
   20.62 -    *dot++ = 0;
   20.63 -  if (mid[0] && strcmp(mid, "*"))
   20.64 -    {
   20.65 -      long int x = strtol(mid, &e, 16);
   20.66 -      if ((e && *e) || (x < 0 || x > 0x1f))
   20.67 -	return "Invalid slot number";
   20.68 -      f->slot = x;
   20.69 -    }
   20.70 -  if (dot && dot[0] && strcmp(dot, "*"))
   20.71 -    {
   20.72 -      long int x = strtol(dot, &e, 16);
   20.73 -      if ((e && *e) || (x < 0 || x > 7))
   20.74 -	return "Invalid function number";
   20.75 -      f->func = x;
   20.76 -    }
   20.77 -  return NULL;
   20.78 -}
   20.79 -
   20.80 -/* ID filter syntax: [vendor]:[device] */
   20.81 -
   20.82 -char *
   20.83 -pci_filter_parse_id(struct pci_filter *f, char *str)
   20.84 -{
   20.85 -  char *s, *e;
   20.86 -
   20.87 -  if (!*str)
   20.88 -    return NULL;
   20.89 -  s = strchr(str, ':');
   20.90 -  if (!s)
   20.91 -    return "':' expected";
   20.92 -  *s++ = 0;
   20.93 -  if (str[0] && strcmp(str, "*"))
   20.94 -    {
   20.95 -      long int x = strtol(str, &e, 16);
   20.96 -      if ((e && *e) || (x < 0 || x >= 0xffff))
   20.97 -	return "Invalid vendor ID";
   20.98 -      f->vendor = x;
   20.99 -    }
  20.100 -  if (s[0] && strcmp(s, "*"))
  20.101 -    {
  20.102 -      long int x = strtol(s, &e, 16);
  20.103 -      if ((e && *e) || (x < 0 || x >= 0xffff))
  20.104 -	return "Invalid device ID";
  20.105 -      f->device = x;
  20.106 -    }
  20.107 -  return NULL;
  20.108 -}
  20.109 -
  20.110 -int
  20.111 -pci_filter_match(struct pci_filter *f, struct pci_dev *d)
  20.112 -{
  20.113 -  if ((f->domain >= 0 && f->domain != d->domain) ||
  20.114 -      (f->bus >= 0 && f->bus != d->bus) ||
  20.115 -      (f->slot >= 0 && f->slot != d->dev) ||
  20.116 -      (f->func >= 0 && f->func != d->func))
  20.117 -    return 0;
  20.118 -  if (f->device >= 0 || f->vendor >= 0)
  20.119 -    {
  20.120 -      pci_fill_info(d, PCI_FILL_IDENT);
  20.121 -      if ((f->device >= 0 && f->device != d->device_id) ||
  20.122 -	  (f->vendor >= 0 && f->vendor != d->vendor_id))
  20.123 -	return 0;
  20.124 -    }
  20.125 -  return 1;
  20.126 -}
    21.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/generic.c	Thu Aug 23 13:42:03 2007 -0700
    21.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    21.3 @@ -1,206 +0,0 @@
    21.4 -/*
    21.5 - *	The PCI Library -- Generic Direct Access Functions
    21.6 - *
    21.7 - *	Copyright (c) 1997--2000 Martin Mares <mj@ucw.cz>
    21.8 - *
    21.9 - *	Can be freely distributed and used under the terms of the GNU GPL.
   21.10 - */
   21.11 -
   21.12 -#include <string.h>
   21.13 -
   21.14 -#include "internal.h"
   21.15 -
   21.16 -void
   21.17 -pci_generic_scan_bus(struct pci_access *a, byte *busmap, int bus)
   21.18 -{
   21.19 -  int dev, multi, ht;
   21.20 -  struct pci_dev *t;
   21.21 -
   21.22 -  a->debug("Scanning bus %02x for devices...\n", bus);
   21.23 -  if (busmap[bus])
   21.24 -    {
   21.25 -      a->warning("Bus %02x seen twice (firmware bug). Ignored.", bus);
   21.26 -      return;
   21.27 -    }
   21.28 -  busmap[bus] = 1;
   21.29 -  t = pci_alloc_dev(a);
   21.30 -  t->bus = bus;
   21.31 -  for(dev=0; dev<32; dev++)
   21.32 -    {
   21.33 -      t->dev = dev;
   21.34 -      multi = 0;
   21.35 -      for(t->func=0; !t->func || multi && t->func<8; t->func++)
   21.36 -	{
   21.37 -	  u32 vd = pci_read_long(t, PCI_VENDOR_ID);
   21.38 -	  struct pci_dev *d;
   21.39 -
   21.40 -	  if (!vd || vd == 0xffffffff)
   21.41 -	    continue;
   21.42 -	  ht = pci_read_byte(t, PCI_HEADER_TYPE);
   21.43 -	  if (!t->func)
   21.44 -	    multi = ht & 0x80;
   21.45 -	  ht &= 0x7f;
   21.46 -	  d = pci_alloc_dev(a);
   21.47 -	  d->bus = t->bus;
   21.48 -	  d->dev = t->dev;
   21.49 -	  d->func = t->func;
   21.50 -	  d->vendor_id = vd & 0xffff;
   21.51 -	  d->device_id = vd >> 16U;
   21.52 -	  d->known_fields = PCI_FILL_IDENT;
   21.53 -	  d->hdrtype = ht;
   21.54 -	  pci_link_dev(a, d);
   21.55 -	  switch (ht)
   21.56 -	    {
   21.57 -	    case PCI_HEADER_TYPE_NORMAL:
   21.58 -	      break;
   21.59 -	    case PCI_HEADER_TYPE_BRIDGE:
   21.60 -	    case PCI_HEADER_TYPE_CARDBUS:
   21.61 -	      pci_generic_scan_bus(a, busmap, pci_read_byte(t, PCI_SECONDARY_BUS));
   21.62 -	      break;
   21.63 -	    default:
   21.64 -	      a->debug("Device %04x:%02x:%02x.%d has unknown header type %02x.\n", d->domain, d->bus, d->dev, d->func, ht);
   21.65 -	    }
   21.66 -	}
   21.67 -    }
   21.68 -  pci_free_dev(t);
   21.69 -}
   21.70 -
   21.71 -void
   21.72 -pci_generic_scan(struct pci_access *a)
   21.73 -{
   21.74 -  byte busmap[256];
   21.75 -
   21.76 -  memset(busmap, 0, sizeof(busmap));
   21.77 -  pci_generic_scan_bus(a, busmap, 0);
   21.78 -}
   21.79 -
   21.80 -int
   21.81 -pci_generic_fill_info(struct pci_dev *d, int flags)
   21.82 -{
   21.83 -  struct pci_access *a = d->access;
   21.84 -
   21.85 -  if ((flags & (PCI_FILL_BASES | PCI_FILL_ROM_BASE)) && d->hdrtype < 0)
   21.86 -    d->hdrtype = pci_read_byte(d, PCI_HEADER_TYPE) & 0x7f;
   21.87 -  if (flags & PCI_FILL_IDENT)
   21.88 -    {
   21.89 -      d->vendor_id = pci_read_word(d, PCI_VENDOR_ID);
   21.90 -      d->device_id = pci_read_word(d, PCI_DEVICE_ID);
   21.91 -    }
   21.92 -  if (flags & PCI_FILL_CLASS)
   21.93 -      d->device_class = pci_read_word(d, PCI_CLASS_DEVICE);
   21.94 -  if (flags & PCI_FILL_IRQ)
   21.95 -    d->irq = pci_read_byte(d, PCI_INTERRUPT_LINE);
   21.96 -  if (flags & PCI_FILL_BASES)
   21.97 -    {
   21.98 -      int cnt = 0, i;
   21.99 -      memset(d->base_addr, 0, sizeof(d->base_addr));
  21.100 -      switch (d->hdrtype)
  21.101 -	{
  21.102 -	case PCI_HEADER_TYPE_NORMAL:
  21.103 -	  cnt = 6;
  21.104 -	  break;
  21.105 -	case PCI_HEADER_TYPE_BRIDGE:
  21.106 -	  cnt = 2;
  21.107 -	  break;
  21.108 -	case PCI_HEADER_TYPE_CARDBUS:
  21.109 -	  cnt = 1;
  21.110 -	  break;
  21.111 -	}
  21.112 -      if (cnt)
  21.113 -	{
  21.114 -	  for(i=0; i<cnt; i++)
  21.115 -	    {
  21.116 -	      u32 x = pci_read_long(d, PCI_BASE_ADDRESS_0 + i*4);
  21.117 -	      if (!x || x == (u32) ~0)
  21.118 -		continue;
  21.119 -	      if ((x & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
  21.120 -		d->base_addr[i] = x;
  21.121 -	      else
  21.122 -		{
  21.123 -		  if ((x & PCI_BASE_ADDRESS_MEM_TYPE_MASK) != PCI_BASE_ADDRESS_MEM_TYPE_64)
  21.124 -		    d->base_addr[i] = x;
  21.125 -		  else if (i >= cnt-1)
  21.126 -		    a->warning("%04x:%02x:%02x.%d: Invalid 64-bit address seen for BAR %d.", d->domain, d->bus, d->dev, d->func, i);
  21.127 -		  else
  21.128 -		    {
  21.129 -		      u32 y = pci_read_long(d, PCI_BASE_ADDRESS_0 + (++i)*4);
  21.130 -#ifdef PCI_HAVE_64BIT_ADDRESS
  21.131 -		      d->base_addr[i-1] = x | (((pciaddr_t) y) << 32);
  21.132 -#else
  21.133 -		      if (y)
  21.134 -			a->warning("%04x:%02x:%02x.%d 64-bit device address ignored.", d->domain, d->bus, d->dev, d->func);
  21.135 -		      else
  21.136 -			d->base_addr[i-1] = x;
  21.137 -#endif
  21.138 -		    }
  21.139 -		}
  21.140 -	    }
  21.141 -	}
  21.142 -    }
  21.143 -  if (flags & PCI_FILL_ROM_BASE)
  21.144 -    {
  21.145 -      int reg = 0;
  21.146 -      d->rom_base_addr = 0;
  21.147 -      switch (d->hdrtype)
  21.148 -	{
  21.149 -	case PCI_HEADER_TYPE_NORMAL:
  21.150 -	  reg = PCI_ROM_ADDRESS;
  21.151 -	  break;
  21.152 -	case PCI_HEADER_TYPE_BRIDGE:
  21.153 -	  reg = PCI_ROM_ADDRESS1;
  21.154 -	  break;
  21.155 -	}
  21.156 -      if (reg)
  21.157 -	{
  21.158 -	  u32 u = pci_read_long(d, reg);
  21.159 -	  if (u != 0xffffffff)
  21.160 -	    d->rom_base_addr = u;
  21.161 -	}
  21.162 -    }
  21.163 -  return flags & ~PCI_FILL_SIZES;
  21.164 -}
  21.165 -
  21.166 -static int
  21.167 -pci_generic_block_op(struct pci_dev *d, int pos, byte *buf, int len,
  21.168 -		 int (*r)(struct pci_dev *d, int pos, byte *buf, int len))
  21.169 -{
  21.170 -  if ((pos & 1) && len >= 1)
  21.171 -    {
  21.172 -      if (!r(d, pos, buf, 1))
  21.173 -	return 0;
  21.174 -      pos++; buf++; len--;
  21.175 -    }
  21.176 -  if ((pos & 3) && len >= 2)
  21.177 -    {
  21.178 -      if (!r(d, pos, buf, 2))
  21.179 -	return 0;
  21.180 -      pos += 2; buf += 2; len -= 2;
  21.181 -    }
  21.182 -  while (len >= 4)
  21.183 -    {
  21.184 -      if (!r(d, pos, buf, 4))
  21.185 -	return 0;
  21.186 -      pos += 4; buf += 4; len -= 4;
  21.187 -    }
  21.188 -  if (len >= 2)
  21.189 -    {
  21.190 -      if (!r(d, pos, buf, 2))
  21.191 -	return 0;
  21.192 -      pos += 2; buf += 2; len -= 2;
  21.193 -    }
  21.194 -  if (len && !r(d, pos, buf, 1))
  21.195 -    return 0;
  21.196 -  return 1;
  21.197 -}
  21.198 -
  21.199 -int
  21.200 -pci_generic_block_read(struct pci_dev *d, int pos, byte *buf, int len)
  21.201 -{
  21.202 -  return pci_generic_block_op(d, pos, buf, len, d->access->methods->read);
  21.203 -}
  21.204 -
  21.205 -int
  21.206 -pci_generic_block_write(struct pci_dev *d, int pos, byte *buf, int len)
  21.207 -{
  21.208 -  return pci_generic_block_op(d, pos, buf, len, d->access->methods->write);
  21.209 -}
    22.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/header.h	Thu Aug 23 13:42:03 2007 -0700
    22.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    22.3 @@ -1,990 +0,0 @@
    22.4 -/*
    22.5 - *	The PCI Library -- PCI Header Structure (based on <linux/pci.h>)
    22.6 - *
    22.7 - *	Copyright (c) 1997--2005 Martin Mares <mj@ucw.cz>
    22.8 - *
    22.9 - *	Can be freely distributed and used under the terms of the GNU GPL.
   22.10 - */
   22.11 -
   22.12 -/*
   22.13 - * Under PCI, each device has 256 bytes of configuration address space,
   22.14 - * of which the first 64 bytes are standardized as follows:
   22.15 - */
   22.16 -#define PCI_VENDOR_ID		0x00	/* 16 bits */
   22.17 -#define PCI_DEVICE_ID		0x02	/* 16 bits */
   22.18 -#define PCI_COMMAND		0x04	/* 16 bits */
   22.19 -#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
   22.20 -#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
   22.21 -#define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
   22.22 -#define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
   22.23 -#define  PCI_COMMAND_INVALIDATE	0x10	/* Use memory write and invalidate */
   22.24 -#define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
   22.25 -#define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
   22.26 -#define  PCI_COMMAND_WAIT 	0x80	/* Enable address/data stepping */
   22.27 -#define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
   22.28 -#define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
   22.29 -
   22.30 -#define PCI_STATUS		0x06	/* 16 bits */
   22.31 -#define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
   22.32 -#define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
   22.33 -#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
   22.34 -#define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
   22.35 -#define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
   22.36 -#define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */
   22.37 -#define  PCI_STATUS_DEVSEL_FAST	0x000
   22.38 -#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
   22.39 -#define  PCI_STATUS_DEVSEL_SLOW 0x400
   22.40 -#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
   22.41 -#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
   22.42 -#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
   22.43 -#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
   22.44 -#define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
   22.45 -
   22.46 -#define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8
   22.47 -					   revision */
   22.48 -#define PCI_REVISION_ID         0x08    /* Revision ID */
   22.49 -#define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
   22.50 -#define PCI_CLASS_DEVICE        0x0a    /* Device class */
   22.51 -
   22.52 -#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
   22.53 -#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
   22.54 -#define PCI_HEADER_TYPE		0x0e	/* 8 bits */
   22.55 -#define  PCI_HEADER_TYPE_NORMAL	0
   22.56 -#define  PCI_HEADER_TYPE_BRIDGE 1
   22.57 -#define  PCI_HEADER_TYPE_CARDBUS 2
   22.58 -
   22.59 -#define PCI_BIST		0x0f	/* 8 bits */
   22.60 -#define PCI_BIST_CODE_MASK	0x0f	/* Return result */
   22.61 -#define PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
   22.62 -#define PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */
   22.63 -
   22.64 -/*
   22.65 - * Base addresses specify locations in memory or I/O space.
   22.66 - * Decoded size can be determined by writing a value of
   22.67 - * 0xffffffff to the register, and reading it back.  Only
   22.68 - * 1 bits are decoded.
   22.69 - */
   22.70 -#define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
   22.71 -#define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */
   22.72 -#define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */
   22.73 -#define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
   22.74 -#define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
   22.75 -#define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */
   22.76 -#define  PCI_BASE_ADDRESS_SPACE	0x01	/* 0 = memory, 1 = I/O */
   22.77 -#define  PCI_BASE_ADDRESS_SPACE_IO 0x01
   22.78 -#define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
   22.79 -#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
   22.80 -#define  PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
   22.81 -#define  PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
   22.82 -#define  PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
   22.83 -#define  PCI_BASE_ADDRESS_MEM_PREFETCH	0x08	/* prefetchable? */
   22.84 -#define  PCI_BASE_ADDRESS_MEM_MASK	(~(pciaddr_t)0x0f)
   22.85 -#define  PCI_BASE_ADDRESS_IO_MASK	(~(pciaddr_t)0x03)
   22.86 -/* bit 1 is reserved if address_space = 1 */
   22.87 -
   22.88 -/* Header type 0 (normal devices) */
   22.89 -#define PCI_CARDBUS_CIS		0x28
   22.90 -#define PCI_SUBSYSTEM_VENDOR_ID	0x2c
   22.91 -#define PCI_SUBSYSTEM_ID	0x2e
   22.92 -#define PCI_ROM_ADDRESS		0x30	/* Bits 31..11 are address, 10..1 reserved */
   22.93 -#define  PCI_ROM_ADDRESS_ENABLE	0x01
   22.94 -#define PCI_ROM_ADDRESS_MASK	(~(pciaddr_t)0x7ff)
   22.95 -
   22.96 -#define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
   22.97 -
   22.98 -/* 0x35-0x3b are reserved */
   22.99 -#define PCI_INTERRUPT_LINE	0x3c	/* 8 bits */
  22.100 -#define PCI_INTERRUPT_PIN	0x3d	/* 8 bits */
  22.101 -#define PCI_MIN_GNT		0x3e	/* 8 bits */
  22.102 -#define PCI_MAX_LAT		0x3f	/* 8 bits */
  22.103 -
  22.104 -/* Header type 1 (PCI-to-PCI bridges) */
  22.105 -#define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
  22.106 -#define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
  22.107 -#define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
  22.108 -#define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */
  22.109 -#define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */
  22.110 -#define PCI_IO_LIMIT		0x1d
  22.111 -#define  PCI_IO_RANGE_TYPE_MASK	0x0f	/* I/O bridging type */
  22.112 -#define  PCI_IO_RANGE_TYPE_16	0x00
  22.113 -#define  PCI_IO_RANGE_TYPE_32	0x01
  22.114 -#define  PCI_IO_RANGE_MASK	~0x0f
  22.115 -#define PCI_SEC_STATUS		0x1e	/* Secondary status register */
  22.116 -#define PCI_MEMORY_BASE		0x20	/* Memory range behind */
  22.117 -#define PCI_MEMORY_LIMIT	0x22
  22.118 -#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0f
  22.119 -#define  PCI_MEMORY_RANGE_MASK	~0x0f
  22.120 -#define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */
  22.121 -#define PCI_PREF_MEMORY_LIMIT	0x26
  22.122 -#define  PCI_PREF_RANGE_TYPE_MASK 0x0f
  22.123 -#define  PCI_PREF_RANGE_TYPE_32	0x00
  22.124 -#define  PCI_PREF_RANGE_TYPE_64	0x01
  22.125 -#define  PCI_PREF_RANGE_MASK	~0x0f
  22.126 -#define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */
  22.127 -#define PCI_PREF_LIMIT_UPPER32	0x2c
  22.128 -#define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
  22.129 -#define PCI_IO_LIMIT_UPPER16	0x32
  22.130 -/* 0x34 same as for htype 0 */
  22.131 -/* 0x35-0x3b is reserved */
  22.132 -#define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
  22.133 -/* 0x3c-0x3d are same as for htype 0 */
  22.134 -#define PCI_BRIDGE_CONTROL	0x3e
  22.135 -#define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */
  22.136 -#define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */
  22.137 -#define  PCI_BRIDGE_CTL_NO_ISA	0x04	/* Disable bridging of ISA ports */
  22.138 -#define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */
  22.139 -#define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
  22.140 -#define  PCI_BRIDGE_CTL_BUS_RESET 0x40	/* Secondary bus reset */
  22.141 -#define  PCI_BRIDGE_CTL_FAST_BACK 0x80	/* Fast Back2Back enabled on secondary interface */
  22.142 -
  22.143 -/* Header type 2 (CardBus bridges) */
  22.144 -/* 0x14-0x15 reserved */
  22.145 -#define PCI_CB_SEC_STATUS	0x16	/* Secondary status */
  22.146 -#define PCI_CB_PRIMARY_BUS	0x18	/* PCI bus number */
  22.147 -#define PCI_CB_CARD_BUS		0x19	/* CardBus bus number */
  22.148 -#define PCI_CB_SUBORDINATE_BUS	0x1a	/* Subordinate bus number */
  22.149 -#define PCI_CB_LATENCY_TIMER	0x1b	/* CardBus latency timer */
  22.150 -#define PCI_CB_MEMORY_BASE_0	0x1c
  22.151 -#define PCI_CB_MEMORY_LIMIT_0	0x20
  22.152 -#define PCI_CB_MEMORY_BASE_1	0x24
  22.153 -#define PCI_CB_MEMORY_LIMIT_1	0x28
  22.154 -#define PCI_CB_IO_BASE_0	0x2c
  22.155 -#define PCI_CB_IO_BASE_0_HI	0x2e
  22.156 -#define PCI_CB_IO_LIMIT_0	0x30
  22.157 -#define PCI_CB_IO_LIMIT_0_HI	0x32
  22.158 -#define PCI_CB_IO_BASE_1	0x34
  22.159 -#define PCI_CB_IO_BASE_1_HI	0x36
  22.160 -#define PCI_CB_IO_LIMIT_1	0x38
  22.161 -#define PCI_CB_IO_LIMIT_1_HI	0x3a
  22.162 -#define  PCI_CB_IO_RANGE_MASK	~0x03
  22.163 -/* 0x3c-0x3d are same as for htype 0 */
  22.164 -#define PCI_CB_BRIDGE_CONTROL	0x3e
  22.165 -#define  PCI_CB_BRIDGE_CTL_PARITY	0x01	/* Similar to standard bridge control register */
  22.166 -#define  PCI_CB_BRIDGE_CTL_SERR		0x02
  22.167 -#define  PCI_CB_BRIDGE_CTL_ISA		0x04
  22.168 -#define  PCI_CB_BRIDGE_CTL_VGA		0x08
  22.169 -#define  PCI_CB_BRIDGE_CTL_MASTER_ABORT	0x20
  22.170 -#define  PCI_CB_BRIDGE_CTL_CB_RESET	0x40	/* CardBus reset */
  22.171 -#define  PCI_CB_BRIDGE_CTL_16BIT_INT	0x80	/* Enable interrupt for 16-bit cards */
  22.172 -#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100	/* Prefetch enable for both memory regions */
  22.173 -#define  PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
  22.174 -#define  PCI_CB_BRIDGE_CTL_POST_WRITES	0x400
  22.175 -#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
  22.176 -#define PCI_CB_SUBSYSTEM_ID	0x42
  22.177 -#define PCI_CB_LEGACY_MODE_BASE	0x44	/* 16-bit PC Card legacy mode base address (ExCa) */
  22.178 -/* 0x48-0x7f reserved */
  22.179 -
  22.180 -/* Capability lists */
  22.181 -
  22.182 -#define PCI_CAP_LIST_ID		0	/* Capability ID */
  22.183 -#define  PCI_CAP_ID_PM		0x01	/* Power Management */
  22.184 -#define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
  22.185 -#define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
  22.186 -#define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
  22.187 -#define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
  22.188 -#define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
  22.189 -#define  PCI_CAP_ID_PCIX        0x07    /* PCI-X */
  22.190 -#define  PCI_CAP_ID_HT          0x08    /* HyperTransport */
  22.191 -#define  PCI_CAP_ID_VNDR	0x09	/* Vendor specific */
  22.192 -#define  PCI_CAP_ID_DBG		0x0A	/* Debug port */
  22.193 -#define  PCI_CAP_ID_CCRC	0x0B	/* CompactPCI Central Resource Control */
  22.194 -#define  PCI_CAP_ID_SSVID	0x0D	/* Bridge subsystem vendor/device ID */
  22.195 -#define  PCI_CAP_ID_AGP3	0x0E	/* AGP 8x */
  22.196 -#define  PCI_CAP_ID_EXP		0x10	/* PCI Express */
  22.197 -#define  PCI_CAP_ID_MSIX	0x11	/* MSI-X */
  22.198 -#define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
  22.199 -#define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
  22.200 -#define PCI_CAP_SIZEOF		4
  22.201 -
  22.202 -/* Capabilities residing in the PCI Express extended configuration space */
  22.203 -
  22.204 -#define PCI_EXT_CAP_ID_AER	0x01	/* Advanced Error Reporting */
  22.205 -#define PCI_EXT_CAP_ID_VC	0x02	/* Virtual Channel */
  22.206 -#define PCI_EXT_CAP_ID_DSN	0x03	/* Device Serial Number */
  22.207 -#define PCI_EXT_CAP_ID_PB	0x04	/* Power Budgeting */
  22.208 -
  22.209 -/* Power Management Registers */
  22.210 -
  22.211 -#define  PCI_PM_CAP_VER_MASK	0x0007	/* Version (2=PM1.1) */
  22.212 -#define  PCI_PM_CAP_PME_CLOCK	0x0008	/* Clock required for PME generation */
  22.213 -#define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization required */
  22.214 -#define  PCI_PM_CAP_AUX_C_MASK	0x01c0	/* Maximum aux current required in D3cold */
  22.215 -#define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
  22.216 -#define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
  22.217 -#define  PCI_PM_CAP_PME_D0	0x0800	/* PME can be asserted from D0 */
  22.218 -#define  PCI_PM_CAP_PME_D1	0x1000	/* PME can be asserted from D1 */
  22.219 -#define  PCI_PM_CAP_PME_D2	0x2000	/* PME can be asserted from D2 */
  22.220 -#define  PCI_PM_CAP_PME_D3_HOT	0x4000	/* PME can be asserted from D3hot */
  22.221 -#define  PCI_PM_CAP_PME_D3_COLD	0x8000	/* PME can be asserted from D3cold */
  22.222 -#define PCI_PM_CTRL		4	/* PM control and status register */
  22.223 -#define  PCI_PM_CTRL_STATE_MASK	0x0003	/* Current power state (D0 to D3) */
  22.224 -#define  PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
  22.225 -#define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* PM table data index */
  22.226 -#define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* PM table data scaling factor */
  22.227 -#define  PCI_PM_CTRL_PME_STATUS	0x8000	/* PME pin status */
  22.228 -#define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions */
  22.229 -#define  PCI_PM_PPB_B2_B3	0x40	/* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */
  22.230 -#define  PCI_PM_BPCC_ENABLE	0x80	/* Secondary bus is power managed */
  22.231 -#define PCI_PM_DATA_REGISTER	7	/* PM table contents read here */
  22.232 -#define PCI_PM_SIZEOF		8
  22.233 -
  22.234 -/* AGP registers */
  22.235 -
  22.236 -#define PCI_AGP_VERSION		2	/* BCD version number */
  22.237 -#define PCI_AGP_RFU		3	/* Rest of capability flags */
  22.238 -#define PCI_AGP_STATUS		4	/* Status register */
  22.239 -#define  PCI_AGP_STATUS_RQ_MASK	0xff000000	/* Maximum number of requests - 1 */
  22.240 -#define  PCI_AGP_STATUS_ISOCH	0x10000	/* Isochronous transactions supported */
  22.241 -#define  PCI_AGP_STATUS_ARQSZ_MASK	0xe000	/* log2(optimum async req size in bytes) - 4 */
  22.242 -#define  PCI_AGP_STATUS_CAL_MASK	0x1c00	/* Calibration cycle timing */
  22.243 -#define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
  22.244 -#define  PCI_AGP_STATUS_ITA_COH	0x0100	/* In-aperture accesses always coherent */
  22.245 -#define  PCI_AGP_STATUS_GART64	0x0080	/* 64-bit GART entries supported */
  22.246 -#define  PCI_AGP_STATUS_HTRANS	0x0040	/* If 0, core logic can xlate host CPU accesses thru aperture */
  22.247 -#define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing cycles supported */
  22.248 -#define  PCI_AGP_STATUS_FW	0x0010	/* Fast write transfers supported */
  22.249 -#define  PCI_AGP_STATUS_AGP3	0x0008	/* AGP3 mode supported */
  22.250 -#define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported (RFU in AGP3 mode) */
  22.251 -#define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported (8x in AGP3 mode) */
  22.252 -#define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported (4x in AGP3 mode) */
  22.253 -#define PCI_AGP_COMMAND		8	/* Control register */
  22.254 -#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
  22.255 -#define  PCI_AGP_COMMAND_ARQSZ_MASK	0xe000	/* log2(optimum async req size in bytes) - 4 */
  22.256 -#define  PCI_AGP_COMMAND_CAL_MASK	0x1c00	/* Calibration cycle timing */
  22.257 -#define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
  22.258 -#define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
  22.259 -#define  PCI_AGP_COMMAND_GART64	0x0080	/* 64-bit GART entries enabled */
  22.260 -#define  PCI_AGP_COMMAND_64BIT	0x0020 	/* Allow generation of 64-bit addr cycles */
  22.261 -#define  PCI_AGP_COMMAND_FW	0x0010 	/* Enable FW transfers */
  22.262 -#define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate (RFU in AGP3 mode) */
  22.263 -#define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 2x rate (8x in AGP3 mode) */
  22.264 -#define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 1x rate (4x in AGP3 mode) */
  22.265 -#define PCI_AGP_SIZEOF		12
  22.266 -
  22.267 -/* Slot Identification */
  22.268 -
  22.269 -#define PCI_SID_ESR		2	/* Expansion Slot Register */
  22.270 -#define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
  22.271 -#define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
  22.272 -#define PCI_SID_CHASSIS_NR	3	/* Chassis Number */
  22.273 -
  22.274 -/* Message Signalled Interrupts registers */
  22.275 -
  22.276 -#define PCI_MSI_FLAGS		2	/* Various flags */
  22.277 -#define  PCI_MSI_FLAGS_MASK_BIT	0x100	/* interrupt masking & reporting supported */
  22.278 -#define  PCI_MSI_FLAGS_64BIT	0x080	/* 64-bit addresses allowed */
  22.279 -#define  PCI_MSI_FLAGS_QSIZE	0x070	/* Message queue size configured */
  22.280 -#define  PCI_MSI_FLAGS_QMASK	0x00e	/* Maximum queue size available */
  22.281 -#define  PCI_MSI_FLAGS_ENABLE	0x001	/* MSI feature enabled */
  22.282 -#define PCI_MSI_RFU		3	/* Rest of capability flags */
  22.283 -#define PCI_MSI_ADDRESS_LO	4	/* Lower 32 bits */
  22.284 -#define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
  22.285 -#define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
  22.286 -#define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */
  22.287 -#define PCI_MSI_MASK_BIT_32	12	/* per-vector masking for 32-bit devices */
  22.288 -#define PCI_MSI_MASK_BIT_64	16	/* per-vector masking for 64-bit devices */
  22.289 -#define PCI_MSI_PENDING_32	16	/* per-vector interrupt pending for 32-bit devices */
  22.290 -#define PCI_MSI_PENDING_64	20	/* per-vector interrupt pending for 64-bit devices */
  22.291 -
  22.292 -/* PCI-X */
  22.293 -#define PCI_PCIX_COMMAND                                                2 /* Command register offset */
  22.294 -#define PCI_PCIX_COMMAND_DPERE                                     0x0001 /* Data Parity Error Recover Enable */
  22.295 -#define PCI_PCIX_COMMAND_ERO                                       0x0002 /* Enable Relaxed Ordering */
  22.296 -#define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT                   0x000c /* Maximum Memory Read Byte Count */
  22.297 -#define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS               0x0070
  22.298 -#define PCI_PCIX_COMMAND_RESERVED                                   0xf80
  22.299 -#define PCI_PCIX_STATUS                                                 4 /* Status register offset */
  22.300 -#define PCI_PCIX_STATUS_FUNCTION                               0x00000007
  22.301 -#define PCI_PCIX_STATUS_DEVICE                                 0x000000f8
  22.302 -#define PCI_PCIX_STATUS_BUS                                    0x0000ff00
  22.303 -#define PCI_PCIX_STATUS_64BIT                                  0x00010000
  22.304 -#define PCI_PCIX_STATUS_133MHZ                                 0x00020000
  22.305 -#define PCI_PCIX_STATUS_SC_DISCARDED                           0x00040000 /* Split Completion Discarded */
  22.306 -#define PCI_PCIX_STATUS_UNEXPECTED_SC                          0x00080000 /* Unexpected Split Completion */
  22.307 -#define PCI_PCIX_STATUS_DEVICE_COMPLEXITY                      0x00100000 /* 0 = simple device, 1 = bridge device */
  22.308 -#define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT       0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */
  22.309 -#define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS   0x03800000
  22.310 -#define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE      0x1c000000
  22.311 -#define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS                       0x20000000 /* Received Split Completion Error Message */
  22.312 -#define PCI_PCIX_STATUS_266MHZ				       0x40000000 /* 266 MHz capable */
  22.313 -#define PCI_PCIX_STATUS_533MHZ				       0x80000000 /* 533 MHz capable */
  22.314 -#define PCI_PCIX_SIZEOF		4
  22.315 -
  22.316 -/* PCI-X Bridges */
  22.317 -#define PCI_PCIX_BRIDGE_SEC_STATUS                                      2 /* Secondary bus status register offset */
  22.318 -#define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT                           0x0001
  22.319 -#define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ                          0x0002
  22.320 -#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED                    0x0004 /* Split Completion Discarded on secondary bus */
  22.321 -#define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC                   0x0008 /* Unexpected Split Completion on secondary bus */
  22.322 -#define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN                      0x0010 /* Split Completion Overrun on secondary bus */
  22.323 -#define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED           0x0020
  22.324 -#define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ                      0x01c0
  22.325 -#define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED                        0xfe00
  22.326 -#define PCI_PCIX_BRIDGE_STATUS                                          4 /* Primary bus status register offset */
  22.327 -#define PCI_PCIX_BRIDGE_STATUS_FUNCTION                        0x00000007
  22.328 -#define PCI_PCIX_BRIDGE_STATUS_DEVICE                          0x000000f8
  22.329 -#define PCI_PCIX_BRIDGE_STATUS_BUS                             0x0000ff00
  22.330 -#define PCI_PCIX_BRIDGE_STATUS_64BIT                           0x00010000
  22.331 -#define PCI_PCIX_BRIDGE_STATUS_133MHZ                          0x00020000
  22.332 -#define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED                    0x00040000 /* Split Completion Discarded */
  22.333 -#define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC                   0x00080000 /* Unexpected Split Completion */
  22.334 -#define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN                      0x00100000 /* Split Completion Overrun */
  22.335 -#define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED           0x00200000
  22.336 -#define PCI_PCIX_BRIDGE_STATUS_RESERVED                        0xffc00000
  22.337 -#define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL                       8 /* Upstream Split Transaction Register offset */
  22.338 -#define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL                    12 /* Downstream Split Transaction Register offset */
  22.339 -#define PCI_PCIX_BRIDGE_STR_CAPACITY                           0x0000ffff
  22.340 -#define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT                   0xffff0000
  22.341 -#define PCI_PCIX_BRIDGE_SIZEOF 12
  22.342 -
  22.343 -/* HyperTransport (as of spec rev. 2.00) */
  22.344 -#define PCI_HT_CMD		2	/* Command Register */
  22.345 -#define  PCI_HT_CMD_TYP_HI	0xe000	/* Capability Type high part */
  22.346 -#define  PCI_HT_CMD_TYP_HI_PRI	0x0000	/* Slave or Primary Interface */
  22.347 -#define  PCI_HT_CMD_TYP_HI_SEC	0x2000	/* Host or Secondary Interface */
  22.348 -#define  PCI_HT_CMD_TYP		0xf800	/* Capability Type */
  22.349 -#define  PCI_HT_CMD_TYP_SW	0x4000	/* Switch */
  22.350 -#define  PCI_HT_CMD_TYP_IDC	0x8000	/* Interrupt Discovery and Configuration */
  22.351 -#define  PCI_HT_CMD_TYP_RID	0x8800	/* Revision ID */
  22.352 -#define  PCI_HT_CMD_TYP_UIDC	0x9000	/* UnitID Clumping */
  22.353 -#define  PCI_HT_CMD_TYP_ECSA	0x9800	/* Extended Configuration Space Access */
  22.354 -#define  PCI_HT_CMD_TYP_AM	0xa000	/* Address Mapping */
  22.355 -#define  PCI_HT_CMD_TYP_MSIM	0xa800	/* MSI Mapping */
  22.356 -#define  PCI_HT_CMD_TYP_DR	0xb000	/* DirectRoute */
  22.357 -#define  PCI_HT_CMD_TYP_VCS	0xb800	/* VCSet */
  22.358 -#define  PCI_HT_CMD_TYP_RM	0xc000	/* Retry Mode */
  22.359 -#define  PCI_HT_CMD_TYP_X86	0xc800	/* X86 (reserved) */
  22.360 -
  22.361 -					/* Link Control Register */
  22.362 -#define  PCI_HT_LCTR_CFLE	0x0002	/* CRC Flood Enable */
  22.363 -#define  PCI_HT_LCTR_CST	0x0004	/* CRC Start Test */
  22.364 -#define  PCI_HT_LCTR_CFE	0x0008	/* CRC Force Error */
  22.365 -#define  PCI_HT_LCTR_LKFAIL	0x0010	/* Link Failure */
  22.366 -#define  PCI_HT_LCTR_INIT	0x0020	/* Initialization Complete */
  22.367 -#define  PCI_HT_LCTR_EOC	0x0040	/* End of Chain */
  22.368 -#define  PCI_HT_LCTR_TXO	0x0080	/* Transmitter Off */
  22.369 -#define  PCI_HT_LCTR_CRCERR	0x0f00	/* CRC Error */
  22.370 -#define  PCI_HT_LCTR_ISOCEN	0x1000	/* Isochronous Flow Control Enable */
  22.371 -#define  PCI_HT_LCTR_LSEN	0x2000	/* LDTSTOP# Tristate Enable */
  22.372 -#define  PCI_HT_LCTR_EXTCTL	0x4000	/* Extended CTL Time */
  22.373 -#define  PCI_HT_LCTR_64B	0x8000	/* 64-bit Addressing Enable */
  22.374 -
  22.375 -					/* Link Configuration Register */
  22.376 -#define  PCI_HT_LCNF_MLWI	0x0007	/* Max Link Width In */
  22.377 -#define  PCI_HT_LCNF_LW_8B	0x0	/* Link Width 8 bits */
  22.378 -#define  PCI_HT_LCNF_LW_16B	0x1	/* Link Width 16 bits */
  22.379 -#define  PCI_HT_LCNF_LW_32B	0x3	/* Link Width 32 bits */
  22.380 -#define  PCI_HT_LCNF_LW_2B	0x4	/* Link Width 2 bits */
  22.381 -#define  PCI_HT_LCNF_LW_4B	0x5	/* Link Width 4 bits */
  22.382 -#define  PCI_HT_LCNF_LW_NC	0x7	/* Link physically not connected */
  22.383 -#define  PCI_HT_LCNF_DFI	0x0008	/* Doubleword Flow Control In */
  22.384 -#define  PCI_HT_LCNF_MLWO	0x0070	/* Max Link Width Out */
  22.385 -#define  PCI_HT_LCNF_DFO	0x0080	/* Doubleword Flow Control Out */
  22.386 -#define  PCI_HT_LCNF_LWI	0x0700	/* Link Width In */
  22.387 -#define  PCI_HT_LCNF_DFIE	0x0800	/* Doubleword Flow Control In Enable */
  22.388 -#define  PCI_HT_LCNF_LWO	0x7000	/* Link Width Out */
  22.389 -#define  PCI_HT_LCNF_DFOE	0x8000	/* Doubleword Flow Control Out Enable */
  22.390 -
  22.391 -					/* Revision ID Register */
  22.392 -#define  PCI_HT_RID_MIN		0x1f	/* Minor Revision */
  22.393 -#define  PCI_HT_RID_MAJ		0xe0	/* Major Revision */
  22.394 -
  22.395 -					/* Link Frequency/Error Register */
  22.396 -#define  PCI_HT_LFRER_FREQ	0x0f	/* Transmitter Clock Frequency */
  22.397 -#define  PCI_HT_LFRER_200	0x00	/* 200MHz */
  22.398 -#define  PCI_HT_LFRER_300	0x01	/* 300MHz */
  22.399 -#define  PCI_HT_LFRER_400	0x02	/* 400MHz */
  22.400 -#define  PCI_HT_LFRER_500	0x03	/* 500MHz */
  22.401 -#define  PCI_HT_LFRER_600	0x04	/* 600MHz */
  22.402 -#define  PCI_HT_LFRER_800	0x05	/* 800MHz */
  22.403 -#define  PCI_HT_LFRER_1000	0x06	/* 1.0GHz */
  22.404 -#define  PCI_HT_LFRER_1200	0x07	/* 1.2GHz */
  22.405 -#define  PCI_HT_LFRER_1400	0x08	/* 1.4GHz */
  22.406 -#define  PCI_HT_LFRER_1600	0x09	/* 1.6GHz */
  22.407 -#define  PCI_HT_LFRER_VEND	0x0f	/* Vendor-Specific */
  22.408 -#define  PCI_HT_LFRER_ERR	0xf0	/* Link Error */
  22.409 -#define  PCI_HT_LFRER_PROT	0x10	/* Protocol Error */
  22.410 -#define  PCI_HT_LFRER_OV	0x20	/* Overflow Error */
  22.411 -#define  PCI_HT_LFRER_EOC	0x40	/* End of Chain Error */
  22.412 -#define  PCI_HT_LFRER_CTLT	0x80	/* CTL Timeout */
  22.413 -
  22.414 -					/* Link Frequency Capability Register */
  22.415 -#define  PCI_HT_LFCAP_200	0x0001	/* 200MHz */
  22.416 -#define  PCI_HT_LFCAP_300	0x0002	/* 300MHz */
  22.417 -#define  PCI_HT_LFCAP_400	0x0004	/* 400MHz */
  22.418 -#define  PCI_HT_LFCAP_500	0x0008	/* 500MHz */
  22.419 -#define  PCI_HT_LFCAP_600	0x0010	/* 600MHz */
  22.420 -#define  PCI_HT_LFCAP_800	0x0020	/* 800MHz */
  22.421 -#define  PCI_HT_LFCAP_1000	0x0040	/* 1.0GHz */
  22.422 -#define  PCI_HT_LFCAP_1200	0x0080	/* 1.2GHz */
  22.423 -#define  PCI_HT_LFCAP_1400	0x0100	/* 1.4GHz */
  22.424 -#define  PCI_HT_LFCAP_1600	0x0200	/* 1.6GHz */
  22.425 -#define  PCI_HT_LFCAP_VEND	0x8000	/* Vendor-Specific */
  22.426 -
  22.427 -					/* Feature Register */
  22.428 -#define  PCI_HT_FTR_ISOCFC	0x0001	/* Isochronous Flow Control Mode */
  22.429 -#define  PCI_HT_FTR_LDTSTOP	0x0002	/* LDTSTOP# Supported */
  22.430 -#define  PCI_HT_FTR_CRCTM	0x0004	/* CRC Test Mode */
  22.431 -#define  PCI_HT_FTR_ECTLT	0x0008	/* Extended CTL Time Required */
  22.432 -#define  PCI_HT_FTR_64BA	0x0010	/* 64-bit Addressing */
  22.433 -#define  PCI_HT_FTR_UIDRD	0x0020	/* UnitID Reorder Disable */
  22.434 -
  22.435 -					/* Error Handling Register */
  22.436 -#define  PCI_HT_EH_PFLE		0x0001	/* Protocol Error Flood Enable */
  22.437 -#define  PCI_HT_EH_OFLE		0x0002	/* Overflow Error Flood Enable */
  22.438 -#define  PCI_HT_EH_PFE		0x0004	/* Protocol Error Fatal Enable */
  22.439 -#define  PCI_HT_EH_OFE		0x0008	/* Overflow Error Fatal Enable */
  22.440 -#define  PCI_HT_EH_EOCFE	0x0010	/* End of Chain Error Fatal Enable */
  22.441 -#define  PCI_HT_EH_RFE		0x0020	/* Response Error Fatal Enable */
  22.442 -#define  PCI_HT_EH_CRCFE	0x0040	/* CRC Error Fatal Enable */
  22.443 -#define  PCI_HT_EH_SERRFE	0x0080	/* System Error Fatal Enable (B */
  22.444 -#define  PCI_HT_EH_CF		0x0100	/* Chain Fail */
  22.445 -#define  PCI_HT_EH_RE		0x0200	/* Response Error */
  22.446 -#define  PCI_HT_EH_PNFE		0x0400	/* Protocol Error Nonfatal Enable */
  22.447 -#define  PCI_HT_EH_ONFE		0x0800	/* Overflow Error Nonfatal Enable */
  22.448 -#define  PCI_HT_EH_EOCNFE	0x1000	/* End of Chain Error Nonfatal Enable */
  22.449 -#define  PCI_HT_EH_RNFE		0x2000	/* Response Error Nonfatal Enable */
  22.450 -#define  PCI_HT_EH_CRCNFE	0x4000	/* CRC Error Nonfatal Enable */
  22.451 -#define  PCI_HT_EH_SERRNFE	0x8000	/* System Error Nonfatal Enable */
  22.452 -
  22.453 -/* HyperTransport: Slave or Primary Interface */
  22.454 -#define PCI_HT_PRI_CMD		2	/* Command Register */
  22.455 -#define  PCI_HT_PRI_CMD_BUID	0x001f	/* Base UnitID */
  22.456 -#define  PCI_HT_PRI_CMD_UC	0x03e0	/* Unit Count */
  22.457 -#define  PCI_HT_PRI_CMD_MH	0x0400	/* Master Host */
  22.458 -#define  PCI_HT_PRI_CMD_DD	0x0800	/* Default Direction */
  22.459 -#define  PCI_HT_PRI_CMD_DUL	0x1000	/* Drop on Uninitialized Link */
  22.460 -
  22.461 -#define PCI_HT_PRI_LCTR0	4	/* Link Control 0 Register */
  22.462 -#define PCI_HT_PRI_LCNF0	6	/* Link Config 0 Register */
  22.463 -#define PCI_HT_PRI_LCTR1	8	/* Link Control 1 Register */
  22.464 -#define PCI_HT_PRI_LCNF1	10	/* Link Config 1 Register */
  22.465 -#define PCI_HT_PRI_RID		12	/* Revision ID Register */
  22.466 -#define PCI_HT_PRI_LFRER0	13	/* Link Frequency/Error 0 Register */
  22.467 -#define PCI_HT_PRI_LFCAP0	14	/* Link Frequency Capability 0 Register */
  22.468 -#define PCI_HT_PRI_FTR		16	/* Feature Register */
  22.469 -#define PCI_HT_PRI_LFRER1	17	/* Link Frequency/Error 1 Register */
  22.470 -#define PCI_HT_PRI_LFCAP1	18	/* Link Frequency Capability 1 Register */
  22.471 -#define PCI_HT_PRI_ES		20	/* Enumeration Scratchpad Register */
  22.472 -#define PCI_HT_PRI_EH		22	/* Error Handling Register */
  22.473 -#define PCI_HT_PRI_MBU		24	/* Memory Base Upper Register */
  22.474 -#define PCI_HT_PRI_MLU		25	/* Memory Limit Upper Register */
  22.475 -#define PCI_HT_PRI_BN		26	/* Bus Number Register */
  22.476 -#define PCI_HT_PRI_SIZEOF	28
  22.477 -
  22.478 -/* HyperTransport: Host or Secondary Interface */
  22.479 -#define PCI_HT_SEC_CMD		2	/* Command Register */
  22.480 -#define  PCI_HT_SEC_CMD_WR	0x0001	/* Warm Reset */
  22.481 -#define  PCI_HT_SEC_CMD_DE	0x0002	/* Double-Ended */
  22.482 -#define  PCI_HT_SEC_CMD_DN	0x0076	/* Device Number */
  22.483 -#define  PCI_HT_SEC_CMD_CS	0x0080	/* Chain Side */
  22.484 -#define  PCI_HT_SEC_CMD_HH	0x0100	/* Host Hide */
  22.485 -#define  PCI_HT_SEC_CMD_AS	0x0400	/* Act as Slave */
  22.486 -#define  PCI_HT_SEC_CMD_HIECE	0x0800	/* Host Inbound End of Chain Error */
  22.487 -#define  PCI_HT_SEC_CMD_DUL	0x1000	/* Drop on Uninitialized Link */
  22.488 -
  22.489 -#define PCI_HT_SEC_LCTR		4	/* Link Control Register */
  22.490 -#define PCI_HT_SEC_LCNF		6	/* Link Config Register */
  22.491 -#define PCI_HT_SEC_RID		8	/* Revision ID Register */
  22.492 -#define PCI_HT_SEC_LFRER	9	/* Link Frequency/Error Register */
  22.493 -#define PCI_HT_SEC_LFCAP	10	/* Link Frequency Capability Register */
  22.494 -#define PCI_HT_SEC_FTR		12	/* Feature Register */
  22.495 -#define  PCI_HT_SEC_FTR_EXTRS	0x0100	/* Extended Register Set */
  22.496 -#define  PCI_HT_SEC_FTR_UCNFE	0x0200	/* Upstream Configuration Enable */
  22.497 -#define PCI_HT_SEC_ES		16	/* Enumeration Scratchpad Register */
  22.498 -#define PCI_HT_SEC_EH		18	/* Error Handling Register */
  22.499 -#define PCI_HT_SEC_MBU		20	/* Memory Base Upper Register */
  22.500 -#define PCI_HT_SEC_MLU		21	/* Memory Limit Upper Register */
  22.501 -#define PCI_HT_SEC_SIZEOF	24
  22.502 -
  22.503 -/* HyperTransport: Switch */
  22.504 -#define PCI_HT_SW_CMD		2	/* Switch Command Register */
  22.505 -#define  PCI_HT_SW_CMD_VIBERR	0x0080	/* VIB Error */
  22.506 -#define  PCI_HT_SW_CMD_VIBFL	0x0100	/* VIB Flood */
  22.507 -#define  PCI_HT_SW_CMD_VIBFT	0x0200	/* VIB Fatal */
  22.508 -#define  PCI_HT_SW_CMD_VIBNFT	0x0400	/* VIB Nonfatal */
  22.509 -#define PCI_HT_SW_PMASK		4	/* Partition Mask Register */
  22.510 -#define PCI_HT_SW_SWINF		8	/* Switch Info Register */
  22.511 -#define  PCI_HT_SW_SWINF_DP	0x0000001f /* Default Port */
  22.512 -#define  PCI_HT_SW_SWINF_EN	0x00000020 /* Enable Decode */
  22.513 -#define  PCI_HT_SW_SWINF_CR	0x00000040 /* Cold Reset */
  22.514 -#define  PCI_HT_SW_SWINF_PCIDX	0x00000f00 /* Performance Counter Index */
  22.515 -#define  PCI_HT_SW_SWINF_BLRIDX	0x0003f000 /* Base/Limit Range Index */
  22.516 -#define  PCI_HT_SW_SWINF_SBIDX	0x00002000 /* Secondary Base Range Index */
  22.517 -#define  PCI_HT_SW_SWINF_HP	0x00040000 /* Hot Plug */
  22.518 -#define  PCI_HT_SW_SWINF_HIDE	0x00080000 /* Hide Port */
  22.519 -#define PCI_HT_SW_PCD		12	/* Performance Counter Data Register */
  22.520 -#define PCI_HT_SW_BLRD		16	/* Base/Limit Range Data Register */
  22.521 -#define PCI_HT_SW_SBD		20	/* Secondary Base Data Register */
  22.522 -#define PCI_HT_SW_SIZEOF	24
  22.523 -
  22.524 -					/* Counter indices */
  22.525 -#define  PCI_HT_SW_PC_PCR	0x0	/* Posted Command Receive */
  22.526 -#define  PCI_HT_SW_PC_NPCR	0x1	/* Nonposted Command Receive */
  22.527 -#define  PCI_HT_SW_PC_RCR	0x2	/* Response Command Receive */
  22.528 -#define  PCI_HT_SW_PC_PDWR	0x3	/* Posted DW Receive */
  22.529 -#define  PCI_HT_SW_PC_NPDWR	0x4	/* Nonposted DW Receive */
  22.530 -#define  PCI_HT_SW_PC_RDWR	0x5	/* Response DW Receive */
  22.531 -#define  PCI_HT_SW_PC_PCT	0x6	/* Posted Command Transmit */
  22.532 -#define  PCI_HT_SW_PC_NPCT	0x7	/* Nonposted Command Transmit */
  22.533 -#define  PCI_HT_SW_PC_RCT	0x8	/* Response Command Transmit */
  22.534 -#define  PCI_HT_SW_PC_PDWT	0x9	/* Posted DW Transmit */
  22.535 -#define  PCI_HT_SW_PC_NPDWT	0xa	/* Nonposted DW Transmit */
  22.536 -#define  PCI_HT_SW_PC_RDWT	0xb	/* Response DW Transmit */
  22.537 -
  22.538 -					/* Base/Limit Range indices */
  22.539 -#define  PCI_HT_SW_BLR_BASE0_LO	0x0	/* Base 0[31:1], Enable */
  22.540 -#define  PCI_HT_SW_BLR_BASE0_HI	0x1	/* Base 0 Upper */
  22.541 -#define  PCI_HT_SW_BLR_LIM0_LO	0x2	/* Limit 0 Lower */
  22.542 -#define  PCI_HT_SW_BLR_LIM0_HI	0x3	/* Limit 0 Upper */
  22.543 -
  22.544 -					/* Secondary Base indices */
  22.545 -#define  PCI_HT_SW_SB_LO	0x0	/* Secondary Base[31:1], Enable */
  22.546 -#define  PCI_HT_SW_S0_HI	0x1	/* Secondary Base Upper */
  22.547 -
  22.548 -/* HyperTransport: Interrupt Discovery and Configuration */
  22.549 -#define PCI_HT_IDC_IDX		2	/* Index Register */
  22.550 -#define PCI_HT_IDC_DATA		4	/* Data Register */
  22.551 -#define PCI_HT_IDC_SIZEOF	8
  22.552 -
  22.553 -					/* Register indices */
  22.554 -#define  PCI_HT_IDC_IDX_LINT	0x01	/* Last Interrupt Register */
  22.555 -#define   PCI_HT_IDC_LINT	0x00ff0000 /* Last interrupt definition */
  22.556 -#define  PCI_HT_IDC_IDX_IDR	0x10	/* Interrupt Definition Registers */
  22.557 -					/* Low part (at index) */
  22.558 -#define   PCI_HT_IDC_IDR_MASK	0x10000001 /* Mask */
  22.559 -#define   PCI_HT_IDC_IDR_POL	0x10000002 /* Polarity */
  22.560 -#define   PCI_HT_IDC_IDR_II_2	0x1000001c /* IntrInfo[4:2]: Message Type */
  22.561 -#define   PCI_HT_IDC_IDR_II_5	0x10000020 /* IntrInfo[5]: Request EOI */
  22.562 -#define   PCI_HT_IDC_IDR_II_6	0x00ffffc0 /* IntrInfo[23:6] */
  22.563 -#define   PCI_HT_IDC_IDR_II_24	0xff000000 /* IntrInfo[31:24] */
  22.564 -					/* High part (at index + 1) */
  22.565 -#define   PCI_HT_IDC_IDR_II_32	0x00ffffff /* IntrInfo[55:32] */
  22.566 -#define   PCI_HT_IDC_IDR_PASSPW	0x40000000 /* PassPW setting for messages */
  22.567 -#define   PCI_HT_IDC_IDR_WEOI	0x80000000 /* Waiting for EOI */
  22.568 -
  22.569 -/* HyperTransport: Revision ID */
  22.570 -#define PCI_HT_RID_RID		2	/* Revision Register */
  22.571 -#define PCI_HT_RID_SIZEOF	4
  22.572 -
  22.573 -/* HyperTransport: UnitID Clumping */
  22.574 -#define PCI_HT_UIDC_CS		4	/* Clumping Support Register */
  22.575 -#define PCI_HT_UIDC_CE		8	/* Clumping Enable Register */
  22.576 -#define PCI_HT_UIDC_SIZEOF	12
  22.577 -
  22.578 -/* HyperTransport: Extended Configuration Space Access */
  22.579 -#define PCI_HT_ECSA_ADDR	4	/* Configuration Address Register */
  22.580 -#define  PCI_HT_ECSA_ADDR_REG	0x00000ffc /* Register */
  22.581 -#define  PCI_HT_ECSA_ADDR_FUN	0x00007000 /* Function */
  22.582 -#define  PCI_HT_ECSA_ADDR_DEV	0x000f1000 /* Device */
  22.583 -#define  PCI_HT_ECSA_ADDR_BUS	0x0ff00000 /* Bus Number */
  22.584 -#define  PCI_HT_ECSA_ADDR_TYPE	0x10000000 /* Access Type */
  22.585 -#define PCI_HT_ECSA_DATA	8	/* Configuration Data Register */
  22.586 -#define PCI_HT_ECSA_SIZEOF	12
  22.587 -
  22.588 -/* HyperTransport: Address Mapping */
  22.589 -#define PCI_HT_AM_CMD		2	/* Command Register */
  22.590 -#define  PCI_HT_AM_CMD_NDMA	0x000f	/* Number of DMA Mappings */
  22.591 -#define  PCI_HT_AM_CMD_IOSIZ	0x01f0	/* I/O Size */
  22.592 -#define  PCI_HT_AM_CMD_MT	0x0600	/* Map Type */
  22.593 -#define  PCI_HT_AM_CMD_MT_40B	0x0000	/* 40-bit */
  22.594 -#define  PCI_HT_AM_CMD_MT_64B	0x0200	/* 64-bit */
  22.595 -
  22.596 -					/* Window Control Register bits */
  22.597 -#define  PCI_HT_AM_SBW_CTR_COMP	0x1	/* Compat */
  22.598 -#define  PCI_HT_AM_SBW_CTR_NCOH	0x2	/* NonCoherent */
  22.599 -#define  PCI_HT_AM_SBW_CTR_ISOC	0x4	/* Isochronous */
  22.600 -#define  PCI_HT_AM_SBW_CTR_EN	0x8	/* Enable */
  22.601 -
  22.602 -/* HyperTransport: 40-bit Address Mapping */
  22.603 -#define PCI_HT_AM40_SBNPW	4	/* Secondary Bus Non-Prefetchable Window Register */
  22.604 -#define  PCI_HT_AM40_SBW_BASE	0x000fffff /* Window Base */
  22.605 -#define  PCI_HT_AM40_SBW_CTR	0xf0000000 /* Window Control */
  22.606 -#define PCI_HT_AM40_SBPW	8	/* Secondary Bus Prefetchable Window Register */
  22.607 -#define PCI_HT_AM40_DMA_PBASE0	12	/* DMA Window Primary Base 0 Register */
  22.608 -#define PCI_HT_AM40_DMA_CTR0	15	/* DMA Window Control 0 Register */
  22.609 -#define  PCI_HT_AM40_DMA_CTR_CTR 0xf0	/* Window Control */
  22.610 -#define PCI_HT_AM40_DMA_SLIM0	16	/* DMA Window Secondary Limit 0 Register */
  22.611 -#define PCI_HT_AM40_DMA_SBASE0	18	/* DMA Window Secondary Base 0 Register */
  22.612 -#define PCI_HT_AM40_SIZEOF	12	/* size is variable: 12 + 8 * NDMA */
  22.613 -
  22.614 -/* HyperTransport: 64-bit Address Mapping */
  22.615 -#define PCI_HT_AM64_IDX		4	/* Index Register */
  22.616 -#define PCI_HT_AM64_DATA_LO	8	/* Data Lower Register */
  22.617 -#define PCI_HT_AM64_DATA_HI	12	/* Data Upper Register */
  22.618 -#define PCI_HT_AM64_SIZEOF	16
  22.619 -
  22.620 -					/* Register indices */
  22.621 -#define  PCI_HT_AM64_IDX_SBNPW	0x00	/* Secondary Bus Non-Prefetchable Window Register */
  22.622 -#define   PCI_HT_AM64_W_BASE_LO	0xfff00000 /* Window Base Lower */
  22.623 -#define   PCI_HT_AM64_W_CTR	0x0000000f /* Window Control */
  22.624 -#define  PCI_HT_AM64_IDX_SBPW	0x01	/* Secondary Bus Prefetchable Window Register */
  22.625 -#define   PCI_HT_AM64_IDX_PBNPW	0x02	/* Primary Bus Non-Prefetchable Window Register */
  22.626 -#define   PCI_HT_AM64_IDX_DMAPB0 0x04	/* DMA Window Primary Base 0 Register */
  22.627 -#define   PCI_HT_AM64_IDX_DMASB0 0x05	/* DMA Window Secondary Base 0 Register */
  22.628 -#define   PCI_HT_AM64_IDX_DMASL0 0x06	/* DMA Window Secondary Limit 0 Register */
  22.629 -
  22.630 -/* HyperTransport: MSI Mapping */
  22.631 -#define PCI_HT_MSIM_CMD		2	/* Command Register */
  22.632 -#define  PCI_HT_MSIM_CMD_EN	0x0001	/* Mapping Active */
  22.633 -#define  PCI_HT_MSIM_CMD_FIXD	0x0002	/* MSI Mapping Address Fixed */
  22.634 -#define PCI_HT_MSIM_ADDR_LO	4	/* MSI Mapping Address Lower Register */
  22.635 -#define PCI_HT_MSIM_ADDR_HI	8	/* MSI Mapping Address Upper Register */
  22.636 -#define PCI_HT_MSIM_SIZEOF	12
  22.637 -
  22.638 -/* HyperTransport: DirectRoute */
  22.639 -#define PCI_HT_DR_CMD		2	/* Command Register */
  22.640 -#define  PCI_HT_DR_CMD_NDRS	0x000f	/* Number of DirectRoute Spaces */
  22.641 -#define  PCI_HT_DR_CMD_IDX	0x01f0	/* Index */
  22.642 -#define PCI_HT_DR_EN		4	/* Enable Vector Register */
  22.643 -#define PCI_HT_DR_DATA		8	/* Data Register */
  22.644 -#define PCI_HT_DR_SIZEOF	12
  22.645 -
  22.646 -					/* Register indices */
  22.647 -#define  PCI_HT_DR_IDX_BASE_LO	0x00	/* DirectRoute Base Lower Register */
  22.648 -#define   PCI_HT_DR_OTNRD	0x00000001 /* Opposite to Normal Request Direction */
  22.649 -#define   PCI_HT_DR_BL_LO	0xffffff00 /* Base/Limit Lower */
  22.650 -#define  PCI_HT_DR_IDX_BASE_HI	0x01	/* DirectRoute Base Upper Register */
  22.651 -#define  PCI_HT_DR_IDX_LIMIT_LO	0x02	/* DirectRoute Limit Lower Register */
  22.652 -#define  PCI_HT_DR_IDX_LIMIT_HI	0x03	/* DirectRoute Limit Upper Register */
  22.653 -
  22.654 -/* HyperTransport: VCSet */
  22.655 -#define PCI_HT_VCS_SUP		4	/* VCSets Supported Register */
  22.656 -#define PCI_HT_VCS_L1EN		5	/* Link 1 VCSets Enabled Register */
  22.657 -#define PCI_HT_VCS_L0EN		6	/* Link 0 VCSets Enabled Register */
  22.658 -#define PCI_HT_VCS_SBD		8	/* Stream Bucket Depth Register */
  22.659 -#define PCI_HT_VCS_SINT		9	/* Stream Interval Register */
  22.660 -#define PCI_HT_VCS_SSUP		10	/* Number of Streaming VCs Supported Register */
  22.661 -#define  PCI_HT_VCS_SSUP_0	0x00	/* Streaming VC 0 */
  22.662 -#define  PCI_HT_VCS_SSUP_3	0x01	/* Streaming VCs 0-3 */
  22.663 -#define  PCI_HT_VCS_SSUP_15	0x02	/* Streaming VCs 0-15 */
  22.664 -#define PCI_HT_VCS_NFCBD	12	/* Non-FC Bucket Depth Register */
  22.665 -#define PCI_HT_VCS_NFCINT	13	/* Non-FC Bucket Interval Register */
  22.666 -#define PCI_HT_VCS_SIZEOF	16
  22.667 -
  22.668 -/* HyperTransport: Retry Mode */
  22.669 -#define PCI_HT_RM_CTR0		4	/* Control 0 Register */
  22.670 -#define  PCI_HT_RM_CTR_LRETEN	0x01	/* Link Retry Enable */
  22.671 -#define  PCI_HT_RM_CTR_FSER	0x02	/* Force Single Error */
  22.672 -#define  PCI_HT_RM_CTR_ROLNEN	0x04	/* Rollover Nonfatal Enable */
  22.673 -#define  PCI_HT_RM_CTR_FSS	0x08	/* Force Single Stomp */
  22.674 -#define  PCI_HT_RM_CTR_RETNEN	0x10	/* Retry Nonfatal Enable */
  22.675 -#define  PCI_HT_RM_CTR_RETFEN	0x20	/* Retry Fatal Enable */
  22.676 -#define  PCI_HT_RM_CTR_AA	0xc0	/* Allowed Attempts */
  22.677 -#define PCI_HT_RM_STS0		5	/* Status 0 Register */
  22.678 -#define  PCI_HT_RM_STS_RETSNT	0x01	/* Retry Sent */
  22.679 -#define  PCI_HT_RM_STS_CNTROL	0x02	/* Count Rollover */
  22.680 -#define  PCI_HT_RM_STS_SRCV	0x04	/* Stomp Received */
  22.681 -#define PCI_HT_RM_CTR1		6	/* Control 1 Register */
  22.682 -#define PCI_HT_RM_STS1		7	/* Status 1 Register */
  22.683 -#define PCI_HT_RM_CNT0		8	/* Retry Count 0 Register */
  22.684 -#define PCI_HT_RM_CNT1		10	/* Retry Count 1 Register */
  22.685 -#define PCI_HT_RM_SIZEOF	12
  22.686 -
  22.687 -/* PCI Express */
  22.688 -#define PCI_EXP_FLAGS		0x2	/* Capabilities register */
  22.689 -#define PCI_EXP_FLAGS_VERS	0x000f	/* Capability version */
  22.690 -#define PCI_EXP_FLAGS_TYPE	0x00f0	/* Device/Port type */
  22.691 -#define  PCI_EXP_TYPE_ENDPOINT	0x0	/* Express Endpoint */
  22.692 -#define  PCI_EXP_TYPE_LEG_END	0x1	/* Legacy Endpoint */
  22.693 -#define  PCI_EXP_TYPE_ROOT_PORT 0x4	/* Root Port */
  22.694 -#define  PCI_EXP_TYPE_UPSTREAM	0x5	/* Upstream Port */
  22.695 -#define  PCI_EXP_TYPE_DOWNSTREAM 0x6	/* Downstream Port */
  22.696 -#define  PCI_EXP_TYPE_PCI_BRIDGE 0x7	/* PCI/PCI-X Bridge */
  22.697 -#define  PCI_EXP_TYPE_PCIE_BRIDGE 0x8	/* PCI/PCI-X to PCIE Bridge */
  22.698 -#define PCI_EXP_FLAGS_SLOT	0x0100	/* Slot implemented */
  22.699 -#define PCI_EXP_FLAGS_IRQ	0x3e00	/* Interrupt message number */
  22.700 -#define PCI_EXP_DEVCAP		0x4	/* Device capabilities */
  22.701 -#define  PCI_EXP_DEVCAP_PAYLOAD	0x07	/* Max_Payload_Size */
  22.702 -#define  PCI_EXP_DEVCAP_PHANTOM	0x18	/* Phantom functions */
  22.703 -#define  PCI_EXP_DEVCAP_EXT_TAG	0x20	/* Extended tags */
  22.704 -#define  PCI_EXP_DEVCAP_L0S	0x1c0	/* L0s Acceptable Latency */
  22.705 -#define  PCI_EXP_DEVCAP_L1	0xe00	/* L1 Acceptable Latency */
  22.706 -#define  PCI_EXP_DEVCAP_ATN_BUT	0x1000	/* Attention Button Present */
  22.707 -#define  PCI_EXP_DEVCAP_ATN_IND	0x2000	/* Attention Indicator Present */
  22.708 -#define  PCI_EXP_DEVCAP_PWR_IND	0x4000	/* Power Indicator Present */
  22.709 -#define  PCI_EXP_DEVCAP_PWR_VAL	0x3fc0000 /* Slot Power Limit Value */
  22.710 -#define  PCI_EXP_DEVCAP_PWR_SCL	0xc000000 /* Slot Power Limit Scale */
  22.711 -#define PCI_EXP_DEVCTL		0x8	/* Device Control */
  22.712 -#define  PCI_EXP_DEVCTL_CERE	0x0001	/* Correctable Error Reporting En. */
  22.713 -#define  PCI_EXP_DEVCTL_NFERE	0x0002	/* Non-Fatal Error Reporting Enable */
  22.714 -#define  PCI_EXP_DEVCTL_FERE	0x0004	/* Fatal Error Reporting Enable */
  22.715 -#define  PCI_EXP_DEVCTL_URRE	0x0008	/* Unsupported Request Reporting En. */
  22.716 -#define  PCI_EXP_DEVCTL_RELAXED	0x0010	/* Enable Relaxed Ordering */
  22.717 -#define  PCI_EXP_DEVCTL_PAYLOAD	0x00e0	/* Max_Payload_Size */
  22.718 -#define  PCI_EXP_DEVCTL_EXT_TAG	0x0100	/* Extended Tag Field Enable */
  22.719 -#define  PCI_EXP_DEVCTL_PHANTOM	0x0200	/* Phantom Functions Enable */
  22.720 -#define  PCI_EXP_DEVCTL_AUX_PME	0x0400	/* Auxiliary Power PM Enable */
  22.721 -#define  PCI_EXP_DEVCTL_NOSNOOP	0x0800	/* Enable No Snoop */
  22.722 -#define  PCI_EXP_DEVCTL_READRQ	0x7000	/* Max_Read_Request_Size */
  22.723 -#define PCI_EXP_DEVSTA		0xa	/* Device Status */
  22.724 -#define  PCI_EXP_DEVSTA_CED	0x01	/* Correctable Error Detected */
  22.725 -#define  PCI_EXP_DEVSTA_NFED	0x02	/* Non-Fatal Error Detected */
  22.726 -#define  PCI_EXP_DEVSTA_FED	0x04	/* Fatal Error Detected */
  22.727 -#define  PCI_EXP_DEVSTA_URD	0x08	/* Unsupported Request Detected */
  22.728 -#define  PCI_EXP_DEVSTA_AUXPD	0x10	/* AUX Power Detected */
  22.729 -#define  PCI_EXP_DEVSTA_TRPND	0x20	/* Transactions Pending */
  22.730 -#define PCI_EXP_LNKCAP		0xc	/* Link Capabilities */
  22.731 -#define  PCI_EXP_LNKCAP_SPEED	0x0000f	/* Maximum Link Speed */
  22.732 -#define  PCI_EXP_LNKCAP_WIDTH	0x003f0	/* Maximum Link Width */
  22.733 -#define  PCI_EXP_LNKCAP_ASPM	0x00c00	/* Active State Power Management */
  22.734 -#define  PCI_EXP_LNKCAP_L0S	0x07000	/* L0s Acceptable Latency */
  22.735 -#define  PCI_EXP_LNKCAP_L1	0x38000	/* L1 Acceptable Latency */
  22.736 -#define  PCI_EXP_LNKCAP_PORT	0xff000000 /* Port Number */
  22.737 -#define PCI_EXP_LNKCTL		0x10	/* Link Control */
  22.738 -#define  PCI_EXP_LNKCTL_ASPM	0x0003	/* ASPM Control */
  22.739 -#define  PCI_EXP_LNKCTL_RCB	0x0008	/* Read Completion Boundary */
  22.740 -#define  PCI_EXP_LNKCTL_DISABLE	0x0010	/* Link Disable */
  22.741 -#define  PCI_EXP_LNKCTL_RETRAIN	0x0020	/* Retrain Link */
  22.742 -#define  PCI_EXP_LNKCTL_CLOCK	0x0040	/* Common Clock Configuration */
  22.743 -#define  PCI_EXP_LNKCTL_XSYNCH	0x0080	/* Extended Synch */
  22.744 -#define PCI_EXP_LNKSTA		0x12	/* Link Status */
  22.745 -#define  PCI_EXP_LNKSTA_SPEED	0x000f	/* Negotiated Link Speed */
  22.746 -#define  PCI_EXP_LNKSTA_WIDTH	0x03f0	/* Negotiated Link Width */
  22.747 -#define  PCI_EXP_LNKSTA_TR_ERR	0x0400	/* Training Error */
  22.748 -#define  PCI_EXP_LNKSTA_TRAIN	0x0800	/* Link Training */
  22.749 -#define  PCI_EXP_LNKSTA_SL_CLK	0x1000	/* Slot Clock Configuration */
  22.750 -#define PCI_EXP_SLTCAP		0x14	/* Slot Capabilities */
  22.751 -#define  PCI_EXP_SLTCAP_ATNB	0x0001	/* Attention Button Present */
  22.752 -#define  PCI_EXP_SLTCAP_PWRC	0x0002	/* Power Controller Present */
  22.753 -#define  PCI_EXP_SLTCAP_MRL	0x0004	/* MRL Sensor Present */
  22.754 -#define  PCI_EXP_SLTCAP_ATNI	0x0008	/* Attention Indicator Present */
  22.755 -#define  PCI_EXP_SLTCAP_PWRI	0x0010	/* Power Indicator Present */
  22.756 -#define  PCI_EXP_SLTCAP_HPS	0x0020	/* Hot-Plug Surprise */
  22.757 -#define  PCI_EXP_SLTCAP_HPC	0x0040	/* Hot-Plug Capable */
  22.758 -#define  PCI_EXP_SLTCAP_PWR_VAL	0x00007f80 /* Slot Power Limit Value */
  22.759 -#define  PCI_EXP_SLTCAP_PWR_SCL	0x00018000 /* Slot Power Limit Scale */
  22.760 -#define  PCI_EXP_SLTCAP_PSN	0xfff80000 /* Physical Slot Number */
  22.761 -#define PCI_EXP_SLTCTL		0x18	/* Slot Control */
  22.762 -#define  PCI_EXP_SLTCTL_ATNB	0x0001	/* Attention Button Pressed Enable */
  22.763 -#define  PCI_EXP_SLTCTL_PWRF	0x0002	/* Power Fault Detected Enable */
  22.764 -#define  PCI_EXP_SLTCTL_MRLS	0x0004	/* MRL Sensor Changed Enable */
  22.765 -#define  PCI_EXP_SLTCTL_PRSD	0x0008	/* Presence Detect Changed Enable */
  22.766 -#define  PCI_EXP_SLTCTL_CMDC	0x0010	/* Command Completed Interrupt Enable */
  22.767 -#define  PCI_EXP_SLTCTL_HPIE	0x0020	/* Hot-Plug Interrupt Enable */
  22.768 -#define  PCI_EXP_SLTCTL_ATNI	0x00C0	/* Attention Indicator Control */
  22.769 -#define  PCI_EXP_SLTCTL_PWRI	0x0300	/* Power Indicator Control */
  22.770 -#define  PCI_EXP_SLTCTL_PWRC	0x0400	/* Power Controller Control */
  22.771 -#define PCI_EXP_SLTSTA		0x1a	/* Slot Status */
  22.772 -#define PCI_EXP_RTCTL		0x1c	/* Root Control */
  22.773 -#define  PCI_EXP_RTCTL_SECEE	0x1	/* System Error on Correctable Error */
  22.774 -#define  PCI_EXP_RTCTL_SENFEE	0x1	/* System Error on Non-Fatal Error */
  22.775 -#define  PCI_EXP_RTCTL_SEFEE	0x1	/* System Error on Fatal Error */
  22.776 -#define  PCI_EXP_RTCTL_PMEIE	0x1	/* PME Interrupt Enable */
  22.777 -#define PCI_EXP_RTSTA		0x20	/* Root Status */
  22.778 -
  22.779 -/* MSI-X */
  22.780 -#define  PCI_MSIX_ENABLE	0x8000
  22.781 -#define  PCI_MSIX_MASK		0x4000
  22.782 -#define  PCI_MSIX_TABSIZE	0x03ff
  22.783 -#define PCI_MSIX_TABLE		4
  22.784 -#define PCI_MSIX_PBA		8
  22.785 -#define  PCI_MSIX_BIR		0x7
  22.786 -
  22.787 -/* Subsystem vendor/device ID for PCI bridges */
  22.788 -#define PCI_SSVID_VENDOR	4
  22.789 -#define PCI_SSVID_DEVICE	6
  22.790 -
  22.791 -/* Advanced Error Reporting */
  22.792 -#define PCI_ERR_UNCOR_STATUS	4	/* Uncorrectable Error Status */
  22.793 -#define  PCI_ERR_UNC_TRAIN	0x00000001	/* Training */
  22.794 -#define  PCI_ERR_UNC_DLP	0x00000010	/* Data Link Protocol */
  22.795 -#define  PCI_ERR_UNC_POISON_TLP	0x00001000	/* Poisoned TLP */
  22.796 -#define  PCI_ERR_UNC_FCP	0x00002000	/* Flow Control Protocol */
  22.797 -#define  PCI_ERR_UNC_COMP_TIME	0x00004000	/* Completion Timeout */
  22.798 -#define  PCI_ERR_UNC_COMP_ABORT	0x00008000	/* Completer Abort */
  22.799 -#define  PCI_ERR_UNC_UNX_COMP	0x00010000	/* Unexpected Completion */
  22.800 -#define  PCI_ERR_UNC_RX_OVER	0x00020000	/* Receiver Overflow */
  22.801 -#define  PCI_ERR_UNC_MALF_TLP	0x00040000	/* Malformed TLP */
  22.802 -#define  PCI_ERR_UNC_ECRC	0x00080000	/* ECRC Error Status */
  22.803 -#define  PCI_ERR_UNC_UNSUP	0x00100000	/* Unsupported Request */
  22.804 -#define PCI_ERR_UNCOR_MASK	8	/* Uncorrectable Error Mask */
  22.805 -	/* Same bits as above */
  22.806 -#define PCI_ERR_UNCOR_SEVER	12	/* Uncorrectable Error Severity */
  22.807 -	/* Same bits as above */
  22.808 -#define PCI_ERR_COR_STATUS	16	/* Correctable Error Status */
  22.809 -#define  PCI_ERR_COR_RCVR	0x00000001	/* Receiver Error Status */
  22.810 -#define  PCI_ERR_COR_BAD_TLP	0x00000040	/* Bad TLP Status */
  22.811 -#define  PCI_ERR_COR_BAD_DLLP	0x00000080	/* Bad DLLP Status */
  22.812 -#define  PCI_ERR_COR_REP_ROLL	0x00000100	/* REPLAY_NUM Rollover */
  22.813 -#define  PCI_ERR_COR_REP_TIMER	0x00001000	/* Replay Timer Timeout */
  22.814 -#define PCI_ERR_COR_MASK	20	/* Correctable Error Mask */
  22.815 -	/* Same bits as above */
  22.816 -#define PCI_ERR_CAP		24	/* Advanced Error Capabilities */
  22.817 -#define  PCI_ERR_CAP_FEP(x)	((x) & 31)	/* First Error Pointer */
  22.818 -#define  PCI_ERR_CAP_ECRC_GENC	0x00000020	/* ECRC Generation Capable */
  22.819 -#define  PCI_ERR_CAP_ECRC_GENE	0x00000040	/* ECRC Generation Enable */
  22.820 -#define  PCI_ERR_CAP_ECRC_CHKC	0x00000080	/* ECRC Check Capable */
  22.821 -#define  PCI_ERR_CAP_ECRC_CHKE	0x00000100	/* ECRC Check Enable */
  22.822 -#define PCI_ERR_HEADER_LOG	28	/* Header Log Register (16 bytes) */
  22.823 -#define PCI_ERR_ROOT_COMMAND	44	/* Root Error Command */
  22.824 -#define PCI_ERR_ROOT_STATUS	48
  22.825 -#define PCI_ERR_ROOT_COR_SRC	52
  22.826 -#define PCI_ERR_ROOT_SRC	54
  22.827 -
  22.828 -/* Virtual Channel */
  22.829 -#define PCI_VC_PORT_REG1	4
  22.830 -#define PCI_VC_PORT_REG2	8
  22.831 -#define PCI_VC_PORT_CTRL	12
  22.832 -#define PCI_VC_PORT_STATUS	14
  22.833 -#define PCI_VC_RES_CAP		16
  22.834 -#define PCI_VC_RES_CTRL		20
  22.835 -#define PCI_VC_RES_STATUS	26
  22.836 -
  22.837 -/* Power Budgeting */
  22.838 -#define PCI_PWR_DSR		4	/* Data Select Register */
  22.839 -#define PCI_PWR_DATA		8	/* Data Register */
  22.840 -#define  PCI_PWR_DATA_BASE(x)	((x) & 0xff)	    /* Base Power */
  22.841 -#define  PCI_PWR_DATA_SCALE(x)	(((x) >> 8) & 3)    /* Data Scale */
  22.842 -#define  PCI_PWR_DATA_PM_SUB(x)	(((x) >> 10) & 7)   /* PM Sub State */
  22.843 -#define  PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
  22.844 -#define  PCI_PWR_DATA_TYPE(x)	(((x) >> 15) & 7)   /* Type */
  22.845 -#define  PCI_PWR_DATA_RAIL(x)	(((x) >> 18) & 7)   /* Power Rail */
  22.846 -#define PCI_PWR_CAP		12	/* Capability */
  22.847 -#define  PCI_PWR_CAP_BUDGET(x)	((x) & 1)	/* Included in system budget */
  22.848 -
  22.849 -/*
  22.850 - * The PCI interface treats multi-function devices as independent
  22.851 - * devices.  The slot/function address of each device is encoded
  22.852 - * in a single byte as follows:
  22.853 - *
  22.854 - *	7:3 = slot
  22.855 - *	2:0 = function
  22.856 - */
  22.857 -#define PCI_DEVFN(slot,func)	((((slot) & 0x1f) << 3) | ((func) & 0x07))
  22.858 -#define PCI_SLOT(devfn)		(((devfn) >> 3) & 0x1f)
  22.859 -#define PCI_FUNC(devfn)		((devfn) & 0x07)
  22.860 -
  22.861 -/* Device classes and subclasses */
  22.862 -
  22.863 -#define PCI_CLASS_NOT_DEFINED		0x0000
  22.864 -#define PCI_CLASS_NOT_DEFINED_VGA	0x0001
  22.865 -
  22.866 -#define PCI_BASE_CLASS_STORAGE		0x01
  22.867 -#define PCI_CLASS_STORAGE_SCSI		0x0100
  22.868 -#define PCI_CLASS_STORAGE_IDE		0x0101
  22.869 -#define PCI_CLASS_STORAGE_FLOPPY	0x0102
  22.870 -#define PCI_CLASS_STORAGE_IPI		0x0103
  22.871 -#define PCI_CLASS_STORAGE_RAID		0x0104
  22.872 -#define PCI_CLASS_STORAGE_ATA		0x0105
  22.873 -#define PCI_CLASS_STORAGE_SATA		0x0106
  22.874 -#define PCI_CLASS_STORAGE_SAS		0x0107
  22.875 -#define PCI_CLASS_STORAGE_OTHER		0x0180
  22.876 -
  22.877 -#define PCI_BASE_CLASS_NETWORK		0x02
  22.878 -#define PCI_CLASS_NETWORK_ETHERNET	0x0200
  22.879 -#define PCI_CLASS_NETWORK_TOKEN_RING	0x0201
  22.880 -#define PCI_CLASS_NETWORK_FDDI		0x0202
  22.881 -#define PCI_CLASS_NETWORK_ATM		0x0203
  22.882 -#define PCI_CLASS_NETWORK_ISDN		0x0204
  22.883 -#define PCI_CLASS_NETWORK_OTHER		0x0280
  22.884 -
  22.885 -#define PCI_BASE_CLASS_DISPLAY		0x03
  22.886 -#define PCI_CLASS_DISPLAY_VGA		0x0300
  22.887 -#define PCI_CLASS_DISPLAY_XGA		0x0301
  22.888 -#define PCI_CLASS_DISPLAY_3D		0x0302
  22.889 -#define PCI_CLASS_DISPLAY_OTHER		0x0380
  22.890 -
  22.891 -#define PCI_BASE_CLASS_MULTIMEDIA	0x04
  22.892 -#define PCI_CLASS_MULTIMEDIA_VIDEO	0x0400
  22.893 -#define PCI_CLASS_MULTIMEDIA_AUDIO	0x0401
  22.894 -#define PCI_CLASS_MULTIMEDIA_PHONE	0x0402
  22.895 -#define PCI_CLASS_MULTIMEDIA_AUDIO_DEV	0x0403
  22.896 -#define PCI_CLASS_MULTIMEDIA_OTHER	0x0480
  22.897 -
  22.898 -#define PCI_BASE_CLASS_MEMORY		0x05
  22.899 -#define  PCI_CLASS_MEMORY_RAM		0x0500
  22.900 -#define  PCI_CLASS_MEMORY_FLASH		0x0501
  22.901 -#define  PCI_CLASS_MEMORY_OTHER		0x0580
  22.902 -
  22.903 -#define PCI_BASE_CLASS_BRIDGE		0x06
  22.904 -#define  PCI_CLASS_BRIDGE_HOST		0x0600
  22.905 -#define  PCI_CLASS_BRIDGE_ISA		0x0601
  22.906 -#define  PCI_CLASS_BRIDGE_EISA		0x0602
  22.907 -#define  PCI_CLASS_BRIDGE_MC		0x0603
  22.908 -#define  PCI_CLASS_BRIDGE_PCI		0x0604
  22.909 -#define  PCI_CLASS_BRIDGE_PCMCIA	0x0605
  22.910 -#define  PCI_CLASS_BRIDGE_NUBUS		0x0606
  22.911 -#define  PCI_CLASS_BRIDGE_CARDBUS	0x0607
  22.912 -#define  PCI_CLASS_BRIDGE_RACEWAY	0x0608
  22.913 -#define  PCI_CLASS_BRIDGE_PCI_SEMI	0x0609
  22.914 -#define  PCI_CLASS_BRIDGE_IB_TO_PCI	0x060a
  22.915 -#define  PCI_CLASS_BRIDGE_OTHER		0x0680
  22.916 -
  22.917 -#define PCI_BASE_CLASS_COMMUNICATION	0x07
  22.918 -#define PCI_CLASS_COMMUNICATION_SERIAL	0x0700
  22.919 -#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
  22.920 -#define PCI_CLASS_COMMUNICATION_MSERIAL	0x0702
  22.921 -#define PCI_CLASS_COMMUNICATION_MODEM	0x0703
  22.922 -#define PCI_CLASS_COMMUNICATION_OTHER	0x0780
  22.923 -
  22.924 -#define PCI_BASE_CLASS_SYSTEM		0x08
  22.925 -#define PCI_CLASS_SYSTEM_PIC		0x0800
  22.926 -#define PCI_CLASS_SYSTEM_DMA		0x0801
  22.927 -#define PCI_CLASS_SYSTEM_TIMER		0x0802
  22.928 -#define PCI_CLASS_SYSTEM_RTC		0x0803
  22.929 -#define PCI_CLASS_SYSTEM_PCI_HOTPLUG	0x0804
  22.930 -#define PCI_CLASS_SYSTEM_OTHER		0x0880
  22.931 -
  22.932 -#define PCI_BASE_CLASS_INPUT		0x09
  22.933 -#define PCI_CLASS_INPUT_KEYBOARD	0x0900
  22.934 -#define PCI_CLASS_INPUT_PEN		0x0901
  22.935 -#define PCI_CLASS_INPUT_MOUSE		0x0902
  22.936 -#define PCI_CLASS_INPUT_SCANNER		0x0903
  22.937 -#define PCI_CLASS_INPUT_GAMEPORT	0x0904
  22.938 -#define PCI_CLASS_INPUT_OTHER		0x0980
  22.939 -
  22.940 -#define PCI_BASE_CLASS_DOCKING		0x0a
  22.941 -#define PCI_CLASS_DOCKING_GENERIC	0x0a00
  22.942 -#define PCI_CLASS_DOCKING_OTHER		0x0a80
  22.943 -
  22.944 -#define PCI_BASE_CLASS_PROCESSOR	0x0b
  22.945 -#define PCI_CLASS_PROCESSOR_386		0x0b00
  22.946 -#define PCI_CLASS_PROCESSOR_486		0x0b01
  22.947 -#define PCI_CLASS_PROCESSOR_PENTIUM	0x0b02
  22.948 -#define PCI_CLASS_PROCESSOR_ALPHA	0x0b10
  22.949 -#define PCI_CLASS_PROCESSOR_POWERPC	0x0b20
  22.950 -#define PCI_CLASS_PROCESSOR_MIPS	0x0b30
  22.951 -#define PCI_CLASS_PROCESSOR_CO		0x0b40
  22.952 -
  22.953 -#define PCI_BASE_CLASS_SERIAL		0x0c
  22.954 -#define PCI_CLASS_SERIAL_FIREWIRE	0x0c00
  22.955 -#define PCI_CLASS_SERIAL_ACCESS		0x0c01
  22.956 -#define PCI_CLASS_SERIAL_SSA		0x0c02
  22.957 -#define PCI_CLASS_SERIAL_USB		0x0c03
  22.958 -#define PCI_CLASS_SERIAL_FIBER		0x0c04
  22.959 -#define PCI_CLASS_SERIAL_SMBUS		0x0c05
  22.960 -#define PCI_CLASS_SERIAL_INFINIBAND	0x0c06
  22.961 -
  22.962 -#define PCI_BASE_CLASS_WIRELESS		0x0d
  22.963 -#define PCI_CLASS_WIRELESS_IRDA		0x0d00
  22.964 -#define PCI_CLASS_WIRELESS_CONSUMER_IR	0x0d01
  22.965 -#define PCI_CLASS_WIRELESS_RF		0x0d10
  22.966 -#define PCI_CLASS_WIRELESS_OTHER	0x0d80
  22.967 -
  22.968 -#define PCI_BASE_CLASS_INTELLIGENT	0x0e
  22.969 -#define PCI_CLASS_INTELLIGENT_I2O	0x0e00
  22.970 -
  22.971 -#define PCI_BASE_CLASS_SATELLITE	0x0f
  22.972 -#define PCI_CLASS_SATELLITE_TV		0x0f00
  22.973 -#define PCI_CLASS_SATELLITE_AUDIO	0x0f01
  22.974 -#define PCI_CLASS_SATELLITE_VOICE	0x0f03
  22.975 -#define PCI_CLASS_SATELLITE_DATA	0x0f04
  22.976 -
  22.977 -#define PCI_BASE_CLASS_CRYPT		0x10
  22.978 -#define PCI_CLASS_CRYPT_NETWORK		0x1000
  22.979 -#define PCI_CLASS_CRYPT_ENTERTAINMENT	0x1010
  22.980 -#define PCI_CLASS_CRYPT_OTHER		0x1080
  22.981 -
  22.982 -#define PCI_BASE_CLASS_SIGNAL		0x11
  22.983 -#define PCI_CLASS_SIGNAL_DPIO		0x1100
  22.984 -#define PCI_CLASS_SIGNAL_PERF_CTR	0x1101
  22.985 -#define PCI_CLASS_SIGNAL_SYNCHRONIZER	0x1110
  22.986 -#define PCI_CLASS_SIGNAL_OTHER		0x1180
  22.987 -
  22.988 -#define PCI_CLASS_OTHERS		0xff
  22.989 -
  22.990 -/* Several ID's we need in the library */
  22.991 -
  22.992 -#define PCI_VENDOR_ID_INTEL		0x8086
  22.993 -#define PCI_VENDOR_ID_COMPAQ		0x0e11
    23.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/i386-io-hurd.h	Thu Aug 23 13:42:03 2007 -0700
    23.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    23.3 @@ -1,27 +0,0 @@
    23.4 -/*
    23.5 - *	The PCI Library -- Access to i386 I/O ports on GNU Hurd
    23.6 - *
    23.7 - *	Copyright (c) 2003 Marco Gerards <metgerards@student.han.nl>
    23.8 - *	Copyright (c) 2003 Martin Mares <mj@ucw.cz>
    23.9 - *	Copyright (c) 2006 Samuel Thibault <samuel.thibault@ens-lyon.org> and
   23.10 - *	                   Thomas Schwinge <tschwinge@gnu.org>
   23.11 - *	Copyright (c) 2007 Thomas Schwinge <tschwinge@gnu.org>
   23.12 - *
   23.13 - *	Can be freely distributed and used under the terms of the GNU GPL.
   23.14 - */
   23.15 -
   23.16 -#include <sys/io.h>
   23.17 -
   23.18 -static inline int
   23.19 -intel_setup_io(struct pci_access *a UNUSED)
   23.20 -{
   23.21 -  return (ioperm (0, 65535, 1) == -1) ? 0 : 1;
   23.22 -}
   23.23 -
   23.24 -static inline int
   23.25 -intel_cleanup_io(struct pci_access *a UNUSED)
   23.26 -{
   23.27 -  ioperm (0, 65535, 0);
   23.28 -
   23.29 -  return -1;
   23.30 -}
    24.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/i386-io-linux.h	Thu Aug 23 13:42:03 2007 -0700
    24.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    24.3 @@ -1,26 +0,0 @@
    24.4 -/*
    24.5 - *	The PCI Library -- Access to i386 I/O ports on Linux
    24.6 - *
    24.7 - *	Copyright (c) 1997--2006 Martin Mares <mj@ucw.cz>
    24.8 - *
    24.9 - *	Can be freely distributed and used under the terms of the GNU GPL.
   24.10 - */
   24.11 -
   24.12 -#ifdef __GLIBC__
   24.13 -#include <sys/io.h>
   24.14 -#else
   24.15 -#include <asm/io.h>
   24.16 -#endif
   24.17 -
   24.18 -static int
   24.19 -intel_setup_io(struct pci_access *a UNUSED)
   24.20 -{
   24.21 -  return (iopl(3) < 0) ? 0 : 1;
   24.22 -}
   24.23 -
   24.24 -static inline int
   24.25 -intel_cleanup_io(struct pci_access *a UNUSED)
   24.26 -{
   24.27 -  iopl(3);
   24.28 -  return -1;
   24.29 -}
    25.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/i386-io-sunos.h	Thu Aug 23 13:42:03 2007 -0700
    25.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    25.3 @@ -1,66 +0,0 @@
    25.4 -/*
    25.5 - *	The PCI Library -- Access to i386 I/O ports on Solaris
    25.6 - *
    25.7 - *	Copyright (c) 2003 Bill Moore <billm@eng.sun.com>
    25.8 - *	Copyright (c) 2003--2006 Martin Mares <mj@ucw.cz>
    25.9 - *
   25.10 - *	Can be freely distributed and used under the terms of the GNU GPL.
   25.11 - */
   25.12 -
   25.13 -#include <sys/sysi86.h>
   25.14 -#include <sys/psw.h>
   25.15 -
   25.16 -static int
   25.17 -intel_setup_io(struct pci_access *a UNUSED)
   25.18 -{
   25.19 -  return (sysi86(SI86V86, V86SC_IOPL, PS_IOPL) < 0) ? 0 : 1;
   25.20 -}
   25.21 -
   25.22 -static inline int
   25.23 -intel_cleanup_io(struct pci_access *a UNUSED)
   25.24 -{
   25.25 -  /* FIXME: How to switch off I/O port access? */
   25.26 -  return 1;
   25.27 -}
   25.28 -
   25.29 -static inline u8
   25.30 -inb (u16 port)
   25.31 -{
   25.32 -  u8 v;
   25.33 -  __asm__ __volatile__ ("inb (%w1)":"=a" (v):"Nd" (port));
   25.34 -  return v;
   25.35 -}
   25.36 -
   25.37 -static inline u16
   25.38 -inw (u16 port)
   25.39 -{
   25.40 -  u16 v;
   25.41 -  __asm__ __volatile__ ("inw (%w1)":"=a" (v):"Nd" (port));
   25.42 -  return v;
   25.43 -}
   25.44 -
   25.45 -static inline u32
   25.46 -inl (u16 port)
   25.47 -{
   25.48 -  u32 v;
   25.49 -  __asm__ __volatile__ ("inl (%w1)":"=a" (v):"Nd" (port));
   25.50 -  return v;
   25.51 -}
   25.52 -
   25.53 -static inline void
   25.54 -outb (u8 value, u16 port)
   25.55 -{
   25.56 -  __asm__ __volatile__ ("outb (%w1)": :"a" (value), "Nd" (port));
   25.57 -}
   25.58 -
   25.59 -static inline void
   25.60 -outw (u16 value, u16 port)
   25.61 -{
   25.62 -  __asm__ __volatile__ ("outw (%w1)": :"a" (value), "Nd" (port));
   25.63 -}
   25.64 -
   25.65 -static inline void
   25.66 -outl (u32 value, u16 port)
   25.67 -{
   25.68 -  __asm__ __volatile__ ("outl (%w1)": :"a" (value), "Nd" (port));
   25.69 -}
    26.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/i386-io-windows.h	Thu Aug 23 13:42:03 2007 -0700
    26.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    26.3 @@ -1,61 +0,0 @@
    26.4 -/*
    26.5 - *	The PCI Library -- Access to i386 I/O ports on Windows
    26.6 - *
    26.7 - *	Copyright (c) 2004 Alexander Stock <stock.alexander@gmx.de>
    26.8 - *	Copyright (c) 2006 Martin Mares <mj@ucw.cz>
    26.9 - *
   26.10 - *	Can be freely distributed and used under the terms of the GNU GPL.
   26.11 - */
   26.12 -
   26.13 -#include <io.h>
   26.14 -#include <conio.h>
   26.15 -#include <windows.h>
   26.16 -
   26.17 -#define outb(x,y) _outp(y,x)
   26.18 -#define outw(x,y) _outpw(y,x)
   26.19 -#define outl(x,y) _outpd(y,x)
   26.20 -
   26.21 -#define inb(x) _inp(x)
   26.22 -#define inw(x) _inpw(x)
   26.23 -#define inl(x) _inpd(x)
   26.24 -
   26.25 -static int
   26.26 -intel_setup_io(struct pci_access *a)
   26.27 -{
   26.28 -  typedef int (*MYPROC)(void);
   26.29 -  MYPROC InitializeWinIo;
   26.30 -  HMODULE lib;
   26.31 -
   26.32 -  intel_iopl_set = 0;
   26.33 -
   26.34 -  lib = LoadLibrary("WinIo.dll");
   26.35 -  if (!lib)
   26.36 -    {
   26.37 -      a->warning("i386-io-windows: Couldn't load WinIo.dll.");
   26.38 -      return 0;
   26.39 -    }
   26.40 -  /* XXX: Is this really needed? --mj */
   26.41 -  GetProcAddress(lib, "InitializeWinIo");
   26.42 -
   26.43 -  InitializeWinIo = (MYPROC) GetProcAddress(lib, "InitializeWinIo");
   26.44 -  if (!InitializeWinIo)
   26.45 -    {
   26.46 -      a->warning("i386-io-windows: Couldn't find InitializeWinIo function.");
   26.47 -      return 0;
   26.48 -    }
   26.49 -
   26.50 -  if (!InitializeWinIo())
   26.51 -    {
   26.52 -      a->warning("i386-io-windows: InitializeWinIo() failed.");
   26.53 -      return 0;
   26.54 -    }
   26.55 -
   26.56 -  return 1;
   26.57 -}
   26.58 -
   26.59 -static inline int
   26.60 -intel_cleanup_io(struct pci_access *a UNUSED)
   26.61 -{
   26.62 -  //TODO: DeInitializeWinIo!
   26.63 -  return 1;
   26.64 -}
    27.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/i386-ports.c	Thu Aug 23 13:42:03 2007 -0700
    27.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    27.3 @@ -1,281 +0,0 @@
    27.4 -/*
    27.5 - *	The PCI Library -- Direct Configuration access via i386 Ports
    27.6 - *
    27.7 - *	Copyright (c) 1997--2006 Martin Mares <mj@ucw.cz>
    27.8 - *
    27.9 - *	Can be freely distributed and used under the terms of the GNU GPL.
   27.10 - */
   27.11 -
   27.12 -#define _GNU_SOURCE
   27.13 -
   27.14 -#include "internal.h"
   27.15 -
   27.16 -#include <unistd.h>
   27.17 -
   27.18 -#if defined(PCI_OS_LINUX)
   27.19 -#include "i386-io-linux.h"
   27.20 -#elif defined(PCI_OS_GNU)
   27.21 -#include "i386-io-hurd.h"
   27.22 -#elif defined(PCI_OS_SUNOS)
   27.23 -#include "i386-io-sunos.h"
   27.24 -#elif defined(PCI_OS_WINDOWS)
   27.25 -#include "i386-io-windows.h"
   27.26 -#else
   27.27 -#error Do not know how to access I/O ports on this OS.
   27.28 -#endif
   27.29 -
   27.30 -static int conf12_io_enabled = -1;		/* -1=haven't tried, 0=failed, 1=succeeded */
   27.31 -
   27.32 -static int
   27.33 -conf12_setup_io(struct pci_access *a)
   27.34 -{
   27.35 -  if (conf12_io_enabled < 0)
   27.36 -    conf12_io_enabled = intel_setup_io(a);
   27.37 -  return conf12_io_enabled;
   27.38 -}
   27.39 -
   27.40 -static void
   27.41 -conf12_init(struct pci_access *a)
   27.42 -{
   27.43 -  if (!conf12_setup_io(a))
   27.44 -    a->error("No permission to access I/O ports (you probably have to be root).");
   27.45 -}
   27.46 -
   27.47 -static void
   27.48 -conf12_cleanup(struct pci_access *a UNUSED)
   27.49 -{
   27.50 -  if (conf12_io_enabled > 0)
   27.51 -    conf12_io_enabled = intel_cleanup_io(a);
   27.52 -}
   27.53 -
   27.54 -/*
   27.55 - * Before we decide to use direct hardware access mechanisms, we try to do some
   27.56 - * trivial checks to ensure it at least _seems_ to be working -- we just test
   27.57 - * whether bus 00 contains a host bridge (this is similar to checking
   27.58 - * techniques used in XFree86, but ours should be more reliable since we
   27.59 - * attempt to make use of direct access hints provided by the PCI BIOS).
   27.60 - *
   27.61 - * This should be close to trivial, but it isn't, because there are buggy
   27.62 - * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
   27.63 - */
   27.64 -
   27.65 -static int
   27.66 -intel_sanity_check(struct pci_access *a, struct pci_methods *m)
   27.67 -{
   27.68 -  struct pci_dev d;
   27.69 -
   27.70 -  a->debug("...sanity check");
   27.71 -  d.bus = 0;
   27.72 -  d.func = 0;
   27.73 -  for(d.dev = 0; d.dev < 32; d.dev++)
   27.74 -    {
   27.75 -      u16 class, vendor;
   27.76 -      if (m->read(&d, PCI_CLASS_DEVICE, (byte *) &class, sizeof(class)) &&
   27.77 -	  (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) ||
   27.78 -	  m->read(&d, PCI_VENDOR_ID, (byte *) &vendor, sizeof(vendor)) &&
   27.79 -	  (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ)))
   27.80 -	{
   27.81 -	  a->debug("...outside the Asylum at 0/%02x/0", d.dev);
   27.82 -	  return 1;
   27.83 -	}
   27.84 -    }
   27.85 -  a->debug("...insane");
   27.86 -  return 0;
   27.87 -}
   27.88 -
   27.89 -/*
   27.90 - *	Configuration type 1
   27.91 - */
   27.92 -
   27.93 -#define CONFIG_CMD(bus, device_fn, where)   (0x80000000 | (bus << 16) | (device_fn << 8) | (where & ~3))
   27.94 -
   27.95 -static int
   27.96 -conf1_detect(struct pci_access *a)
   27.97 -{
   27.98 -  unsigned int tmp;
   27.99 -  int res = 0;
  27.100 -
  27.101 -  if (!conf12_setup_io(a))
  27.102 -    {
  27.103 -      a->debug("...no I/O permission");
  27.104 -      return 0;
  27.105 -    }
  27.106 -  outb (0x01, 0xCFB);
  27.107 -  tmp = inl (0xCF8);
  27.108 -  outl (0x80000000, 0xCF8);
  27.109 -  if (inl (0xCF8) == 0x80000000)
  27.110 -    res = 1;
  27.111 -  outl (tmp, 0xCF8);
  27.112 -  if (res)
  27.113 -    res = intel_sanity_check(a, &pm_intel_conf1);
  27.114 -  return res;
  27.115 -}
  27.116 -
  27.117 -static int
  27.118 -conf1_read(struct pci_dev *d, int pos, byte *buf, int len)
  27.119 -{
  27.120 -  int addr = 0xcfc + (pos&3);
  27.121 -
  27.122 -  if (pos >= 256)
  27.123 -    return 0;
  27.124 -
  27.125 -  outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
  27.126 -
  27.127 -  switch (len)
  27.128 -    {
  27.129 -    case 1:
  27.130 -      buf[0] = inb(addr);
  27.131 -      break;
  27.132 -    case 2:
  27.133 -      ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
  27.134 -      break;
  27.135 -    case 4:
  27.136 -      ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
  27.137 -      break;
  27.138 -    default:
  27.139 -      return pci_generic_block_read(d, pos, buf, len);
  27.140 -    }
  27.141 -  return 1;
  27.142 -}
  27.143 -
  27.144 -static int
  27.145 -conf1_write(struct pci_dev *d, int pos, byte *buf, int len)
  27.146 -{
  27.147 -  int addr = 0xcfc + (pos&3);
  27.148 -
  27.149 -  if (pos >= 256)
  27.150 -    return 0;
  27.151 -
  27.152 -  outl(0x80000000 | ((d->bus & 0xff) << 16) | (PCI_DEVFN(d->dev, d->func) << 8) | (pos&~3), 0xcf8);
  27.153 -
  27.154 -  switch (len)
  27.155 -    {
  27.156 -    case 1:
  27.157 -      outb(buf[0], addr);
  27.158 -      break;
  27.159 -    case 2:
  27.160 -      outw(le16_to_cpu(((u16 *) buf)[0]), addr);
  27.161 -      break;
  27.162 -    case 4:
  27.163 -      outl(le32_to_cpu(((u32 *) buf)[0]), addr);
  27.164 -      break;
  27.165 -    default:
  27.166 -      return pci_generic_block_write(d, pos, buf, len);
  27.167 -    }
  27.168 -  return 1;
  27.169 -}
  27.170 -
  27.171 -/*
  27.172 - *	Configuration type 2. Obsolete and brain-damaged, but existing.
  27.173 - */
  27.174 -
  27.175 -static int
  27.176 -conf2_detect(struct pci_access *a)
  27.177 -{
  27.178 -  if (!conf12_setup_io(a))
  27.179 -    {
  27.180 -      a->debug("...no I/O permission");
  27.181 -      return 0;
  27.182 -    }
  27.183 -
  27.184 -  /* This is ugly and tends to produce false positives. Beware. */
  27.185 -
  27.186 -  outb(0x00, 0xCFB);
  27.187 -  outb(0x00, 0xCF8);
  27.188 -  outb(0x00, 0xCFA);
  27.189 -  if (inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)
  27.190 -    return intel_sanity_check(a, &pm_intel_conf2);
  27.191 -  else
  27.192 -    return 0;
  27.193 -}
  27.194 -
  27.195 -static int
  27.196 -conf2_read(struct pci_dev *d, int pos, byte *buf, int len)
  27.197 -{
  27.198 -  int addr = 0xc000 | (d->dev << 8) | pos;
  27.199 -
  27.200 -  if (pos >= 256)
  27.201 -    return 0;
  27.202 -
  27.203 -  if (d->dev >= 16)
  27.204 -    /* conf2 supports only 16 devices per bus */
  27.205 -    return 0;
  27.206 -  outb((d->func << 1) | 0xf0, 0xcf8);
  27.207 -  outb(d->bus, 0xcfa);
  27.208 -  switch (len)
  27.209 -    {
  27.210 -    case 1:
  27.211 -      buf[0] = inb(addr);
  27.212 -      break;
  27.213 -    case 2:
  27.214 -      ((u16 *) buf)[0] = cpu_to_le16(inw(addr));
  27.215 -      break;
  27.216 -    case 4:
  27.217 -      ((u32 *) buf)[0] = cpu_to_le32(inl(addr));
  27.218 -      break;
  27.219 -    default:
  27.220 -      outb(0, 0xcf8);
  27.221 -      return pci_generic_block_read(d, pos, buf, len);
  27.222 -    }
  27.223 -  outb(0, 0xcf8);
  27.224 -  return 1;
  27.225 -}
  27.226 -
  27.227 -static int
  27.228 -conf2_write(struct pci_dev *d, int pos, byte *buf, int len)
  27.229 -{
  27.230 -  int addr = 0xc000 | (d->dev << 8) | pos;
  27.231 -
  27.232 -  if (pos >= 256)
  27.233 -    return 0;
  27.234 -
  27.235 -  if (d->dev >= 16)
  27.236 -    d->access->error("conf2_write: only first 16 devices exist.");
  27.237 -  outb((d->func << 1) | 0xf0, 0xcf8);
  27.238 -  outb(d->bus, 0xcfa);
  27.239 -  switch (len)
  27.240 -    {
  27.241 -    case 1:
  27.242 -      outb(buf[0], addr);
  27.243 -      break;
  27.244 -    case 2:
  27.245 -      outw(le16_to_cpu(* (u16 *) buf), addr);
  27.246 -      break;
  27.247 -    case 4:
  27.248 -      outl(le32_to_cpu(* (u32 *) buf), addr);
  27.249 -      break;
  27.250 -    default:
  27.251 -      outb(0, 0xcf8);
  27.252 -      return pci_generic_block_write(d, pos, buf, len);
  27.253 -    }
  27.254 -  outb(0, 0xcf8);
  27.255 -  return 1;
  27.256 -}
  27.257 -
  27.258 -struct pci_methods pm_intel_conf1 = {
  27.259 -  "Intel-conf1",
  27.260 -  NULL,					/* config */
  27.261 -  conf1_detect,
  27.262 -  conf12_init,
  27.263 -  conf12_cleanup,
  27.264 -  pci_generic_scan,
  27.265 -  pci_generic_fill_info,
  27.266 -  conf1_read,
  27.267 -  conf1_write,
  27.268 -  NULL,					/* init_dev */
  27.269 -  NULL					/* cleanup_dev */
  27.270 -};
  27.271 -
  27.272 -struct pci_methods pm_intel_conf2 = {
  27.273 -  "Intel-conf2",
  27.274 -  NULL,					/* config */
  27.275 -  conf2_detect,
  27.276 -  conf12_init,
  27.277 -  conf12_cleanup,
  27.278 -  pci_generic_scan,
  27.279 -  pci_generic_fill_info,
  27.280 -  conf2_read,
  27.281 -  conf2_write,
  27.282 -  NULL,					/* init_dev */
  27.283 -  NULL					/* cleanup_dev */
  27.284 -};
    28.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/internal.h	Thu Aug 23 13:42:03 2007 -0700
    28.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    28.3 @@ -1,43 +0,0 @@
    28.4 -/*
    28.5 - *	The PCI Library -- Internal Stuff
    28.6 - *
    28.7 - *	Copyright (c) 1997--2004 Martin Mares <mj@ucw.cz>
    28.8 - *
    28.9 - *	Can be freely distributed and used under the terms of the GNU GPL.
   28.10 - */
   28.11 -
   28.12 -#include "pci.h"
   28.13 -#include "sysdep.h"
   28.14 -
   28.15 -struct pci_methods {
   28.16 -  char *name;
   28.17 -  void (*config)(struct pci_access *);
   28.18 -  int (*detect)(struct pci_access *);
   28.19 -  void (*init)(struct pci_access *);
   28.20 -  void (*cleanup)(struct pci_access *);
   28.21 -  void (*scan)(struct pci_access *);
   28.22 -  int (*fill_info)(struct pci_dev *, int flags);
   28.23 -  int (*read)(struct pci_dev *, int pos, byte *buf, int len);
   28.24 -  int (*write)(struct pci_dev *, int pos, byte *buf, int len);
   28.25 -  void (*init_dev)(struct pci_dev *);
   28.26 -  void (*cleanup_dev)(struct pci_dev *);
   28.27 -#ifdef PT_LIBPCI
   28.28 -  int (*get_object)(struct pci_dev *d, char *object);
   28.29 -#endif
   28.30 -};
   28.31 -
   28.32 -void pci_generic_scan_bus(struct pci_access *, byte *busmap, int bus);
   28.33 -void pci_generic_scan(struct pci_access *);
   28.34 -int pci_generic_fill_info(struct pci_dev *, int flags);
   28.35 -int pci_generic_block_read(struct pci_dev *, int pos, byte *buf, int len);
   28.36 -int pci_generic_block_write(struct pci_dev *, int pos, byte *buf, int len);
   28.37 -
   28.38 -void *pci_malloc(struct pci_access *, int);
   28.39 -void pci_mfree(void *);
   28.40 -
   28.41 -struct pci_dev *pci_alloc_dev(struct pci_access *);
   28.42 -int pci_link_dev(struct pci_access *, struct pci_dev *);
   28.43 -
   28.44 -extern struct pci_methods pm_intel_conf1, pm_intel_conf2, pm_linux_proc,
   28.45 -	pm_fbsd_device, pm_aix_device, pm_nbsd_libpci, pm_obsd_device,
   28.46 -	pm_dump, pm_linux_sysfs;
    29.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/libpci.pc.in	Thu Aug 23 13:42:03 2007 -0700
    29.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    29.3 @@ -1,10 +0,0 @@
    29.4 -prefix=@PREFIX@
    29.5 -includedir=@INCDIR@
    29.6 -libdir=@LIBDIR@
    29.7 -idsdir=@IDSDIR@
    29.8 -
    29.9 -Name: libpci
   29.10 -Description: libpci
   29.11 -Version: @VERSION@
   29.12 -Libs: -L${libdir} -lpci @LIBZ@
   29.13 -Cflags: -I${includedir}
    30.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/names.c	Thu Aug 23 13:42:03 2007 -0700
    30.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    30.3 @@ -1,519 +0,0 @@
    30.4 -/*
    30.5 - *	The PCI Library -- ID to Name Translation
    30.6 - *
    30.7 - *	Copyright (c) 1997--2006 Martin Mares <mj@ucw.cz>
    30.8 - *
    30.9 - *	Can be freely distributed and used under the terms of the GNU GPL.
   30.10 - */
   30.11 -
   30.12 -#include <stdio.h>
   30.13 -#include <stdlib.h>
   30.14 -#include <stdarg.h>
   30.15 -#include <string.h>
   30.16 -#include <errno.h>
   30.17 -
   30.18 -#include "internal.h"
   30.19 -
   30.20 -#ifdef PCI_COMPRESSED_IDS
   30.21 -#include <zlib.h>
   30.22 -typedef gzFile pci_file;
   30.23 -#define pci_gets(f, l, s)	gzgets(f, l, s)
   30.24 -#define pci_eof(f)		gzeof(f)
   30.25 -
   30.26 -static pci_file pci_open(struct pci_access *a)
   30.27 -{
   30.28 -  pci_file result;
   30.29 -  size_t len;
   30.30 -  char *new_name;
   30.31 -
   30.32 -  result = gzopen(a->id_file_name, "r");
   30.33 -  if (result)
   30.34 -    return result;
   30.35 -  len = strlen(a->id_file_name);
   30.36 -  if (len >= 3 && memcmp(a->id_file_name + len - 3, ".gz", 3) != 0)
   30.37 -    return result;
   30.38 -  new_name = malloc(len - 2);
   30.39 -  memcpy(new_name, a->id_file_name, len - 3);
   30.40 -  new_name[len - 3] = 0;
   30.41 -  pci_set_name_list_path(a, new_name, 1);
   30.42 -  return gzopen(a->id_file_name, "r");
   30.43 -}
   30.44 -
   30.45 -#define pci_close(f)		gzclose(f)
   30.46 -#define PCI_ERROR(f, err)						\
   30.47 -	if (!err) {							\
   30.48 -		int errnum;						\
   30.49 -		err = gzerror(f, &errnum);				\
   30.50 -		if (errnum == Z_ERRNO)	err = "I/O error";		\
   30.51 -		else if (errnum >= 0)	err = NULL;			\
   30.52 -	}
   30.53 -#else
   30.54 -typedef FILE * pci_file;
   30.55 -#define pci_gets(f, l, s)	fgets(l, s, f)
   30.56 -#define pci_eof(f)		feof(f)
   30.57 -#define pci_open(a)		fopen(a->id_file_name, "r")
   30.58 -#define pci_close(f)		fclose(f)
   30.59 -#define PCI_ERROR(f, err)	if (!err && ferror(f))	err = "I/O error";
   30.60 -#endif
   30.61 -
   30.62 -struct id_entry {
   30.63 -  struct id_entry *next;
   30.64 -  u32 id12, id34;
   30.65 -  byte cat;
   30.66 -  char name[1];
   30.67 -};
   30.68 -
   30.69 -enum id_entry_type {
   30.70 -  ID_UNKNOWN,
   30.71 -  ID_VENDOR,
   30.72 -  ID_DEVICE,
   30.73 -  ID_SUBSYSTEM,
   30.74 -  ID_GEN_SUBSYSTEM,
   30.75 -  ID_CLASS,
   30.76 -  ID_SUBCLASS,
   30.77 -  ID_PROGIF
   30.78 -};
   30.79 -
   30.80 -struct id_bucket {
   30.81 -  struct id_bucket *next;
   30.82 -  unsigned int full;
   30.83 -};
   30.84 -
   30.85 -#define MAX_LINE 1024
   30.86 -#define BUCKET_SIZE 8192
   30.87 -#define HASH_SIZE 4099
   30.88 -
   30.89 -#ifdef __GNUC__
   30.90 -#define BUCKET_ALIGNMENT __alignof__(struct id_bucket)
   30.91 -#else
   30.92 -union id_align {
   30.93 -  struct id_bucket *next;
   30.94 -  unsigned int full;
   30.95 -};
   30.96 -#define BUCKET_ALIGNMENT sizeof(union id_align)
   30.97 -#endif
   30.98 -#define BUCKET_ALIGN(n) ((n)+BUCKET_ALIGNMENT-(n)%BUCKET_ALIGNMENT)
   30.99 -
  30.100 -static void *id_alloc(struct pci_access *a, unsigned int size)
  30.101 -{
  30.102 -  struct id_bucket *buck = a->current_id_bucket;
  30.103 -  unsigned int pos;
  30.104 -  if (!buck || buck->full + size > BUCKET_SIZE)
  30.105 -    {
  30.106 -      buck = pci_malloc(a, BUCKET_SIZE);
  30.107 -      buck->next = a->current_id_bucket;
  30.108 -      a->current_id_bucket = buck;
  30.109 -      buck->full = BUCKET_ALIGN(sizeof(struct id_bucket));
  30.110 -    }
  30.111 -  pos = buck->full;
  30.112 -  buck->full = BUCKET_ALIGN(buck->full + size);
  30.113 -  return (byte *)buck + pos;
  30.114 -}
  30.115 -
  30.116 -static inline u32 id_pair(unsigned int x, unsigned int y)
  30.117 -{
  30.118 -  return ((x << 16) | y);
  30.119 -}
  30.120 -
  30.121 -static inline unsigned int id_hash(int cat, u32 id12, u32 id34)
  30.122 -{
  30.123 -  unsigned int h;
  30.124 -
  30.125 -  h = id12 ^ (id34 << 3) ^ (cat << 5);
  30.126 -  return h % HASH_SIZE;
  30.127 -}
  30.128 -
  30.129 -static char *id_lookup(struct pci_access *a, int cat, int id1, int id2, int id3, int id4)
  30.130 -{
  30.131 -  struct id_entry *n;
  30.132 -  u32 id12 = id_pair(id1, id2);
  30.133 -  u32 id34 = id_pair(id3, id4);
  30.134 -
  30.135 -  if (!a->id_hash)
  30.136 -    return NULL;
  30.137 -  n = a->id_hash[id_hash(cat, id12, id34)];
  30.138 -  while (n && (n->id12 != id12 || n->id34 != id34 || n->cat != cat))
  30.139 -    n = n->next;
  30.140 -  return n ? n->name : NULL;
  30.141 -}
  30.142 -
  30.143 -static int id_insert(struct pci_access *a, int cat, int id1, int id2, int id3, int id4, char *text)
  30.144 -{
  30.145 -  u32 id12 = id_pair(id1, id2);
  30.146 -  u32 id34 = id_pair(id3, id4);
  30.147 -  unsigned int h = id_hash(cat, id12, id34);
  30.148 -  struct id_entry *n = a->id_hash[h];
  30.149 -  int len = strlen(text);
  30.150 -
  30.151 -  while (n && (n->id12 != id12 || n->id34 != id34 || n->cat != cat))
  30.152 -    n = n->next;
  30.153 -  if (n)
  30.154 -    return 1;
  30.155 -  n = id_alloc(a, sizeof(struct id_entry) + len);
  30.156 -  n->id12 = id12;
  30.157 -  n->id34 = id34;
  30.158 -  n->cat = cat;
  30.159 -  memcpy(n->name, text, len+1);
  30.160 -  n->next = a->id_hash[h];
  30.161 -  a->id_hash[h] = n;
  30.162 -  return 0;
  30.163 -}
  30.164 -
  30.165 -static int id_hex(char *p, int cnt)
  30.166 -{
  30.167 -  int x = 0;
  30.168 -  while (cnt--)
  30.169 -    {
  30.170 -      x <<= 4;
  30.171 -      if (*p >= '0' && *p <= '9')
  30.172 -	x += (*p - '0');
  30.173 -      else if (*p >= 'a' && *p <= 'f')
  30.174 -	x += (*p - 'a' + 10);
  30.175 -      else if (*p >= 'A' && *p <= 'F')
  30.176 -	x += (*p - 'A' + 10);
  30.177 -      else
  30.178 -	return -1;
  30.179 -      p++;
  30.180 -    }
  30.181 -  return x;
  30.182 -}
  30.183 -
  30.184 -static inline int id_white_p(int c)
  30.185 -{
  30.186 -  return (c == ' ') || (c == '\t');
  30.187 -}
  30.188 -
  30.189 -static const char *id_parse_list(struct pci_access *a, pci_file f, int *lino)
  30.190 -{
  30.191 -  char line[MAX_LINE];
  30.192 -  char *p;
  30.193 -  int id1=0, id2=0, id3=0, id4=0;
  30.194 -  int cat = -1;
  30.195 -  int nest;
  30.196 -  static const char parse_error[] = "Parse error";
  30.197 -
  30.198 -  *lino = 0;
  30.199 -  while (pci_gets(f, line, sizeof(line)))
  30.200 -    {
  30.201 -      (*lino)++;
  30.202 -      p = line;
  30.203 -      while (*p && *p != '\n' && *p != '\r')
  30.204 -	p++;
  30.205 -      if (!*p && !pci_eof(f))
  30.206 -	return "Line too long";
  30.207 -      *p = 0;
  30.208 -      if (p > line && (p[-1] == ' ' || p[-1] == '\t'))
  30.209 -	*--p = 0;
  30.210 -
  30.211 -      p = line;
  30.212 -      while (id_white_p(*p))
  30.213 -	p++;
  30.214 -      if (!*p || *p == '#')
  30.215 -	continue;
  30.216 -
  30.217 -      p = line;
  30.218 -      while (*p == '\t')
  30.219 -	p++;
  30.220 -      nest = p - line;
  30.221 -
  30.222 -      if (!nest)					/* Top-level entries */
  30.223 -	{
  30.224 -	  if (p[0] == 'C' && p[1] == ' ')		/* Class block */
  30.225 -	    {
  30.226 -	      if ((id1 = id_hex(p+2, 2)) < 0 || !id_white_p(p[4]))
  30.227 -		return parse_error;
  30.228 -	      cat = ID_CLASS;
  30.229 -	      p += 5;
  30.230 -	    }
  30.231 -	  else if (p[0] == 'S' && p[1] == ' ')
  30.232 -	    {						/* Generic subsystem block */
  30.233 -	      if ((id1 = id_hex(p+2, 4)) < 0 || p[6])
  30.234 -		return parse_error;
  30.235 -	      if (!id_lookup(a, ID_VENDOR, id1, 0, 0, 0))
  30.236 -		return "Vendor does not exist";
  30.237 -	      cat = ID_GEN_SUBSYSTEM;
  30.238 -	      continue;
  30.239 -	    }
  30.240 -	  else if (p[0] >= 'A' && p[0] <= 'Z' && p[1] == ' ')
  30.241 -	    {						/* Unrecognized block (RFU) */
  30.242 -	      cat = ID_UNKNOWN;
  30.243 -	      continue;
  30.244 -	    }
  30.245 -	  else						/* Vendor ID */
  30.246 -	    {
  30.247 -	      if ((id1 = id_hex(p, 4)) < 0 || !id_white_p(p[4]))
  30.248 -		return parse_error;
  30.249 -	      cat = ID_VENDOR;
  30.250 -	      p += 5;
  30.251 -	    }
  30.252 -	  id2 = id3 = id4 = 0;
  30.253 -	}
  30.254 -      else if (cat == ID_UNKNOWN)			/* Nested entries in RFU blocks are skipped */
  30.255 -	continue;
  30.256 -      else if (nest == 1)				/* Nesting level 1 */
  30.257 -	switch (cat)
  30.258 -	  {
  30.259 -	  case ID_VENDOR:
  30.260 -	  case ID_DEVICE:
  30.261 -	  case ID_SUBSYSTEM:
  30.262 -	    if ((id2 = id_hex(p, 4)) < 0 || !id_white_p(p[4]))
  30.263 -	      return parse_error;
  30.264 -	    p += 5;
  30.265 -	    cat = ID_DEVICE;
  30.266 -	    id3 = id4 = 0;
  30.267 -	    break;
  30.268 -	  case ID_GEN_SUBSYSTEM:
  30.269 -	    if ((id2 = id_hex(p, 4)) < 0 || !id_white_p(p[4]))
  30.270 -	      return parse_error;
  30.271 -	    p += 5;
  30.272 -	    id3 = id4 = 0;
  30.273 -	    break;
  30.274 -	  case ID_CLASS:
  30.275 -	  case ID_SUBCLASS:
  30.276 -	  case ID_PROGIF:
  30.277 -	    if ((id2 = id_hex(p, 2)) < 0 || !id_white_p(p[2]))
  30.278 -	      return parse_error;
  30.279 -	    p += 3;
  30.280 -	    cat = ID_SUBCLASS;
  30.281 -	    id3 = id4 = 0;
  30.282 -	    break;
  30.283 -	  default:
  30.284 -	    return parse_error;
  30.285 -	  }
  30.286 -      else if (nest == 2)				/* Nesting level 2 */
  30.287 -	switch (cat)
  30.288 -	  {
  30.289 -	  case ID_DEVICE:
  30.290 -	  case ID_SUBSYSTEM:
  30.291 -	    if ((id3 = id_hex(p, 4)) < 0 || !id_white_p(p[4]) || (id4 = id_hex(p+5, 4)) < 0 || !id_white_p(p[9]))
  30.292 -	      return parse_error;
  30.293 -	    p += 10;
  30.294 -	    cat = ID_SUBSYSTEM;
  30.295 -	    break;
  30.296 -	  case ID_CLASS:
  30.297 -	  case ID_SUBCLASS:
  30.298 -	  case ID_PROGIF:
  30.299 -	    if ((id3 = id_hex(p, 2)) < 0 || !id_white_p(p[2]))
  30.300 -	      return parse_error;
  30.301 -	    p += 3;
  30.302 -	    cat = ID_PROGIF;
  30.303 -	    id4 = 0;
  30.304 -	    break;
  30.305 -	  default:
  30.306 -	    return parse_error;
  30.307 -	  }
  30.308 -      else						/* Nesting level 3 or more */
  30.309 -	return parse_error;
  30.310 -      while (id_white_p(*p))
  30.311 -	p++;
  30.312 -      if (!*p)
  30.313 -	return parse_error;
  30.314 -      if (id_insert(a, cat, id1, id2, id3, id4, p))
  30.315 -	return "Duplicate entry";
  30.316 -    }
  30.317 -  return NULL;
  30.318 -}
  30.319 -
  30.320 -int
  30.321 -pci_load_name_list(struct pci_access *a)
  30.322 -{
  30.323 -  pci_file f;
  30.324 -  int lino;
  30.325 -  const char *err;
  30.326 -
  30.327 -  pci_free_name_list(a);
  30.328 -  a->hash_load_failed = 1;
  30.329 -  if (!(f = pci_open(a)))
  30.330 -    return 0;
  30.331 -  a->id_hash = pci_malloc(a, sizeof(struct id_entry *) * HASH_SIZE);
  30.332 -  memset(a->id_hash, 0, sizeof(struct id_entry *) * HASH_SIZE);
  30.333 -  err = id_parse_list(a, f, &lino);
  30.334 -  PCI_ERROR(f, err);
  30.335 -  pci_close(f);
  30.336 -  if (err)
  30.337 -    a->error("%s at %s, line %d\n", err, a->id_file_name, lino);
  30.338 -  a->hash_load_failed = 0;
  30.339 -  return 1;
  30.340 -}
  30.341 -
  30.342 -void
  30.343 -pci_free_name_list(struct pci_access *a)
  30.344 -{
  30.345 -  pci_mfree(a->id_hash);
  30.346 -  a->id_hash = NULL;
  30.347 -  while (a->current_id_bucket)
  30.348 -    {
  30.349 -      struct id_bucket *buck = a->current_id_bucket;
  30.350 -      a->current_id_bucket = buck->next;
  30.351 -      pci_mfree(buck);
  30.352 -    }
  30.353 -}
  30.354 -
  30.355 -static char *
  30.356 -id_lookup_subsys(struct pci_access *a, int iv, int id, int isv, int isd)
  30.357 -{
  30.358 -  char *d = NULL;
  30.359 -  if (iv > 0 && id > 0)						/* Per-device lookup */
  30.360 -    d = id_lookup(a, ID_SUBSYSTEM, iv, id, isv, isd);
  30.361 -  if (!d)							/* Generic lookup */
  30.362 -    d = id_lookup(a, ID_GEN_SUBSYSTEM, isv, isd, 0, 0);
  30.363 -  if (!d && iv == isv && id == isd)				/* Check for subsystem == device */
  30.364 -    d = id_lookup(a, ID_DEVICE, iv, id, 0, 0);
  30.365 -  return d;
  30.366 -}
  30.367 -
  30.368 -static char *
  30.369 -format_name(char *buf, int size, int flags, char *name, char *num, char *unknown)
  30.370 -{
  30.371 -  int res;
  30.372 -  if ((flags & PCI_LOOKUP_NO_NUMBERS) && !name)
  30.373 -    return NULL;
  30.374 -  else if (flags & PCI_LOOKUP_NUMERIC)
  30.375 -    res = snprintf(buf, size, "%s", num);
  30.376 -  else if (!name)
  30.377 -    res = snprintf(buf, size, ((flags & PCI_LOOKUP_MIXED) ? "%s [%s]" : "%s %s"), unknown, num);
  30.378 -  else if (!(flags & PCI_LOOKUP_MIXED))
  30.379 -    res = snprintf(buf, size, "%s", name);
  30.380 -  else
  30.381 -    res = snprintf(buf, size, "%s [%s]", name, num);
  30.382 -  if (res < 0 || res >= size)
  30.383 -    return "<pci_lookup_name: buffer too small>";
  30.384 -  else
  30.385 -    return buf;
  30.386 -}
  30.387 -
  30.388 -static char *
  30.389 -format_name_pair(char *buf, int size, int flags, char *v, char *d, char *num)
  30.390 -{
  30.391 -  int res;
  30.392 -  if ((flags & PCI_LOOKUP_NO_NUMBERS) && (!v || !d))
  30.393 -    return NULL;
  30.394 -  if (flags & PCI_LOOKUP_NUMERIC)
  30.395 -    res = snprintf(buf, size, "%s", num);
  30.396 -  else if (flags & PCI_LOOKUP_MIXED)
  30.397 -    {
  30.398 -      if (v && d)
  30.399 -	res = snprintf(buf, size, "%s %s [%s]", v, d, num);
  30.400 -      else if (!v)
  30.401 -	res = snprintf(buf, size, "Unknown device [%s]", num);
  30.402 -      else /* v && !d */
  30.403 -	res = snprintf(buf, size, "%s Unknown device [%s]", v, num);
  30.404 -    }
  30.405 -  else
  30.406 -    {
  30.407 -      if (v && d)
  30.408 -	res = snprintf(buf, size, "%s %s", v, d);
  30.409 -      else if (!v)
  30.410 -	res = snprintf(buf, size, "Unknown device %s", num);
  30.411 -      else /* v && !d */
  30.412 -	res = snprintf(buf, size, "%s Unknown device %s", v, num+5);
  30.413 -    }
  30.414 -  if (res < 0 || res >= size)
  30.415 -    return "<pci_lookup_name: buffer too small>";
  30.416 -  else
  30.417 -    return buf;
  30.418 -}
  30.419 -
  30.420 -char *
  30.421 -pci_lookup_name(struct pci_access *a, char *buf, int size, int flags, ...)
  30.422 -{
  30.423 -  va_list args;
  30.424 -  char *v, *d, *cls, *pif;
  30.425 -  int iv, id, isv, isd, icls, ipif;
  30.426 -  char numbuf[16], pifbuf[32];
  30.427 -
  30.428 -  va_start(args, flags);
  30.429 -
  30.430 -  if (!(flags & PCI_LOOKUP_NO_NUMBERS))
  30.431 -    {
  30.432 -      if (a->numeric_ids > 1)
  30.433 -	flags |= PCI_LOOKUP_MIXED;
  30.434 -      else if (a->numeric_ids)
  30.435 -	flags |= PCI_LOOKUP_NUMERIC;
  30.436 -    }
  30.437 -  if (flags & PCI_LOOKUP_MIXED)
  30.438 -    flags &= ~PCI_LOOKUP_NUMERIC;
  30.439 -
  30.440 -  if (!a->id_hash && !(flags & PCI_LOOKUP_NUMERIC) && !a->hash_load_failed)
  30.441 -    pci_load_name_list(a);
  30.442 -
  30.443 -  switch (flags & 0xffff)
  30.444 -    {
  30.445 -    case PCI_LOOKUP_VENDOR:
  30.446 -      iv = va_arg(args, int);
  30.447 -      sprintf(numbuf, "%04x", iv);
  30.448 -      return format_name(buf, size, flags, id_lookup(a, ID_VENDOR, iv, 0, 0, 0), numbuf, "Unknown vendor");
  30.449 -    case PCI_LOOKUP_DEVICE:
  30.450 -      iv = va_arg(args, int);
  30.451 -      id = va_arg(args, int);
  30.452 -      sprintf(numbuf, "%04x", id);
  30.453 -      return format_name(buf, size, flags, id_lookup(a, ID_DEVICE, iv, id, 0, 0), numbuf, "Unknown device");
  30.454 -    case PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE:
  30.455 -      iv = va_arg(args, int);
  30.456 -      id = va_arg(args, int);
  30.457 -      sprintf(numbuf, "%04x:%04x", iv, id);
  30.458 -      v = id_lookup(a, ID_VENDOR, iv, 0, 0, 0);
  30.459 -      d = id_lookup(a, ID_DEVICE, iv, id, 0, 0);
  30.460 -      return format_name_pair(buf, size, flags, v, d, numbuf);
  30.461 -    case PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_VENDOR:
  30.462 -      isv = va_arg(args, int);
  30.463 -      sprintf(numbuf, "%04x", isv);
  30.464 -      v = id_lookup(a, ID_VENDOR, isv, 0, 0, 0);
  30.465 -      return format_name(buf, size, flags, v, numbuf, "Unknown vendor");
  30.466 -    case PCI_LOOKUP_SUBSYSTEM | PCI_LOOKUP_DEVICE:
  30.467 -      iv = va_arg(args, int);
  30.468 -      id = va_arg(args, int);
  30.469 -      isv = va_arg(args, int);
  30.470 -      isd = va_arg(args, int);
  30.471 -      sprintf(numbuf, "%04x", isd);
  30.472 -      return format_name(buf, size, flags, id_lookup_subsys(a, iv, id, isv, isd), numbuf, "Unknown device");
  30.473 -    case PCI_LOOKUP_VENDOR | PCI_LOOKUP_DEVICE | PCI_LOOKUP_SUBSYSTEM:
  30.474 -      iv = va_arg(args, int);
  30.475 -      id = va_arg(args, int);
  30.476 -      isv = va_arg(args, int);
  30.477 -      isd = va_arg(args, int);
  30.478 -      v = id_lookup(a, ID_VENDOR, isv, 0, 0, 0);
  30.479 -      d = id_lookup_subsys(a, iv, id, isv, isd);
  30.480 -      sprintf(numbuf, "%04x:%04x", isv, isd);
  30.481 -      return format_name_pair(buf, size, flags, v, d, numbuf);
  30.482 -    case PCI_LOOKUP_CLASS:
  30.483 -      icls = va_arg(args, int);
  30.484 -      sprintf(numbuf, "%04x", icls);
  30.485 -      cls = id_lookup(a, ID_SUBCLASS, icls >> 8, icls & 0xff, 0, 0);
  30.486 -      if (!cls && (cls = id_lookup(a, ID_CLASS, icls >> 8, 0, 0, 0)))
  30.487 -	{
  30.488 -	  if (!(flags & PCI_LOOKUP_NUMERIC)) /* Include full class number */
  30.489 -	    flags |= PCI_LOOKUP_MIXED;
  30.490 -	}
  30.491 -      return format_name(buf, size, flags, cls, numbuf, ((flags & PCI_LOOKUP_MIXED) ? "Unknown class" : "Class"));
  30.492 -    case PCI_LOOKUP_PROGIF:
  30.493 -      icls = va_arg(args, int);
  30.494 -      ipif = va_arg(args, int);
  30.495 -      sprintf(numbuf, "%02x", ipif);
  30.496 -      pif = id_lookup(a, ID_PROGIF, icls >> 8, icls & 0xff, ipif, 0);
  30.497 -      if (!pif && icls == 0x0101 && !(ipif & 0x70))
  30.498 -	{
  30.499 -	  /* IDE controllers have complex prog-if semantics */
  30.500 -	  sprintf(pifbuf, "%s%s%s%s%s",
  30.501 -		  (ipif & 0x80) ? " Master" : "",
  30.502 -		  (ipif & 0x08) ? " SecP" : "",
  30.503 -		  (ipif & 0x04) ? " SecO" : "",
  30.504 -		  (ipif & 0x02) ? " PriP" : "",
  30.505 -		  (ipif & 0x01) ? " PriO" : "");
  30.506 -	  pif = pifbuf;
  30.507 -	  if (*pif)
  30.508 -	    pif++;
  30.509 -	}
  30.510 -      return format_name(buf, size, flags, pif, numbuf, "ProgIf");
  30.511 -    default:
  30.512 -      return "<pci_lookup_name: invalid request>";
  30.513 -    }
  30.514 -}
  30.515 -
  30.516 -void pci_set_name_list_path(struct pci_access *a, char *name, int to_be_freed)
  30.517 -{
  30.518 -  if (a->free_id_name)
  30.519 -    free(a->id_file_name);
  30.520 -  a->id_file_name = name;
  30.521 -  a->free_id_name = to_be_freed;
  30.522 -}
    31.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/nbsd-libpci.c	Thu Aug 23 13:42:03 2007 -0700
    31.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    31.3 @@ -1,157 +0,0 @@
    31.4 -/*
    31.5 - *	The PCI Library -- NetBSD libpci access
    31.6 - *         (based on FreeBSD /dev/pci access)
    31.7 - *
    31.8 - *	Copyright (c) 1999 Jari Kirma <kirma@cs.hut.fi>
    31.9 - *      Copyright (c) 2002 Quentin Garnier <cube@cubidou.net>
   31.10 - *	Copyright (c) 2002 Martin Mares <mj@ucw.cz>
   31.11 - *
   31.12 - *	Can be freely distributed and used under the terms of the GNU GPL.
   31.13 - */
   31.14 -
   31.15 -/*
   31.16 - *      Read functionality of this driver is briefly tested, and seems
   31.17 - *      to supply basic information correctly, but I promise no more.
   31.18 - */
   31.19 -
   31.20 -#include <fcntl.h>
   31.21 -#include <string.h>
   31.22 -#include <unistd.h>
   31.23 -
   31.24 -#include <pci.h>
   31.25 -
   31.26 -#include "internal.h"
   31.27 -
   31.28 -static void
   31.29 -nbsd_config(struct pci_access *a)
   31.30 -{
   31.31 -  a->method_params[PCI_ACCESS_NBSD_LIBPCI] = PCI_PATH_NBSD_DEVICE;
   31.32 -}
   31.33 -
   31.34 -static int
   31.35 -nbsd_detect(struct pci_access *a)
   31.36 -{
   31.37 -  char *name = a->method_params[PCI_ACCESS_NBSD_LIBPCI];
   31.38 -
   31.39 -  if (access(name, R_OK))
   31.40 -    {
   31.41 -      a->warning("Cannot open %s", name);
   31.42 -      return 0;
   31.43 -    }
   31.44 -
   31.45 -  if (!access(name, W_OK))
   31.46 -    {
   31.47 -      a->writeable = O_RDWR;
   31.48 -    }
   31.49 -  a->debug("...using %s", name);
   31.50 -  return 1;
   31.51 -}
   31.52 -
   31.53 -static void
   31.54 -nbsd_init(struct pci_access *a)
   31.55 -{
   31.56 -  char *name = a->method_params[PCI_ACCESS_NBSD_LIBPCI];
   31.57 -  int mode = a->writeable ? O_RDWR : O_RDONLY;
   31.58 -
   31.59 -  a->fd = open(name, mode, 0);
   31.60 -  if (a->fd < 0)
   31.61 -    a->error("nbsd_init: %s open failed", name);
   31.62 -}
   31.63 -
   31.64 -static void
   31.65 -nbsd_cleanup(struct pci_access *a)
   31.66 -{
   31.67 -  close(a->fd);
   31.68 -}
   31.69 -
   31.70 -static int
   31.71 -nbsd_read(struct pci_dev *d, int pos, byte *buf, int len)
   31.72 -{
   31.73 -  pcireg_t val;
   31.74 -  int shift;
   31.75 -
   31.76 -  if (!(len == 1 || len == 2 || len == 4))
   31.77 -    return pci_generic_block_read(d, pos, buf, len);
   31.78 -
   31.79 -  if (pos >= 256)
   31.80 -    return 0;
   31.81 -
   31.82 -  shift = 8*(pos % 4);
   31.83 -  pos &= ~3;
   31.84 -
   31.85 -  if (pcibus_conf_read(d->access->fd, d->bus, d->dev, d->func, pos, &val) < 0)
   31.86 -    d->access->error("nbsd_read: pci_bus_conf_read() failed");
   31.87 -
   31.88 -  switch (len)
   31.89 -    {
   31.90 -    case 1:
   31.91 -      *buf = val >> shift;
   31.92 -      break;
   31.93 -    case 2:
   31.94 -      *(u16*)buf = cpu_to_le16(val >> shift);
   31.95 -      break;
   31.96 -    case 4:
   31.97 -      *(u32*)buf = cpu_to_le32(val);
   31.98 -      break;
   31.99 -    }
  31.100 -  return 1;
  31.101 -}
  31.102 -
  31.103 -static int
  31.104 -nbsd_write(struct pci_dev *d, int pos, byte *buf, int len)
  31.105 -{
  31.106 -  pcireg_t val = 0;
  31.107 -  int shift;
  31.108 -
  31.109 -  if (!(len == 1 || len == 2 || len == 4))
  31.110 -    return pci_generic_block_write(d, pos, buf, len);
  31.111 -
  31.112 -  if (pos >= 256)
  31.113 -    return 0;
  31.114 -
  31.115 -  /*
  31.116 -   *  BEWARE: NetBSD seems to support only 32-bit access, so we have
  31.117 -   *  to emulate byte and word writes by read-modify-write, possibly
  31.118 -   *  causing troubles.
  31.119 -   */
  31.120 -
  31.121 -  shift = 8*(pos % 4);
  31.122 -  pos &= ~3;
  31.123 -  if (len != 4)
  31.124 -    {
  31.125 -      if (pcibus_conf_read(d->access->fd, d->bus, d->dev, d->func, pos, &val) < 0)
  31.126 -	d->access->error("nbsd_write: pci_bus_conf_read() failed");
  31.127 -    }
  31.128 -
  31.129 -  switch (len)
  31.130 -    {
  31.131 -    case 1:
  31.132 -      val = (val & ~(0xff << shift)) | (buf[0] << shift);
  31.133 -      break;
  31.134 -    case 2:
  31.135 -      val = (val & ~(0xffff << shift)) | (le16_to_cpu(*(u16*)buf) << shift);
  31.136 -      break;
  31.137 -    case 4:
  31.138 -      val = le32_to_cpu(*(u32*)buf);
  31.139 -      break;
  31.140 -    }
  31.141 -
  31.142 -  if (pcibus_conf_write(d->access->fd, d->bus, d->dev, d->func, pos, val) < 0)
  31.143 -    d->access->error("nbsd_write: pci_bus_conf_write() failed");
  31.144 -
  31.145 -  return 1;
  31.146 -}
  31.147 -
  31.148 -struct pci_methods pm_nbsd_libpci = {
  31.149 -  "NetBSD-libpci",
  31.150 -  nbsd_config,
  31.151 -  nbsd_detect,
  31.152 -  nbsd_init,
  31.153 -  nbsd_cleanup,
  31.154 -  pci_generic_scan,
  31.155 -  pci_generic_fill_info,
  31.156 -  nbsd_read,
  31.157 -  nbsd_write,
  31.158 -  NULL,                                 /* dev_init */
  31.159 -  NULL                                  /* dev_cleanup */
  31.160 -};
    32.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/obsd-device.c	Thu Aug 23 13:42:03 2007 -0700
    32.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    32.3 @@ -1,159 +0,0 @@
    32.4 -/*
    32.5 - *	The PCI Library -- OpenBSD /dev/pci access
    32.6 - *
    32.7 - *	Adapted from fbsd-device.c by Matthieu Herrb <matthieu.herrb@laas.fr>, 2006
    32.8 - *
    32.9 - *	Can be freely distributed and used under the terms of the GNU GPL.
   32.10 - */
   32.11 -
   32.12 -#include <fcntl.h>
   32.13 -#include <string.h>
   32.14 -#include <unistd.h>
   32.15 -#include <errno.h>
   32.16 -#include <sys/endian.h>
   32.17 -#include <sys/types.h>
   32.18 -#include <sys/ioctl.h>
   32.19 -#include <sys/pciio.h>
   32.20 -#include "internal.h"
   32.21 -
   32.22 -static void
   32.23 -obsd_config(struct pci_access *a)
   32.24 -{
   32.25 -  a->method_params[PCI_ACCESS_OBSD_DEVICE] = PCI_PATH_OBSD_DEVICE;
   32.26 -}
   32.27 -
   32.28 -static int
   32.29 -obsd_detect(struct pci_access *a)
   32.30 -{
   32.31 -  char *name = a->method_params[PCI_ACCESS_OBSD_DEVICE];
   32.32 -
   32.33 -  if (access(name, R_OK))
   32.34 -    {
   32.35 -      a->warning("Cannot open %s", name);
   32.36 -      return 0;
   32.37 -    }
   32.38 -  a->debug("...using %s", name);
   32.39 -  return 1;
   32.40 -}
   32.41 -
   32.42 -static void
   32.43 -obsd_init(struct pci_access *a)
   32.44 -{
   32.45 -  char *name = a->method_params[PCI_ACCESS_OBSD_DEVICE];
   32.46 -
   32.47 -  a->fd = open(name, O_RDWR, 0);
   32.48 -  if (a->fd < 0)
   32.49 -    {
   32.50 -      a->error("obsd_init: %s open failed", name);
   32.51 -    }
   32.52 -}
   32.53 -
   32.54 -static void
   32.55 -obsd_cleanup(struct pci_access *a)
   32.56 -{
   32.57 -  close(a->fd);
   32.58 -}
   32.59 -
   32.60 -static int
   32.61 -obsd_read(struct pci_dev *d, int pos, byte *buf, int len)
   32.62 -{
   32.63 -  struct pci_io pi;
   32.64 -  union {
   32.65 -	  u_int32_t u32;
   32.66 -	  u_int16_t u16[2];
   32.67 -	  u_int8_t u8[4];
   32.68 -  } u;
   32.69 -
   32.70 -  if (!(len == 1 || len == 2 || len == 4))
   32.71 -    {
   32.72 -      return pci_generic_block_read(d, pos, buf, len);
   32.73 -    }
   32.74 -
   32.75 -  if (pos >= 256)
   32.76 -    return 0;
   32.77 -
   32.78 -  pi.pi_sel.pc_bus = d->bus;
   32.79 -  pi.pi_sel.pc_dev = d->dev;
   32.80 -  pi.pi_sel.pc_func = d->func;
   32.81 -
   32.82 -  pi.pi_reg = pos - (pos % 4);
   32.83 -  pi.pi_width = 4;
   32.84 -
   32.85 -  if (ioctl(d->access->fd, PCIOCREAD, &pi) < 0) {
   32.86 -	  if (errno == ENXIO) {
   32.87 -		  pi.pi_data = 0xffffffff;
   32.88 -	  } else {
   32.89 -		  d->access->error("obsd_read: ioctl(PCIOCREAD) failed");
   32.90 -	  }
   32.91 -  }
   32.92 -  u.u32 = pi.pi_data;
   32.93 -
   32.94 -  switch (len)
   32.95 -    {
   32.96 -    case 1:
   32.97 -      buf[0] = (u8) u.u8[pos % 4];
   32.98 -      break;
   32.99 -    case 2:
  32.100 -      ((u16 *) buf)[0] = letoh16(u.u16[(pos % 4) / 2]);
  32.101 -      break;
  32.102 -    case 4:
  32.103 -      ((u32 *) buf)[0] = (u32) letoh32(pi.pi_data);
  32.104 -      break;
  32.105 -    }
  32.106 -  return 1;
  32.107 -}
  32.108 -
  32.109 -static int
  32.110 -obsd_write(struct pci_dev *d, int pos, byte *buf, int len)
  32.111 -{
  32.112 -  struct pci_io pi;
  32.113 -
  32.114 -  if (!(len == 1 || len == 2 || len == 4))
  32.115 -    {
  32.116 -      return pci_generic_block_write(d, pos, buf, len);
  32.117 -    }
  32.118 -
  32.119 -  if (pos >= 256)
  32.120 -    return 0;
  32.121 -
  32.122 -  pi.pi_sel.pc_bus = d->bus;
  32.123 -  pi.pi_sel.pc_dev = d->dev;
  32.124 -  pi.pi_sel.pc_func = d->func;
  32.125 -
  32.126 -  pi.pi_reg = pos;
  32.127 -  pi.pi_width = len;
  32.128 -
  32.129 -  switch (len)
  32.130 -    {
  32.131 -    case 1:
  32.132 -      pi.pi_data = buf[0];
  32.133 -      break;
  32.134 -    case 2:
  32.135 -      pi.pi_data = ((u16 *) buf)[0];
  32.136 -      break;
  32.137 -    case 4:
  32.138 -      pi.pi_data = ((u32 *) buf)[0];
  32.139 -      break;
  32.140 -    }
  32.141 -
  32.142 -  if (ioctl(d->access->fd, PCIOCWRITE, &pi) < 0)
  32.143 -    {
  32.144 -      d->access->error("obsd_write: ioctl(PCIOCWRITE) failed");
  32.145 -    }
  32.146 -
  32.147 -  return 1;
  32.148 -}
  32.149 -
  32.150 -struct pci_methods pm_obsd_device = {
  32.151 -  "OpenBSD-device",
  32.152 -  obsd_config,
  32.153 -  obsd_detect,
  32.154 -  obsd_init,
  32.155 -  obsd_cleanup,
  32.156 -  pci_generic_scan,
  32.157 -  pci_generic_fill_info,
  32.158 -  obsd_read,
  32.159 -  obsd_write,
  32.160 -  NULL,                                 /* dev_init */
  32.161 -  NULL                                  /* dev_cleanup */
  32.162 -};
    33.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/pci.h	Thu Aug 23 13:42:03 2007 -0700
    33.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    33.3 @@ -1,181 +0,0 @@
    33.4 -/*
    33.5 - *	The PCI Library
    33.6 - *
    33.7 - *	Copyright (c) 1997--2006 Martin Mares <mj@ucw.cz>
    33.8 - *
    33.9 - *	Can be freely distributed and used under the terms of the GNU GPL.
   33.10 - */
   33.11 -
   33.12 -#ifndef _PCI_LIB_H
   33.13 -#define _PCI_LIB_H
   33.14 -
   33.15 -#include "config.h"
   33.16 -#include "header.h"
   33.17 -#include "types.h"
   33.18 -
   33.19 -#define PCI_LIB_VERSION 0x020204
   33.20 -
   33.21 -/*
   33.22 - *	PCI Access Structure
   33.23 - */
   33.24 -
   33.25 -struct pci_methods;
   33.26 -
   33.27 -enum pci_access_type {
   33.28 -  /* Known access methods, remember to update access.c as well */
   33.29 -  PCI_ACCESS_AUTO,			/* Autodetection (params: none) */
   33.30 -  PCI_ACCESS_SYS_BUS_PCI,		/* Linux /sys/bus/pci (params: path) */
   33.31 -  PCI_ACCESS_PROC_BUS_PCI,		/* Linux /proc/bus/pci (params: path) */
   33.32 -  PCI_ACCESS_I386_TYPE1,		/* i386 ports, type 1 (params: none) */
   33.33 -  PCI_ACCESS_I386_TYPE2,		/* i386 ports, type 2 (params: none) */
   33.34 -  PCI_ACCESS_FBSD_DEVICE,		/* FreeBSD /dev/pci (params: path) */
   33.35 -  PCI_ACCESS_AIX_DEVICE,		/* /dev/pci0, /dev/bus0, etc. */
   33.36 -  PCI_ACCESS_NBSD_LIBPCI,		/* NetBSD libpci */
   33.37 -  PCI_ACCESS_OBSD_DEVICE,		/* OpenBSD /dev/pci */
   33.38 -  PCI_ACCESS_DUMP,			/* Dump file (params: filename) */
   33.39 -  PCI_ACCESS_MAX
   33.40 -};
   33.41 -
   33.42 -struct pci_access {
   33.43 -  /* Options you can change: */
   33.44 -  unsigned int method;			/* Access method */
   33.45 -  char *method_params[PCI_ACCESS_MAX];	/* Parameters for the methods */
   33.46 -  int writeable;			/* Open in read/write mode */
   33.47 -  int buscentric;			/* Bus-centric view of the world */
   33.48 -  char *id_file_name;			/* Name of ID list file */
   33.49 -  int free_id_name;			/* Set if id_file_name is malloced */
   33.50 -  int numeric_ids;			/* Enforce PCI_LOOKUP_NUMERIC (>1 => PCI_LOOKUP_MIXED) */
   33.51 -  int debugging;			/* Turn on debugging messages */
   33.52 -
   33.53 -  /* Functions you can override: */
   33.54 -  void (*error)(char *msg, ...);	/* Write error message and quit */
   33.55 -  void (*warning)(char *msg, ...);	/* Write a warning message */
   33.56 -  void (*debug)(char *msg, ...);	/* Write a debugging message */
   33.57 -
   33.58 -  struct pci_dev *devices;		/* Devices found on this bus */
   33.59 -
   33.60 -  /* Fields used internally: */
   33.61 -  struct pci_methods *methods;
   33.62 -  struct id_entry **id_hash;		/* names.c */
   33.63 -  struct id_bucket *current_id_bucket;
   33.64 -  int hash_load_failed;
   33.65 -  int fd;				/* proc: fd */
   33.66 -  int fd_rw;				/* proc: fd opened read-write */
   33.67 -  struct pci_dev *cached_dev;		/* proc: device the fd is for */
   33.68 -#ifdef PT_LIBPCI
   33.69 -  u8 cached_b, cached_d, cached_f;    /* proc: cached device bdf */
   33.70 -#endif
   33.71 -  int fd_pos;				/* proc: current position */
   33.72 -};
   33.73 -
   33.74 -/* Initialize PCI access */
   33.75 -struct pci_access *pci_alloc(void);
   33.76 -void pci_init(struct pci_access *);
   33.77 -void pci_cleanup(struct pci_access *);
   33.78 -
   33.79 -/* Scanning of devices */
   33.80 -void pci_scan_bus(struct pci_access *acc);
   33.81 -struct pci_dev *pci_get_dev(struct pci_access *acc, int domain, int bus, int dev, int func); /* Raw access to specified device */
   33.82 -void pci_free_dev(struct pci_dev *);
   33.83 -
   33.84 -/*
   33.85 - *	Devices
   33.86 - */
   33.87 -
   33.88 -struct pci_dev {
   33.89 -  struct pci_dev *next;			/* Next device in the chain */
   33.90 -  u16 domain;				/* PCI domain (host bridge) */
   33.91 -  u8 bus, dev, func;			/* Bus inside domain, device and function */
   33.92 -
   33.93 -  /* These fields are set by pci_fill_info() */
   33.94 -  int known_fields;			/* Set of info fields already known */
   33.95 -  u16 vendor_id, device_id;		/* Identity of the device */
   33.96 -  u16 device_class;			/* PCI device class */
   33.97 -  int irq;				/* IRQ number */
   33.98 -  pciaddr_t base_addr[6];		/* Base addresses */
   33.99 -  pciaddr_t size[6];			/* Region sizes */
  33.100 -  pciaddr_t rom_base_addr;		/* Expansion ROM base address */
  33.101 -  pciaddr_t rom_size;			/* Expansion ROM size */
  33.102 -
  33.103 -  /* Fields used internally: */
  33.104 -  struct pci_access *access;
  33.105 -  struct pci_methods *methods;
  33.106 -  u8 *cache;				/* Cached config registers */
  33.107 -  int cache_len;
  33.108 -  int hdrtype;				/* Cached low 7 bits of header type, -1 if unknown */
  33.109 -  void *aux;				/* Auxillary data */
  33.110 -};
  33.111 -
  33.112 -#define PCI_ADDR_IO_MASK (~(pciaddr_t) 0x3)
  33.113 -#define PCI_ADDR_MEM_MASK (~(pciaddr_t) 0xf)
  33.114 -
  33.115 -#ifndef PT_LIBPCI
  33.116 -u8 pci_read_byte(struct pci_dev *, int pos); /* Access to configuration space */
  33.117 -u16 pci_read_word(struct pci_dev *, int pos);
  33.118 -u32  pci_read_long(struct pci_dev *, int pos);
  33.119 -int pci_read_block(struct pci_dev *, int pos, u8 *buf, int len);
  33.120 -int pci_write_byte(struct pci_dev *, int pos, u8 data);
  33.121 -int pci_write_word(struct pci_dev *, int pos, u16 data);
  33.122 -int pci_write_long(struct pci_dev *, int pos, u32 data);
  33.123 -int pci_write_block(struct pci_dev *, int pos, u8 *buf, int len);
  33.124 -#endif
  33.125 -int pci_fill_info(struct pci_dev *, int flags); /* Fill in device information */
  33.126 -
  33.127 -#define PCI_FILL_IDENT		1
  33.128 -#define PCI_FILL_IRQ		2
  33.129 -#define PCI_FILL_BASES		4
  33.130 -#define PCI_FILL_ROM_BASE	8
  33.131 -#define PCI_FILL_SIZES		16
  33.132 -#define PCI_FILL_CLASS		32
  33.133 -#define PCI_FILL_RESCAN		0x10000
  33.134 -
  33.135 -void pci_setup_cache(struct pci_dev *, u8 *cache, int len);
  33.136 -
  33.137 -/*
  33.138 - *	Filters
  33.139 - */
  33.140 -
  33.141 -struct pci_filter {
  33.142 -  int domain, bus, slot, func;			/* -1 = ANY */
  33.143 -  int vendor, device;
  33.144 -};
  33.145 -
  33.146 -void pci_filter_init(struct pci_access *, struct pci_filter *);
  33.147 -char *pci_filter_parse_slot(struct pci_filter *, char *);
  33.148 -char *pci_filter_parse_id(struct pci_filter *, char *);
  33.149 -int pci_filter_match(struct pci_filter *, struct pci_dev *);
  33.150 -
  33.151 -/*
  33.152 - *	Conversion of PCI ID's to names (according to the pci.ids file)
  33.153 - *
  33.154 - *	Call pci_lookup_name() to identify different types of ID's:
  33.155 - *
  33.156 - *	VENDOR				(vendorID) -> vendor
  33.157 - *	DEVICE				(vendorID, deviceID) -> device
  33.158 - *	VENDOR | DEVICE			(vendorID, deviceID) -> combined vendor and device
  33.159 - *	SUBSYSTEM | VENDOR		(subvendorID) -> subsystem vendor
  33.160 - *	SUBSYSTEM | DEVICE		(vendorID, deviceID, subvendorID, subdevID) -> subsystem device
  33.161 - *	SUBSYSTEM | VENDOR | DEVICE	(vendorID, deviceID, subvendorID, subdevID) -> combined subsystem v+d
  33.162 - *	SUBSYSTEM | ...			(-1, -1, subvendorID, subdevID) -> generic subsystem
  33.163 - *	CLASS				(classID) -> class
  33.164 - *	PROGIF				(classID, progif) -> programming interface
  33.165 - */
  33.166 -
  33.167 -char *pci_lookup_name(struct pci_access *a, char *buf, int size, int flags, ...);
  33.168 -
  33.169 -int pci_load_name_list(struct pci_access *a);	/* Called automatically by pci_lookup_*() when needed; returns success */
  33.170 -void pci_free_name_list(struct pci_access *a);	/* Called automatically by pci_cleanup() */
  33.171 -void pci_set_name_list_path(struct pci_access *a, char *name, int to_be_freed);
  33.172 -
  33.173 -enum pci_lookup_mode {
  33.174 -  PCI_LOOKUP_VENDOR = 1,		/* Vendor name (args: vendorID) */
  33.175 -  PCI_LOOKUP_DEVICE = 2,		/* Device name (args: vendorID, deviceID) */
  33.176 -  PCI_LOOKUP_CLASS = 4,			/* Device class (args: classID) */
  33.177 -  PCI_LOOKUP_SUBSYSTEM = 8,
  33.178 -  PCI_LOOKUP_PROGIF = 16,		/* Programming interface (args: classID, prog_if) */
  33.179 -  PCI_LOOKUP_NUMERIC = 0x10000,		/* Want only formatted numbers; default if access->numeric_ids is set */
  33.180 -  PCI_LOOKUP_NO_NUMBERS = 0x20000,	/* Return NULL if not found in the database; default is to print numerically */
  33.181 -  PCI_LOOKUP_MIXED = 0x40000,		/* Include both numbers and names */
  33.182 -};
  33.183 -
  33.184 -#endif
    34.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/pread.h	Thu Aug 23 13:42:03 2007 -0700
    34.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    34.3 @@ -1,66 +0,0 @@
    34.4 -/*
    34.5 - *	The PCI Library -- Portable interface to pread() and pwrite()
    34.6 - *
    34.7 - *	Copyright (c) 1997--2003 Martin Mares <mj@ucw.cz>
    34.8 - *
    34.9 - *	Can be freely distributed and used under the terms of the GNU GPL.
   34.10 - */
   34.11 -
   34.12 -/*
   34.13 - *  We'd like to use pread/pwrite for configuration space accesses, but
   34.14 - *  unfortunately it isn't simple at all since all libc's until glibc 2.1
   34.15 - *  don't define it.
   34.16 - */
   34.17 -
   34.18 -#if defined(__GLIBC__) && __GLIBC__ == 2 && __GLIBC_MINOR__ > 0
   34.19 -/* glibc 2.1 or newer -> pread/pwrite supported automatically */
   34.20 -
   34.21 -#elif defined(i386) && defined(__GLIBC__)
   34.22 -/* glibc 2.0 on i386 -> call syscalls directly */
   34.23 -#include <asm/unistd.h>
   34.24 -#include <syscall-list.h>
   34.25 -#ifndef SYS_pread
   34.26 -#define SYS_pread 180
   34.27 -#endif
   34.28 -static int pread(unsigned int fd, void *buf, size_t size, loff_t where)
   34.29 -{ return syscall(SYS_pread, fd, buf, size, where); }
   34.30 -#ifndef SYS_pwrite
   34.31 -#define SYS_pwrite 181
   34.32 -#endif
   34.33 -static int pwrite(unsigned int fd, void *buf, size_t size, loff_t where)
   34.34 -{ return syscall(SYS_pwrite, fd, buf, size, where); }
   34.35 -
   34.36 -#elif defined(i386)
   34.37 -/* old libc on i386 -> call syscalls directly the old way */
   34.38 -#include <asm/unistd.h>
   34.39 -static _syscall5(int, pread, unsigned int, fd, void *, buf, size_t, size, u32, where_lo, u32, where_hi);
   34.40 -static _syscall5(int, pwrite, unsigned int, fd, void *, buf, size_t, size, u32, where_lo, u32, where_hi);
   34.41 -static int do_read(struct pci_dev *d UNUSED, int fd, void *buf, size_t size, int where) { return pread(fd, buf, size, where, 0); }
   34.42 -static int do_write(struct pci_dev *d UNUSED, int fd, void *buf, size_t size, int where) { return pwrite(fd, buf, size, where, 0); }
   34.43 -#define PCI_HAVE_DO_READ
   34.44 -
   34.45 -#else
   34.46 -/* In all other cases we use lseek/read/write instead to be safe */
   34.47 -#define make_rw_glue(op) \
   34.48 -	static int do_##op(struct pci_dev *d, int fd, void *buf, size_t size, int where)	\
   34.49 -	{											\
   34.50 -	  struct pci_access *a = d->access;							\
   34.51 -	  int r;										\
   34.52 -	  if (a->fd_pos != where && lseek(fd, where, SEEK_SET) < 0)				\
   34.53 -	    return -1;										\
   34.54 -	  r = op(fd, buf, size);								\
   34.55 -	  if (r < 0)										\
   34.56 -	    a->fd_pos = -1;									\
   34.57 -	  else											\
   34.58 -	    a->fd_pos = where + r;								\
   34.59 -	  return r;										\
   34.60 -	}
   34.61 -make_rw_glue(read)
   34.62 -make_rw_glue(write)
   34.63 -#define PCI_HAVE_DO_READ
   34.64 -#endif
   34.65 -
   34.66 -#ifndef PCI_HAVE_DO_READ
   34.67 -#define do_read(d,f,b,l,p) pread(f,b,l,p)
   34.68 -#define do_write(d,f,b,l,p) pwrite(f,b,l,p)
   34.69 -#endif
    35.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/proc.c	Thu Aug 23 13:42:03 2007 -0700
    35.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    35.3 @@ -1,226 +0,0 @@
    35.4 -/*
    35.5 - *	The PCI Library -- Configuration Access via /proc/bus/pci
    35.6 - *
    35.7 - *	Copyright (c) 1997--2003 Martin Mares <mj@ucw.cz>
    35.8 - *
    35.9 - *	Can be freely distributed and used under the terms of the GNU GPL.
   35.10 - */
   35.11 -
   35.12 -#define _GNU_SOURCE
   35.13 -
   35.14 -#include <stdio.h>
   35.15 -#include <string.h>
   35.16 -#include <unistd.h>
   35.17 -#include <errno.h>
   35.18 -#include <fcntl.h>
   35.19 -#include <sys/types.h>
   35.20 -
   35.21 -#include "internal.h"
   35.22 -#include "pread.h"
   35.23 -
   35.24 -static void
   35.25 -proc_config(struct pci_access *a)
   35.26 -{
   35.27 -  a->method_params[PCI_ACCESS_PROC_BUS_PCI] = PCI_PATH_PROC_BUS_PCI;
   35.28 -}
   35.29 -
   35.30 -static int
   35.31 -proc_detect(struct pci_access *a)
   35.32 -{
   35.33 -  char *name = a->method_params[PCI_ACCESS_PROC_BUS_PCI];
   35.34 -
   35.35 -  if (access(name, R_OK))
   35.36 -    {
   35.37 -      a->warning("Cannot open %s", name);
   35.38 -      return 0;
   35.39 -    }
   35.40 -  a->debug("...using %s", name);
   35.41 -  return 1;
   35.42 -}
   35.43 -
   35.44 -static void
   35.45 -proc_init(struct pci_access *a)
   35.46 -{
   35.47 -  a->fd = -1;
   35.48 -#ifdef PT_LIBPCI
   35.49 -  a->cached_b = -1;
   35.50 -  a->cached_d = -1;
   35.51 -  a->cached_f = -1;
   35.52 -#endif
   35.53 -}
   35.54 -
   35.55 -static void
   35.56 -proc_cleanup(struct pci_access *a)
   35.57 -{
   35.58 -  if (a->fd >= 0)
   35.59 -    {
   35.60 -      close(a->fd);
   35.61 -      a->fd = -1;
   35.62 -    }
   35.63 -}
   35.64 -
   35.65 -static void
   35.66 -proc_scan(struct pci_access *a)
   35.67 -{
   35.68 -  FILE *f;
   35.69 -  char buf[512];
   35.70 -
   35.71 -  if (snprintf(buf, sizeof(buf), "%s/devices", a->method_params[PCI_ACCESS_PROC_BUS_PCI]) == sizeof(buf))
   35.72 -    a->error("File name too long");
   35.73 -  f = fopen(buf, "r");
   35.74 -  if (!f)
   35.75 -    a->error("Cannot open %s", buf);
   35.76 -  while (fgets(buf, sizeof(buf)-1, f))
   35.77 -    {
   35.78 -      struct pci_dev *d = pci_alloc_dev(a);
   35.79 -      unsigned int dfn, vend, cnt, known;
   35.80 -
   35.81 -#define F " " PCIADDR_T_FMT
   35.82 -      cnt = sscanf(buf, "%x %x %x" F F F F F F F F F F F F F F,
   35.83 -	     &dfn,
   35.84 -	     &vend,
   35.85 -	     &d->irq,
   35.86 -	     &d->base_addr[0],
   35.87 -	     &d->base_addr[1],
   35.88 -	     &d->base_addr[2],
   35.89 -	     &d->base_addr[3],
   35.90 -	     &d->base_addr[4],
   35.91 -	     &d->base_addr[5],
   35.92 -	     &d->rom_base_addr,
   35.93 -	     &d->size[0],
   35.94 -	     &d->size[1],
   35.95 -	     &d->size[2],
   35.96 -	     &d->size[3],
   35.97 -	     &d->size[4],
   35.98 -	     &d->size[5],
   35.99 -	     &d->rom_size);
  35.100 -#undef F
  35.101 -      if (cnt != 9 && cnt != 10 && cnt != 17)
  35.102 -	a->error("proc: parse error (read only %d items)", cnt);
  35.103 -      d->bus = dfn >> 8U;
  35.104 -      d->dev = PCI_SLOT(dfn & 0xff);
  35.105 -      d->func = PCI_FUNC(dfn & 0xff);
  35.106 -      d->vendor_id = vend >> 16U;
  35.107 -      d->device_id = vend & 0xffff;
  35.108 -      known = PCI_FILL_IDENT;
  35.109 -      if (!a->buscentric)
  35.110 -	{
  35.111 -	  known |= PCI_FILL_IRQ | PCI_FILL_BASES;
  35.112 -	  if (cnt >= 10)
  35.113 -	    known |= PCI_FILL_ROM_BASE;
  35.114 -	  if (cnt >= 17)
  35.115 -	    known |= PCI_FILL_SIZES;
  35.116 -	}
  35.117 -      d->known_fields = known;
  35.118 -      pci_link_dev(a, d);
  35.119 -    }
  35.120 -  fclose(f);
  35.121 -}
  35.122 -
  35.123 -static int
  35.124 -proc_setup(struct pci_dev *d, int rw)
  35.125 -{
  35.126 -  struct pci_access *a = d->access;
  35.127 -
  35.128 -#ifndef PT_LIBPCI
  35.129 -  if (a->cached_dev != d || a->fd_rw < rw)
  35.130 -#else
  35.131 -  if (a->cached_b != d->bus || 
  35.132 -      a->cached_d != d->dev ||
  35.133 -      a->cached_f != d->func || 
  35.134 -      a->fd_rw < rw)
  35.135 -#endif
  35.136 -    {
  35.137 -      char buf[1024];
  35.138 -      int e;
  35.139 -      if (a->fd >= 0)
  35.140 -	close(a->fd);
  35.141 -      e = snprintf(buf, sizeof(buf), "%s/%02x/%02x.%d",
  35.142 -		   a->method_params[PCI_ACCESS_PROC_BUS_PCI],
  35.143 -		   d->bus, d->dev, d->func);
  35.144 -      if (e < 0 || e >= (int) sizeof(buf))
  35.145 -	a->error("File name too long");
  35.146 -      a->fd_rw = a->writeable || rw;
  35.147 -      a->fd = open(buf, a->fd_rw ? O_RDWR : O_RDONLY);
  35.148 -      if (a->fd < 0)
  35.149 -	a->warning("Cannot open %s", buf);
  35.150 -#ifndef PT_LIBPCI
  35.151 -      a->cached_dev = d;
  35.152 -#else
  35.153 -      a->cached_b = d->bus;
  35.154 -      a->cached_d = d->dev;
  35.155 -      a->cached_f = d->func;      
  35.156 -#endif
  35.157 -      a->fd_pos = 0;
  35.158 -    }
  35.159 -  return a->fd;
  35.160 -}
  35.161 -
  35.162 -static int
  35.163 -proc_read(struct pci_dev *d, int pos, byte *buf, int len)
  35.164 -{
  35.165 -  int fd = proc_setup(d, 0);
  35.166 -  int res;
  35.167 -
  35.168 -  if (fd < 0)
  35.169 -    return 0;
  35.170 -  res = do_read(d, fd, buf, len, pos);
  35.171 -  if (res < 0)
  35.172 -    {
  35.173 -      d->access->warning("proc_read: read failed: %s", strerror(errno));
  35.174 -      return 0;
  35.175 -    }
  35.176 -  else if (res != len)
  35.177 -    return 0;
  35.178 -  return 1;
  35.179 -}
  35.180 -
  35.181 -static int
  35.182 -proc_write(struct pci_dev *d, int pos, byte *buf, int len)
  35.183 -{
  35.184 -  int fd = proc_setup(d, 1);
  35.185 -  int res;
  35.186 -
  35.187 -  if (fd < 0)
  35.188 -    return 0;
  35.189 -  res = do_write(d, fd, buf, len, pos);
  35.190 -  if (res < 0)
  35.191 -    {
  35.192 -      d->access->warning("proc_write: write failed: %s", strerror(errno));
  35.193 -      return 0;
  35.194 -    }
  35.195 -  else if (res != len)
  35.196 -    {
  35.197 -      d->access->warning("proc_write: tried to write %d bytes at %d, but only %d succeeded", len, pos, res);
  35.198 -      return 0;
  35.199 -    }
  35.200 -  return 1;
  35.201 -}
  35.202 -
  35.203 -static void
  35.204 -proc_cleanup_dev(struct pci_dev *d)
  35.205 -{
  35.206 -  if (d->access->cached_dev == d)
  35.207 -    d->access->cached_dev = NULL;
  35.208 -}
  35.209 -
  35.210 -struct pci_methods pm_linux_proc = {
  35.211 -  "Linux-proc",
  35.212 -  proc_config,
  35.213 -  proc_detect,
  35.214 -  proc_init,
  35.215 -  proc_cleanup,
  35.216 -  proc_scan,
  35.217 -#ifdef PT_LIBPCI
  35.218 -  NULL,
  35.219 -#else
  35.220 -  pci_generic_fill_info,
  35.221 -#endif
  35.222 -  proc_read,
  35.223 -  proc_write,
  35.224 -  NULL,					/* init_dev */
  35.225 -  proc_cleanup_dev
  35.226 -#ifdef PT_LIBPCI
  35.227 -  , NULL
  35.228 -#endif
  35.229 -};
    36.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/sysdep.h	Thu Aug 23 13:42:03 2007 -0700
    36.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    36.3 @@ -1,92 +0,0 @@
    36.4 -/*
    36.5 - *	The PCI Library -- System-Dependent Stuff
    36.6 - *
    36.7 - *	Copyright (c) 1997--2004 Martin Mares <mj@ucw.cz>
    36.8 - *
    36.9 - *	Can be freely distributed and used under the terms of the GNU GPL.
   36.10 - */
   36.11 -#ifndef __SYSDEP_H__
   36.12 -#define __SYSDEP_H__
   36.13 -
   36.14 -#ifdef __GNUC__
   36.15 -#define UNUSED __attribute__((unused))
   36.16 -#define NONRET __attribute__((noreturn))
   36.17 -#else
   36.18 -#define UNUSED
   36.19 -#define NONRET
   36.20 -#define inline
   36.21 -#endif
   36.22 -
   36.23 -typedef u8 byte;
   36.24 -typedef u16 word;
   36.25 -
   36.26 -#ifdef PCI_OS_WINDOWS
   36.27 -#define strcasecmp strcmpi
   36.28 -#endif
   36.29 -
   36.30 -#ifdef PCI_HAVE_LINUX_BYTEORDER_H
   36.31 -
   36.32 -#include <asm/byteorder.h>
   36.33 -#define cpu_to_le16 __cpu_to_le16
   36.34 -#define cpu_to_le32 __cpu_to_le32
   36.35 -#define le16_to_cpu __le16_to_cpu
   36.36 -#define le32_to_cpu __le32_to_cpu
   36.37 -
   36.38 -#else
   36.39 -
   36.40 -#ifdef PCI_OS_LINUX
   36.41 -#include <endian.h>
   36.42 -#define BYTE_ORDER __BYTE_ORDER
   36.43 -#define BIG_ENDIAN __BIG_ENDIAN
   36.44 -#endif
   36.45 -
   36.46 -#ifdef PCI_OS_SUNOS
   36.47 -#include <sys/byteorder.h>
   36.48 -#define BIG_ENDIAN 4321
   36.49 -#ifdef _LITTLE_ENDIAN
   36.50 -#define BYTE_ORDER 1234
   36.51 -#else
   36.52 -#define BYTE_ORDER 4321
   36.53 -#endif
   36.54 -#endif
   36.55 -
   36.56 -#ifdef PCI_OS_WINDOWS
   36.57 -#ifdef __MINGW32__
   36.58 -  #include <sys/param.h>
   36.59 -#else
   36.60 -  #include <io.h>
   36.61 -  #define BIG_ENDIAN 4321
   36.62 -  #define LITTLE_ENDIAN	1234
   36.63 -  #define BYTE_ORDER LITTLE_ENDIAN
   36.64 -  #define snprintf _snprintf
   36.65 -#endif
   36.66 -#endif
   36.67 -
   36.68 -#if BYTE_ORDER == BIG_ENDIAN
   36.69 -#define cpu_to_le16 swab16
   36.70 -#define cpu_to_le32 swab32
   36.71 -#define le16_to_cpu swab16
   36.72 -#define le32_to_cpu swab32
   36.73 -
   36.74 -static inline word swab16(word w)
   36.75 -{
   36.76 -  return (w << 8) | ((w >> 8) & 0xff);
   36.77 -}
   36.78 -
   36.79 -static inline u32 swab32(u32 w)
   36.80 -{
   36.81 -  return ((w & 0xff000000) >> 24) |
   36.82 -         ((w & 0x00ff0000) >> 8) |
   36.83 -         ((w & 0x0000ff00) << 8)  |
   36.84 -         ((w & 0x000000ff) << 24);
   36.85 -}
   36.86 -#else
   36.87 -#define cpu_to_le16(x) (x)
   36.88 -#define cpu_to_le32(x) (x)
   36.89 -#define le16_to_cpu(x) (x)
   36.90 -#define le32_to_cpu(x) (x)
   36.91 -#endif
   36.92 -
   36.93 -#endif
   36.94 -
   36.95 -#endif /* __SYSDEP_H__ */
    37.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/sysfs.c	Thu Aug 23 13:42:03 2007 -0700
    37.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    37.3 @@ -1,289 +0,0 @@
    37.4 -/*
    37.5 - *	The PCI Library -- Configuration Access via /sys/bus/pci
    37.6 - *
    37.7 - * 	Copyright (c) 2003 Matthew Wilcox <willy@fc.hp.com>
    37.8 - *	Copyright (c) 1997--2003 Martin Mares <mj@ucw.cz>
    37.9 - *
   37.10 - *	Can be freely distributed and used under the terms of the GNU GPL.
   37.11 - */
   37.12 -
   37.13 -#define _GNU_SOURCE
   37.14 -
   37.15 -#include <stdio.h>
   37.16 -#include <stdlib.h>
   37.17 -#include <string.h>
   37.18 -#include <stdarg.h>
   37.19 -#include <unistd.h>
   37.20 -#include <errno.h>
   37.21 -#include <dirent.h>
   37.22 -#include <fcntl.h>
   37.23 -#include <sys/types.h>
   37.24 -
   37.25 -#include "internal.h"
   37.26 -#include "pread.h"
   37.27 -
   37.28 -static void
   37.29 -sysfs_config(struct pci_access *a)
   37.30 -{
   37.31 -  a->method_params[PCI_ACCESS_SYS_BUS_PCI] = PCI_PATH_SYS_BUS_PCI;
   37.32 -}
   37.33 -
   37.34 -static inline char *
   37.35 -sysfs_name(struct pci_access *a)
   37.36 -{
   37.37 -  return a->method_params[PCI_ACCESS_SYS_BUS_PCI];
   37.38 -}
   37.39 -
   37.40 -static int
   37.41 -sysfs_detect(struct pci_access *a)
   37.42 -{
   37.43 -  if (access(sysfs_name(a), R_OK))
   37.44 -    {
   37.45 -      a->debug("...cannot open %s", sysfs_name(a));
   37.46 -      return 0;
   37.47 -    }
   37.48 -  a->debug("...using %s", sysfs_name(a));
   37.49 -  return 1;
   37.50 -}
   37.51 -
   37.52 -static void
   37.53 -sysfs_init(struct pci_access *a)
   37.54 -{
   37.55 -  a->fd = -1;
   37.56 -#ifdef PT_LIBPCI
   37.57 -  a->cached_b = -1;
   37.58 -  a->cached_d = -1;
   37.59 -  a->cached_f = -1;
   37.60 -#endif
   37.61 -}
   37.62 -
   37.63 -static void
   37.64 -sysfs_cleanup(struct pci_access *a)
   37.65 -{
   37.66 -  if (a->fd >= 0)
   37.67 -    {
   37.68 -      close(a->fd);
   37.69 -      a->fd = -1;
   37.70 -    }
   37.71 -}
   37.72 -
   37.73 -#define OBJNAMELEN 1024
   37.74 -static void
   37.75 -sysfs_obj_name(struct pci_dev *d, char *object, char *buf)
   37.76 -{
   37.77 -  int n = snprintf(buf, OBJNAMELEN, "%s/devices/%04x:%02x:%02x.%d/%s",
   37.78 -		   sysfs_name(d->access), d->domain, d->bus, d->dev, d->func, object);
   37.79 -  if (n < 0 || n >= OBJNAMELEN)
   37.80 -    d->access->error("File name too long");
   37.81 -}
   37.82 -
   37.83 -static int
   37.84 -sysfs_get_value(struct pci_dev *d, char *object)
   37.85 -{
   37.86 -  struct pci_access *a = d->access;
   37.87 -  int fd, n;
   37.88 -  char namebuf[OBJNAMELEN], buf[256];
   37.89 -
   37.90 -  sysfs_obj_name(d, object, namebuf);
   37.91 -  fd = open(namebuf, O_RDONLY);
   37.92 -  if (fd < 0)
   37.93 -    a->error("Cannot open %s: %s", namebuf, strerror(errno));
   37.94 -  n = read(fd, buf, sizeof(buf));
   37.95 -  close(fd);
   37.96 -  if (n < 0)
   37.97 -    a->error("Error reading %s: %s", namebuf, strerror(errno));
   37.98 -  if (n >= (int) sizeof(buf))
   37.99 -    a->error("Value in %s too long", namebuf);
  37.100 -  buf[n] = 0;
  37.101 -  return strtol(buf, NULL, 0);
  37.102 -}
  37.103 -
  37.104 -static void
  37.105 -sysfs_get_resources(struct pci_dev *d)
  37.106 -{
  37.107 -  struct pci_access *a = d->access;
  37.108 -  char namebuf[OBJNAMELEN], buf[256];
  37.109 -  FILE *file;
  37.110 -  int i;
  37.111 -
  37.112 -  sysfs_obj_name(d, "resource", namebuf);
  37.113 -  file = fopen(namebuf, "r");
  37.114 -  if (!file)
  37.115 -    a->error("Cannot open %s: %s", namebuf, strerror(errno));
  37.116 -  for (i = 0; i < 7; i++)
  37.117 -    {
  37.118 -      unsigned long long start, end, size;
  37.119 -      if (!fgets(buf, sizeof(buf), file))
  37.120 -	break;
  37.121 -      if (sscanf(buf, "%llx %llx", &start, &end) != 2)
  37.122 -	a->error("Syntax error in %s", namebuf);
  37.123 -      if (start)
  37.124 -	size = end - start + 1;
  37.125 -      else
  37.126 -	size = 0;
  37.127 -      if (i < 6)
  37.128 -	{
  37.129 -	  d->base_addr[i] = start;
  37.130 -	  d->size[i] = size;
  37.131 -	}
  37.132 -      else
  37.133 -	{
  37.134 -	  d->rom_base_addr = start;
  37.135 -	  d->rom_size = size;
  37.136 -	}
  37.137 -    }
  37.138 -  fclose(file);
  37.139 -}
  37.140 -
  37.141 -static void sysfs_scan(struct pci_access *a)
  37.142 -{
  37.143 -  char dirname[1024];
  37.144 -  DIR *dir;
  37.145 -  struct dirent *entry;
  37.146 -  int n;
  37.147 -
  37.148 -  n = snprintf(dirname, sizeof(dirname), "%s/devices", sysfs_name(a));
  37.149 -  if (n < 0 || n >= (int) sizeof(dirname))
  37.150 -    a->error("Directory name too long");
  37.151 -  dir = opendir(dirname);
  37.152 -  if (!dir)
  37.153 -    a->error("Cannot open %s", dirname);
  37.154 -  while ((entry = readdir(dir)))
  37.155 -    {
  37.156 -      struct pci_dev *d;
  37.157 -      unsigned int dom, bus, dev, func;
  37.158 -
  37.159 -      /* ".", ".." or a special non-device perhaps */
  37.160 -      if (entry->d_name[0] == '.')
  37.161 -	continue;
  37.162 -
  37.163 -      d = pci_alloc_dev(a);
  37.164 -      if (sscanf(entry->d_name, "%x:%x:%x.%d", &dom, &bus, &dev, &func) < 4)
  37.165 -	a->error("sysfs_scan: Couldn't parse entry name %s", entry->d_name);
  37.166 -      d->domain = dom;
  37.167 -      d->bus = bus;
  37.168 -      d->dev = dev;
  37.169 -      d->func = func;
  37.170 -      if (!a->buscentric)
  37.171 -	{
  37.172 -	  sysfs_get_resources(d);
  37.173 -	  d->irq = sysfs_get_value(d, "irq");
  37.174 -	  /*
  37.175 -	   *  We could read these faster from the config registers, but we want to give
  37.176 -	   *  the kernel a chance to fix up ID's and especially classes of broken devices.
  37.177 -	   */
  37.178 -	  d->vendor_id = sysfs_get_value(d, "vendor");
  37.179 -	  d->device_id = sysfs_get_value(d, "device");
  37.180 -	  d->device_class = sysfs_get_value(d, "class") >> 8;
  37.181 -	  d->known_fields = PCI_FILL_IDENT | PCI_FILL_CLASS | PCI_FILL_IRQ | PCI_FILL_BASES | PCI_FILL_ROM_BASE | PCI_FILL_SIZES;
  37.182 -	}
  37.183 -      pci_link_dev(a, d);
  37.184 -    }
  37.185 -  closedir(dir);
  37.186 -}
  37.187 -
  37.188 -static int
  37.189 -sysfs_setup(struct pci_dev *d, int rw)
  37.190 -{
  37.191 -  struct pci_access *a = d->access;
  37.192 -
  37.193 -#ifndef PT_LIBPCI
  37.194 -  if (a->cached_dev != d || a->fd_rw < rw)
  37.195 -#else
  37.196 -  if (a->cached_b != d->bus || 
  37.197 -      a->cached_d != d->dev ||
  37.198 -      a->cached_f != d->func || 
  37.199 -      a->fd_rw < rw)
  37.200 -#endif
  37.201 -    {
  37.202 -      char namebuf[OBJNAMELEN];
  37.203 -      if (a->fd >= 0)
  37.204 -	close(a->fd);
  37.205 -      sysfs_obj_name(d, "config", namebuf);
  37.206 -      a->fd_rw = a->writeable || rw;
  37.207 -      a->fd = open(namebuf, a->fd_rw ? O_RDWR : O_RDONLY);
  37.208 -      if (a->fd < 0)
  37.209 -	a->warning("Cannot open %s", namebuf);
  37.210 -#ifndef PT_LIBPCI
  37.211 -      a->cached_dev = d;
  37.212 -#else
  37.213 -      a->cached_b = d->bus;
  37.214 -      a->cached_d = d->dev;
  37.215 -      a->cached_f = d->func;      
  37.216 -#endif
  37.217 -      a->fd_pos = 0;
  37.218 -    }
  37.219 -  return a->fd;
  37.220 -}
  37.221 -
  37.222 -static int sysfs_read(struct pci_dev *d, int pos, byte *buf, int len)
  37.223 -{
  37.224 -  int fd = sysfs_setup(d, 0);
  37.225 -  int res;
  37.226 -
  37.227 -  if (fd < 0)
  37.228 -    return 0;
  37.229 -  res = do_read(d, fd, buf, len, pos);
  37.230 -  if (res < 0)
  37.231 -    {
  37.232 -      d->access->warning("sysfs_read: read failed: %s", strerror(errno));
  37.233 -      return 0;
  37.234 -    }
  37.235 -  else if (res != len)
  37.236 -    return 0;
  37.237 -  return 1;
  37.238 -}
  37.239 -
  37.240 -static int sysfs_write(struct pci_dev *d, int pos, byte *buf, int len)
  37.241 -{
  37.242 -  int fd = sysfs_setup(d, 1);
  37.243 -  int res;
  37.244 -
  37.245 -  if (fd < 0)
  37.246 -    return 0;
  37.247 -  res = do_write(d, fd, buf, len, pos);
  37.248 -  if (res < 0)
  37.249 -    {
  37.250 -      d->access->warning("sysfs_write: write failed: %s", strerror(errno));
  37.251 -      return 0;
  37.252 -    }
  37.253 -  else if (res != len)
  37.254 -    {
  37.255 -      d->access->warning("sysfs_write: tried to write %d bytes at %d, but only %d succeeded", len, pos, res);
  37.256 -      return 0;
  37.257 -    }
  37.258 -  return 1;
  37.259 -}
  37.260 -
  37.261 -static void sysfs_cleanup_dev(struct pci_dev *d)
  37.262 -{
  37.263 -  struct pci_access *a = d->access;
  37.264 -
  37.265 -  if (a->cached_dev == d)
  37.266 -    {
  37.267 -      a->cached_dev = NULL;
  37.268 -      close(a->fd);
  37.269 -      a->fd = -1;
  37.270 -    }
  37.271 -}
  37.272 -
  37.273 -struct pci_methods pm_linux_sysfs = {
  37.274 -  "Linux-sysfs",
  37.275 -  sysfs_config,
  37.276 -  sysfs_detect,
  37.277 -  sysfs_init,
  37.278 -  sysfs_cleanup,
  37.279 -  sysfs_scan,
  37.280 -#ifndef PT_LIBPCI
  37.281 -  pci_generic_fill_info,
  37.282 -#else
  37.283 -  NULL,
  37.284 -#endif
  37.285 -  sysfs_read,
  37.286 -  sysfs_write,
  37.287 -  NULL,					/* init_dev */
  37.288 -  sysfs_cleanup_dev
  37.289 -#ifdef PT_LIBPCI
  37.290 -  , sysfs_get_value
  37.291 -#endif
  37.292 -};
    38.1 --- a/tools/ioemu/pt-libpci/lib2.2.6/types.h	Thu Aug 23 13:42:03 2007 -0700
    38.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    38.3 @@ -1,62 +0,0 @@
    38.4 -/*
    38.5 - *	The PCI Library -- Types and Format Strings
    38.6 - *
    38.7 - *	Copyright (c) 1997--2007 Martin Mares <mj@ucw.cz>
    38.8 - *
    38.9 - *	Can be freely distributed and used under the terms of the GNU GPL.
   38.10 - */
   38.11 -#ifndef __TYPES_H__
   38.12 -#define __TYPES_H__
   38.13 -
   38.14 -#include <sys/types.h>
   38.15 -
   38.16 -#ifndef PCI_HAVE_Uxx_TYPES
   38.17 -
   38.18 -#ifdef PCI_OS_WINDOWS
   38.19 -typedef unsigned __int8 u8;
   38.20 -typedef unsigned __int16 u16;
   38.21 -typedef unsigned __int32 u32;
   38.22 -#elif defined(PCI_HAVE_STDINT_H)
   38.23 -#include <stdint.h>
   38.24 -typedef uint8_t u8;
   38.25 -typedef uint16_t u16;
   38.26 -typedef uint32_t u32;
   38.27 -#else
   38.28 -typedef u_int8_t u8;
   38.29 -typedef u_int16_t u16;
   38.30 -typedef u_int32_t u32;
   38.31 -#endif
   38.32 -
   38.33 -#ifdef PCI_HAVE_64BIT_ADDRESS
   38.34 -#include <limits.h>
   38.35 -#if ULONG_MAX > 0xffffffff
   38.36 -typedef unsigned long u64;
   38.37 -#define PCI_U64_FMT "l"
   38.38 -#else
   38.39 -typedef unsigned long long u64;
   38.40 -#define PCI_U64_FMT "ll"
   38.41 -#endif
   38.42 -#endif
   38.43 -
   38.44 -#endif	/* PCI_HAVE_Uxx_TYPES */
   38.45 -
   38.46 -#ifdef PCI_HAVE_64BIT_ADDRESS
   38.47 -typedef u64 pciaddr_t;
   38.48 -#define PCIADDR_T_FMT "%08" PCI_U64_FMT "x"
   38.49 -#define PCIADDR_PORT_FMT "%04" PCI_U64_FMT "x"
   38.50 -#else
   38.51 -typedef u32 pciaddr_t;
   38.52 -#define PCIADDR_T_FMT "%08x"
   38.53 -#define PCIADDR_PORT_FMT "%04x"
   38.54 -#endif
   38.55 -
   38.56 -#ifdef PCI_ARCH_SPARC64
   38.57 -/* On sparc64 Linux the kernel reports remapped port addresses and IRQ numbers */
   38.58 -#undef PCIADDR_PORT_FMT
   38.59 -#define PCIADDR_PORT_FMT PCIADDR_T_FMT
   38.60 -#define PCIIRQ_FMT "%08x"
   38.61 -#else
   38.62 -#define PCIIRQ_FMT "%d"
   38.63 -#endif
   38.64 -
   38.65 -#endif /* __TYPES_H__ */
    39.1 --- a/tools/ioemu/pt-libpci/lspci.c	Thu Aug 23 13:42:03 2007 -0700
    39.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    39.3 @@ -1,22 +0,0 @@
    39.4 -/*****************************************************************************
    39.5 -
    39.6 -    Copyright (c) 2007, Neocleus: Alex Novik, Guy Zana
    39.7 -
    39.8 -******************************************************************************/
    39.9 -#include <stdio.h>
   39.10 -#include <string.h>
   39.11 -#include <stdlib.h>
   39.12 -#include <stdarg.h>
   39.13 -#include <unistd.h>
   39.14 -
   39.15 -#include "pt_libpci.h"
   39.16 -#include "pt_pci_probe.h"
   39.17 -#include "pt_pci_tree.h"
   39.18 -
   39.19 -int main()
   39.20 -{
   39.21 -    pt_libpci_init(stdout);
   39.22 -    pt_bus_probe(0, 1);
   39.23 -    pt_print_device_map();
   39.24 -    pt_libpci_clean();
   39.25 -}
    40.1 --- a/tools/ioemu/pt-libpci/pt_libpci.c	Thu Aug 23 13:42:03 2007 -0700
    40.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    40.3 @@ -1,52 +0,0 @@
    40.4 -/*****************************************************************************
    40.5 -
    40.6 -    Copyright (c) 2007, Neocleus: Alex Novik, Guy Zana
    40.7 -
    40.8 -******************************************************************************/
    40.9 -#include <stdio.h>
   40.10 -#include <stdlib.h>
   40.11 -#include <stdarg.h>
   40.12 -#include <string.h>
   40.13 -#include <errno.h>
   40.14 -
   40.15 -#include "pt_libpci.h"
   40.16 -#include "pt_pci_access.h"
   40.17 -
   40.18 -FILE * logfile;
   40.19 -
   40.20 -void pt_libpci_log(char *msg, ...)
   40.21 -{
   40.22 -#ifdef PT_LIBPCI_LOG
   40.23 -  va_list args;
   40.24 -
   40.25 -  va_start(args, msg);
   40.26 -  fputs("pt-pcilib: ", logfile);
   40.27 -  vfprintf(logfile, msg, args);
   40.28 -  fputc('\n', logfile);
   40.29 -#endif
   40.30 -}
   40.31 -
   40.32 -pt_libpci_rc_t pt_libpci_clean(void)
   40.33 -{
   40.34 -    pt_clean_tree();
   40.35 -    pt_pci_access_clean();
   40.36 -}
   40.37 -
   40.38 -pt_libpci_rc_t pt_libpci_init(FILE * fileout)
   40.39 -{  
   40.40 -    pt_libpci_rc_t rc;
   40.41 -    
   40.42 -    logfile = fileout;
   40.43 -    
   40.44 -    /* Initialize our place holder */
   40.45 -    rc = pt_device_tree_init();
   40.46 -    if ( PT_RC_FAILURE == rc )
   40.47 -        return rc;
   40.48 -
   40.49 -    rc = pt_pci_access_init();
   40.50 -    if ( PT_RC_FAILURE == rc )
   40.51 -        return rc;
   40.52 -
   40.53 -    return PT_RC_SUCCESS;
   40.54 -} 
   40.55 -
    41.1 --- a/tools/ioemu/pt-libpci/pt_libpci.h	Thu Aug 23 13:42:03 2007 -0700
    41.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    41.3 @@ -1,100 +0,0 @@
    41.4 -/*****************************************************************************
    41.5 -
    41.6 -    Copyright (c) 2007, Neocleus: Alex Novik, Guy Zana
    41.7 -
    41.8 -******************************************************************************/
    41.9 -#ifndef __PT_LIBPCI_H__
   41.10 -#define __PT_LIBPCI_H__
   41.11 -
   41.12 -#include <stdio.h>
   41.13 -
   41.14 -#include "lib2.2.6/pci.h"
   41.15 -#include "lib2.2.6/internal.h"
   41.16 -
   41.17 -/* Enable libpci debug log */
   41.18 -//#define PT_LIBPCI_LOG
   41.19 -
   41.20 -/* Return types for functions */
   41.21 -typedef enum pt_rc_e {
   41.22 -    PT_RC_SUCCESS = 0,
   41.23 -    PT_RC_FAILURE	
   41.24 -} pt_libpci_rc_t;
   41.25 -
   41.26 -typedef enum pt_pci_address_width_e {
   41.27 -    PT_PCI_ADDRESS_WIDTH_8         = 8,
   41.28 -    PT_PCI_ADDRESS_WIDTH_16        = 16,
   41.29 -    PT_PCI_ADDRESS_WIDTH_24        = 24,
   41.30 -    PT_PCI_ADDRESS_WIDTH_32        = 32,
   41.31 -    PT_PCI_ADDRESS_WIDTH_64        = 64,
   41.32 -    PT_PCI_ADDRESS_WIDTH_UNKNOWN   = -1
   41.33 -} pci_address_width_t;
   41.34 -
   41.35 -typedef enum pt_pci_address_e {
   41.36 -    PT_PCI_ADDRESS_SPACE_MEM           = 0x00,
   41.37 -    PT_PCI_ADDRESS_SPACE_IO            = 0x01,
   41.38 -    PT_PCI_ADDRESS_SPACE_MEM_PREFETCH  = 0x08
   41.39 -} pt_pci_address_t;
   41.40 -
   41.41 -#define PT_GET_TYPE_STR(type) \
   41.42 -    (type == PT_PCI_ADDRESS_SPACE_MEM) ? \
   41.43 -        "PT_PCI_ADDRESS_SPACE_MEM" : ((type == PT_PCI_ADDRESS_SPACE_IO) ? \
   41.44 -                "PT_PCI_ADDRESS_SPACE_IO": "PT_PCI_ADDRESS_SPACE_MEM_PREFETCH")
   41.45 -
   41.46 -#define PT_GET64(high, low) (u64)(((u64)(high)<<32) | (u64)low)
   41.47 -
   41.48 -typedef enum pt_pci_memory_region_e {
   41.49 -    /* Values for the flag field */
   41.50 -    PT_PCI_REGION_UNASSIGNED   = 0x0001,
   41.51 -    PT_PCI_REGION_DISABLED     = 0x0002,
   41.52 -    PT_PCI_REGION_IGNORED      = 0x0004,
   41.53 -    PT_PCI_REGION_INVALID      = 0x0008,
   41.54 -    PT_PCI_REGION_VALID        = 0x0010
   41.55 -} pt_pci_memory_region_t;
   41.56 -
   41.57 -#define PCI_REGION_IS_VALID(pcidev, region)     (pcidev->regions[region].flags == PT_PCI_REGION_VALID)
   41.58 -#define IS_VALID_REGION(region)                 (region->flags == PT_PCI_REGION_VALID)
   41.59 -
   41.60 -#define MAX_IO_REGIONS			(6) 
   41.61 -typedef struct pci_region_s {
   41.62 -    /* Memory or port I/O */
   41.63 -    pt_pci_address_t type;
   41.64 -    /* Region flags */
   41.65 -    u16 flags;
   41.66 -    /* Granularity of the size (used for PCI bridges) */
   41.67 -    pciaddr_t size_granularity;
   41.68 -    pciaddr_t base_addr;
   41.69 -    /* Size of the region */
   41.70 -    pciaddr_t size;
   41.71 -    /* 16, 32, 64 bits */
   41.72 -    pci_address_width_t addr_width;
   41.73 -} pci_region_t;
   41.74 -
   41.75 -typedef struct pci_phys_dev_s {
   41.76 -    /* Bus inside domain, device and function */
   41.77 -    u8 bus, dev, func;
   41.78 -    /* Identity of the device */
   41.79 -    u16 vendor_id, device_id;
   41.80 -    u32 device_class;
   41.81 -    u8 header_type;
   41.82 -    u8 irq;
   41.83 -    /* secondary bus number (used for PCI bridges) */
   41.84 -    u8 secondary_bus;	
   41.85 -    int is_pcie;    /* not implemented yet */
   41.86 -    /* Number of active regions */
   41.87 -    u16 region_number;
   41.88 -    /* PIO / MMIO Regions */
   41.89 -    pci_region_t regions[MAX_IO_REGIONS];
   41.90 -    /* Is ROM enabled */
   41.91 -    u8 rom_enabled;
   41.92 -    /* Expansion ROM base address */
   41.93 -    pciaddr_t rom_base_addr;
   41.94 -    /* Expansion ROM size */
   41.95 -    pciaddr_t rom_size;
   41.96 -} pci_phys_dev_t;
   41.97 -
   41.98 -void pt_libpci_log(char *msg, ...);
   41.99 -pt_libpci_rc_t pt_libpci_clean(void);
  41.100 -pt_libpci_rc_t pt_libpci_init(FILE * fileout);
  41.101 -
  41.102 -#endif /* __PT_LIBPCI_H__ */
  41.103 -
    42.1 --- a/tools/ioemu/pt-libpci/pt_pci_access.c	Thu Aug 23 13:42:03 2007 -0700
    42.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    42.3 @@ -1,246 +0,0 @@
    42.4 -/*****************************************************************************
    42.5 -
    42.6 -    Copyright (c) 2007, Neocleus: Alex Novik, Guy Zana
    42.7 -
    42.8 -    Based on code that were taken from the PCI library (pciutils)
    42.9 -    Copyright (c) 1997--2000 Martin Mares <mj@ucw.cz>
   42.10 -
   42.11 -******************************************************************************/
   42.12 -#include <stdio.h>
   42.13 -#include <stdlib.h>
   42.14 -#include <stdarg.h>
   42.15 -#include <string.h>
   42.16 -#include <unistd.h>
   42.17 -#include <sys/io.h>
   42.18 -
   42.19 -#include "pt_libpci.h"
   42.20 -#include "pt_pci_probe.h"
   42.21 -#include "pt_pci_access.h"
   42.22 -#include "pt_pci_tree.h"
   42.23 -
   42.24 -struct pci_access * sysfs_access;
   42.25 -
   42.26 -extern void pt_libpci_log(char *msg, ...);
   42.27 -
   42.28 -int pci_set_access_permissions(void)
   42.29 -{
   42.30 -    static int intel_iopl_set=-1;
   42.31 -    
   42.32 -    if (intel_iopl_set < 0)
   42.33 -        intel_iopl_set = (iopl(3) < 0) ? 0 : 1;
   42.34 -        
   42.35 -    return (intel_iopl_set);
   42.36 -}
   42.37 -
   42.38 -u32 pt_pio_read(u32 addr, u32 size)
   42.39 -{
   42.40 -    u32 val = 0;	
   42.41 -
   42.42 -    switch (size) {
   42.43 -    case 1:
   42.44 -        val = (u32) inb(addr);
   42.45 -        break;
   42.46 -        
   42.47 -    case 2:
   42.48 -        val = (u32) inw(addr);
   42.49 -        break;
   42.50 -        
   42.51 -    case 4:
   42.52 -        val = (u32) inl(addr);
   42.53 -        break;
   42.54 -        
   42.55 -    default:
   42.56 -        val = PCI_INAVLID;
   42.57 -        break;
   42.58 -    }
   42.59 -
   42.60 -    return (val);
   42.61 -}
   42.62 -
   42.63 -int pt_pio_write(u32 addr, u32 val, u32 size)
   42.64 -{
   42.65 -
   42.66 -    switch (size) {
   42.67 -    case 1:
   42.68 -        outb(val, addr);
   42.69 -        break;
   42.70 -        
   42.71 -    case 2:
   42.72 -        outw(val, addr);
   42.73 -        break;
   42.74 -        
   42.75 -    case 4:
   42.76 -        outl(val, addr);
   42.77 -        break;
   42.78 -        
   42.79 -    default:
   42.80 -        return (PCI_INAVLID);
   42.81 -    }
   42.82 -
   42.83 -    /* success */
   42.84 -    return (0);
   42.85 -
   42.86 -} /* end of neo_pio_write */
   42.87 -
   42.88 -u32 pt_mmio_read( u32 addr, u32 size)
   42.89 -{
   42.90 -    u32 val = 0;
   42.91 -
   42.92 -    switch (size) {
   42.93 -        case 1:		
   42.94 -            val = (u32)(*(u8 *)addr);
   42.95 -            break;
   42.96 -            
   42.97 -        case 2:
   42.98 -            val = (u32)(*(u16 *)addr);
   42.99 -            break;
  42.100 -            
  42.101 -        case 4:
  42.102 -            val = (u32)(*(u32 *)addr);
  42.103 -            break;
  42.104 -            
  42.105 -        default:
  42.106 -            return (PCI_INAVLID);
  42.107 -    }
  42.108 -
  42.109 -    return (val);
  42.110 -} 
  42.111 -
  42.112 -u32 pt_mmio_write(u32 addr, u32 value, u32 size)
  42.113 -{
  42.114 -
  42.115 -    switch (size) {
  42.116 -    case 1:
  42.117 -        *((u8 *) addr) = (u8) value;
  42.118 -        break;
  42.119 -        
  42.120 -    case 2:
  42.121 -        *((u16 *) addr) = (u16) value;
  42.122 -        break;
  42.123 -        
  42.124 -    case 4:
  42.125 -        *((u32 *) addr) = (u32) value;
  42.126 -        break;
  42.127 -        
  42.128 -    default:
  42.129 -        return (PCI_INAVLID);
  42.130 -    }
  42.131 -
  42.132 -    /* success */
  42.133 -    return (0);
  42.134 -
  42.135 -}
  42.136 -
  42.137 -void pci_read_data(u8 bus, u8 device, u8 func, void *buf, int pos, int len)
  42.138 -{
  42.139 -    struct pci_dev tmp;
  42.140 -    memset(&tmp, 0, sizeof(struct pci_dev ));
  42.141 -    
  42.142 -    tmp.bus = bus;
  42.143 -    tmp.dev = device;
  42.144 -    tmp.func = func;
  42.145 -    tmp.access = sysfs_access;
  42.146 -    sysfs_access->methods->read(&tmp, pos, buf, len);
  42.147 -}
  42.148 -
  42.149 -u8 pci_read_byte(u8 bus, u8 device, u8 func, int pos)
  42.150 -{
  42.151 -    u8 buf;
  42.152 -
  42.153 -    pci_read_data(bus,device,func, &buf, pos, 1);
  42.154 -    return buf;
  42.155 -}
  42.156 -
  42.157 -u16 pci_read_word(u8 bus, u8 device, u8 func, int pos)
  42.158 -{
  42.159 -    u16 buf;
  42.160 -
  42.161 -    pci_read_data(bus,device,func, &buf, pos, 2);
  42.162 -    return buf;
  42.163 -}
  42.164 -
  42.165 -u32 pci_read_long(u8 bus, u8 device, u8 func, int pos)
  42.166 -{
  42.167 -    u32 buf;
  42.168 -
  42.169 -    pci_read_data(bus,device,func, &buf, pos, 4);
  42.170 -    return buf;
  42.171 -}
  42.172 -
  42.173 -int pci_write_data(u8 bus, u8 device, u8 func, void *buf, int pos, int len)
  42.174 -{
  42.175 -    struct pci_dev tmp;
  42.176 -    int res;
  42.177 -    memset(&tmp, 0, sizeof(struct pci_dev ));
  42.178 -    
  42.179 -    tmp.bus = bus;
  42.180 -    tmp.dev = device;
  42.181 -    tmp.func = func;
  42.182 -    tmp.access = sysfs_access;
  42.183 -    res = sysfs_access->methods->write(&tmp, pos, buf, len);
  42.184 -
  42.185 -    return res;
  42.186 -}
  42.187 -
  42.188 -int pci_write_byte(u8 bus, u8 device, u8 func, int pos, u8 data)
  42.189 -{
  42.190 -    return pci_write_data(bus, device, func, &data, pos, 1);
  42.191 -}
  42.192 -
  42.193 -int pci_write_word(u8 bus, u8 device, u8 func, int pos, u16 data)
  42.194 -{
  42.195 -    u16 buf = data;
  42.196 -    return pci_write_data(bus, device, func, &buf, pos, 2);
  42.197 -}
  42.198 -
  42.199 -int pci_write_long(u8 bus, u8 device, u8 func, int pos, u32 data)
  42.200 -{
  42.201 -    u32 buf = data;
  42.202 -    return pci_write_data(bus, device, func, &buf, pos, 4);
  42.203 -}
  42.204 -
  42.205 -u8 pci_get_irq(u8 bus, u8 device, u8 func)
  42.206 -{
  42.207 -    u8 res;
  42.208 -    struct pci_dev tmp;
  42.209 -    memset(&tmp, 0, sizeof(struct pci_dev ));
  42.210 -    
  42.211 -    tmp.bus = bus;
  42.212 -    tmp.dev = device;
  42.213 -    tmp.func = func;
  42.214 -    tmp.access = sysfs_access;
  42.215 -
  42.216 -    res = sysfs_access->methods->get_object(&tmp, "irq");
  42.217 -    return (res);
  42.218 -}
  42.219 -
  42.220 -pt_libpci_rc_t pt_pci_access_clean(void)
  42.221 -{
  42.222 -    pci_cleanup(sysfs_access);
  42.223 -    return PT_RC_SUCCESS;
  42.224 -}
  42.225 -
  42.226 -pt_libpci_rc_t pt_pci_access_init(void)
  42.227 -{
  42.228 -
  42.229 -    /* Initialize access for PIO access */
  42.230 -    if ( pci_set_access_permissions() < 0 )
  42.231 -        return PT_RC_FAILURE;
  42.232 -
  42.233 -    /* Initialize access methods */
  42.234 -    sysfs_access = pci_alloc();
  42.235 -    
  42.236 -    sysfs_access->error = pt_libpci_log;
  42.237 -    sysfs_access->warning = pt_libpci_log;
  42.238 -    sysfs_access->debug = pt_libpci_log;
  42.239 -
  42.240 -    /* Init sysfs */
  42.241 -    sysfs_access->methods = &pm_linux_sysfs;
  42.242 -    sysfs_access->methods->config(sysfs_access);
  42.243 -    if ( !sysfs_access->methods->detect(sysfs_access) )
  42.244 -        return PT_RC_FAILURE;
  42.245 -
  42.246 -    sysfs_access->methods->init(sysfs_access);
  42.247 -    
  42.248 -    return PT_RC_SUCCESS;
  42.249 -}
    43.1 --- a/tools/ioemu/pt-libpci/pt_pci_access.h	Thu Aug 23 13:42:03 2007 -0700
    43.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    43.3 @@ -1,40 +0,0 @@
    43.4 -/*****************************************************************************
    43.5 -
    43.6 -    Low-level PCI access routines.
    43.7 -    Copyright (c) 2007, Neocleus: Alex Novik, Guy Zana
    43.8 -
    43.9 -******************************************************************************/
   43.10 -#ifndef __PT_PCI_ACCESS_H__
   43.11 -#define __PT_PCI_ACCESS_H__
   43.12 -
   43.13 -#include "pt_libpci.h"
   43.14 -
   43.15 -#define PCI_CONFIG_SIZE     (256)
   43.16 -#define PCI_INAVLID         (0xFFFFFFFF)
   43.17 -
   43.18 -/* Permissions to access the ports enable */ 
   43.19 -int pci_set_access_permissions(void);
   43.20 -
   43.21 -/* Access to io memory */
   43.22 -u32 pt_mmio_write(u32 addr, u32 value, u32 size);
   43.23 -u32 pt_mmio_read(u32 addr, u32 size);
   43.24 -
   43.25 -/* Access to io ports */
   43.26 -u32 pt_pio_read(u32 addr, u32 size);
   43.27 -int pt_pio_write(u32 addr, u32 val, u32 size);
   43.28 -
   43.29 -/* Access to config space */
   43.30 -void pci_read_data(u8 bus, u8 device, u8 func, void *buf, int pos, int len);
   43.31 -u8 pci_read_byte(u8 bus, u8 device, u8 func, int pos);
   43.32 -u16 pci_read_word(u8 bus, u8 device, u8 func, int pos);
   43.33 -u32 pci_read_long(u8 bus, u8 device, u8 func, int pos);
   43.34 -int pci_write_data(u8 bus, u8 device, u8 func, void *buf, int pos, int len);
   43.35 -int pci_write_byte(u8 bus, u8 device, u8 func, int pos, u8 data);
   43.36 -int pci_write_word(u8 bus, u8 device, u8 func, int pos, u16 data);
   43.37 -int pci_write_long(u8 bus, u8 device, u8 func, int pos, u32 data);
   43.38 -u8 pci_get_irq(u8 bus, u8 device, u8 func);
   43.39 -
   43.40 -pt_libpci_rc_t pt_pci_access_clean(void);
   43.41 -pt_libpci_rc_t pt_pci_access_init(void);
   43.42 -
   43.43 -#endif /* __PT_PCI_ACCESS_H__ */
    44.1 --- a/tools/ioemu/pt-libpci/pt_pci_probe.c	Thu Aug 23 13:42:03 2007 -0700
    44.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    44.3 @@ -1,439 +0,0 @@
    44.4 -/*****************************************************************************
    44.5 -
    44.6 -    Copyright (c) 2007, Neocleus: Alex Novik, Guy Zana
    44.7 -
    44.8 -    Based on code that were taken from the pciutils (lspci)
    44.9 -    Copyright (c) 1997--2000 Martin Mares <mj@ucw.cz>
   44.10 -
   44.11 -******************************************************************************/
   44.12 -#include <string.h>
   44.13 -
   44.14 -#include "pt_libpci.h"
   44.15 -#include "pt_pci_probe.h"
   44.16 -#include "pt_pci_access.h"
   44.17 -#include "pt_pci_tree.h"
   44.18 -/* 
   44.19 -    PCI test of BAR size. Proceed with caution, 
   44.20 -    since this call writes to hardware PCI configuration for a while. 
   44.21 -*/
   44.22 -static u32 size_test(u8 bus, u8 dev, u8 func, int test_position, int test_size)
   44.23 -{
   44.24 -    u16 command;
   44.25 -    u32 bar_data;
   44.26 -    u32 test_result;
   44.27 -
   44.28 -    if (test_size > 4)
   44.29 -        return 0;
   44.30 -
   44.31 -    test_result = 0xffffffff;
   44.32 -
   44.33 -    /* disable the io of the device and the bus mastering
   44.34 -       to be on the safe side, save the command register content as well */
   44.35 -    command =  pci_read_word(bus, dev, func, PCI_COMMAND);
   44.36 -    pci_write_word(bus, dev, func, PCI_COMMAND, command & (~0x7));
   44.37 -
   44.38 -    /* do size test */
   44.39 -    pci_read_data(bus , dev, func, &bar_data, test_position, test_size);
   44.40 -    pci_write_data(bus, dev, func, &test_result, test_position, test_size);
   44.41 -    pci_read_data(bus, dev, func, &test_result, test_position, test_size);
   44.42 -
   44.43 -    /* restore previous state */
   44.44 -    pci_write_data(bus, dev, func, &bar_data, test_position, test_size);
   44.45 -    pci_write_word(bus, dev, func, PCI_COMMAND, command);	
   44.46 -
   44.47 -    return (test_result);
   44.48 -}
   44.49 -
   44.50 -static void get_bases0(pci_phys_dev_t * pt_dev, pt_pci_scan_t do_safe_probe, 
   44.51 -                        u32 regions_nr, u32 romaddress)
   44.52 -{
   44.53 -    u32 i;
   44.54 -    u32 bar_data;
   44.55 -    u32 mem_modifier = 0;
   44.56 -    u32 bar_size = 0;
   44.57 -    u8 b = pt_dev->bus;
   44.58 -    u8 d = pt_dev->dev;
   44.59 -    u8 f = pt_dev->func;
   44.60 -	
   44.61 -    for (i=0; i < regions_nr; i++) {
   44.62 -    
   44.63 -        bar_data = pci_read_long(b, d, f, PCI_BASE_ADDRESS_0 + 4*i);
   44.64 -
   44.65 -        if (do_safe_probe == PT_PCI_SCAN_FORCE_UNSAFE) {
   44.66 -            mem_modifier = size_test(b, d, f, PCI_BASE_ADDRESS_0 +4*i, 4);	
   44.67 -        }
   44.68 -
   44.69 -        if (bar_data & PCI_BASE_ADDRESS_SPACE_IO) {
   44.70 -            pt_dev->regions[i].base_addr = bar_data & PCI_BASE_ADDRESS_IO_MASK;
   44.71 -            pt_dev->regions[i].type = PT_PCI_ADDRESS_SPACE_IO;
   44.72 -            pt_dev->regions[i].addr_width = PT_PCI_ADDRESS_WIDTH_32;	
   44.73 -            mem_modifier &= PCI_BASE_ADDRESS_IO_MASK;
   44.74 -            pt_dev->regions[i].flags = PT_PCI_REGION_VALID;						
   44.75 -        } else {
   44.76 -            pt_dev->regions[i].type = PT_PCI_ADDRESS_SPACE_MEM;
   44.77 -            mem_modifier &= PCI_BASE_ADDRESS_MEM_MASK;
   44.78 -            pt_dev->regions[i].flags = PT_PCI_REGION_VALID;			
   44.79 -            pt_dev->regions[i].base_addr = bar_data &  PCI_BASE_ADDRESS_MEM_MASK;			
   44.80 -        }
   44.81 -
   44.82 -        /* Read size */
   44.83 -        bar_size = FIND_1(mem_modifier);
   44.84 -        if (bar_size == 0) {
   44.85 -            pt_dev->regions[i].flags = PT_PCI_REGION_UNASSIGNED;
   44.86 -            continue;
   44.87 -        }
   44.88 -
   44.89 -        if (do_safe_probe == PT_PCI_SCAN_FORCE_UNSAFE) {
   44.90 -            pt_dev->regions[i].size_granularity = pt_dev->regions[i].size = bar_size;
   44.91 -        }
   44.92 -        else if ((do_safe_probe == PT_PCI_SCAN_FORCE_SAFE) && (pt_dev->regions[i].size == 0))
   44.93 -            continue;
   44.94 -
   44.95 -        if (pt_dev->regions[i].type == PT_PCI_ADDRESS_SPACE_MEM) {
   44.96 -            if ((bar_data & PCI_BASE_ADDRESS_MEM_PREFETCH) == PCI_BASE_ADDRESS_MEM_PREFETCH)				
   44.97 -                pt_dev->regions[i].type = PT_PCI_ADDRESS_SPACE_MEM_PREFETCH;
   44.98 -
   44.99 -            if ((bar_data & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_32) {
  44.100 -                pt_dev->regions[i].addr_width = PT_PCI_ADDRESS_WIDTH_32;
  44.101 -            } else if((bar_data & PCI_BASE_ADDRESS_MEM_TYPE_MASK)  == PCI_BASE_ADDRESS_MEM_TYPE_64) {
  44.102 -                pt_dev->regions[i].addr_width = PT_PCI_ADDRESS_WIDTH_64;
  44.103 -                /* fatal on this one */
  44.104 -                if ((++i) == regions_nr) {
  44.105 -                    pt_dev->regions[i].flags = PT_PCI_REGION_INVALID;
  44.106 -                } else {
  44.107 -                    pt_dev->regions[i].base_addr = pci_read_long(b, d, f, PCI_BASE_ADDRESS_0 + 4*i);
  44.108 -                    pt_dev->regions[i].size = 0;					
  44.109 -                }				
  44.110 -            }
  44.111 -        else
  44.112 -            pt_dev->regions[i].flags = PT_PCI_REGION_INVALID;	
  44.113 -        
  44.114 -        }
  44.115 -    }
  44.116 -	
  44.117 -    pt_dev->region_number = regions_nr;	
  44.118 -
  44.119 -    /* Handle ROM Address */
  44.120 -    if (0 != romaddress) {
  44.121 -        /* Get expansion ROM address */
  44.122 -        bar_data = pci_read_long(b, d, f, romaddress);
  44.123 -        pt_dev->rom_base_addr = bar_data & PCI_ROM_ADDRESS_MASK;
  44.124 -        /* Get expansion ROM size */
  44.125 -        mem_modifier = size_test(b, d, f, romaddress, 4);	
  44.126 -        pt_dev->rom_size = FIND_1(mem_modifier & PCI_ROM_ADDRESS_MASK);
  44.127 -        pt_dev->rom_enabled = bar_data & PCI_ROM_ADDRESS_ENABLE;
  44.128 -    }
  44.129 -	
  44.130 -}
  44.131 -
  44.132 -static void get_bases1(pci_phys_dev_t * pt_dev, pt_pci_scan_t do_safe_probe)
  44.133 -{
  44.134 -    u32 io_base =  pci_read_byte(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_IO_BASE);
  44.135 -    u32 io_limit = pci_read_byte(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_IO_LIMIT);
  44.136 -    u32 io_type = io_base & PCI_IO_RANGE_TYPE_MASK;
  44.137 -    u32 mem_base = pci_read_word(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_MEMORY_BASE);
  44.138 -    u32 mem_limit = pci_read_word(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_MEMORY_LIMIT);
  44.139 -    u32 mem_type = mem_base & PCI_MEMORY_RANGE_TYPE_MASK;
  44.140 -    u32 pref_base = pci_read_word(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_PREF_MEMORY_BASE);
  44.141 -    u32 pref_limit = pci_read_word(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_PREF_MEMORY_LIMIT);
  44.142 -    u32 pref_type = pref_base & PCI_PREF_RANGE_TYPE_MASK;
  44.143 -    u8 io_modifier;
  44.144 -    u16 mem_modifier;
  44.145 -  
  44.146 -    if ( io_type == PCI_IO_RANGE_TYPE_32 ) 
  44.147 -    {
  44.148 -        pt_dev->regions[pt_dev->region_number].flags = PT_PCI_REGION_VALID;
  44.149 -        pt_dev->regions[pt_dev->region_number].type = PT_PCI_ADDRESS_SPACE_IO;
  44.150 -        pt_dev->regions[pt_dev->region_number].addr_width = PT_PCI_ADDRESS_WIDTH_32;
  44.151 -    }
  44.152 -    else if ( io_type == PCI_IO_RANGE_TYPE_16 )
  44.153 -    {
  44.154 -        pt_dev->regions[pt_dev->region_number].flags = PT_PCI_REGION_VALID;
  44.155 -        pt_dev->regions[pt_dev->region_number].type = PT_PCI_ADDRESS_SPACE_IO;
  44.156 -        pt_dev->regions[pt_dev->region_number].addr_width = PT_PCI_ADDRESS_WIDTH_16;
  44.157 -    }
  44.158 -    else
  44.159 -    {
  44.160 -        pt_dev->regions[pt_dev->region_number].flags = PT_PCI_REGION_INVALID;
  44.161 -        pt_dev->regions[pt_dev->region_number].type = PT_PCI_ADDRESS_SPACE_IO;
  44.162 -        pt_dev->regions[pt_dev->region_number].addr_width = PT_PCI_ADDRESS_WIDTH_UNKNOWN;
  44.163 -    }
  44.164 -
  44.165 -    io_base = (io_base & PCI_IO_RANGE_MASK) << 8;
  44.166 -    io_limit = (io_limit & PCI_IO_RANGE_MASK) << 8;
  44.167 -
  44.168 -    if ( io_type == PCI_IO_RANGE_TYPE_32 )
  44.169 -    {
  44.170 -        io_base |= (pci_read_word(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_IO_BASE_UPPER16) << 16);
  44.171 -        io_limit |= (pci_read_word(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_IO_LIMIT_UPPER16) << 16);
  44.172 -    }
  44.173 -    
  44.174 -    pt_dev->regions[pt_dev->region_number].base_addr= io_base;
  44.175 -
  44.176 -    if ( io_base <= io_limit )
  44.177 -    {
  44.178 -        if ( PT_PCI_SCAN_FORCE_UNSAFE == do_safe_probe )
  44.179 -        {
  44.180 -            io_modifier = (u16)size_test(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_IO_BASE, 1) &(~1);
  44.181 -            io_modifier = FIND_1(io_modifier);
  44.182 -            pt_dev->regions[pt_dev->region_number].size_granularity = MAX(io_modifier<< 8,0x1000);
  44.183 -        }
  44.184 -
  44.185 -        pt_dev->regions[pt_dev->region_number].size = io_limit - io_base + 
  44.186 -            pt_dev->regions[pt_dev->region_number].size_granularity;
  44.187 -    }
  44.188 -    else
  44.189 -    {
  44.190 -        pt_dev->regions[pt_dev->region_number].size = 0;  
  44.191 -        pt_dev->regions[pt_dev->region_number].flags |= PT_PCI_REGION_UNASSIGNED;
  44.192 -    }
  44.193 -    
  44.194 -    pt_dev->region_number++;
  44.195 -
  44.196 -    if ( mem_type )
  44.197 -    {
  44.198 -        pt_dev->regions[pt_dev->region_number].flags = PT_PCI_REGION_INVALID;
  44.199 -        pt_dev->regions[pt_dev->region_number].type = PT_PCI_ADDRESS_SPACE_MEM;
  44.200 -        pt_dev->regions[pt_dev->region_number].addr_width = PT_PCI_ADDRESS_WIDTH_UNKNOWN;
  44.201 -    }
  44.202 -    else
  44.203 -    {
  44.204 -        pt_dev->regions[pt_dev->region_number].flags = PT_PCI_REGION_VALID;
  44.205 -        pt_dev->regions[pt_dev->region_number].type = PT_PCI_ADDRESS_SPACE_MEM;
  44.206 -        pt_dev->regions[pt_dev->region_number].addr_width = PT_PCI_ADDRESS_WIDTH_32;
  44.207 -    }
  44.208 -
  44.209 -    mem_base = (mem_base & PCI_MEMORY_RANGE_MASK) << 16;
  44.210 -    mem_limit = (mem_limit & PCI_MEMORY_RANGE_MASK) << 16;
  44.211 -    pt_dev->regions[pt_dev->region_number].base_addr = mem_base;
  44.212 -    
  44.213 -    if ( mem_base <= mem_limit )
  44.214 -    {
  44.215 -        if ( PT_PCI_SCAN_FORCE_UNSAFE == do_safe_probe )
  44.216 -        {
  44.217 -            mem_modifier = (u16)size_test(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_MEMORY_BASE, 2);
  44.218 -            mem_modifier = FIND_1(mem_modifier);
  44.219 -            pt_dev->regions[pt_dev->region_number].size_granularity = MAX(mem_modifier << 16, 0x100000);
  44.220 -        }
  44.221 -
  44.222 -        pt_dev->regions[pt_dev->region_number].size = mem_limit - mem_base + 
  44.223 -            pt_dev->regions[pt_dev->region_number].size_granularity;
  44.224 -    }
  44.225 -    else
  44.226 -    {
  44.227 -        pt_dev->regions[pt_dev->region_number].size = 0;
  44.228 -        pt_dev->regions[pt_dev->region_number].flags |= PT_PCI_REGION_UNASSIGNED;
  44.229 -    }
  44.230 -    pt_dev->region_number ++;
  44.231 -
  44.232 -    if ( pref_type != (pref_limit & PCI_PREF_RANGE_TYPE_MASK) ||
  44.233 -         (pref_type != PCI_PREF_RANGE_TYPE_32 && pref_type != PCI_PREF_RANGE_TYPE_64) )
  44.234 -    {
  44.235 -        pt_dev->regions[pt_dev->region_number].flags = PT_PCI_REGION_INVALID;
  44.236 -        pt_dev->regions[pt_dev->region_number].type = PT_PCI_ADDRESS_SPACE_MEM_PREFETCH;
  44.237 -        pt_dev->regions[pt_dev->region_number].addr_width = PT_PCI_ADDRESS_WIDTH_UNKNOWN;
  44.238 -    }
  44.239 -    else
  44.240 -    {
  44.241 -        pt_dev->regions[pt_dev->region_number].flags = PT_PCI_REGION_VALID;
  44.242 -        pt_dev->regions[pt_dev->region_number].type = PT_PCI_ADDRESS_SPACE_MEM_PREFETCH;
  44.243 -        pt_dev->regions[pt_dev->region_number].addr_width = PT_PCI_ADDRESS_WIDTH_32;
  44.244 -    }
  44.245 -    
  44.246 -    pref_base = (pref_base & PCI_PREF_RANGE_MASK) << 16;
  44.247 -    pref_limit = (pref_limit & PCI_PREF_RANGE_MASK) << 16;
  44.248 -    pt_dev->regions[pt_dev->region_number].base_addr = pref_base;
  44.249 -
  44.250 -    if ( pref_base <= pref_limit )
  44.251 -    {
  44.252 -
  44.253 -        /* we're not dealing with devices that maps more then 4G memory, hopefully*/ 
  44.254 -        if ( PT_PCI_SCAN_FORCE_UNSAFE == do_safe_probe )
  44.255 -        {
  44.256 -            mem_modifier = (u16)size_test(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_PREF_MEMORY_BASE, 2);
  44.257 -            mem_modifier = FIND_1(mem_modifier);
  44.258 -            pt_dev->regions[pt_dev->region_number].size_granularity = MAX(mem_modifier<< 16,0x100000);
  44.259 -        }
  44.260 -
  44.261 -        pt_dev->regions[pt_dev->region_number].size = pref_limit - pref_base + 
  44.262 -            pt_dev->regions[pt_dev->region_number].size_granularity;
  44.263 -            
  44.264 -        if ( pref_type == PCI_PREF_RANGE_TYPE_64 )
  44.265 -        {
  44.266 -            pt_dev->regions[pt_dev->region_number].addr_width = PT_PCI_ADDRESS_WIDTH_64;    				
  44.267 -            pt_dev->regions[++pt_dev->region_number].base_addr = pci_read_long(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_PREF_BASE_UPPER32);
  44.268 -            pt_dev->regions[pt_dev->region_number].size = pci_read_long(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_PREF_LIMIT_UPPER32) - pt_dev->regions[pt_dev->region_number].base_addr;
  44.269 -        }
  44.270 -
  44.271 -    }
  44.272 -    else
  44.273 -    {
  44.274 -        pt_dev->regions[pt_dev->region_number].size = 0;
  44.275 -        pt_dev->regions[pt_dev->region_number].flags |= PT_PCI_REGION_UNASSIGNED;
  44.276 -    }
  44.277 -
  44.278 -    pt_dev->region_number++;
  44.279 -}
  44.280 -
  44.281 -static void get_bases2(pci_phys_dev_t * pt_dev,pt_pci_scan_t do_safe_probe  )
  44.282 -{
  44.283 -    int i;
  44.284 -    u32 mem_modifier;
  44.285 -    u16 cmd = pci_read_word(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_COMMAND);
  44.286 -    u16 brc = pci_read_word(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_CB_BRIDGE_CONTROL);
  44.287 -    u16 exca = pci_read_word(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_CB_LEGACY_MODE_BASE);
  44.288 -
  44.289 -    for (i=0; i<2; i++)
  44.290 -    {
  44.291 -        int p = 8*i;
  44.292 -        u32 base = pci_read_long(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_CB_MEMORY_BASE_0 + p);
  44.293 -        u32 limit = pci_read_long(pt_dev->bus, pt_dev->dev, pt_dev->func, PCI_CB_MEMORY_LIMIT_0 + p);
  44.294 -
  44.295 -        if ( (limit >= base) && (limit > 0) )
  44.296 -        {
  44.297 -            if ( PT_PCI_SCAN_FORCE_UNSAFE == do_safe_probe )
  44.298 -            {
  44.299 -                mem_modifier = (u32)size_test(pt_dev->bus, pt_dev->dev, pt_dev->func, (PCI_CB_MEMORY_BASE_0+p) ,4);
  44.300 -                mem_modifier = FIND_1(mem_modifier);
  44.301 -                pt_dev->regions[pt_dev->region_number].size_granularity = MAX(mem_modifier,0x1000);
  44.302 -            }
  44.303 -
  44.304 -            pt_dev->regions[pt_dev->region_number].flags = PT_PCI_REGION_VALID;
  44.305 -            pt_dev->regions[pt_dev->region_number].addr_width = PT_PCI_ADDRESS_WIDTH_32;
  44.306 -            pt_dev->regions[pt_dev->region_number].base_addr = base;
  44.307 -            pt_dev->regions[pt_dev->region_number].size = limit - base + pt_dev->regions[pt_dev->region_number].size_granularity;
  44.308 -            
  44.309 -            if ( brc & (PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 << i) )
  44.310 -                pt_dev->regions[pt_dev->region_number].type = PT_PCI_ADDRESS_SPACE_MEM_PREFETCH;
  44.311 -            else
  44.312 -                pt_dev->regions[pt_dev->region_number].type = PT_PCI_ADDRESS_SPACE_MEM;
  44.313 -
  44.314 -            pt_dev->region_number++;
  44.315 -        }
  44.316 -    }
  44.317 -    
  44.318 -    for (i=0; i<2; i++)
  44.319 -    {
  44.320 -        int p = 8*i;
  44.321 -        u32 base = pci_read_long(pt_dev->bus,pt_dev->dev,pt_dev->func,PCI_CB_IO_BASE_0 + p);
  44.322 -        u32 limit = pci_read_long(pt_dev->bus,pt_dev->dev,pt_dev->func,PCI_CB_IO_LIMIT_0 + p);
  44.323 -        
  44.324 -        /* spec claims that this is the only choice */ 
  44.325 -        pt_dev->regions[pt_dev->region_number].size_granularity = 4;
  44.326 -        pt_dev->regions[pt_dev->region_number].addr_width = PT_PCI_ADDRESS_WIDTH_32;
  44.327 -        pt_dev->regions[pt_dev->region_number].type = PT_PCI_ADDRESS_SPACE_IO;
  44.328 -        
  44.329 -        if ( !(base & PCI_IO_RANGE_TYPE_32) )
  44.330 -        {
  44.331 -            base &= 0xffff;
  44.332 -            limit &= 0xffff;
  44.333 -            pt_dev->regions[pt_dev->region_number].addr_width = PT_PCI_ADDRESS_WIDTH_16;
  44.334 -        }
  44.335 -
  44.336 -        base &= PCI_CB_IO_RANGE_MASK;
  44.337 -
  44.338 -        if ( base <= limit )
  44.339 -        {
  44.340 -            pt_dev->regions[pt_dev->region_number].base_addr = base;
  44.341 -            pt_dev->regions[pt_dev->region_number].size = limit - base + 
  44.342 -                pt_dev->regions[pt_dev->region_number].size_granularity;
  44.343 -            pt_dev->regions[pt_dev->region_number].flags = PT_PCI_REGION_VALID;
  44.344 -            pt_dev->region_number++;
  44.345 -        }
  44.346 -    }
  44.347 -
  44.348 -#warning "TBD: The exca handling should be added here"	
  44.349 -}
  44.350 -
  44.351 -static pt_libpci_rc_t  pt_pci_read_regions(pci_phys_dev_t * a_dev, pt_pci_scan_t do_safe_probe)
  44.352 -{
  44.353 -    switch (a_dev->header_type & 0x7f) 
  44.354 -    {
  44.355 -    case PCI_HEADER_TYPE_NORMAL:
  44.356 -        get_bases0(a_dev, do_safe_probe, 6, PCI_ROM_ADDRESS);
  44.357 -        break;
  44.358 -    case PCI_HEADER_TYPE_BRIDGE:
  44.359 -        /*  the part that coincide with the PCI device is 0x10 and 0x14*/
  44.360 -        get_bases0(a_dev, do_safe_probe, 2, PCI_ROM_ADDRESS1);
  44.361 -        get_bases1(a_dev, do_safe_probe);
  44.362 -        break;
  44.363 -    case PCI_HEADER_TYPE_CARDBUS:
  44.364 -        /*  the part that coincide with the PCI device is 0x10*/
  44.365 -        get_bases0(a_dev, do_safe_probe, 1, 0);
  44.366 -        get_bases2(a_dev, do_safe_probe);
  44.367 -        break;
  44.368 -    }
  44.369 -}
  44.370 -
  44.371 -pt_libpci_rc_t pt_bus_probe(u8 bus, pt_pci_scan_t do_safe_probe)
  44.372 -{
  44.373 -    u8 dev, multi, func, ht;
  44.374 -    pci_phys_dev_t * current;
  44.375 -    
  44.376 -    for (dev=0; dev<32; dev++)
  44.377 -    {
  44.378 -        for (func=0, multi=1; ((multi != 0) && (func < 8)); func++)
  44.379 -        {
  44.380 -            if ( (current = pt_devfn_probe(bus, dev, func, do_safe_probe)) == NULL )
  44.381 -            {
  44.382 -                /* it could be anything, we can not recognize the device or it simply is not present -
  44.383 -                anyway just skip the given device and all its functions */
  44.384 -                continue;
  44.385 -            }
  44.386 -
  44.387 -            if ( func == 0 )
  44.388 -                multi = current->header_type & 0x80;
  44.389 -            
  44.390 -            switch (current->header_type & 0x7f) {
  44.391 -            case PCI_HEADER_TYPE_NORMAL:
  44.392 -                break;
  44.393 -            case PCI_HEADER_TYPE_BRIDGE:
  44.394 -            case PCI_HEADER_TYPE_CARDBUS:
  44.395 -                current->secondary_bus = pci_read_byte(bus, dev, func, PCI_SECONDARY_BUS);
  44.396 -                pt_bus_probe(current->secondary_bus, do_safe_probe);
  44.397 -                break;
  44.398 -            }
  44.399 -        }
  44.400 -    }
  44.401 -    
  44.402 -    return PT_RC_SUCCESS;
  44.403 -}
  44.404 -
  44.405 -pci_phys_dev_t * pt_devfn_probe(u8 bus, u8 dev, u8 func, pt_pci_scan_t do_safe_probe)
  44.406 -{
  44.407 -    u32 vd;
  44.408 -    u16 tmp;
  44.409 -    pci_phys_dev_t * current;  
  44.410 -
  44.411 -    /* Check the vital signs of the device */    
  44.412 -    tmp =  pci_read_word(bus, dev, func, PCI_VENDOR_ID);
  44.413 -    if ( !tmp || tmp == 0xffff )
  44.414 -        return NULL;
  44.415 -
  44.416 -    /* do we have this guy already? */
  44.417 -    if ( (current = pt_lookup_device_in_tree(bus, dev, func)) == NULL )
  44.418 -    {
  44.419 -        current = pt_alloc_pci_device();
  44.420 -        current->bus = bus;
  44.421 -        current->dev = dev;
  44.422 -        current->func = func;
  44.423 -        pt_add_device_to_tree(current);
  44.424 -        if (do_safe_probe == PT_PCI_SCAN_FORCE_AUTO) 
  44.425 -            do_safe_probe = PT_PCI_SCAN_FORCE_UNSAFE;
  44.426 -    } 
  44.427 -    else
  44.428 -        /* we have already handled this device, no need to take risks */
  44.429 -        do_safe_probe = PT_PCI_SCAN_FORCE_SAFE;
  44.430 -    
  44.431 -    /* Start rescan */
  44.432 -    current->region_number = 0;
  44.433 -    current->vendor_id = tmp;
  44.434 -    current->device_id =  pci_read_word(bus, dev, func, PCI_DEVICE_ID);
  44.435 -    current->device_class = pci_read_long(bus, dev, func, PCI_CLASS_REVISION);
  44.436 -    current->irq = pci_get_irq(bus, dev, func);
  44.437 -    current->header_type = pci_read_byte(bus, dev, func, PCI_HEADER_TYPE);
  44.438 -    pt_pci_read_regions(current, do_safe_probe);
  44.439 -    
  44.440 -    return current;
  44.441 -}
  44.442 -
    45.1 --- a/tools/ioemu/pt-libpci/pt_pci_probe.h	Thu Aug 23 13:42:03 2007 -0700
    45.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    45.3 @@ -1,28 +0,0 @@
    45.4 -/*****************************************************************************
    45.5 -
    45.6 -    Copyright (c) 2007, Neocleus: Guy Zana, Alex Novik
    45.7 -
    45.8 -******************************************************************************/
    45.9 -#ifndef __PT_PCI_PROBE_H__
   45.10 -#define __PT_PCI_PROBE_H__
   45.11 -
   45.12 -#include "pt_libpci.h"
   45.13 -
   45.14 -#ifndef MAX
   45.15 -#define MAX(x,y) (((x)>(y))?(x) : (y))
   45.16 -#endif
   45.17 -
   45.18 -#define FIND_1(input) (((((input)-1)^(input))+1)>>1)
   45.19 -
   45.20 -typedef enum pt_pci_scan_e {
   45.21 -    PT_PCI_SCAN_FORCE_SAFE     = 0,
   45.22 -    PT_PCI_SCAN_FORCE_UNSAFE   = 1,	
   45.23 -    PT_PCI_SCAN_FORCE_AUTO     = 2
   45.24 -} pt_pci_scan_t;
   45.25 -
   45.26 -pci_phys_dev_t * pt_devfn_probe(u8 bus, u8 dev, u8 func, 
   45.27 -                                pt_pci_scan_t do_safe_probe);
   45.28 -pt_libpci_rc_t pt_bus_probe(u8 bus, pt_pci_scan_t do_safe_probe);
   45.29 -
   45.30 -#endif /* __PT_PCI_PROBE_H__ */
   45.31 -
    46.1 --- a/tools/ioemu/pt-libpci/pt_pci_tree.c	Thu Aug 23 13:42:03 2007 -0700
    46.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    46.3 @@ -1,202 +0,0 @@
    46.4 -/*****************************************************************************
    46.5 -
    46.6 -    Copyright (c) 2007, Neocleus: Alex Novik, Guy Zana
    46.7 -
    46.8 -******************************************************************************/
    46.9 -#include <stdio.h>
   46.10 -#include <stdlib.h>
   46.11 -#include <string.h>
   46.12 -
   46.13 -#include "pt_libpci.h"
   46.14 -#include "pt_pci_probe.h"
   46.15 -#include "pt_pci_access.h"
   46.16 -#include "pt_pci_tree.h"
   46.17 -
   46.18 -extern FILE * logfile;
   46.19 -
   46.20 -/* 
   46.21 -    pci_tree is our hash array for the pci devices in the system.
   46.22 -
   46.23 -    Each device is placed in its position which is computed by this function:
   46.24 -    ((bus << 8) | (device << 5) | (function)) % MAX_PCI_HASH_ARRAY
   46.25 -
   46.26 -*/
   46.27 -pci_phys_dev_t * pci_tree[MAX_PCI_HASH_ARRAY];
   46.28 -
   46.29 -
   46.30 -pt_libpci_rc_t pt_device_tree_init(void)
   46.31 -{
   46.32 -    unsigned long i;
   46.33 -
   46.34 -    for (i=0; i < MAX_PCI_HASH_ARRAY; i++) {
   46.35 -        pci_tree[i] = NULL;
   46.36 -    }
   46.37 -
   46.38 -    return (PT_RC_SUCCESS);
   46.39 -}
   46.40 -
   46.41 -pci_phys_dev_t * pt_alloc_pci_device(void)
   46.42 -{
   46.43 -    pci_phys_dev_t * dev;
   46.44 -
   46.45 -    dev = (pci_phys_dev_t *) malloc(sizeof(pci_phys_dev_t));
   46.46 -
   46.47 -    /* Initialize data */
   46.48 -    memset(dev, 0, sizeof(pci_phys_dev_t));
   46.49 -    dev->device_id = dev->vendor_id = 0xffff;
   46.50 -    dev->device_class = 0xffffffff;
   46.51 -    
   46.52 -    return (dev);
   46.53 -}
   46.54 -
   46.55 -pt_libpci_rc_t pt_free_pci_device(pci_phys_dev_t * a_dev)
   46.56 -{
   46.57 -    if (a_dev)
   46.58 -        free(a_dev);
   46.59 -
   46.60 -    a_dev = NULL;
   46.61 -    
   46.62 -    return PT_RC_SUCCESS;
   46.63 -}
   46.64 -
   46.65 -pt_libpci_rc_t pt_add_device_to_tree(pci_phys_dev_t * a_dev)
   46.66 -{
   46.67 -
   46.68 -    unsigned long dev_key;
   46.69 -    unsigned long i;
   46.70 -
   46.71 -    if (NULL == a_dev) {
   46.72 -        return (PT_RC_FAILURE);
   46.73 -    }
   46.74 -
   46.75 -    dev_key = PCI_DEV_GET_INDEX(a_dev);
   46.76 -
   46.77 -    /* find an empty slot */
   46.78 -    for (i=0; i < MAX_PCI_HASH_ARRAY; i++) {
   46.79 -        if (NULL == pci_tree[(dev_key+i) % MAX_PCI_HASH_ARRAY]) {
   46.80 -            break;
   46.81 -        }
   46.82 -    }
   46.83 -
   46.84 -    /* check errors */
   46.85 -    if (i == MAX_PCI_HASH_ARRAY) {
   46.86 -        return (PT_RC_FAILURE);
   46.87 -    }
   46.88 -
   46.89 -    pci_tree[(dev_key+i) % MAX_PCI_HASH_ARRAY] = a_dev;
   46.90 -    return (PT_RC_SUCCESS);	
   46.91 -
   46.92 -}
   46.93 -
   46.94 -pci_phys_dev_t * pt_lookup_device_in_tree(u8 bus, u8 dev, u8 func)
   46.95 -{
   46.96 -
   46.97 -    unsigned long dev_key;
   46.98 -    pci_phys_dev_t * cur_dev;
   46.99 -    unsigned long i;
  46.100 -
  46.101 -    dev_key = PCI_GET_INDEX(bus, dev, func);
  46.102 -
  46.103 -    for (i=0; i < MAX_PCI_HASH_ARRAY; i++) {
  46.104 -        cur_dev = pci_tree[(dev_key+i) % MAX_PCI_HASH_ARRAY];
  46.105 -        if ((NULL != cur_dev) && ((bus == cur_dev->bus) && (dev == cur_dev->dev) && (func == cur_dev->func))) {
  46.106 -            break;
  46.107 -        }
  46.108 -    }
  46.109 -
  46.110 -    /* check errors */
  46.111 -    if (i == MAX_PCI_HASH_ARRAY) {
  46.112 -        return (NULL);
  46.113 -    }
  46.114 -
  46.115 -    return (cur_dev);
  46.116 -
  46.117 -}
  46.118 -
  46.119 -pci_phys_dev_t * pt_remove_device_from_tree(u8 bus, u8 dev, u8 func)
  46.120 -{
  46.121 -    unsigned long dev_key;
  46.122 -    pci_phys_dev_t * cur_dev;
  46.123 -    unsigned long i;
  46.124 -
  46.125 -    dev_key = PCI_GET_INDEX(bus, dev, func);
  46.126 -
  46.127 -    for (i=0; i < MAX_PCI_HASH_ARRAY; i++) {
  46.128 -        cur_dev = pci_tree[(dev_key+i) % MAX_PCI_HASH_ARRAY];
  46.129 -        if ((NULL != cur_dev) && ((bus == cur_dev->bus) && (dev == cur_dev->dev) && (func == cur_dev->func))) {
  46.130 -            pci_tree[(dev_key+i) % MAX_PCI_HASH_ARRAY] = NULL;
  46.131 -            break;
  46.132 -        }
  46.133 -    }
  46.134 -
  46.135 -    /* check errors */
  46.136 -    if (i == MAX_PCI_HASH_ARRAY) {
  46.137 -        return (NULL);
  46.138 -    }
  46.139 -
  46.140 -    return (cur_dev);	
  46.141 -}
  46.142 -
  46.143 -pt_libpci_rc_t pt_clean_tree(void)
  46.144 -{
  46.145 -    unsigned long i;
  46.146 -
  46.147 -    for (i=0; i < MAX_PCI_HASH_ARRAY; i++)
  46.148 -        pt_free_pci_device(pci_tree[i]);
  46.149 -
  46.150 -    return PT_RC_SUCCESS;
  46.151 -}
  46.152 -
  46.153 -void pt_print_device(FILE * fout, pci_phys_dev_t * dev)
  46.154 -{
  46.155 -    unsigned long i;
  46.156 -
  46.157 -    fprintf(fout, "-----=[ %02x:%02x.%x ]=-----\n", dev->bus, dev->dev, dev->func);
  46.158 -    fprintf(fout, "Regions:\n");
  46.159 -    
  46.160 -    for (i=0; i < dev->region_number; i++) {
  46.161 -
  46.162 -        if (!PCI_REGION_IS_VALID(dev, i)) {
  46.163 -            continue;
  46.164 -        }
  46.165 -        
  46.166 -        fprintf(fout, "[%d] \t%dBits: %s (flags=0x%04x)\n", i, dev->regions[i].addr_width,
  46.167 -            PT_GET_TYPE_STR(dev->regions[i].type), (u32)dev->regions[i].flags);
  46.168 -            
  46.169 -        if (dev->regions[i].addr_width == PT_PCI_ADDRESS_WIDTH_64) {
  46.170 -            fprintf(fout, "\t\tBase: 0x%016Lx Size: 0x%016Lx\n", 
  46.171 -                PT_GET64(dev->regions[i+1].base_addr, dev->regions[i].base_addr),
  46.172 -                PT_GET64(dev->regions[i+1].size, dev->regions[i].size));
  46.173 -                
  46.174 -            i++;
  46.175 -        } else {
  46.176 -            fprintf(fout, "\t\tBase: 0x%08x Size: 0x%08x\n",
  46.177 -                (u32) dev->regions[i].base_addr, (u32) dev->regions[i].size);
  46.178 -        }
  46.179 -    }
  46.180 -
  46.181 -    /* Expansion ROM */
  46.182 -    if ((dev->rom_size != 0) && (dev->rom_base_addr != 0)) {
  46.183 -        fprintf(fout, "[6] ROM:\n");
  46.184 -        fprintf(fout, "\t\tBase: 0x%08x Size: 0x%08x\n", dev->rom_base_addr, dev->rom_size);
  46.185 -    }
  46.186 -
  46.187 -    fprintf(fout, "IRQ: %d\n", dev->irq);
  46.188 -    fprintf(fout, "[END: %02x:%02x.%x ]\n\n", dev->bus, dev->dev, dev->func);
  46.189 -
  46.190 -}
  46.191 -
  46.192 -void pt_print_device_map(void)
  46.193 -{
  46.194 -    pci_phys_dev_t * cur_dev;
  46.195 -    unsigned long i,devnum=0;
  46.196 -
  46.197 -    for (i=0; i < MAX_PCI_HASH_ARRAY; i++) {
  46.198 -        if (NULL != pci_tree[i]) { 
  46.199 -            devnum++;
  46.200 -            pt_print_device(logfile, pci_tree[i]);
  46.201 -        }
  46.202 -    }
  46.203 -    
  46.204 -    fprintf(logfile, "Number of devices = %d\n", devnum);
  46.205 -}
    47.1 --- a/tools/ioemu/pt-libpci/pt_pci_tree.h	Thu Aug 23 13:42:03 2007 -0700
    47.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    47.3 @@ -1,31 +0,0 @@
    47.4 -/*****************************************************************************
    47.5 -
    47.6 -    Copyright (c) 2007, Neocleus: Alex Novik, Guy Zana
    47.7 -
    47.8 -******************************************************************************/
    47.9 -#ifndef __PT_PCI_TREE_H__
   47.10 -#define __PT_PCI_TREE_H__
   47.11 -
   47.12 -#include <stdio.h>
   47.13 -
   47.14 -#include "pt_libpci.h"
   47.15 -
   47.16 -/* Our PCI device tree is hashed into an array of 1021 pointers */
   47.17 -#define MAX_PCI_HASH_ARRAY      (1021)
   47.18 -#define PCI_GET_INDEX(b,d,f)    ((unsigned long)((((((b)&0xFF)<<8) | (((d)&0x1F)<<5) | ((f)&0x7))) % MAX_PCI_HASH_ARRAY))
   47.19 -#define PCI_DEV_GET_INDEX(a)    PCI_GET_INDEX(a->bus, a->dev, a->func)
   47.20 -
   47.21 -
   47.22 -/* PCI tree data structures */
   47.23 -pt_libpci_rc_t pt_device_tree_init(void);
   47.24 -pci_phys_dev_t * pt_alloc_pci_device(void);
   47.25 -pt_libpci_rc_t pt_free_pci_device(pci_phys_dev_t * a_dev);
   47.26 -pt_libpci_rc_t pt_add_device_to_tree(pci_phys_dev_t * a_dev);
   47.27 -pci_phys_dev_t * pt_lookup_device_in_tree(u8 bus, u8 dev, u8 func);
   47.28 -pci_phys_dev_t * pt_remove_device_in_tree(u8 bus, u8 dev, u8 func);
   47.29 -pt_libpci_rc_t pt_clean_tree(void);
   47.30 -
   47.31 -void pt_print_device(FILE * fout, pci_phys_dev_t * dev);
   47.32 -void pt_print_device_map(void);
   47.33 -
   47.34 -#endif /* __PT_PCI_TREE_H__ */
    48.1 --- a/tools/ioemu/pt-libpci/pt_util.c	Thu Aug 23 13:42:03 2007 -0700
    48.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
    48.3 @@ -1,62 +0,0 @@
    48.4 -#include <stdio.h>
    48.5 -#include <stdlib.h>
    48.6 -#include <string.h>
    48.7 -
    48.8 -#include "pt_libpci.h"
    48.9 -#include "pt_pci_probe.h"
   48.10 -#include "pt_pci_access.h"
   48.11 -#include "pt_pci_tree.h"
   48.12 -
   48.13 -u8 find_cap_offset(u8 bus, u8 device, u8 func, u8 cap)
   48.14 -{
   48.15 -    int id;
   48.16 -    int max_cap = 48;
   48.17 -    int pos = PCI_CAPABILITY_LIST;
   48.18 -    int status;
   48.19 -
   48.20 -    status = pci_read_byte(bus, device, func, PCI_STATUS);
   48.21 -    if ( (status & PCI_STATUS_CAP_LIST) == 0 )
   48.22 -        return 0;
   48.23 -
   48.24 -    while ( max_cap-- )
   48.25 -    {
   48.26 -        pos = pci_read_byte(bus, device, func, pos);
   48.27 -        if ( pos < 0x40 )
   48.28 -            break;
   48.29 -
   48.30 -        pos &= ~3;
   48.31 -        id = pci_read_byte(bus, device, func, pos + PCI_CAP_LIST_ID);
   48.32 -
   48.33 -        if ( id == 0xff )
   48.34 -            break;
   48.35 -        if ( id == cap )
   48.36 -            return pos;
   48.37 -
   48.38 -        pos += PCI_CAP_LIST_NEXT;
   48.39 -    }
   48.40 -    return 0;
   48.41 -}
   48.42 -
   48.43 -#define PCI_EXP_DEVCAP_FLR    (1 << 28)
   48.44 -#define PCI_EXP_DEVCTL_FLR     0x1b
   48.45 -
   48.46 -void pdev_flr(u8 bus, u8 device, u8 func)
   48.47 -{
   48.48 -    int pos;
   48.49 -    int dev_cap;
   48.50 -    int dev_status;
   48.51 -
   48.52 -    pos = find_cap_offset(bus, device, func, PCI_CAP_ID_EXP);
   48.53 -    if ( pos )
   48.54 -    {
   48.55 -        dev_cap = pci_read_long(bus, device, func, pos + PCI_EXP_DEVCAP);
   48.56 -        if ( dev_cap & PCI_EXP_DEVCAP_FLR )
   48.57 -        {
   48.58 -            pci_write_word(bus, device, func, pos + PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_FLR);
   48.59 -            do {
   48.60 -                dev_status = pci_read_long(bus, device, func, pos + PCI_EXP_DEVSTA);
   48.61 -            } while (dev_status & PCI_EXP_DEVSTA_TRPND);
   48.62 -        }
   48.63 -    }
   48.64 -}
   48.65 -
    49.1 --- a/tools/ioemu/target-i386-dm/exec-dm.c	Thu Aug 23 13:42:03 2007 -0700
    49.2 +++ b/tools/ioemu/target-i386-dm/exec-dm.c	Wed Aug 29 00:48:01 2007 +0300
    49.3 @@ -568,8 +568,6 @@ void cpu_physical_memory_rw(target_phys_
    49.4                  memcpy_words(buf, ptr, l);
    49.5              } else {
    49.6                  /* Neither RAM nor known MMIO space */
    49.7 -                fprintf(logfile,"cpu_physical_memory_rw error: Neither RAM nor known MMIO space.\n"
    49.8 -                    "\taddr=" TARGET_FMT_lx " len=%08x is_write=%d\n", addr, len, is_write);                
    49.9                  memset(buf, 0xff, len); 
   49.10              }
   49.11          }
    50.1 --- a/tools/ioemu/target-i386-dm/helper2.c	Thu Aug 23 13:42:03 2007 -0700
    50.2 +++ b/tools/ioemu/target-i386-dm/helper2.c	Wed Aug 29 00:48:01 2007 +0300
    50.3 @@ -92,36 +92,6 @@ int send_vcpu = 0;
    50.4  #define NR_CPUS 32
    50.5  evtchn_port_t ioreq_local_port[NR_CPUS];
    50.6  
    50.7 -void dump_ioreq(ioreq_t * ioreq)
    50.8 -{
    50.9 -    char csize;
   50.10 -
   50.11 -    switch (ioreq->size) {
   50.12 -    case 1:
   50.13 -        csize = 'B';
   50.14 -        break;
   50.15 -    case 2:
   50.16 -        csize = 'W';
   50.17 -        break;
   50.18 -    case 4:
   50.19 -        csize = 'L';
   50.20 -        break;
   50.21 -    default:
   50.22 -        csize = '?';
   50.23 -    }
   50.24 -
   50.25 -    fprintf(logfile, TARGET_FMT_lx ": [%c%c] addr: 0x" TARGET_FMT_lx " [count: %u] data: 0x" TARGET_FMT_lx " data_is_ptr=%u\n",
   50.26 -        ioreq->io_count,
   50.27 -        (ioreq->dir==IOREQ_READ)?'R':'W',
   50.28 -        csize,
   50.29 -        ioreq->addr,
   50.30 -        (uint32_t)ioreq->count,
   50.31 -        ioreq->data,
   50.32 -        ioreq->data_is_ptr); 
   50.33 -        
   50.34 -} 
   50.35 -
   50.36 -
   50.37  CPUX86State *cpu_x86_init(void)
   50.38  {
   50.39      CPUX86State *env;
   50.40 @@ -561,7 +531,6 @@ void __handle_ioreq(CPUState *env, ioreq
   50.41          qemu_invalidate_map_cache();
   50.42          break;
   50.43      default:
   50.44 -        dump_ioreq(req);
   50.45          hw_error("Invalid ioreq type 0x%x\n", req->type);
   50.46      }
   50.47  }
    51.1 --- a/tools/ioemu/target-i386-dm/piix_pci-dm.c	Thu Aug 23 13:42:03 2007 -0700
    51.2 +++ b/tools/ioemu/target-i386-dm/piix_pci-dm.c	Wed Aug 29 00:48:01 2007 +0300
    51.3 @@ -40,46 +40,6 @@ static uint32_t i440fx_addr_readl(void* 
    51.4      return s->config_reg;
    51.5  }
    51.6  
    51.7 -static void i440fx_addr_writew(void* opaque, uint32_t addr, uint32_t val)
    51.8 -{
    51.9 -    I440FXState *s = opaque;
   51.10 -    uint32_t offset_bits = (addr - 0xcf8) * 8;
   51.11 -
   51.12 -    s->config_reg &= ~(0x0000FFFF << offset_bits);
   51.13 -    s->config_reg |= ((uint16_t)val << offset_bits);
   51.14 -}
   51.15 -
   51.16 -static uint32_t i440fx_addr_readw(void* opaque, uint32_t addr)
   51.17 -{
   51.18 -    I440FXState *s = opaque;
   51.19 -    uint32_t offset_bits = (addr - 0xcf8) * 8;
   51.20 -    uint32_t val;
   51.21 -
   51.22 -    val = (s->config_reg >> offset_bits) & 0xFFFF;
   51.23 -    
   51.24 -    return val;
   51.25 -}
   51.26 -
   51.27 -static void i440fx_addr_writeb(void* opaque, uint32_t addr, uint32_t val)
   51.28 -{
   51.29 -    I440FXState *s = opaque;
   51.30 -    uint32_t offset_bits = (addr - 0xcf8) * 8;
   51.31 -
   51.32 -    s->config_reg &= ~(0x000000FF << offset_bits);
   51.33 -    s->config_reg |= ((val & 0xFF) << offset_bits);
   51.34 -}
   51.35 -
   51.36 -static uint32_t i440fx_addr_readb(void* opaque, uint32_t addr)
   51.37 -{
   51.38 -    I440FXState *s = opaque;
   51.39 -    uint32_t offset_bits = (addr - 0xcf8) * 8;
   51.40 -    uint32_t val;
   51.41 -
   51.42 -    val = (s->config_reg >> offset_bits) & 0xFF;
   51.43 -    
   51.44 -    return val;
   51.45 -}
   51.46 -
   51.47  /* return the global irq number corresponding to a given device irq
   51.48     pin. We could also use the bus number to have a more precise
   51.49     mapping. */
   51.50 @@ -136,11 +96,7 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_
   51.51      b = pci_register_bus(i440fx_set_irq, pci_slot_get_pirq, NULL, 0, 128);
   51.52      s->bus = b;
   51.53  
   51.54 -    register_ioport_write(0xcf8, 4, 1, i440fx_addr_writeb, s);
   51.55 -    register_ioport_write(0xcf8, 4, 2, i440fx_addr_writew, s);
   51.56      register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
   51.57 -    register_ioport_read(0xcf8, 4, 1, i440fx_addr_readb, s);
   51.58 -    register_ioport_read(0xcf8, 4, 2, i440fx_addr_readw, s);
   51.59      register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
   51.60  
   51.61      register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
    52.1 --- a/tools/ioemu/vl.c	Thu Aug 23 13:42:03 2007 -0700
    52.2 +++ b/tools/ioemu/vl.c	Wed Aug 29 00:48:01 2007 +0300
    52.3 @@ -195,13 +195,10 @@ unsigned char challenge[AUTHCHALLENGESIZ
    52.4  target_phys_addr_t isa_mem_base = 0;
    52.5  PicState2 *isa_pic;
    52.6  
    52.7 -/* Tells whether this is a NativeDom instance of qemu (1:1 mapping is enabled) */
    52.8 -uint8_t is_nativedom = 0;
    52.9 -
   52.10  uint32_t default_ioport_readb(void *opaque, uint32_t address)
   52.11  {
   52.12  #ifdef DEBUG_UNUSED_IOPORT
   52.13 -    fprintf(logfile, "inb: port=0x%04x\n", address);
   52.14 +    fprintf(stderr, "inb: port=0x%04x\n", address);
   52.15  #endif
   52.16      return 0xff;
   52.17  }
   52.18 @@ -209,8 +206,7 @@ uint32_t default_ioport_readb(void *opaq
   52.19  void default_ioport_writeb(void *opaque, uint32_t address, uint32_t data)
   52.20  {
   52.21  #ifdef DEBUG_UNUSED_IOPORT
   52.22 -    fprintf(logfile, "outb: port=0x%04x data=0x%02x %c\n", 
   52.23 -        address, data, (address==0xe9)?(char)data:' ');
   52.24 +    fprintf(stderr, "outb: port=0x%04x data=0x%02x\n", address, data);
   52.25  #endif
   52.26  }
   52.27  
   52.28 @@ -218,11 +214,6 @@ void default_ioport_writeb(void *opaque,
   52.29  uint32_t default_ioport_readw(void *opaque, uint32_t address)
   52.30  {
   52.31      uint32_t data;
   52.32 -
   52.33 -#ifdef DEBUG_UNUSED_IOPORT
   52.34 -    fprintf(logfile, "inw port=0x%04x (breaking to two reads)\n", address);
   52.35 -#endif
   52.36 -    
   52.37      data = ioport_read_table[0][address](ioport_opaque[address], address);
   52.38      address = (address + 1) & (MAX_IOPORTS - 1);
   52.39      data |= ioport_read_table[0][address](ioport_opaque[address], address) << 8;
   52.40 @@ -231,11 +222,6 @@ uint32_t default_ioport_readw(void *opaq
   52.41  
   52.42  void default_ioport_writew(void *opaque, uint32_t address, uint32_t data)
   52.43  {
   52.44 -
   52.45 -#ifdef DEBUG_UNUSED_IOPORT
   52.46 -    fprintf(logfile, "outw port=0x%04x data=0x%04x (breaking to two reads)\n", address, data);
   52.47 -#endif
   52.48 -
   52.49      ioport_write_table[0][address](ioport_opaque[address], address, data & 0xff);
   52.50      address = (address + 1) & (MAX_IOPORTS - 1);
   52.51      ioport_write_table[0][address](ioport_opaque[address], address, (data >> 8) & 0xff);
   52.52 @@ -244,7 +230,7 @@ void default_ioport_writew(void *opaque,
   52.53  uint32_t default_ioport_readl(void *opaque, uint32_t address)
   52.54  {
   52.55  #ifdef DEBUG_UNUSED_IOPORT
   52.56 -    fprintf(logfile, "inl: port=0x%04x\n", address);
   52.57 +    fprintf(stderr, "inl: port=0x%04x\n", address);
   52.58  #endif
   52.59      return 0xffffffff;
   52.60  }
   52.61 @@ -252,8 +238,7 @@ uint32_t default_ioport_readl(void *opaq
   52.62  void default_ioport_writel(void *opaque, uint32_t address, uint32_t data)
   52.63  {
   52.64  #ifdef DEBUG_UNUSED_IOPORT
   52.65 -    fprintf(logfile, "outl: port=0x%04x data=0x%02x (cs=%04x eip=%08x)\n", 
   52.66 -        address, data);
   52.67 +    fprintf(stderr, "outl: port=0x%04x data=0x%02x\n", address, data);
   52.68  #endif
   52.69  }
   52.70  
   52.71 @@ -6512,9 +6497,6 @@ enum {
   52.72      QEMU_OPTION_acpi,
   52.73      QEMU_OPTION_vncviewer,
   52.74      QEMU_OPTION_vncunused,
   52.75 -
   52.76 -    QEMU_OPTION_nativedom,
   52.77 -    QEMU_OPTION_pci,
   52.78  };
   52.79  
   52.80  typedef struct QEMUOption {
   52.81 @@ -6612,10 +6594,6 @@ const QEMUOption qemu_options[] = {
   52.82      { "d", HAS_ARG, QEMU_OPTION_d },
   52.83      { "vcpus", 1, QEMU_OPTION_vcpus },
   52.84      { "acpi", 0, QEMU_OPTION_acpi },
   52.85 -
   52.86 -    { "nativedom", HAS_ARG, QEMU_OPTION_nativedom },
   52.87 -    { "pci", HAS_ARG, QEMU_OPTION_pci},
   52.88 -    
   52.89      { NULL },
   52.90  };
   52.91  
   52.92 @@ -7081,8 +7059,7 @@ int main(int argc, char **argv)
   52.93  #endif
   52.94  
   52.95      char qemu_dm_logfilename[128];
   52.96 -    const char *direct_pci = NULL;
   52.97 -
   52.98 +    
   52.99      /* Ensure that SIGUSR2 is blocked by default when a new thread is created,
  52.100         then only the threads that use the signal unblock it -- this fixes a
  52.101         race condition in Qcow support where the AIO signal is misdelivered.  */
  52.102 @@ -7580,12 +7557,6 @@ int main(int argc, char **argv)
  52.103              case QEMU_OPTION_vncunused:
  52.104                  vncunused++;
  52.105                  break;
  52.106 -            case QEMU_OPTION_nativedom:
  52.107 -                is_nativedom=1;
  52.108 -                break;
  52.109 -            case QEMU_OPTION_pci:
  52.110 -                direct_pci = optarg;
  52.111 -                break;
  52.112              }
  52.113          }
  52.114      }
  52.115 @@ -7643,21 +7614,6 @@ int main(int argc, char **argv)
  52.116  #endif
  52.117  
  52.118  #ifdef CONFIG_DM
  52.119 -    xc_handle = xc_interface_open();
  52.120 -
  52.121 -    /* Compute the RAM size of nativedom */    
  52.122 -    if ( is_nativedom )
  52.123 -    {
  52.124 -        if ( !xc_is_nativedom_enabled(xc_handle) )
  52.125 -        {
  52.126 -            fprintf(logfile, "Error: NativeDom is not enabled. Use the enable_nativedom=1 boot parameter\n");
  52.127 -            exit(1);
  52.128 -        }
  52.129 -
  52.130 -        /* Recompute the size of RAM */
  52.131 -        ram_size = xc_get_nativedom_last_mfn(xc_handle) << 12;
  52.132 -    }
  52.133 -
  52.134      bdrv_init();
  52.135      xenstore_parse_domain_config(domid);
  52.136  #endif /* CONFIG_DM */
  52.137 @@ -7756,6 +7712,8 @@ int main(int argc, char **argv)
  52.138  
  52.139  #ifdef CONFIG_DM
  52.140  
  52.141 +    xc_handle = xc_interface_open();
  52.142 +
  52.143  #if defined(__i386__) || defined(__x86_64__)
  52.144  
  52.145      if (qemu_map_cache_init()) {
  52.146 @@ -7965,8 +7923,7 @@ int main(int argc, char **argv)
  52.147  
  52.148      machine->init(ram_size, vga_ram_size, boot_device,
  52.149                    ds, fd_filename, snapshot,
  52.150 -                  kernel_filename, kernel_cmdline, initrd_filename,
  52.151 -                  direct_pci);
  52.152 +                  kernel_filename, kernel_cmdline, initrd_filename);
  52.153      free(boot_device);
  52.154  
  52.155      /* init USB devices */
    53.1 --- a/tools/ioemu/vl.h	Thu Aug 23 13:42:03 2007 -0700
    53.2 +++ b/tools/ioemu/vl.h	Wed Aug 29 00:48:01 2007 +0300
    53.3 @@ -727,7 +727,7 @@ typedef void QEMUMachineInitFunc(uint64_
    53.4                                   char *boot_device,
    53.5               DisplayState *ds, const char **fd_filename, int snapshot,
    53.6               const char *kernel_filename, const char *kernel_cmdline,
    53.7 -             const char *initrd_filename, const char *direct_pci);
    53.8 +             const char *initrd_filename);
    53.9  
   53.10  typedef struct QEMUMachine {
   53.11      const char *name;