direct-io.hg

changeset 14087:6253b8d32eb9

xentrace: Add a relative TSC field (kept track per CPU) to xentrace_format.

Additionally a default line is added (key 0x00000000) which is used
when no specific entry in the format file is found.

Signed-off-by: Thomas Friebel <thomas.friebel@amd.com>
author kfraser@localhost.localdomain
date Fri Feb 23 16:36:55 2007 +0000 (2007-02-23)
parents 58086aa7c70a
children c64aa7fb7712 77298360e365
files tools/xentrace/formats tools/xentrace/xentrace_format
line diff
     1.1 --- a/tools/xentrace/formats	Fri Feb 23 16:24:07 2007 +0000
     1.2 +++ b/tools/xentrace/formats	Fri Feb 23 16:36:55 2007 +0000
     1.3 @@ -1,42 +1,44 @@
     1.4 -0x0001f001	CPU%(cpu)d	%(tsc)d		lost_records        0x%(1)08x
     1.5 +0x00000000  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  unknown (0x%(event)016x)  [ 0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x ]
     1.6 +
     1.7 +0x0001f001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  lost_records        0x%(1)08x
     1.8  
     1.9 -0x0002f001	CPU%(cpu)d	%(tsc)d		sched_add_domain	[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.10 -0x0002f002	CPU%(cpu)d	%(tsc)d		sched_rem_domain	[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.11 -0x0002f003	CPU%(cpu)d	%(tsc)d		domain_sleep		[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.12 -0x0002f004	CPU%(cpu)d	%(tsc)d		domain_wake		[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.13 -0x0002f005	CPU%(cpu)d	%(tsc)d		do_yield		[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.14 -0x0002f006	CPU%(cpu)d	%(tsc)d		do_block		[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.15 -0x0002f007	CPU%(cpu)d	%(tsc)d		domain_shutdown		[ domid = 0x%(1)08x, edomid = 0x%(2)08x, reason = 0x%(3)08x ]
    1.16 -0x0002f008	CPU%(cpu)d	%(tsc)d		sched_ctl
    1.17 -0x0002f009	CPU%(cpu)d	%(tsc)d		sched_adjdom		[ domid = 0x%(1)08x ]
    1.18 -0x0002f00a	CPU%(cpu)d	%(tsc)d		__enter_scheduler	[ prev<domid:edomid> = 0x%(1)08x : 0x%(2)08x, next<domid:edomid> = 0x%(3)08x : 0x%(4)08x ]
    1.19 -0x0002f00B	CPU%(cpu)d	%(tsc)d		s_timer_fn
    1.20 -0x0002f00c	CPU%(cpu)d	%(tsc)d		t_timer_fn
    1.21 -0x0002f00d	CPU%(cpu)d	%(tsc)d		dom_timer_fn
    1.22 +0x0002f001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  sched_add_domain	[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.23 +0x0002f002  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  sched_rem_domain	[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.24 +0x0002f003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  domain_sleep		[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.25 +0x0002f004  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  domain_wake		[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.26 +0x0002f005  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  do_yield		[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.27 +0x0002f006  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  do_block		[ domid = 0x%(1)08x, edomid = 0x%(2)08x ]
    1.28 +0x0002f007  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  domain_shutdown		[ domid = 0x%(1)08x, edomid = 0x%(2)08x, reason = 0x%(3)08x ]
    1.29 +0x0002f008  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  sched_ctl
    1.30 +0x0002f009  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  sched_adjdom		[ domid = 0x%(1)08x ]
    1.31 +0x0002f00a  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  __enter_scheduler	[ prev<domid:edomid> = 0x%(1)08x : 0x%(2)08x, next<domid:edomid> = 0x%(3)08x : 0x%(4)08x ]
    1.32 +0x0002f00B  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  s_timer_fn
    1.33 +0x0002f00c  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  t_timer_fn
    1.34 +0x0002f00d  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  dom_timer_fn
    1.35  
    1.36 -0x00080001	CPU%(cpu)d	%(tsc)d		VMX_VMEXIT		[ domid = 0x%(1)08x, eip = 0x%(2)08x, reason = 0x%(3)08x ]
    1.37 -0x00084001	CPU%(cpu)d	%(tsc)d		VMX_INTR		[ domid = 0x%(1)08x, trap = 0x%(2)08x, va = 0x%(3)08x ]
    1.38 +0x00080001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMX_VMEXIT  [ domid = 0x%(1)08x, eip = 0x%(2)08x, reason = 0x%(3)08x ]
    1.39 +0x00084001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMX_INTR    [ domid = 0x%(1)08x, trap = 0x%(2)08x, va = 0x%(3)08x ]
    1.40  
    1.41 -0x00081001	CPU%(cpu)d	%(tsc)d		VMEXIT_0		0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.42 -0x00082001	CPU%(cpu)d	%(tsc)d		VMENTRY_0		0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.43 +0x00081001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMEXIT_0    0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.44 +0x00082001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMENTRY_0   0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.45  
    1.46 -0x00081002	CPU%(cpu)d	%(tsc)d		VMEXIT_1		0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.47 -0x00082002	CPU%(cpu)d	%(tsc)d		VMENTRY_1		0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.48 +0x00081002  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMEXIT_1    0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.49 +0x00082002  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMENTRY_1   0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.50  
    1.51 -0x00081003	CPU%(cpu)d	%(tsc)d		VMEXIT_2		0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.52 -0x00082003	CPU%(cpu)d	%(tsc)d		VMENTRY_2		0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.53 +0x00081003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMEXIT_2    0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.54 +0x00082003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMENTRY_2   0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.55  
    1.56 -0x00081004	CPU%(cpu)d	%(tsc)d		VMEXIT_3		0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.57 -0x00082004	CPU%(cpu)d	%(tsc)d		VMENTRY_3		0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.58 +0x00081004  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMEXIT_3    0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.59 +0x00082004  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMENTRY_3   0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.60  
    1.61 -0x00081005	CPU%(cpu)d	%(tsc)d		VMEXIT_4		0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.62 -0x00082005	CPU%(cpu)d	%(tsc)d		VMENTRY_4		0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.63 +0x00081005  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMEXIT_4    0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.64 +0x00082005  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMENTRY_4   0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.65  
    1.66 -0x00081006	CPU%(cpu)d	%(tsc)d		VMEXIT_5		0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.67 -0x00082006	CPU%(cpu)d	%(tsc)d		VMENTRY_5		0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.68 +0x00081006  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMEXIT_5    0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.69 +0x00082006  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMENTRY_5   0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.70  
    1.71 -0x00081007	CPU%(cpu)d	%(tsc)d		VMEXIT_6		0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.72 -0x00082007	CPU%(cpu)d	%(tsc)d		VMENTRY_6		0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.73 +0x00081007  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMEXIT_6    0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.74 +0x00082007  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMENTRY_6   0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.75  
    1.76 -0x00081008	CPU%(cpu)d	%(tsc)d		VMEXIT_7		0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.77 -0x00082008	CPU%(cpu)d	%(tsc)d		VMENTRY_7		0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
    1.78 +0x00081008  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMEXIT_7    0x%(1)08x 0x%(2)08x 0x%(3)08x
    1.79 +0x00082008  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  VMENTRY_7   0x%(1)08x 0x%(2)08x 0x%(3)08x 0x%(4)08x 0x%(5)08x
     2.1 --- a/tools/xentrace/xentrace_format	Fri Feb 23 16:24:07 2007 +0000
     2.2 +++ b/tools/xentrace/xentrace_format	Fri Feb 23 16:36:55 2007 +0000
     2.3 @@ -119,6 +119,12 @@ while not interrupted:
     2.4  	elif tsc < last_tsc[cpu]:
     2.5  	    print "TSC stepped backward cpu %d !  %d %d" % (cpu,tsc,last_tsc[cpu])
     2.6  
     2.7 +	# provide relative TSC
     2.8 +	if last_tsc[cpu] > 0:
     2.9 +		reltsc = tsc - last_tsc[cpu]
    2.10 +	else:
    2.11 +		reltsc = 0
    2.12 +
    2.13  	last_tsc[cpu] = tsc
    2.14  
    2.15  	if mhz:
    2.16 @@ -127,6 +133,7 @@ while not interrupted:
    2.17          args = {'cpu'   : cpu,
    2.18                  'tsc'   : tsc,
    2.19                  'event' : event,
    2.20 +                'reltsc': reltsc,
    2.21                  '1'     : d1,
    2.22                  '2'     : d2,
    2.23                  '3'     : d3,