direct-io.hg

changeset 12411:622bb65e2011

[IA64] Accelerate RSM, SSM and MOV_TO_PSR

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author awilliam@xenbuild.aw
date Sun Oct 29 11:18:17 2006 -0700 (2006-10-29)
parents 5cd95a6f8412
children fa4281cb7a5b
files xen/arch/ia64/vmx/optvfault.S xen/arch/ia64/vmx/vmx_ivt.S xen/include/asm-ia64/vmx_vpd.h
line diff
     1.1 --- a/xen/arch/ia64/vmx/optvfault.S	Sun Oct 29 11:13:30 2006 -0700
     1.2 +++ b/xen/arch/ia64/vmx/optvfault.S	Sun Oct 29 11:18:17 2006 -0700
     1.3 @@ -19,6 +19,9 @@
     1.4  #define ACCE_MOV_FROM_AR
     1.5  #define ACCE_MOV_FROM_RR
     1.6  #define ACCE_MOV_TO_RR
     1.7 +#define ACCE_RSM
     1.8 +#define ACCE_SSM
     1.9 +#define ACCE_MOV_TO_PSR
    1.10  
    1.11  //mov r1=ar3
    1.12  GLOBAL_ENTRY(vmx_asm_mov_from_ar)
    1.13 @@ -154,6 +157,243 @@ vmx_asm_mov_to_rr_back_2:
    1.14  END(vmx_asm_mov_to_rr)
    1.15  
    1.16  
    1.17 +//rsm 
    1.18 +GLOBAL_ENTRY(vmx_asm_rsm)
    1.19 +#ifndef ACCE_RSM
    1.20 +    br.many vmx_virtualization_fault_back
    1.21 +#endif
    1.22 +    add r16=IA64_VPD_BASE_OFFSET,r21
    1.23 +    extr.u r26=r25,6,21
    1.24 +    extr.u r27=r25,31,2
    1.25 +    ;;
    1.26 +    ld8 r16=[r16]
    1.27 +    extr.u r28=r25,36,1
    1.28 +    dep r26=r27,r26,21,2
    1.29 +    ;;
    1.30 +    add r17=VPD_VPSR_START_OFFSET,r16
    1.31 +    add r22=IA64_VCPU_MODE_FLAGS_OFFSET,r21
    1.32 +    //r26 is imm24
    1.33 +    dep r26=r28,r26,23,1
    1.34 +    ;;
    1.35 +    ld8 r18=[r17]
    1.36 +    movl r28=IA64_PSR_IC+IA64_PSR_I+IA64_PSR_DT+IA64_PSR_SI
    1.37 +    ld8 r23=[r22]
    1.38 +    sub r27=-1,r26
    1.39 +    mov r24=b0
    1.40 +    ;;
    1.41 +    mov r20=cr.ipsr
    1.42 +    or r28=r27,r28
    1.43 +    and r19=r18,r27
    1.44 +    ;;   
    1.45 +    st8 [r17]=r19
    1.46 +    and r20=r20,r28
    1.47 +    ;;
    1.48 +    mov cr.ipsr=r20
    1.49 +    tbit.nz p6,p0=r23,0
    1.50 +    ;;
    1.51 +    tbit.z.or p6,p0=r26,IA64_PSR_DT_BIT
    1.52 +    (p6) br.dptk vmx_resume_to_guest
    1.53 +    ;;
    1.54 +    add r26=IA64_VCPU_META_RR0_OFFSET,r21
    1.55 +    add r27=IA64_VCPU_META_RR0_OFFSET+8,r21
    1.56 +    dep r23=-1,r23,0,1
    1.57 +    ;;
    1.58 +    ld8 r26=[r26]
    1.59 +    ld8 r27=[r27]
    1.60 +    st8 [r22]=r23
    1.61 +    dep.z r28=4,61,3
    1.62 +    ;;
    1.63 +    mov rr[r0]=r26
    1.64 +    mov rr[r28]=r27
    1.65 +    br.many vmx_resume_to_guest
    1.66 +END(vmx_asm_rsm)
    1.67 +
    1.68 +
    1.69 +//ssm 
    1.70 +GLOBAL_ENTRY(vmx_asm_ssm)
    1.71 +#ifndef ACCE_SSM
    1.72 +    br.many vmx_virtualization_fault_back
    1.73 +#endif
    1.74 +    add r16=IA64_VPD_BASE_OFFSET,r21
    1.75 +    extr.u r26=r25,6,21
    1.76 +    extr.u r27=r25,31,2
    1.77 +    ;;
    1.78 +    ld8 r16=[r16]
    1.79 +    extr.u r28=r25,36,1
    1.80 +    dep r26=r27,r26,21,2
    1.81 +    ;;  //r26 is imm24
    1.82 +    add r27=VPD_VPSR_START_OFFSET,r16
    1.83 +    dep r26=r28,r26,23,1
    1.84 +    ;;  //r19 vpsr
    1.85 +    ld8 r29=[r27]
    1.86 +    mov r24=b0
    1.87 +    ;;
    1.88 +    add r22=IA64_VCPU_MODE_FLAGS_OFFSET,r21
    1.89 +    mov r20=cr.ipsr
    1.90 +    or r19=r29,r26
    1.91 +    ;;
    1.92 +    ld8 r23=[r22]
    1.93 +    st8 [r27]=r19
    1.94 +    or r20=r20,r26
    1.95 +    ;;
    1.96 +    mov cr.ipsr=r20
    1.97 +    movl r28=IA64_PSR_DT+IA64_PSR_RT+IA64_PSR_IT
    1.98 +    ;;
    1.99 +    and r19=r28,r19
   1.100 +    tbit.z p6,p0=r23,0
   1.101 +    ;;
   1.102 +    cmp.ne.or p6,p0=r28,r19
   1.103 +    (p6) br.dptk vmx_asm_ssm_1
   1.104 +    ;;
   1.105 +    add r26=IA64_VCPU_META_SAVED_RR0_OFFSET,r21
   1.106 +    add r27=IA64_VCPU_META_SAVED_RR0_OFFSET+8,r21
   1.107 +    dep r23=0,r23,0,1
   1.108 +    ;;
   1.109 +    ld8 r26=[r26]
   1.110 +    ld8 r27=[r27]
   1.111 +    st8 [r22]=r23
   1.112 +    dep.z r28=4,61,3
   1.113 +    ;;
   1.114 +    mov rr[r0]=r26
   1.115 +    mov rr[r28]=r27
   1.116 +    ;;
   1.117 +    srlz.i
   1.118 +    ;;
   1.119 +vmx_asm_ssm_1:
   1.120 +    tbit.nz p6,p0=r29,IA64_PSR_I_BIT
   1.121 +    ;;
   1.122 +    tbit.z.or p6,p0=r19,IA64_PSR_I_BIT
   1.123 +    (p6) br.dptk vmx_resume_to_guest
   1.124 +    ;;
   1.125 +    add r29=VPD_VTPR_START_OFFSET,r16
   1.126 +    add r30=VPD_VHPI_START_OFFSET,r16
   1.127 +    ;;
   1.128 +    ld8 r29=[r29]
   1.129 +    ld8 r30=[r30]
   1.130 +    ;;
   1.131 +    extr.u r17=r29,4,4
   1.132 +    extr.u r18=r29,16,1
   1.133 +    ;;
   1.134 +    dep r17=r18,r17,4,1
   1.135 +    ;;
   1.136 +    cmp.gt p6,p0=r30,r17
   1.137 +    (p6) br.dpnt.few vmx_asm_dispatch_vexirq
   1.138 +    br.many vmx_resume_to_guest
   1.139 +END(vmx_asm_ssm)
   1.140 +
   1.141 +
   1.142 +//mov psr.l=r2 
   1.143 +GLOBAL_ENTRY(vmx_asm_mov_to_psr)
   1.144 +#ifndef ACCE_MOV_TO_PSR
   1.145 +    br.many vmx_virtualization_fault_back
   1.146 +#endif
   1.147 +    add r16=IA64_VPD_BASE_OFFSET,r21
   1.148 +    extr.u r26=r25,13,7 //r2
   1.149 +    ;;
   1.150 +    ld8 r16=[r16]
   1.151 +    movl r20=asm_mov_from_reg
   1.152 +    ;;
   1.153 +    adds r30=vmx_asm_mov_to_psr_back-asm_mov_from_reg,r20
   1.154 +    shladd r26=r26,4,r20
   1.155 +    mov r24=b0
   1.156 +    ;;
   1.157 +    add r27=VPD_VPSR_START_OFFSET,r16
   1.158 +    mov b0=r26
   1.159 +    br.many b0
   1.160 +    ;;   
   1.161 +vmx_asm_mov_to_psr_back:
   1.162 +    ld8 r17=[r27]
   1.163 +    add r22=IA64_VCPU_MODE_FLAGS_OFFSET,r21
   1.164 +    dep r19=0,r19,32,32
   1.165 +    ;;   
   1.166 +    ld8 r23=[r22]
   1.167 +    dep r18=0,r17,0,32
   1.168 +    ;; 
   1.169 +    add r30=r18,r19
   1.170 +    movl r28=IA64_PSR_DT+IA64_PSR_RT+IA64_PSR_IT
   1.171 +    ;;
   1.172 +    st8 [r27]=r30
   1.173 +    and r27=r28,r30
   1.174 +    and r29=r28,r17
   1.175 +    ;;
   1.176 +    cmp.eq p5,p0=r29,r27
   1.177 +    cmp.eq p6,p7=r28,r27
   1.178 +    (p5) br.many vmx_asm_mov_to_psr_1
   1.179 +    ;;
   1.180 +    //virtual to physical
   1.181 +    (p7) add r26=IA64_VCPU_META_RR0_OFFSET,r21
   1.182 +    (p7) add r27=IA64_VCPU_META_RR0_OFFSET+8,r21
   1.183 +    (p7) dep r23=-1,r23,0,1
   1.184 +    ;;
   1.185 +    //physical to virtual
   1.186 +    (p6) add r26=IA64_VCPU_META_SAVED_RR0_OFFSET,r21
   1.187 +    (p6) add r27=IA64_VCPU_META_SAVED_RR0_OFFSET+8,r21
   1.188 +    (p6) dep r23=0,r23,0,1
   1.189 +    ;;
   1.190 +    ld8 r26=[r26]
   1.191 +    ld8 r27=[r27]
   1.192 +    st8 [r22]=r23
   1.193 +    dep.z r28=4,61,3
   1.194 +    ;;
   1.195 +    mov rr[r0]=r26
   1.196 +    mov rr[r28]=r27
   1.197 +    ;;
   1.198 +    srlz.i
   1.199 +    ;;
   1.200 +vmx_asm_mov_to_psr_1:
   1.201 +    mov r20=cr.ipsr
   1.202 +    movl r28=IA64_PSR_IC+IA64_PSR_I+IA64_PSR_DT+IA64_PSR_SI+IA64_PSR_RT
   1.203 +    ;;
   1.204 +    or r19=r19,r28
   1.205 +    dep r20=0,r20,0,32
   1.206 +    ;;
   1.207 +    add r20=r19,r20
   1.208 +    mov b0=r24
   1.209 +    ;;
   1.210 +    mov cr.ipsr=r20
   1.211 +    cmp.ne p6,p0=r0,r0
   1.212 +    ;;
   1.213 +    tbit.nz.or p6,p0=r17,IA64_PSR_I_BIT
   1.214 +    tbit.z.or p6,p0=r30,IA64_PSR_I_BIT
   1.215 +    (p6) br.dpnt.few vmx_resume_to_guest
   1.216 +    ;;
   1.217 +    add r29=VPD_VTPR_START_OFFSET,r16
   1.218 +    add r30=VPD_VHPI_START_OFFSET,r16
   1.219 +    ;;
   1.220 +    ld8 r29=[r29]
   1.221 +    ld8 r30=[r30]
   1.222 +    ;;
   1.223 +    extr.u r17=r29,4,4
   1.224 +    extr.u r18=r29,16,1
   1.225 +    ;;
   1.226 +    dep r17=r18,r17,4,1
   1.227 +    ;;
   1.228 +    cmp.gt p6,p0=r30,r17
   1.229 +    (p6) br.dpnt.few vmx_asm_dispatch_vexirq
   1.230 +    br.many vmx_resume_to_guest
   1.231 +END(vmx_asm_mov_to_psr)
   1.232 +
   1.233 +
   1.234 +ENTRY(vmx_asm_dispatch_vexirq)
   1.235 +//increment iip
   1.236 +    mov r16=cr.ipsr
   1.237 +    ;;
   1.238 +    extr.u r17=r16,IA64_PSR_RI_BIT,2
   1.239 +    tbit.nz p6,p7=r16,IA64_PSR_RI_BIT+1
   1.240 +    ;;	
   1.241 +    (p6) mov r18=cr.iip
   1.242 +    (p6) mov r17=r0
   1.243 +    (p7) add r17=1,r17
   1.244 +    ;;    
   1.245 +    (p6) add r18=0x10,r18
   1.246 +    dep r16=r17,r16,IA64_PSR_RI_BIT,2
   1.247 +    ;;		
   1.248 +    (p6) mov cr.iip=r18
   1.249 +    mov cr.ipsr=r16
   1.250 +    br.many vmx_dispatch_vexirq
   1.251 +END(vmx_asm_dispatch_vexirq)
   1.252 +
   1.253 +
   1.254  #define MOV_TO_REG0	\
   1.255  {;			\
   1.256      nop.b 0x0;		\
     2.1 --- a/xen/arch/ia64/vmx/vmx_ivt.S	Sun Oct 29 11:13:30 2006 -0700
     2.2 +++ b/xen/arch/ia64/vmx/vmx_ivt.S	Sun Oct 29 11:18:17 2006 -0700
     2.3 @@ -791,9 +791,15 @@ ENTRY(vmx_virtualization_fault)
     2.4      cmp.eq p6,p0=EVENT_MOV_FROM_AR,r24
     2.5      cmp.eq p7,p0=EVENT_MOV_FROM_RR,r24
     2.6      cmp.eq p8,p0=EVENT_MOV_TO_RR,r24
     2.7 +    cmp.eq p9,p0=EVENT_RSM,r24
     2.8 +    cmp.eq p10,p0=EVENT_SSM,r24
     2.9 +    cmp.eq p11,p0=EVENT_MOV_TO_PSR,r24
    2.10      (p6) br.dptk.many vmx_asm_mov_from_ar
    2.11      (p7) br.dptk.many vmx_asm_mov_from_rr
    2.12      (p8) br.dptk.many vmx_asm_mov_to_rr
    2.13 +    (p9) br.dptk.many vmx_asm_rsm
    2.14 +    (p10) br.dptk.many vmx_asm_ssm
    2.15 +    (p11) br.dptk.many vmx_asm_mov_to_psr
    2.16      ;;
    2.17  vmx_virtualization_fault_back:
    2.18      mov r19=37
    2.19 @@ -1067,7 +1073,7 @@ ENTRY(vmx_dispatch_virtualization_fault)
    2.20  END(vmx_dispatch_virtualization_fault)
    2.21  
    2.22  
    2.23 -ENTRY(vmx_dispatch_vexirq)
    2.24 +GLOBAL_ENTRY(vmx_dispatch_vexirq)
    2.25      VMX_SAVE_MIN_WITH_COVER_R19
    2.26      alloc r14=ar.pfs,0,0,1,0
    2.27      mov out0=r13
     3.1 --- a/xen/include/asm-ia64/vmx_vpd.h	Sun Oct 29 11:13:30 2006 -0700
     3.2 +++ b/xen/include/asm-ia64/vmx_vpd.h	Sun Oct 29 11:18:17 2006 -0700
     3.3 @@ -140,6 +140,7 @@ extern unsigned int opt_vmx_debug_level;
     3.4  #define VPD_VPR_START_OFFSET		1432
     3.5  #define VPD_VRSE_CFLE_START_OFFSET	1440
     3.6  #define VPD_VCR_START_OFFSET		2048
     3.7 +#define VPD_VTPR_START_OFFSET		2576
     3.8  #define VPD_VRR_START_OFFSET		3072
     3.9  #define VPD_VMM_VAIL_START_OFFSET	31744
    3.10