1.1 --- a/xen/arch/ia64/hyperprivop.S	Mon Jun 20 15:26:55 2005 +0000
     1.2 +++ b/xen/arch/ia64/hyperprivop.S	Mon Jun 20 17:29:54 2005 +0000
     1.3 @@ -93,6 +93,10 @@ 1:	// when we get to here r20=~=interrup
     1.4  	cmp.eq p7,p6=XEN_HYPER_SET_TPR,r17
     1.5  (p7)	br.sptk.many hyper_set_tpr;;
     1.6  
     1.7 +	// HYPERPRIVOP_EOI?
     1.8 +	cmp.eq p7,p6=XEN_HYPER_EOI,r17
     1.9 +(p7)	br.sptk.many hyper_eoi;;
    1.10 +
    1.11  	// if not one of the above, give up for now and do it the slow way
    1.12  	br.sptk.many dispatch_break_fault ;;
    1.13  
    1.14 @@ -594,6 +598,115 @@ ENTRY(hyper_set_tpr)
    1.15  	;;
    1.16  END(hyper_set_tpr)
    1.17  
    1.18 +#if 1
    1.19 +// This seems to work, but I saw a flurry of "timer tick before it's due"
    1.20 +// so will leave the old version around until this gets understood/tracked down
    1.21 +// Also, vcpu_get_ivr provides a domain "heartbeat" for debugging, so we
    1.22 +// need to be able to easily turn that back on.
    1.23 +ENTRY(hyper_get_ivr)
    1.24 +#ifdef FAST_HYPERPRIVOP_CNT
    1.25 +	movl r22=fast_hyperpriv_cnt+(8*XEN_HYPER_GET_IVR);;
    1.26 +	ld8 r21=[r22];;
    1.27 +	adds r21=1,r21;;
    1.28 +	st8 [r22]=r21;;
    1.29 +#endif
    1.30 +	mov r30=r0;;
    1.31 +	mov r8=15;;
    1.32 +	// when we get to here r20=~=interrupts pending
    1.33 +	cmp.eq p7,p0=r20,r0;;
    1.34 +(p7)	adds r20=XSI_PEND_OFS-XSI_PSR_IC_OFS,r18 ;;
    1.35 +(p7)	st4 [r20]=r30;;
    1.36 +(p7)	br.spnt.many 1f ;;
    1.37 +	mov r22=IA64_KR(CURRENT);;
    1.38 +	adds r24=IA64_VCPU_INSVC3_OFFSET,r22;;
    1.39 +	mov r25=192
    1.40 +	adds r22=IA64_VCPU_IRR3_OFFSET,r22;;
    1.41 +	ld8 r23=[r22];;
    1.42 +	cmp.eq p6,p0=r23,r0;;
    1.43 +(p6)	adds r22=-8,r22;;
    1.44 +(p6)	adds r24=-8,r24;;
    1.45 +(p6)	adds r25=-64,r25;;
    1.46 +(p6)	ld8 r23=[r22];;
    1.47 +(p6)	cmp.eq p6,p0=r23,r0;;
    1.48 +(p6)	adds r22=-8,r22;;
    1.49 +(p6)	adds r24=-8,r24;;
    1.50 +(p6)	adds r25=-64,r25;;
    1.51 +(p6)	ld8 r23=[r22];;
    1.52 +(p6)	cmp.eq p6,p0=r23,r0;;
    1.53 +(p6)	adds r22=-8,r22;;
    1.54 +(p6)	adds r24=-8,r24;;
    1.55 +(p6)	adds r25=-64,r25;;
    1.56 +(p6)	ld8 r23=[r22];;
    1.57 +(p6)	cmp.eq p6,p0=r23,r0;;
    1.58 +	cmp.eq p6,p0=r23,r0
    1.59 +(p6)	br.cond.sptk.many 1f;	// this is actually an error
    1.60 +	// r22 points to non-zero element of irr, r23 has value
    1.61 +	// r24 points to corr element of insvc, r25 has elt*64
    1.62 +	ld8 r26=[r24];;
    1.63 +	cmp.geu p6,p0=r26,r23
    1.64 +(p6)	br.cond.spnt.many 1f;
    1.65 +	// not masked by insvc, get vector number
    1.66 +	shr.u r26=r23,1;;
    1.67 +	or r26=r23,r26;;
    1.68 +	shr.u r27=r26,2;;
    1.69 +	or r26=r26,r27;;
    1.70 +	shr.u r27=r26,4;;
    1.71 +	or r26=r26,r27;;
    1.72 +	shr.u r27=r26,8;;
    1.73 +	or r26=r26,r27;;
    1.74 +	shr.u r27=r26,16;;
    1.75 +	or r26=r26,r27;;
    1.76 +	shr.u r27=r26,32;;
    1.77 +	or r26=r26,r27;;
    1.78 +	andcm r26=0xffffffffffffffff,r26;;
    1.79 +	popcnt r26=r26;;
    1.80 +	sub r26=63,r26;;
    1.81 +	// r26 now contains the bit index (mod 64)
    1.82 +	mov r27=1;;
    1.83 +	shl r27=r27,r26;;
    1.84 +	// r27 now contains the (within the proper word) bit mask 
    1.85 +	add r26=r25,r26
    1.86 +	// r26 now contains the vector [0..255]
    1.87 +	adds r20=XSI_TPR_OFS-XSI_PSR_IC_OFS,r18 ;;
    1.88 +	ld8 r20=[r20] ;;
    1.89 +	extr.u r28=r20,16,1
    1.90 +	extr.u r29=r20,4,4 ;;
    1.91 +	cmp.ne p6,p0=r28,r0	// if tpr.mmi is set, return SPURIOUS
    1.92 +(p6)	br.cond.sptk.many 1f;
    1.93 +	shl r29=r29,4;;
    1.94 +	adds r29=15,r29;;
    1.95 +	cmp.ge p6,p0=r29,r26
    1.96 +(p6)	br.cond.sptk.many 1f;
    1.97 +	// OK, have an unmasked vector to process/return
    1.98 +	ld8 r25=[r24];;
    1.99 +	or r25=r25,r27;;
   1.100 +	st8 [r24]=r25;;
   1.101 +	ld8 r25=[r22];;
   1.102 +	andcm r25=r25,r27;;
   1.103 +	st8 [r22]=r25;;
   1.104 +	mov r8=r26;;
   1.105 +1:	mov r24=cr.ipsr
   1.106 +	mov r25=cr.iip;;
   1.107 +	extr.u r26=r24,41,2 ;;
   1.108 +	cmp.eq p6,p7=2,r26 ;;
   1.109 +(p6)	mov r26=0
   1.110 +(p6)	adds r25=16,r25
   1.111 +(p7)	adds r26=1,r26
   1.112 +	;;
   1.113 +	dep r24=r26,r24,41,2
   1.114 +	;;
   1.115 +	mov cr.ipsr=r24
   1.116 +	mov cr.iip=r25
   1.117 +	mov pr=r31,-1 ;;
   1.118 +	rfi
   1.119 +	;;
   1.120 +END(hyper_get_ivr)
   1.121 +#else
   1.122 +// This version goes to slow path unless all irr bits are zero, in which
   1.123 +// case it simply returns SPURIOUS and sets pending to zero.  Since a domain
   1.124 +// gets cr.ivr approx twice per interrupt (once to get the vector and
   1.125 +// once to see if there are any more), this version still gets used
   1.126 +// for approximately half of all gets of cr.ivr
   1.127  ENTRY(hyper_get_ivr)
   1.128  	// when we get to here r20=~=interrupts pending
   1.129  	cmp.ne p7,p0=r20,r0
   1.130 @@ -625,3 +738,67 @@ ENTRY(hyper_get_ivr)
   1.131  	rfi
   1.132  	;;
   1.133  END(hyper_get_ivr)
   1.134 +#endif
   1.135 +
   1.136 +ENTRY(hyper_eoi)
   1.137 +	// when we get to here r20=~=interrupts pending
   1.138 +	cmp.ne p7,p0=r20,r0
   1.139 +(p7)	br.spnt.many dispatch_break_fault ;;
   1.140 +#ifdef FAST_HYPERPRIVOP_CNT
   1.141 +	movl r20=fast_hyperpriv_cnt+(8*XEN_HYPER_EOI);;
   1.142 +	ld8 r21=[r20];;
   1.143 +	adds r21=1,r21;;
   1.144 +	st8 [r20]=r21;;
   1.145 +#endif
   1.146 +	mov r22=IA64_KR(CURRENT);;
   1.147 +	adds r22=IA64_VCPU_INSVC3_OFFSET,r22;;
   1.148 +	ld8 r23=[r22];;
   1.149 +	cmp.eq p6,p0=r23,r0;;
   1.150 +(p6)	adds r22=-8,r22;;
   1.151 +(p6)	ld8 r23=[r22];;
   1.152 +(p6)	cmp.eq p6,p0=r23,r0;;
   1.153 +(p6)	adds r22=-8,r22;;
   1.154 +(p6)	ld8 r23=[r22];;
   1.155 +(p6)	cmp.eq p6,p0=r23,r0;;
   1.156 +(p6)	adds r22=-8,r22;;
   1.157 +(p6)	ld8 r23=[r22];;
   1.158 +(p6)	cmp.eq p6,p0=r23,r0;;
   1.159 +	cmp.eq p6,p0=r23,r0
   1.160 +(p6)	br.cond.sptk.many 1f;	// this is actually an error
   1.161 +	// r22 points to non-zero element of insvc, r23 has value
   1.162 +	shr.u r24=r23,1;;
   1.163 +	or r24=r23,r24;;
   1.164 +	shr.u r25=r24,2;;
   1.165 +	or r24=r24,r25;;
   1.166 +	shr.u r25=r24,4;;
   1.167 +	or r24=r24,r25;;
   1.168 +	shr.u r25=r24,8;;
   1.169 +	or r24=r24,r25;;
   1.170 +	shr.u r25=r24,16;;
   1.171 +	or r24=r24,r25;;
   1.172 +	shr.u r25=r24,32;;
   1.173 +	or r24=r24,r25;;
   1.174 +	andcm r24=0xffffffffffffffff,r24;;
   1.175 +	popcnt r24=r24;;
   1.176 +	sub r24=63,r24;;
   1.177 +	// r24 now contains the bit index
   1.178 +	mov r25=1;;
   1.179 +	shl r25=r25,r24;;
   1.180 +	andcm r23=r23,r25;;
   1.181 +	st8 [r22]=r23;;
   1.182 +1:	mov r24=cr.ipsr
   1.183 +	mov r25=cr.iip;;
   1.184 +	extr.u r26=r24,41,2 ;;
   1.185 +	cmp.eq p6,p7=2,r26 ;;
   1.186 +(p6)	mov r26=0
   1.187 +(p6)	adds r25=16,r25
   1.188 +(p7)	adds r26=1,r26
   1.189 +	;;
   1.190 +	dep r24=r26,r24,41,2
   1.191 +	;;
   1.192 +	mov cr.ipsr=r24
   1.193 +	mov cr.iip=r25
   1.194 +	mov pr=r31,-1 ;;
   1.195 +	rfi
   1.196 +	;;
   1.197 +END(hyper_eoi)