1.1 --- a/linux-2.6-xen-sparse/drivers/acpi/tables.c	Tue Nov 15 17:22:04 2005 +0100
     1.2 +++ b/linux-2.6-xen-sparse/drivers/acpi/tables.c	Tue Nov 15 17:22:42 2005 +0100
     1.3 @@ -565,7 +565,7 @@ acpi_table_get_sdt (
     1.4   * 
     1.5   * result: sdt_entry[] is initialized
     1.6   */
     1.7 -#if CONFIG_XEN
     1.8 +#ifdef CONFIG_XEN_X86
     1.9  #define acpi_rsdp_phys_to_va(rsdp_phys) (__fix_to_virt(FIX_ACPI_RSDP_PAGE) + \
    1.10  					   (rsdp_phys & ~PAGE_MASK))
    1.11  #else

     2.1 --- a/xen/arch/x86/nmi.c	Tue Nov 15 17:22:04 2005 +0100
     2.2 +++ b/xen/arch/x86/nmi.c	Tue Nov 15 17:22:42 2005 +0100
     2.3 @@ -49,8 +49,6 @@ static unsigned int nmi_timer_ticks[NR_C
     2.4  #define P6_EVENT_CPU_CLOCKS_NOT_HALTED	0x79
     2.5  #define P6_NMI_EVENT		P6_EVENT_CPU_CLOCKS_NOT_HALTED
     2.6  
     2.7 -#define MSR_P4_PERFCTR0		0x300
     2.8 -#define MSR_P4_CCCR0		0x360
     2.9  #define P4_ESCR_EVENT_SELECT(N)	((N)<<25)
    2.10  #define P4_CCCR_OVF_PMI0	(1<<26)
    2.11  #define P4_CCCR_OVF_PMI1	(1<<27)
    2.12 @@ -61,13 +59,10 @@ static unsigned int nmi_timer_ticks[NR_C
    2.13  #define P4_CCCR_ESCR_SELECT(N)	((N)<<13)
    2.14  #define P4_CCCR_ENABLE		(1<<12)
    2.15  /* 
    2.16 - * Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
    2.17 + * Set up IQ_PERFCTR0 to behave like a clock, by having IQ_CCCR0 filter
    2.18   * CRU_ESCR0 (with any non-null event selector) through a complemented
    2.19   * max threshold. [IA32-Vol3, Section 14.9.9] 
    2.20   */
    2.21 -#define MSR_P4_IQ_COUNTER0	0x30C
    2.22 -#define MSR_P4_IQ_CCCR0		0x36C
    2.23 -#define MSR_P4_CRU_ESCR0	0x3B8 /* ESCR no. 4 */
    2.24  #define P4_NMI_CRU_ESCR0	P4_ESCR_EVENT_SELECT(0x3F)
    2.25  #define P4_NMI_IQ_CCCR0	\
    2.26      (P4_CCCR_OVF_PMI0|P4_CCCR_THRESHOLD(15)|P4_CCCR_COMPLEMENT| \
    2.27 @@ -183,7 +178,7 @@ static int __pminit setup_p4_watchdog(vo
    2.28      if (!(misc_enable & MSR_IA32_MISC_ENABLE_PERF_AVAIL))
    2.29          return 0;
    2.30  
    2.31 -    nmi_perfctr_msr = MSR_P4_IQ_COUNTER0;
    2.32 +    nmi_perfctr_msr = MSR_P4_IQ_PERFCTR0;
    2.33      nmi_p4_cccr_val = P4_NMI_IQ_CCCR0;
    2.34      if ( smp_num_siblings == 2 )
    2.35          nmi_p4_cccr_val |= P4_CCCR_OVF_PMI1;
    2.36 @@ -196,13 +191,13 @@ static int __pminit setup_p4_watchdog(vo
    2.37      clear_msr_range(0x3C0, 6);
    2.38      clear_msr_range(0x3C8, 6);
    2.39      clear_msr_range(0x3E0, 2);
    2.40 -    clear_msr_range(MSR_P4_CCCR0, 18);
    2.41 -    clear_msr_range(MSR_P4_PERFCTR0, 18);
    2.42 +    clear_msr_range(MSR_P4_BPU_CCCR0, 18);
    2.43 +    clear_msr_range(MSR_P4_BPU_PERFCTR0, 18);
    2.44          
    2.45      wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
    2.46      wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
    2.47 -    Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000));
    2.48 -    wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1);
    2.49 +    Dprintk("setting P4_IQ_PERFCTR0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000));
    2.50 +    wrmsr(MSR_P4_IQ_PERFCTR0, -(cpu_khz/nmi_hz*1000), -1);
    2.51      apic_write(APIC_LVTPC, APIC_DM_NMI);
    2.52      wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
    2.53  
    2.54 @@ -314,7 +309,7 @@ void nmi_watchdog_tick(struct cpu_user_r
    2.55  
    2.56      if ( nmi_perfctr_msr )
    2.57      {
    2.58 -        if ( nmi_perfctr_msr == MSR_P4_IQ_COUNTER0 )
    2.59 +        if ( nmi_perfctr_msr == MSR_P4_IQ_PERFCTR0 )
    2.60          {
    2.61              /*
    2.62               * P4 quirks:

     3.1 --- a/xen/include/asm-x86/msr.h	Tue Nov 15 17:22:04 2005 +0100
     3.2 +++ b/xen/include/asm-x86/msr.h	Tue Nov 15 17:22:42 2005 +0100
     3.3 @@ -133,36 +133,29 @@
     3.4  #define MSR_IA32_SYSENTER_ESP		0x175
     3.5  #define MSR_IA32_SYSENTER_EIP		0x176
     3.6  
     3.7 -#define MSR_IA32_MCG_CAP       0x179
     3.8 -#define MSR_IA32_MCG_STATUS        0x17a
     3.9 -#define MSR_IA32_MCG_CTL       0x17b
    3.10 -
    3.11 -#define MSR_MTRRfix64K_00000	0x250
    3.12 -#define MSR_MTRRfix16K_80000	0x258
    3.13 -#define MSR_MTRRfix16K_A0000	0x259
    3.14 -#define MSR_MTRRfix4K_C0000	0x268
    3.15 -#define MSR_MTRRfix4K_C8000	0x269
    3.16 -#define MSR_MTRRfix4K_D0000	0x26a
    3.17 -#define MSR_MTRRfix4K_D8000	0x26b
    3.18 -#define MSR_MTRRfix4K_E0000	0x26c
    3.19 -#define MSR_MTRRfix4K_E8000	0x26d
    3.20 -#define MSR_MTRRfix4K_F0000	0x26e
    3.21 -#define MSR_MTRRfix4K_F8000	0x26f
    3.22 -#define MSR_MTRRdefType		0x2ff
    3.23 -
    3.24 -#define MSR_IA32_MC0_CTL       0x400
    3.25 -#define MSR_IA32_MC0_STATUS        0x401
    3.26 -#define MSR_IA32_MC0_ADDR      0x402
    3.27 -#define MSR_IA32_MC0_MISC      0x403
    3.28 -
    3.29 -#define MSR_IA32_DS_AREA	0x600
    3.30 -
    3.31 -#define MSR_IA32_BBL_CR_CTL		0x119
    3.32 -
    3.33  #define MSR_IA32_MCG_CAP		0x179
    3.34  #define MSR_IA32_MCG_STATUS		0x17a
    3.35  #define MSR_IA32_MCG_CTL		0x17b
    3.36  
    3.37 +/* P4/Xeon+ specific */
    3.38 +#define MSR_IA32_MCG_EAX		0x180
    3.39 +#define MSR_IA32_MCG_EBX		0x181
    3.40 +#define MSR_IA32_MCG_ECX		0x182
    3.41 +#define MSR_IA32_MCG_EDX		0x183
    3.42 +#define MSR_IA32_MCG_ESI		0x184
    3.43 +#define MSR_IA32_MCG_EDI		0x185
    3.44 +#define MSR_IA32_MCG_EBP		0x186
    3.45 +#define MSR_IA32_MCG_ESP		0x187
    3.46 +#define MSR_IA32_MCG_EFLAGS		0x188
    3.47 +#define MSR_IA32_MCG_EIP		0x189
    3.48 +#define MSR_IA32_MCG_RESERVED		0x18A
    3.49 +
    3.50 +#define MSR_P6_EVNTSEL0			0x186
    3.51 +#define MSR_P6_EVNTSEL1			0x187
    3.52 +
    3.53 +#define MSR_IA32_PERF_STATUS		0x198
    3.54 +#define MSR_IA32_PERF_CTL		0x199
    3.55 +
    3.56  #define MSR_IA32_THERM_CONTROL		0x19a
    3.57  #define MSR_IA32_THERM_INTERRUPT	0x19b
    3.58  #define MSR_IA32_THERM_STATUS		0x19c
    3.59 @@ -173,47 +166,101 @@
    3.60  #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
    3.61  
    3.62  #define MSR_IA32_DEBUGCTLMSR		0x1d9
    3.63 -#define MSR_IA32_DEBUGCTLMSR_LBR        (1<<0)
    3.64 -#define MSR_IA32_DEBUGCTLMSR_BTF        (1<<1)
    3.65 -#define MSR_IA32_DEBUGCTLMSR_TR		(1<<2)
    3.66 -#define MSR_IA32_DEBUGCTLMSR_BTS        (1<<3)
    3.67 -#define MSR_IA32_DEBUGCTLMSR_BTINT      (1<<4)
    3.68 -
    3.69 -#define MSR_IA32_LASTBRANCH_TOS         0x1da
    3.70 -#define MSR_IA32_LASTBRANCH_0		0x1db
    3.71 -#define MSR_IA32_LASTBRANCH_1		0x1dc
    3.72 -#define MSR_IA32_LASTBRANCH_2		0x1dd
    3.73 -#define MSR_IA32_LASTBRANCH_3		0x1de
    3.74 +#define MSR_IA32_LASTBRANCHFROMIP	0x1db
    3.75 +#define MSR_IA32_LASTBRANCHTOIP		0x1dc
    3.76 +#define MSR_IA32_LASTINTFROMIP		0x1dd
    3.77 +#define MSR_IA32_LASTINTTOIP		0x1de
    3.78  
    3.79  #define MSR_IA32_MC0_CTL		0x400
    3.80  #define MSR_IA32_MC0_STATUS		0x401
    3.81  #define MSR_IA32_MC0_ADDR		0x402
    3.82  #define MSR_IA32_MC0_MISC		0x403
    3.83  
    3.84 -#define MSR_P6_PERFCTR0			0xc1
    3.85 -#define MSR_P6_PERFCTR1			0xc2
    3.86 -#define MSR_P6_EVNTSEL0			0x186
    3.87 -#define MSR_P6_EVNTSEL1			0x187
    3.88 -
    3.89 +/* Pentium IV performance counter MSRs */
    3.90 +#define MSR_P4_BPU_PERFCTR0 		0x300
    3.91 +#define MSR_P4_BPU_PERFCTR1 		0x301
    3.92 +#define MSR_P4_BPU_PERFCTR2 		0x302
    3.93 +#define MSR_P4_BPU_PERFCTR3 		0x303
    3.94 +#define MSR_P4_MS_PERFCTR0 		0x304
    3.95 +#define MSR_P4_MS_PERFCTR1 		0x305
    3.96 +#define MSR_P4_MS_PERFCTR2 		0x306
    3.97 +#define MSR_P4_MS_PERFCTR3 		0x307
    3.98 +#define MSR_P4_FLAME_PERFCTR0 		0x308
    3.99 +#define MSR_P4_FLAME_PERFCTR1 		0x309
   3.100 +#define MSR_P4_FLAME_PERFCTR2 		0x30a
   3.101 +#define MSR_P4_FLAME_PERFCTR3 		0x30b
   3.102 +#define MSR_P4_IQ_PERFCTR0 		0x30c
   3.103 +#define MSR_P4_IQ_PERFCTR1 		0x30d
   3.104 +#define MSR_P4_IQ_PERFCTR2 		0x30e
   3.105 +#define MSR_P4_IQ_PERFCTR3 		0x30f
   3.106 +#define MSR_P4_IQ_PERFCTR4 		0x310
   3.107 +#define MSR_P4_IQ_PERFCTR5 		0x311
   3.108 +#define MSR_P4_BPU_CCCR0 		0x360
   3.109 +#define MSR_P4_BPU_CCCR1 		0x361
   3.110 +#define MSR_P4_BPU_CCCR2 		0x362
   3.111 +#define MSR_P4_BPU_CCCR3 		0x363
   3.112 +#define MSR_P4_MS_CCCR0 		0x364
   3.113 +#define MSR_P4_MS_CCCR1 		0x365
   3.114 +#define MSR_P4_MS_CCCR2 		0x366
   3.115 +#define MSR_P4_MS_CCCR3 		0x367
   3.116 +#define MSR_P4_FLAME_CCCR0 		0x368
   3.117 +#define MSR_P4_FLAME_CCCR1 		0x369
   3.118 +#define MSR_P4_FLAME_CCCR2 		0x36a
   3.119 +#define MSR_P4_FLAME_CCCR3 		0x36b
   3.120 +#define MSR_P4_IQ_CCCR0 		0x36c
   3.121 +#define MSR_P4_IQ_CCCR1 		0x36d
   3.122 +#define MSR_P4_IQ_CCCR2 		0x36e
   3.123 +#define MSR_P4_IQ_CCCR3 		0x36f
   3.124 +#define MSR_P4_IQ_CCCR4 		0x370
   3.125 +#define MSR_P4_IQ_CCCR5 		0x371
   3.126 +#define MSR_P4_ALF_ESCR0 		0x3ca
   3.127 +#define MSR_P4_ALF_ESCR1 		0x3cb
   3.128 +#define MSR_P4_BPU_ESCR0 		0x3b2
   3.129 +#define MSR_P4_BPU_ESCR1 		0x3b3
   3.130 +#define MSR_P4_BSU_ESCR0 		0x3a0
   3.131 +#define MSR_P4_BSU_ESCR1 		0x3a1
   3.132 +#define MSR_P4_CRU_ESCR0 		0x3b8
   3.133 +#define MSR_P4_CRU_ESCR1 		0x3b9
   3.134 +#define MSR_P4_CRU_ESCR2 		0x3cc
   3.135 +#define MSR_P4_CRU_ESCR3 		0x3cd
   3.136 +#define MSR_P4_CRU_ESCR4 		0x3e0
   3.137 +#define MSR_P4_CRU_ESCR5 		0x3e1
   3.138 +#define MSR_P4_DAC_ESCR0 		0x3a8
   3.139 +#define MSR_P4_DAC_ESCR1 		0x3a9
   3.140 +#define MSR_P4_FIRM_ESCR0 		0x3a4
   3.141 +#define MSR_P4_FIRM_ESCR1 		0x3a5
   3.142 +#define MSR_P4_FLAME_ESCR0 		0x3a6
   3.143 +#define MSR_P4_FLAME_ESCR1 		0x3a7
   3.144 +#define MSR_P4_FSB_ESCR0 		0x3a2
   3.145 +#define MSR_P4_FSB_ESCR1 		0x3a3
   3.146 +#define MSR_P4_IQ_ESCR0 		0x3ba
   3.147 +#define MSR_P4_IQ_ESCR1 		0x3bb
   3.148 +#define MSR_P4_IS_ESCR0 		0x3b4
   3.149 +#define MSR_P4_IS_ESCR1 		0x3b5
   3.150 +#define MSR_P4_ITLB_ESCR0 		0x3b6
   3.151 +#define MSR_P4_ITLB_ESCR1 		0x3b7
   3.152 +#define MSR_P4_IX_ESCR0 		0x3c8
   3.153 +#define MSR_P4_IX_ESCR1 		0x3c9
   3.154 +#define MSR_P4_MOB_ESCR0 		0x3aa
   3.155 +#define MSR_P4_MOB_ESCR1 		0x3ab
   3.156 +#define MSR_P4_MS_ESCR0 		0x3c0
   3.157 +#define MSR_P4_MS_ESCR1 		0x3c1
   3.158 +#define MSR_P4_PMH_ESCR0 		0x3ac
   3.159 +#define MSR_P4_PMH_ESCR1 		0x3ad
   3.160 +#define MSR_P4_RAT_ESCR0 		0x3bc
   3.161 +#define MSR_P4_RAT_ESCR1 		0x3bd
   3.162 +#define MSR_P4_SAAT_ESCR0 		0x3ae
   3.163 +#define MSR_P4_SAAT_ESCR1 		0x3af
   3.164 +#define MSR_P4_SSU_ESCR0 		0x3be
   3.165 +#define MSR_P4_SSU_ESCR1 		0x3bf    /* guess: not defined in manual */
   3.166 +#define MSR_P4_TBPU_ESCR0 		0x3c2
   3.167 +#define MSR_P4_TBPU_ESCR1 		0x3c3
   3.168 +#define MSR_P4_TC_ESCR0 		0x3c4
   3.169 +#define MSR_P4_TC_ESCR1 		0x3c5
   3.170 +#define MSR_P4_U2L_ESCR0 		0x3b0
   3.171 +#define MSR_P4_U2L_ESCR1 		0x3b1
   3.172  
   3.173 -/* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */
   3.174 -#define MSR_K7_EVNTSEL0            0xC0010000
   3.175 -#define MSR_K7_PERFCTR0            0xC0010004
   3.176 -#define MSR_K7_EVNTSEL1            0xC0010001
   3.177 -#define MSR_K7_PERFCTR1            0xC0010005
   3.178 -#define MSR_K7_EVNTSEL2            0xC0010002
   3.179 -#define MSR_K7_PERFCTR2            0xC0010006
   3.180 -#define MSR_K7_EVNTSEL3            0xC0010003
   3.181 -#define MSR_K7_PERFCTR3            0xC0010007
   3.182 -#define MSR_K8_TOP_MEM1		   0xC001001A
   3.183 -#define MSR_K8_TOP_MEM2		   0xC001001D
   3.184 -#define MSR_K8_SYSCFG		   0xC0000010	
   3.185 -#define MSR_K7_HWCR			0xC0010015
   3.186 -#define MSR_K7_CLK_CTL			0xC001001b
   3.187 -#define MSR_K7_FID_VID_CTL		0xC0010041
   3.188 -#define MSR_K7_VID_STATUS		0xC0010042
   3.189 -
   3.190 -/* K6 MSRs */
   3.191 +/* AMD Defined MSRs */
   3.192  #define MSR_K6_EFER			0xC0000080
   3.193  #define MSR_K6_STAR			0xC0000081
   3.194  #define MSR_K6_WHCR			0xC0000082
   3.195 @@ -222,6 +269,19 @@
   3.196  #define MSR_K6_PSOR			0xC0000087
   3.197  #define MSR_K6_PFIR			0xC0000088
   3.198  
   3.199 +#define MSR_K7_EVNTSEL0			0xC0010000
   3.200 +#define MSR_K7_EVNTSEL1			0xC0010001
   3.201 +#define MSR_K7_EVNTSEL2			0xC0010002
   3.202 +#define MSR_K7_EVNTSEL3			0xC0010003
   3.203 +#define MSR_K7_PERFCTR0			0xC0010004
   3.204 +#define MSR_K7_PERFCTR1			0xC0010005
   3.205 +#define MSR_K7_PERFCTR2			0xC0010006
   3.206 +#define MSR_K7_PERFCTR3			0xC0010007
   3.207 +#define MSR_K7_HWCR			0xC0010015
   3.208 +#define MSR_K7_CLK_CTL			0xC001001b
   3.209 +#define MSR_K7_FID_VID_CTL		0xC0010041
   3.210 +#define MSR_K7_FID_VID_STATUS		0xC0010042
   3.211 +
   3.212  /* Centaur-Hauls/IDT defined MSRs. */
   3.213  #define MSR_IDT_FCR1			0x107
   3.214  #define MSR_IDT_FCR2			0x108