1.1 --- a/.rootkeys	Tue May 03 14:42:00 2005 +0000
     1.2 +++ b/.rootkeys	Tue May 10 08:49:59 2005 +0000
     1.3 @@ -21,6 +21,7 @@ 4022a73cgxX1ryj1HgS-IwwB6NUi2A docs/misc
     1.4  412f4bd9sm5mCQ8BkrgKcAKZGadq7Q docs/misc/blkif-drivers-explained.txt
     1.5  420b949cy9ZGzED74Fz_DaWlK7tT4g docs/misc/crashdb.txt
     1.6  4251a1f82AexscYEiF4Iku8Gc_kWfQ docs/misc/grant-tables.txt
     1.7 +424d462b5GuApQ_NyMsRFt9LbrsWow docs/misc/sedf_scheduler_mini-HOWTO.txt
     1.8  40d6ccbfKKBq8jE0ula4eHEzBiQuDA docs/misc/xen_config.html
     1.9  410a4c2bAO_m_l4RsiiPHnZ4ixHWbQ docs/misc/xend.tex
    1.10  3f9e7d564bWFB-Czjv1qdmE6o0GqNg docs/src/interface.tex
    1.11 @@ -353,7 +354,6 @@ 41979925z1MsKU1SfuuheM1IFDQ_bA linux-2.6
    1.12  4118b6a418gnL6AZsTdglC92YGqYTg linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/highmem.h
    1.13  42539fb5A9hsS3NFQ-2VY4y1TONZZQ linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/hypercall.h
    1.14  40f5623aJVXQwpJMOLE99XgvGsfQ8Q linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/io.h
    1.15 -42778a69MXZVxch4pQqYsMPS0WnNSg linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/io_apic.h
    1.16  40f5623aKXkBBxgpLx2NcvkncQ1Yyw linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/mach-xen/irq_vectors.h
    1.17  40f5623aDMCsWOFO0jktZ4e8sjwvEg linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/mach-xen/setup_arch_post.h
    1.18  40f5623arsFXkGdPvIqvFi3yFXGR0Q linux-2.6.11-xen-sparse/include/asm-xen/asm-i386/mach-xen/setup_arch_pre.h
    1.19 @@ -745,6 +745,7 @@ 3fbba6dctWRWlFJkYb6hdix2X4WMuw tools/lib
    1.20  3fbba6dcbVrG2hPzEzwdeV_UC8kydQ tools/libxc/xc_private.h
    1.21  42337174PxyzzPk62raDiYCIsfStDg tools/libxc/xc_ptrace.c
    1.22  4273458duzL--nsTfT6e_q6Kfij48g tools/libxc/xc_ptrace_core.c
    1.23 +41ebbfe9U0b0kI-HgjK7VEY4EvW7_w tools/libxc/xc_sedf.c
    1.24  41dde8b0pLfAKMs_L9Uri2hnzHiCRQ tools/libxc/xc_vmx_build.c
    1.25  40e1b09dMYB4ItGCqcMIzirdMd9I-w tools/libxutil/Makefile
    1.26  40e033325Sjqs-_4TuzeUEprP_gYFg tools/libxutil/allocate.c
    1.27 @@ -1188,7 +1189,7 @@ 421098b6lY2JzrV1oFDbrt7XQhtElg xen/arch/
    1.28  427664f5eygrc3nEhI3RKf0Y37PzyA xen/arch/ia64/xentime.c
    1.29  3ddb79bcZbRBzT3elFWSX7u6NtMagQ xen/arch/x86/Makefile
    1.30  3ddb79bcBQF85CfLS4i1WGZ4oLLaCA xen/arch/x86/Rules.mk
    1.31 -3e5636e5FAYZ5_vQnmgwFJfSdmO5Mw xen/arch/x86/acpi.c
    1.32 +3e5636e5FAYZ5_vQnmgwFJfSdmO5Mw xen/arch/x86/acpi/boot.c
    1.33  3ddb79bcsjinG9k1KcvbVBuas1R2dA xen/arch/x86/apic.c
    1.34  42360b3244-Q6BpEKhR_A1YtG1wPNQ xen/arch/x86/audit.c
    1.35  3ddb79c4yGZ7_22QAFFwPzqP4NSHwA xen/arch/x86/boot/mkelf32.c
    1.36 @@ -1218,10 +1219,7 @@ 41aaf567tqrKGSTDK8OVeAbpeoccPw xen/arch/
    1.37  41aaf567a36esU-rUK7twPiv-yTFyw xen/arch/x86/mtrr/mtrr.h
    1.38  41aaf567DcTL6pqVtLZJI5cSryyA1A xen/arch/x86/mtrr/state.c
    1.39  3f12cff65EV3qOG2j37Qm0ShgvXGRw xen/arch/x86/nmi.c
    1.40 -3ddb79bdHe6_Uij4-glW91vInNtBYQ xen/arch/x86/pci-irq.c
    1.41 -3ddb79bcZ_2FxINljqNSkqa17ISyJw xen/arch/x86/pci-pc.c
    1.42 -3ddb79bdeJ7_86z03yTAPIeeywOg3Q xen/arch/x86/pci-x86.c
    1.43 -3ddb79bdIKgipvGoqExEQ7jawfVowA xen/arch/x86/pci-x86.h
    1.44 +4051bcecFeq4DE70p4zGO5setf47CA xen/arch/x86/physdev.c
    1.45  3ddb79bc7KxGCEJsgBnkDX7XjD_ZEQ xen/arch/x86/rwlock.c
    1.46  3ddb79bcrD6Z_rUvSDgrvjyb4846Eg xen/arch/x86/setup.c
    1.47  405b8599xI_PoEr3zZoJ2on-jdn7iw xen/arch/x86/shadow.c
    1.48 @@ -1253,6 +1251,7 @@ 40e96d3akN3Hu_J5Bk-WXD8OGscrYQ xen/arch/
    1.49  422f27c8J9DQfCpegccMid59XhSmGA xen/arch/x86/x86_emulate.c
    1.50  3ddb79bdff-gj-jFGKjOejeHLqL8Lg xen/common/Makefile
    1.51  3e397e66AyyD5fYraAySWuwi9uqSXg xen/common/ac_timer.c
    1.52 +427fa2d0J0LU2s5oKbsM0nTZ2iyd2Q xen/common/bitmap.c
    1.53  3ddb79bdLX_P6iB7ILiblRLWvebapg xen/common/dom0_ops.c
    1.54  3e6377e4i0c9GtKN65e99OtRbw3AZw xen/common/dom_mem_ops.c
    1.55  3ddb79bdYO5D8Av12NHqPeSviav7cg xen/common/domain.c
    1.56 @@ -1265,9 +1264,9 @@ 3ddb79bduhSEZI8xa7IbGQCpap5y2A xen/commo
    1.57  41a61536SZbR6cj1ukWTb0DYU-vz9w xen/common/multicall.c
    1.58  3ddb79bdD4SLmmdMD7yLW5HcUWucXw xen/common/page_alloc.c
    1.59  3e54c38dkHAev597bPr71-hGzTdocg xen/common/perfc.c
    1.60 -4051bcecFeq4DE70p4zGO5setf47CA xen/common/physdev.c
    1.61  3ddb79bdHqdQpATqC0rmUZNbsb6L6A xen/common/resource.c
    1.62  40589968dD2D1aejwSOvrROg7fOvGQ xen/common/sched_bvt.c
    1.63 +41ebbfe9oF1BF3cH5v7yE3eOL9uPbA xen/common/sched_sedf.c
    1.64  3e397e6619PgAfBbw2XFbXkewvUWgw xen/common/schedule.c
    1.65  3ddb79bd0gVQYmL2zvuJnldvD0AGxQ xen/common/softirq.c
    1.66  3e7f358awXBC3Vw-wFRwPw18qL1khg xen/common/string.c
    1.67 @@ -1276,50 +1275,29 @@ 3ddb79bd3zgV33PHdt-cgh3sxcb1hw xen/commo
    1.68  4203fb92Qcy7mGpauBdq09J-WAqfoA xen/common/xmalloc.c
    1.69  3ddb79c0ppNeJtjC4va8j41ADCnchA xen/drivers/Makefile
    1.70  40715b2bi9gU43-cYzlmPDgreYQchw xen/drivers/acpi/Makefile
    1.71 -40715b2bDxNCz5LFV8FAXihmYJZFUQ xen/drivers/acpi/acpi_ksyms.c
    1.72  40715b2cNVOegtvyft_AHFKJYRprfA xen/drivers/acpi/tables.c
    1.73  3e4a8cb7alzQCDKS7MlioPoHBKYkdQ xen/drivers/char/Makefile
    1.74  4049e6bfNSIq7s7OV-Bd69QD0RpR2Q xen/drivers/char/console.c
    1.75  3e4a8cb7nMChlro4wvOBo76n__iCFA xen/drivers/char/serial.c
    1.76 -3ddb79beUWngyIhMHgyPtuTem4o4JA xen/drivers/pci/Makefile
    1.77 -3ddb79beU9td0Mnm0VUMklerBa37qQ xen/drivers/pci/compat.c
    1.78 -3ddb79beHkGQE58z5t5gyUCYiwOxvw xen/drivers/pci/gen-devlist.c
    1.79 -3ddb79bfoQcFKLf5P6wZlDl36alWdQ xen/drivers/pci/names.c
    1.80 -3ddb79bfyX7-pD6XdxY_mdNrJR20iw xen/drivers/pci/pci.c
    1.81 -3ddb79bf2AS7YBGwooE_Kbv7XgUqNQ xen/drivers/pci/pci.ids
    1.82 -3ddb79bf7sTn85WtP_8Nc2YEmmVExQ xen/drivers/pci/quirks.c
    1.83 -3ddb79bfJaf0bkE1Y67bnll8-kjEPg xen/drivers/pci/setup-res.c
    1.84  40715b2cFpte_UNWnBZW0Du7z9AhTQ xen/include/acpi/acconfig.h
    1.85 -40715b2cEQWX-PaxEH30qI48K1krnQ xen/include/acpi/acdebug.h
    1.86 -40715b2c_7j-oy3ZNAuqE3IFNPzArg xen/include/acpi/acdisasm.h
    1.87 -40715b2cFdcPx-2FHGM1Q-M-592xYQ xen/include/acpi/acdispat.h
    1.88 -40715b2cKqD_Lihnlmvnyl4AAl3EFw xen/include/acpi/acevents.h
    1.89  40715b2ctNvVZ058w8eM8DR9hOat_A xen/include/acpi/acexcep.h
    1.90  40715b2com8I01qcHcAw47e93XsCqQ xen/include/acpi/acglobal.h
    1.91  40715b2cS1t4uI3sMsu-c0M4qqAIrw xen/include/acpi/achware.h
    1.92 -40715b2chSz545A4Tq-y3WAtanzPMQ xen/include/acpi/acinterp.h
    1.93  40715b2cGf23lRI58NphiaDQl698-w xen/include/acpi/aclocal.h
    1.94  40715b2cdG7tCF2NMk0j1RCQQPzPXg xen/include/acpi/acmacros.h
    1.95 -40715b2ckP2XZZDkSTehu6riuMogDA xen/include/acpi/acnamesp.h
    1.96  40715b2c4AvHYn2-2YIyt3mx-Mm5tw xen/include/acpi/acobject.h
    1.97  40715b2cPUXsHzmchvXx7QHAfW0nMw xen/include/acpi/acoutput.h
    1.98 -40715b2cNbYpt9CHmCHg3RG7fBdACA xen/include/acpi/acparser.h
    1.99  40715b2cWM_6zR14U9Tp0s_q8D002A xen/include/acpi/acpi.h
   1.100  40715b2dcJDTiROgyMk9swD_veWktA xen/include/acpi/acpi_bus.h
   1.101  40715b2dRFlZK6apnH7WkUCBdyFXWA xen/include/acpi/acpi_drivers.h
   1.102  40715b2dtgZhNGAzlyBMe3kqve3mqw xen/include/acpi/acpiosxf.h
   1.103  40715b2dpW5TY7n5rzCufsDhJVWuMQ xen/include/acpi/acpixf.h
   1.104 -40715b2dp9-_D9LTjcvtf-Yopih5mQ xen/include/acpi/acresrc.h
   1.105  40715b2djvd97KbIpt4wyJgxwqCqmg xen/include/acpi/acstruct.h
   1.106 -40715b2dRIU9cQgmTjtCRNleIJDAYg xen/include/acpi/actables.h
   1.107  40715b2dy8ECRkSo9x0tRRueAjPx1g xen/include/acpi/actbl.h
   1.108  40715b2ds4J-XWn9Ix-lgBiJffNgxw xen/include/acpi/actbl1.h
   1.109  40715b2d_aMKMjKKNImJR4km52KRHA xen/include/acpi/actbl2.h
   1.110 -40715b2dxC03aemijgL-iDH_-BkKRw xen/include/acpi/actbl71.h
   1.111  40715b2d0oQUijKwEw6SDJ4LhD8c4g xen/include/acpi/actypes.h
   1.112  40715b2dBByvcAtRpN5mafyEYLcBWA xen/include/acpi/acutils.h
   1.113 -40715b2d_iPcZ0uUVGblPvjsHOwE5Q xen/include/acpi/amlcode.h
   1.114 -40715b2d3CdS6dIpZDTiCJRlDG3LCA xen/include/acpi/amlresrc.h
   1.115  40715b2dKRW7A71SNaeV6zfrEzYxPw xen/include/acpi/platform/acenv.h
   1.116  40715b2d8fYydJMcODFrV1ocLklGDg xen/include/acpi/platform/acgcc.h
   1.117  40715b2d1yZkqyAt0kgx2xEwsatuuA xen/include/acpi/platform/aclinux.h
   1.118 @@ -1369,18 +1347,39 @@ 3ddb79c3TMDjkxVndKFKnGiwY0HzDg xen/inclu
   1.119  4204e7acwXDo-5iAAiO2eQbtDeYZXA xen/include/asm-x86/init.h
   1.120  3ddb79c3fQ_O3o5NHK2N8AJdk0Ea4Q xen/include/asm-x86/io.h
   1.121  3ddb79c2TKeScYHQZreTdHqYNLbehQ xen/include/asm-x86/io_apic.h
   1.122 -42605109qxLSrHVE2SRhGXmgk907iw xen/include/asm-x86/io_ports.h
   1.123  3ddb79c2L7rTlFzazOLW1XuSZefpFw xen/include/asm-x86/irq.h
   1.124  404f1b93OjLO4bFfBXYNaJdIqlNz-Q xen/include/asm-x86/ldt.h
   1.125 -4260510aYPj2kr6rMbBfMxcvvmXndQ xen/include/asm-x86/mach_apic.h
   1.126 +427fa2d0m8MOSSXT13zgb-q0fGA_Dw xen/include/asm-x86/mach-default/apm.h
   1.127 +427fa2d0suK9Av7vsAXhsQxZjqpc_Q xen/include/asm-x86/mach-default/bios_ebda.h
   1.128 +427fa2d0yC3KzLozoeK3Xa3uGVfIdw xen/include/asm-x86/mach-default/do_timer.h
   1.129 +427fa2d0bWQkR1mW5OBYxn07AN-bDw xen/include/asm-x86/mach-default/entry_arch.h
   1.130 +427fa2d0-SWcuwbdSypo4953bc2JdQ xen/include/asm-x86/mach-default/io_ports.h
   1.131 +427fa2d0eyAl7LAeO-SVV4IW7lZPGQ xen/include/asm-x86/mach-default/irq_vectors.h
   1.132 +427fa2d0df7VWG4KKpnKbKR2Cbd1_w xen/include/asm-x86/mach-default/irq_vectors_limits.h
   1.133 +4260510aYPj2kr6rMbBfMxcvvmXndQ xen/include/asm-x86/mach-default/mach_apic.h
   1.134 +427fa2d0I3FWjE2tWdOhlEOJn7stcg xen/include/asm-x86/mach-default/mach_apicdef.h
   1.135 +427fa2d093fDS2gOBLcl7Yndzl7HmA xen/include/asm-x86/mach-default/mach_ipi.h
   1.136 +427fa2d0Y7bD35d-FvDAeiJDIdRw2A xen/include/asm-x86/mach-default/mach_mpparse.h
   1.137 +427fa2d0aLQgE9e1GY9ZP5jrMOC8pQ xen/include/asm-x86/mach-default/mach_mpspec.h
   1.138 +427fa2d0fJ5nNn5ydJuOaZIL6F2fjQ xen/include/asm-x86/mach-default/mach_reboot.h
   1.139 +427fa2d0VlN555TE68TjKMsrOoFXNA xen/include/asm-x86/mach-default/mach_time.h
   1.140 +427fa2d0C0jWTKYjy7WJjGKeujSpSg xen/include/asm-x86/mach-default/mach_timer.h
   1.141 +427fa2d0UXLiS1scpNrK26ZT6Oes3g xen/include/asm-x86/mach-default/mach_traps.h
   1.142 +427fa2d0OfglYyfpDTD5DII4M0uZRw xen/include/asm-x86/mach-default/mach_wakecpu.h
   1.143 +427fa2d0_OBPxdi5Qo04JWgZhz7BFA xen/include/asm-x86/mach-default/pci-functions.h
   1.144 +427fa2d0mrTtXrliqDfLuJc5LLVXaA xen/include/asm-x86/mach-default/setup_arch_post.h
   1.145 +427fa2d0Uoo7gC61Kep6Yy7Os367Hg xen/include/asm-x86/mach-default/setup_arch_pre.h
   1.146 +427fa2d1EKnA8zCq2QLHiGOUqOgszg xen/include/asm-x86/mach-default/smpboot_hooks.h
   1.147  3ddb79c3I98vWcQR8xEo34JMJ4Ahyw xen/include/asm-x86/mc146818rtc.h
   1.148  40ec25fd7cSvbP7Biw91zaU_g0xsEQ xen/include/asm-x86/mm.h
   1.149  3ddb79c3n_UbPuxlkNxvvLycClIkxA xen/include/asm-x86/mpspec.h
   1.150 +427fa2d1eJRenftJJnRyLsHKl1ghtA xen/include/asm-x86/mpspec_def.h
   1.151  3ddb79c2wa0dA_LGigxOelSGbJ284Q xen/include/asm-x86/msr.h
   1.152  41aaf567Mi3OishhvrCtET1y-mxQBg xen/include/asm-x86/mtrr.h
   1.153  41a61536MFhNalgbVmYGXAhQsPTZNw xen/include/asm-x86/multicall.h
   1.154  3ddb79c3xjYnrv5t3VqYlR4tNEOl4Q xen/include/asm-x86/page.h
   1.155  3ddb79c3ysKUbxZuwKBRK3WXU2TlEg xen/include/asm-x86/pci.h
   1.156 +42422fb0FVX-TJkSvAXnbfwMf19XFA xen/include/asm-x86/physdev.h
   1.157  3ddb79c2QF5-pZGzuX4QukPCDAl59A xen/include/asm-x86/processor.h
   1.158  40cf1596bim9F9DNdV75klgRSZ6Y2A xen/include/asm-x86/regs.h
   1.159  3ddb79c2plf7ciNgoNjU-RsbUzawsw xen/include/asm-x86/rwlock.h
   1.160 @@ -1436,11 +1435,15 @@ 4266bd01Ul-pC01ZVvBkhBnv5eqzvw xen/inclu
   1.161  3ddb79c25UE59iu4JJcbRalx95mvcg xen/include/public/xen.h
   1.162  3e397e66m2tO3s-J8Jnr7Ws_tGoPTg xen/include/xen/ac_timer.h
   1.163  40715b2epYl2jBbxzz9CI2rgIca7Zg xen/include/xen/acpi.h
   1.164 +422f0995xCgnbsVhTjSncnqIABs64g xen/include/xen/adv_sched_hist.h
   1.165 +427fa2d1wyoVbvCyZRLposYjA_D_4g xen/include/xen/bitmap.h
   1.166 +427fa2d1ItcC_yWuBUkhc7adedP5ow xen/include/xen/bitops.h
   1.167  3ddb79c0c0cX_DZE209-Bb-Rx1v-Aw xen/include/xen/cache.h
   1.168  41f2cea7Yna7xc0X9fyavIjoSFFeVg xen/include/xen/compile.h.in
   1.169  3f840f12CkbYSlwMrY2S11Mpyxg7Nw xen/include/xen/compiler.h
   1.170  3ddb79c259jh8hE7vre_8NuE7nwNSA xen/include/xen/config.h
   1.171  3eb165e0eawr3R-p2ZQtSdLWtLRN_A xen/include/xen/console.h
   1.172 +427fa2d1bQCWgEQqTTh5MjG4MPEH9g xen/include/xen/cpumask.h
   1.173  3ddb79c1V44RD26YqCUm-kqIupM37A xen/include/xen/ctype.h
   1.174  3ddb79c05DdHQ0UxX_jKsXdR4QlMCA xen/include/xen/delay.h
   1.175  40f2b4a2hC3HtChu-ArD8LyojxWMjg xen/include/xen/domain.h
   1.176 @@ -1463,7 +1466,6 @@ 3ddb79c2Fg44_PBPVxHSC0gTOMq4Ow xen/inclu
   1.177  3ddb79c0MOVXq8qZDQRGb6z64_xAwg xen/include/xen/pci_ids.h
   1.178  3e54c38dlSCVdyVM4PKcrSfzLLxWUQ xen/include/xen/perfc.h
   1.179  3e54c38de9SUSYSAwxDf_DwkpAnQFA xen/include/xen/perfc_defn.h
   1.180 -42422fb0FVX-TJkSvAXnbfwMf19XFA xen/include/xen/physdev.h
   1.181  3ddb79c04nQVR3EYM5L4zxDV_MCo1g xen/include/xen/prefetch.h
   1.182  3e4540ccU1sgCx8seIMGlahmMfv7yQ xen/include/xen/reboot.h
   1.183  40589969nPq3DMzv24RDb5LXE9brHw xen/include/xen/sched-if.h

     3.1 --- a/BitKeeper/etc/logging_ok	Tue May 03 14:42:00 2005 +0000
     3.2 +++ b/BitKeeper/etc/logging_ok	Tue May 10 08:49:59 2005 +0000
     3.3 @@ -60,6 +60,7 @@ kmacy@shemp.lab.netapp.com
     3.4  kraxel@bytesex.org
     3.5  laudney@eclipse.(none)
     3.6  leendert@watson.ibm.com
     3.7 +lists-xen@pimb.org
     3.8  lynx@idefix.cl.cam.ac.uk
     3.9  maf46@burn.cl.cam.ac.uk
    3.10  mafetter@fleming.research
    3.11 @@ -99,3 +100,4 @@ vh249@airwolf.cl.cam.ac.uk
    3.12  vh249@arcadians.cl.cam.ac.uk
    3.13  xen-ia64.adm@bkbits.net
    3.14  xenbk@gandalf.hpl.hp.com
    3.15 +ydroneaud@mandriva.com

     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/docs/misc/sedf_scheduler_mini-HOWTO.txt	Tue May 10 08:49:59 2005 +0000
     4.3 @@ -0,0 +1,44 @@
     4.4 +sEDF scheduler
     4.5 +--------------
     4.6 +Author:
     4.7 +   Stephan.Diestelhorst@{cl.cam.ac.uk, inf.tu-dresden.de}
     4.8 +   
     4.9 +Overview:
    4.10 +  This scheduler provides weighted CPU sharing in an intuitive way and
    4.11 +  uses realtime-algorithms to ensure time guarantees.
    4.12 +
    4.13 +Usage:
    4.14 +   -add "sched=sedf" on Xen's boot command-line
    4.15 +   -create domains as usual
    4.16 +   -use "xm sedf <dom-id> <period> <slice> <latency-hint> <extra> <weight>"
    4.17 +    Where:
    4.18 +      -period/slice are the normal EDF scheduling parameters in nanosecs
    4.19 +      -latency-hint is the scaled period in case the domain is doing heavy I/O
    4.20 +         (unused by the currently compiled version)
    4.21 +      -extra is a flag (0/1), which controls whether the domain can run in
    4.22 +       extra-time
    4.23 +      -weight is mutually exclusive with period/slice and specifies another
    4.24 +       way of setting a domains cpu slice
    4.25 +
    4.26 +Examples:
    4.27 + normal EDF (20ms/5ms):
    4.28 +  xm sedf <dom-id> 20000000 5000000 0 0 0
    4.29 +  
    4.30 + best-effort domains (i.e. non-realtime):
    4.31 +  xm sedf <dom-id> 20000000 0 0 1 0
    4.32 + 
    4.33 + normal EDF (20ms/5ms) + share of extra-time:
    4.34 +  xm sedf <dom-id> 20000000 5000000 0 1 0
    4.35 +  
    4.36 + 4 domains with weights 2:3:4:2
    4.37 +  xm sedf <d1> 0 0 0 0 2
    4.38 +  xm sedf <d2> 0 0 0 0 3
    4.39 +  xm sedf <d3> 0 0 0 0 4
    4.40 +  xm sedf <d4> 0 0 0 0 2
    4.41 +  
    4.42 + 1 fully-specified (10ms/3ms) domain, 3 other domains share
    4.43 + available rest in 2:7:3 ratio:
    4.44 +  xm sedf <d1> 10000000 3000000 0 0 0
    4.45 +  xm sedf <d2> 0 0 0 0 2
    4.46 +  xm sedf <d3> 0 0 0 0 7
    4.47 +  xm sedf <d4> 0 0 0 0 3
    4.48 \ No newline at end of file

     5.1 --- a/freebsd-5.3-xen-sparse/i386-xen/i386-xen/clock.c	Tue May 03 14:42:00 2005 +0000
     5.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/clock.c	Tue May 10 08:49:59 2005 +0000
     5.3 @@ -87,6 +87,12 @@
     5.4  
     5.5  /* XEN specific defines */
     5.6  #include <machine/xen_intr.h>
     5.7 +#include <vm/vm.h>   /* needed by machine/pmap.h */
     5.8 +#include <vm/pmap.h> /* needed by machine/pmap.h */
     5.9 +#include <machine/pmap.h> /* needed by xen-os.h */
    5.10 +#include <machine/hypervisor-ifs.h>
    5.11 +#include <machine/xen-os.h> /* needed by xenfunc.h */
    5.12 +#include <machine/xenfunc.h>
    5.13  
    5.14  /*
    5.15   * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
    5.16 @@ -129,7 +135,15 @@ static uint64_t shadow_system_time;
    5.17  static uint32_t shadow_time_version;
    5.18  static struct timeval shadow_tv;
    5.19  
    5.20 +#define DEFINE_PER_CPU(type, name) \
    5.21 +    __typeof__(type) per_cpu__##name
    5.22 +
    5.23 +#define per_cpu(var, cpu)           (*((void)cpu, &per_cpu__##var))
    5.24 +
    5.25 +
    5.26  static uint64_t processed_system_time;/* System time (ns) at last processing. */
    5.27 +static DEFINE_PER_CPU(uint64_t, processed_system_time);
    5.28 +
    5.29  
    5.30  #define NS_PER_TICK (1000000000ULL/hz)
    5.31  
    5.32 @@ -202,18 +216,19 @@ static struct timecounter xen_timecounte
    5.33  static void 
    5.34  clkintr(struct clockframe *frame)
    5.35  {
    5.36 -    int64_t delta;
    5.37 +    int64_t cpu_delta, delta;
    5.38 +    int cpu = smp_processor_id();
    5.39      long ticks = 0;
    5.40  
    5.41 -
    5.42      do {
    5.43      	__get_time_values_from_xen();
    5.44 -    	delta = (int64_t)(shadow_system_time + 
    5.45 -			  xen_get_offset() * 1000 - 
    5.46 -			  processed_system_time);
    5.47 +    	delta = cpu_delta = (int64_t)shadow_system_time + 
    5.48 +		(int64_t)xen_get_offset() * 1000;
    5.49 +	delta -= processed_system_time;
    5.50 +	cpu_delta -= per_cpu(processed_system_time, cpu);
    5.51      } while (!TIME_VALUES_UP_TO_DATE);
    5.52  
    5.53 -    if (unlikely(delta < 0)) {
    5.54 +    if (unlikely(delta < 0) || unlikely(cpu_delta < 0)) {
    5.55          printk("Timer ISR: Time went backwards: %lld\n", delta);
    5.56          return;
    5.57      }
    5.58 @@ -225,15 +240,28 @@ clkintr(struct clockframe *frame)
    5.59          delta -= NS_PER_TICK;
    5.60          processed_system_time += NS_PER_TICK;
    5.61      }
    5.62 -
    5.63 -    if (ticks > 0) {
    5.64 -	if (frame)
    5.65 -		timer_func(frame);
    5.66 -#ifdef SMP
    5.67 -	if (timer_func == hardclock && frame)
    5.68 -		forward_hardclock();
    5.69 +    /* Local CPU jiffy work. */
    5.70 +    while (cpu_delta >= NS_PER_TICK) {
    5.71 +	    cpu_delta -= NS_PER_TICK;
    5.72 +	    per_cpu(processed_system_time, cpu) += NS_PER_TICK;
    5.73 +#if 0
    5.74 +	    update_process_times(user_mode(regs));
    5.75 +	    profile_tick(CPU_PROFILING, regs);
    5.76  #endif
    5.77      }
    5.78 +    if (ticks > 0) {
    5.79 +	if (frame) timer_func(frame);
    5.80 +    }
    5.81 +    
    5.82 +    if (cpu != 0)
    5.83 +	    return;
    5.84 +    /*
    5.85 +     * Take synchronised time from Xen once a minute if we're not
    5.86 +     * synchronised ourselves, and we haven't chosen to keep an independent
    5.87 +     * time base.
    5.88 +     */
    5.89 +    
    5.90 +    /* XXX TODO */
    5.91  }
    5.92  
    5.93  #include "opt_ddb.h"
    5.94 @@ -429,7 +457,7 @@ resettodr()
    5.95   * Start clocks running.
    5.96   */
    5.97  void
    5.98 -cpu_initclocks()
    5.99 +cpu_initclocks(void)
   5.100  {
   5.101  	int diag;
   5.102  	int time_irq = bind_virq_to_irq(VIRQ_TIMER);
   5.103 @@ -445,8 +473,26 @@ cpu_initclocks()
   5.104  	/* initialize xen values */
   5.105  	__get_time_values_from_xen();
   5.106  	processed_system_time = shadow_system_time;
   5.107 +	per_cpu(processed_system_time, 0) = processed_system_time;
   5.108 +
   5.109  }
   5.110  
   5.111 +#ifdef SMP 
   5.112 +void
   5.113 +ap_cpu_initclocks(void)
   5.114 +{
   5.115 +	int irq;
   5.116 +	int cpu = smp_processor_id();
   5.117 +
   5.118 +	per_cpu(processed_system_time, cpu) = shadow_system_time;
   5.119 +	
   5.120 +	irq = bind_virq_to_irq(VIRQ_TIMER);
   5.121 +	PCPU_SET(time_irq, irq);
   5.122 +	PANIC_IF(intr_add_handler("clk", irq, (driver_intr_t *)clkintr, 
   5.123 +				  NULL, INTR_TYPE_CLK | INTR_FAST, NULL));
   5.124 +}
   5.125 +#endif
   5.126 +
   5.127  void
   5.128  cpu_startprofclock(void)
   5.129  {

     6.1 --- a/freebsd-5.3-xen-sparse/i386-xen/i386-xen/evtchn.c	Tue May 03 14:42:00 2005 +0000
     6.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/evtchn.c	Tue May 10 08:49:59 2005 +0000
     6.3 @@ -79,9 +79,14 @@ evtchn_do_upcall(struct intrframe *frame
     6.4                  l2 &= ~(1 << l2i);
     6.5              
     6.6                  port = (l1i << 5) + l2i;
     6.7 +		irq = evtchn_to_irq[port];
     6.8 +#ifdef SMP		
     6.9 +		if (irq == PCPU_GET(cpuast)) 
    6.10 +			continue;
    6.11 +#endif
    6.12                  if ( (owned = mtx_owned(&sched_lock)) != 0 )
    6.13                      mtx_unlock_spin_flags(&sched_lock, MTX_QUIET);
    6.14 -                if ( (irq = evtchn_to_irq[port]) != -1 ) {
    6.15 +                if ( irq != -1 ) {
    6.16  		    struct intsrc *isrc = intr_lookup_source(irq);
    6.17  		    intr_execute_handlers(isrc, frame);
    6.18  		} else {
    6.19 @@ -584,6 +589,7 @@ ap_evtchn_init(int cpu)
    6.20          PCPU_GET(virq_to_irq)[i] = -1;
    6.21  }
    6.22  
    6.23 +
    6.24  static void 
    6.25  evtchn_init(void *dummy __unused)
    6.26  {
    6.27 @@ -591,13 +597,6 @@ evtchn_init(void *dummy __unused)
    6.28      struct xenpic *xp;
    6.29      struct xenpic_intsrc *pin;
    6.30  
    6.31 -    /*
    6.32 -     * xenpic_lock: in order to allow an interrupt to occur in a critical
    6.33 -     * 	        section, to set pcpu->ipending (etc...) properly, we
    6.34 -     *	        must be able to get the icu lock, so it can't be
    6.35 -     *	        under witness.
    6.36 -     */
    6.37 -    mtx_init(&irq_mapping_update_lock, "xp", NULL, MTX_DEF);
    6.38  
    6.39      /* XXX -- expedience hack */
    6.40      PCPU_SET(virq_to_irq, (int *)&virq_to_irq[0]);
    6.41 @@ -657,3 +656,11 @@ evtchn_init(void *dummy __unused)
    6.42  }
    6.43  
    6.44  SYSINIT(evtchn_init, SI_SUB_INTR, SI_ORDER_ANY, evtchn_init, NULL);
    6.45 +    /*
    6.46 +     * xenpic_lock: in order to allow an interrupt to occur in a critical
    6.47 +     * 	        section, to set pcpu->ipending (etc...) properly, we
    6.48 +     *	        must be able to get the icu lock, so it can't be
    6.49 +     *	        under witness.
    6.50 +     */
    6.51 +
    6.52 +MTX_SYSINIT(irq_mapping_update_lock, &irq_mapping_update_lock, "xp", MTX_DEF|MTX_NOWITNESS);

     7.1 --- a/freebsd-5.3-xen-sparse/i386-xen/i386-xen/machdep.c	Tue May 03 14:42:00 2005 +0000
     7.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/machdep.c	Tue May 10 08:49:59 2005 +0000
     7.3 @@ -78,6 +78,7 @@
     7.4  #include <sys/sched.h>
     7.5  #include <sys/sysent.h>
     7.6  #include <sys/sysctl.h>
     7.7 +#include <sys/smp.h>
     7.8  #include <sys/ucontext.h>
     7.9  #include <sys/vmmeter.h>
    7.10  #include <sys/bus.h>
    7.11 @@ -883,14 +884,6 @@ SYSCTL_INT(_machdep, OID_AUTO, cpu_idle_
    7.12  static void
    7.13  cpu_idle_default(void)
    7.14  {
    7.15 -#if 0
    7.16 -	/*
    7.17 -	 * we must absolutely guarentee that hlt is the
    7.18 -	 * absolute next instruction after sti or we
    7.19 -	 * introduce a timing window.
    7.20 -	 */
    7.21 -	__asm __volatile("sti; hlt");
    7.22 -#endif
    7.23  	idle_block();
    7.24  	enable_intr();
    7.25  }
    7.26 @@ -1376,6 +1369,7 @@ pteinfo_t *pteinfo_list;
    7.27  unsigned long *xen_machine_phys = ((unsigned long *)VADDR(1008, 0));
    7.28  int preemptable;
    7.29  int gdt_set;
    7.30 +static int ncpus;
    7.31  
    7.32  /* Linux infection */
    7.33  #define PAGE_OFFSET  KERNBASE
    7.34 @@ -1387,6 +1381,10 @@ initvalues(start_info_t *startinfo)
    7.35      int i;
    7.36      vm_paddr_t pdir_shadow_ma, KPTphys;
    7.37      vm_offset_t *pdir_shadow;
    7.38 +#ifdef SMP
    7.39 +    int j;
    7.40 +#endif
    7.41 +
    7.42  #ifdef WRITABLE_PAGETABLES
    7.43      printk("using writable pagetables\n");
    7.44      HYPERVISOR_vm_assist(VMASST_CMD_enable, VMASST_TYPE_writable_pagetables);
    7.45 @@ -1447,18 +1445,19 @@ initvalues(start_info_t *startinfo)
    7.46  
    7.47  
    7.48  #ifdef SMP
    7.49 +#if 0
    7.50      /* allocate cpu0 private page */
    7.51      cpu0prvpage = (KERNBASE + (tmpindex << PAGE_SHIFT));
    7.52      tmpindex++; 
    7.53 -
    7.54 +#endif
    7.55      /* allocate SMP page table */
    7.56      SMPpt = (unsigned long *)(KERNBASE + (tmpindex << PAGE_SHIFT));
    7.57 -
    7.58 +#if 0
    7.59      /* Map the private page into the SMP page table */
    7.60      SMPpt[0] = vtomach(cpu0prvpage) | PG_RW | PG_M | PG_V | PG_A;
    7.61 -
    7.62 +#endif
    7.63      /* map SMP page table RO */
    7.64 -    PT_SET_MA(SMPpt, vtomach(SMPpt) & ~PG_RW);
    7.65 +    PT_SET_MA(SMPpt, *vtopte((vm_offset_t)SMPpt) & ~PG_RW);
    7.66  
    7.67      /* put the page table into the page directory */
    7.68      xen_queue_pt_update((vm_paddr_t)(IdlePTD + MPPTDI), 
    7.69 @@ -1496,44 +1495,61 @@ initvalues(start_info_t *startinfo)
    7.70      tmpindex++;
    7.71  
    7.72      HYPERVISOR_shared_info->arch.pfn_to_mfn_frame_list = (unsigned long)xen_phys_machine;
    7.73 +    ncpus = HYPERVISOR_shared_info->n_vcpu; 
    7.74 +#ifdef SMP
    7.75 +    for (i = 0; i < ncpus; i++) {
    7.76 +	    int npages = (sizeof(struct privatespace) + 1)/PAGE_SIZE;
    7.77 +	    for (j = 0; j < npages; j++) {
    7.78 +		    vm_paddr_t ma = xpmap_ptom(tmpindex << PAGE_SHIFT);
    7.79 +		    tmpindex++;
    7.80 +		    PT_SET_VA_MA(SMPpt + i*npages + j, ma | PG_A | PG_V | PG_RW | PG_M, FALSE);
    7.81 +	    }
    7.82 +    }
    7.83 +    xen_flush_queue();
    7.84 +#endif
    7.85      
    7.86      init_first = tmpindex;
    7.87      
    7.88  }
    7.89  
    7.90 +
    7.91 +trap_info_t trap_table[] = {
    7.92 +	{ 0,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(div)},
    7.93 +	{ 1,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(dbg)},
    7.94 +	{ 3,   3, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(bpt)},
    7.95 +	{ 4,   3, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(ofl)},
    7.96 +	/* This is UPL on Linux and KPL on BSD */
    7.97 +	{ 5,   3, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(bnd)},
    7.98 +	{ 6,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(ill)},
    7.99 +	{ 7,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(dna)},
   7.100 +	/*
   7.101 +	 * { 8,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(XXX)},
   7.102 +	 *   no handler for double fault
   7.103 +	 */
   7.104 +	{ 9,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(fpusegm)},
   7.105 +	{10,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(tss)},
   7.106 +	{11,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(missing)},
   7.107 +	{12,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(stk)},
   7.108 +	{13,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(prot)},
   7.109 +	{14,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(page)},
   7.110 +	{15,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(rsvd)},
   7.111 +	{16,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(fpu)},
   7.112 +	{17,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(align)},
   7.113 +	{18,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(mchk)},
   7.114 +	{19,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(xmm)},
   7.115 +	{0x80, 3, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(int0x80_syscall)},
   7.116 +	{  0, 0,           0, 0 }
   7.117 +};
   7.118 +
   7.119  void
   7.120  init386(void)
   7.121  {
   7.122  	int gsel_tss, metadata_missing, off, x, error;
   7.123  	struct pcpu *pc;
   7.124  	unsigned long gdtmachpfn;
   7.125 -	trap_info_t trap_table[] = {
   7.126 -	    { 0,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(div)},
   7.127 -	    { 1,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(dbg)},
   7.128 -	    { 3,   3, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(bpt)},
   7.129 -	    { 4,   3, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(ofl)},
   7.130 -	    /* This is UPL on Linux and KPL on BSD */
   7.131 -	    { 5,   3, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(bnd)},
   7.132 -	    { 6,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(ill)},
   7.133 -	    { 7,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(dna)},
   7.134 -	    /*
   7.135 -	     * { 8,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(XXX)},
   7.136 -	     *   no handler for double fault
   7.137 -	     */
   7.138 -	    { 9,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(fpusegm)},
   7.139 -	    {10,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(tss)},
   7.140 -	    {11,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(missing)},
   7.141 -	    {12,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(stk)},
   7.142 -	    {13,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(prot)},
   7.143 -	    {14,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(page)},
   7.144 -	    {15,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(rsvd)},
   7.145 -	    {16,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(fpu)},
   7.146 -	    {17,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(align)},
   7.147 -	    {18,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(mchk)},
   7.148 -	    {19,   0, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(xmm)},
   7.149 -	    {0x80, 3, GSEL(GCODE_SEL, SEL_KPL), (unsigned long) &IDTVEC(int0x80_syscall)},
   7.150 -	    {  0, 0,           0, 0 }
   7.151 -        };
   7.152 +#ifdef SMP
   7.153 +	int i;
   7.154 +#endif
   7.155  	proc0.p_uarea = proc0uarea;
   7.156  	thread0.td_kstack = proc0kstack;
   7.157  	thread0.td_pcb = (struct pcb *)
   7.158 @@ -1583,26 +1599,42 @@ init386(void)
   7.159  	gdt_segs[GDATA_SEL].ssd_limit = atop(0 - ((1 << 26) - (1 << 22) + (1 << 16))); 
   7.160  #endif
   7.161  #ifdef SMP
   7.162 -	/* this correspond to the cpu private page as mapped into the SMP page 
   7.163 -	 * table in initvalues
   7.164 +	/* XXX this will blow up if there are more than 512/NGDT vcpus - will never 
   7.165 +	 * be an issue in the real world but should add an assert on general principles
   7.166 +	 * we'll likely blow up when we hit LAST_RESERVED_GDT_ENTRY, at which point we
   7.167 +	 * would need to start allocating more pages for the GDT
   7.168  	 */
   7.169  	pc = &SMP_prvspace[0].pcpu;
   7.170 -	gdt_segs[GPRIV_SEL].ssd_limit =
   7.171 -		atop(sizeof(struct privatespace) - 1);
   7.172 +	for (i = 0; i < ncpus; i++) {
   7.173 +		cpu_add(i, (i == 0));
   7.174 +
   7.175 +		gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[i];
   7.176 +		gdt_segs[GPRIV_SEL].ssd_limit =
   7.177 +			atop(sizeof(struct privatespace) - 1);
   7.178 +		gdt_segs[GPROC0_SEL].ssd_base =
   7.179 +			(int) &SMP_prvspace[i].pcpu.pc_common_tss;
   7.180 +		SMP_prvspace[i].pcpu.pc_prvspace =
   7.181 +			&SMP_prvspace[i].pcpu;
   7.182 +		
   7.183 +		for (x = 0; x < NGDT; x++) {
   7.184 +			ssdtosd(&gdt_segs[x], &gdt[i * NGDT + x].sd);
   7.185 +		}
   7.186 +	}
   7.187  #else
   7.188  	pc = &__pcpu;
   7.189  	gdt_segs[GPRIV_SEL].ssd_limit =
   7.190  		atop(sizeof(struct pcpu) - 1);
   7.191 -#endif
   7.192  	gdt_segs[GPRIV_SEL].ssd_base = (int) pc;
   7.193  	gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss;
   7.194  	for (x = 0; x < NGDT; x++)
   7.195  	    ssdtosd(&gdt_segs[x], &gdt[x].sd);
   7.196 +#endif
   7.197 +
   7.198  
   7.199  	PT_SET_MA(gdt, *vtopte((unsigned long)gdt) & ~PG_RW);
   7.200  	gdtmachpfn = vtomach(gdt) >> PAGE_SHIFT;
   7.201 -	if ((error = HYPERVISOR_set_gdt(&gdtmachpfn, LAST_RESERVED_GDT_ENTRY + 1))) 
   7.202 -	    panic("set_gdt failed");
   7.203 +	PANIC_IF(HYPERVISOR_set_gdt(&gdtmachpfn, LAST_RESERVED_GDT_ENTRY + 1) != 0);
   7.204 +
   7.205  	
   7.206  	lgdt_finish();
   7.207  	gdt_set = 1;

     8.1 --- a/freebsd-5.3-xen-sparse/i386-xen/i386-xen/mp_machdep.c	Tue May 03 14:42:00 2005 +0000
     8.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/mp_machdep.c	Tue May 10 08:49:59 2005 +0000
     8.3 @@ -83,7 +83,16 @@
     8.4  #include <machine/specialreg.h>
     8.5  #include <machine/privatespace.h>
     8.6  
     8.7 +
     8.8 +/* XEN includes */
     8.9  #include <machine/xenfunc.h>
    8.10 +#include <machine/xen_intr.h>
    8.11 +
    8.12 +void Xhypervisor_callback(void);
    8.13 +void failsafe_callback(void);
    8.14 +
    8.15 +/***************/
    8.16 +
    8.17  
    8.18  #define WARMBOOT_TARGET		0
    8.19  #define WARMBOOT_OFF		(KERNBASE + 0x0467)
    8.20 @@ -94,6 +103,10 @@
    8.21  #define BIOS_RESET		(0x0f)
    8.22  #define BIOS_WARM		(0x0a)
    8.23  
    8.24 +
    8.25 +#undef POSTCODE
    8.26 +#define POSTCODE(x)
    8.27 +
    8.28  /*
    8.29   * this code MUST be enabled here and in mpboot.s.
    8.30   * it follows the very early stages of AP boot by placing values in CMOS ram.
    8.31 @@ -175,6 +188,8 @@ extern pt_entry_t *KPTphys;
    8.32  /* SMP page table page */
    8.33  extern pt_entry_t *SMPpt;
    8.34  
    8.35 +extern trap_info_t trap_table[];
    8.36 +
    8.37  struct pcb stoppcbs[MAXCPU];
    8.38  
    8.39  /* Variables needed for SMP tlb shootdown. */
    8.40 @@ -208,7 +223,9 @@ static u_int boot_address;
    8.41  
    8.42  static void	set_logical_apic_ids(void);
    8.43  static int	start_all_aps(void);
    8.44 +#if 0
    8.45  static void	install_ap_tramp(void);
    8.46 +#endif
    8.47  static int	start_ap(int apic_id);
    8.48  static void	release_aps(void *dummy);
    8.49  
    8.50 @@ -314,6 +331,7 @@ int
    8.51  cpu_mp_probe(void)
    8.52  {
    8.53  
    8.54 +	mp_ncpus = HYPERVISOR_shared_info->n_vcpu;
    8.55  	/*
    8.56  	 * Always record BSP in CPU map so that the mbuf init code works
    8.57  	 * correctly.
    8.58 @@ -342,20 +360,24 @@ cpu_mp_probe(void)
    8.59  	return (1);
    8.60  }
    8.61  
    8.62 -/*
    8.63 - * Initialize the IPI handlers and start up the AP's.
    8.64 - */
    8.65 -void
    8.66 -cpu_mp_start(void)
    8.67 +static void
    8.68 +cpu_mp_ipi_init(void)
    8.69  {
    8.70 -	int i;
    8.71 -
    8.72 -	POSTCODE(MP_START_POST);
    8.73 -
    8.74 -	/* Initialize the logical ID to APIC ID table. */
    8.75 -	for (i = 0; i < MAXCPU; i++)
    8.76 -		cpu_apic_ids[i] = -1;
    8.77 -
    8.78 +	int irq;
    8.79 +	int cpu = smp_processor_id();
    8.80 +	/* 
    8.81 +	 * these are not needed by XenFreeBSD - from Keir:
    8.82 +	 * For TLB-flush related IPIs, Xen has hypercalls 
    8.83 +	 * you should use instead. You can pass a pointer 
    8.84 +	 * to a vcpu bitmap to update_va_mapping(), and to
    8.85 +	 * MMUEXT_flush_tlb_multi and MMEXT_invlpg_multi. 
    8.86 +	 * Xen will then make sure that those vcpus get 
    8.87 +	 * flushed appropriately before returning to the
    8.88 +	 * caller.
    8.89 +	 * There is also no indication that we need to forward
    8.90 +	 * clock interrupts.
    8.91 +	 */
    8.92 +#if 0 
    8.93  	/* Install an inter-CPU IPI for TLB invalidation */
    8.94  	setidt(IPI_INVLTLB, IDTVEC(invltlb),
    8.95  	       SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
    8.96 @@ -371,22 +393,69 @@ cpu_mp_start(void)
    8.97  	/* Install an inter-CPU IPI for forwarding statclock() */
    8.98  	setidt(IPI_STATCLOCK, IDTVEC(statclock),
    8.99  	       SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
   8.100 -	
   8.101 +#endif
   8.102 +
   8.103 +	/* 
   8.104 +	 * These can all be consolidated. For now leaving 
   8.105 +	 * as individual IPIs.
   8.106 +	 *
   8.107 +	 */
   8.108 +#if 0
   8.109  	/* Install an inter-CPU IPI for lazy pmap release */
   8.110  	setidt(IPI_LAZYPMAP, IDTVEC(lazypmap),
   8.111  	       SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
   8.112 +#else
   8.113 +	irq = bind_ipi_on_cpu_to_irq(cpu, IPI_LAZYPMAP);
   8.114 +	PCPU_SET(lazypmap, irq);
   8.115 +	PANIC_IF(intr_add_handler("pmap_lazyfix", irq, 
   8.116 +				  (driver_intr_t *)pmap_lazyfix_action, 
   8.117 +				  NULL, INTR_TYPE_CLK | INTR_FAST, NULL));
   8.118 +#endif
   8.119  
   8.120 +#if 0
   8.121  	/* Install an inter-CPU IPI for all-CPU rendezvous */
   8.122  	setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous),
   8.123  	       SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
   8.124 +#else 
   8.125 +	irq = bind_ipi_on_cpu_to_irq(cpu, IPI_RENDEZVOUS);
   8.126 +	PCPU_SET(rendezvous, irq);
   8.127 +	PANIC_IF(intr_add_handler("smp_rendezvous", irq, 
   8.128 +				  (driver_intr_t *)smp_rendezvous_action, 
   8.129 +				  NULL, INTR_TYPE_CLK | INTR_FAST, NULL));
   8.130 +#endif
   8.131  
   8.132 +#if 0
   8.133  	/* Install an inter-CPU IPI for forcing an additional software trap */
   8.134  	setidt(IPI_AST, IDTVEC(cpuast),
   8.135  	       SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
   8.136 -
   8.137 +#else
   8.138 +	irq = bind_ipi_on_cpu_to_irq(cpu, IPI_AST);
   8.139 +	PCPU_SET(cpuast, irq);
   8.140 +#endif
   8.141 +	/* XXX ignore for now */
   8.142 +#if 0 
   8.143  	/* Install an inter-CPU IPI for CPU stop/restart */
   8.144  	setidt(IPI_STOP, IDTVEC(cpustop),
   8.145  	       SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
   8.146 +#endif
   8.147 +
   8.148 +}
   8.149 +
   8.150 +SYSINIT(ipi_setup, SI_SUB_INTR, SI_ORDER_ANY, cpu_mp_ipi_init, NULL);
   8.151 +
   8.152 +/*
   8.153 + * Initialize the IPI handlers and start up the AP's.
   8.154 + */
   8.155 +void
   8.156 +cpu_mp_start(void) /* --- Start here --- */
   8.157 +{
   8.158 +	int i;
   8.159 +
   8.160 +	POSTCODE(MP_START_POST);
   8.161 +
   8.162 +	/* Initialize the logical ID to APIC ID table. */
   8.163 +	for (i = 0; i < MAXCPU; i++)
   8.164 +		cpu_apic_ids[i] = -1;
   8.165  
   8.166  
   8.167  	/* Set boot_cpu_id if needed. */
   8.168 @@ -437,35 +506,44 @@ cpu_mp_announce(void)
   8.169  void
   8.170  init_secondary(void)
   8.171  {
   8.172 -	int	gsel_tss;
   8.173 -	int	x, myid;
   8.174 +	int	myid;
   8.175 +	unsigned long gdtmachpfn;
   8.176 +	printk("MADE IT!!");
   8.177 +
   8.178  #if 0
   8.179  	u_int	cr0;
   8.180  #endif
   8.181 +	/* Steps to booting SMP on xen as gleaned from XenLinux:
   8.182 +	 * - cpu_init() - processor specific initialization
   8.183 +	 * - smp_callin() 
   8.184 +	 *    - wait 2s for BP to finish its startup sequence
   8.185 +	 *    - map_cpu_to_logical_apicid()
   8.186 +	 *    - save cpuid info
   8.187 +	 *    - set bit in callin map to let master (BP?) continue
   8.188 +	 * - local setup timer() - per cpu timer initialization
   8.189 +	 * - ldebug_setup() - bind debug IRQ to local CPU.
   8.190 +	 * - smp_intr_init() - IPI setup that we do in cpu_mp_start
   8.191 +	 * - local_irq_enable() - enable interrupts locally
   8.192 +	 * - cpu_set(id, map) - announce that we're up
   8.193 +	 * - cpu_idle() - make us schedulable
   8.194 +	 */
   8.195 +
   8.196 +
   8.197  	/* bootAP is set in start_ap() to our ID. */
   8.198  	myid = bootAP;
   8.199 -	gdt_segs[GPRIV_SEL].ssd_base = (int) &SMP_prvspace[myid];
   8.200 -	gdt_segs[GPROC0_SEL].ssd_base =
   8.201 -		(int) &SMP_prvspace[myid].pcpu.pc_common_tss;
   8.202 -	SMP_prvspace[myid].pcpu.pc_prvspace =
   8.203 -		&SMP_prvspace[myid].pcpu;
   8.204 +
   8.205 +	gdtmachpfn = vtomach(gdt) >> PAGE_SHIFT;
   8.206 +	PANIC_IF(HYPERVISOR_set_gdt(&gdtmachpfn, LAST_RESERVED_GDT_ENTRY + 1) != 0); 
   8.207  
   8.208 -	for (x = 0; x < NGDT; x++) {
   8.209 -		ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
   8.210 -	}
   8.211 +	
   8.212 +	lgdt_finish();
   8.213  
   8.214 -#if 0
   8.215 -	r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
   8.216 -	r_gdt.rd_base = (int) &gdt[myid * NGDT];
   8.217 -	lgdt(&r_gdt);			/* does magic intra-segment return */
   8.218 +	PCPU_SET(cpuid, myid);
   8.219  
   8.220 -	lidt(&r_idt);
   8.221 -	lldt(_default_ldt);
   8.222 -#endif
   8.223 +
   8.224 +	set_user_ldt((struct mdproc *)_default_ldt);
   8.225  	PCPU_SET(currentldt, _default_ldt);
   8.226  
   8.227 -	gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
   8.228 -	gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
   8.229  	PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
   8.230  	PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
   8.231  	PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
   8.232 @@ -557,6 +635,13 @@ init_secondary(void)
   8.233  	while (smp_started == 0)
   8.234  		ia32_pause();
   8.235  
   8.236 +	/* need to wait until now to setup the IPIs as SI_SUB_CPU is
   8.237 +	 * much earlier than SI_SUB_INTR
   8.238 +	 */  
   8.239 +	ap_evtchn_init(myid);
   8.240 +	ap_cpu_initclocks();
   8.241 +	cpu_mp_ipi_init();
   8.242 +
   8.243  	/* ok, now grab sched_lock and enter the scheduler */
   8.244  	mtx_lock_spin(&sched_lock);
   8.245  
   8.246 @@ -610,28 +695,35 @@ set_logical_apic_ids(void)
   8.247  static int
   8.248  start_all_aps(void)
   8.249  {
   8.250 -#ifndef PC98
   8.251 -	u_char mpbiosreason;
   8.252 -#endif
   8.253 -	u_long mpbioswarmvec;
   8.254  	struct pcpu *pc;
   8.255  	char *stack;
   8.256 -	uintptr_t kptbase;
   8.257 -	int i, pg, apic_id, cpu;
   8.258 +	int i, apic_id, cpu;
   8.259 +
   8.260 +	/* 
   8.261 +	 * This function corresponds most closely to 
   8.262 +	 * smp_boot_cpus in XenLinux - the sequence there 
   8.263 +	 * is:
   8.264 +	 * - check if SMP config is found - if not:
   8.265 +	 *     - clear the I/O APIC IRQs
   8.266 +	 *     - map cpu to logical apicid
   8.267 +	 *     - exit
   8.268 +	 * - smp_intr_init - IPI initialization
   8.269 +	 * - map cpu to logical apicid
   8.270 +	 * - boot each of the vcpus
   8.271 +	 * - clear and then construct the cpu sibling [logical CPUs] map.
   8.272 +	 *
   8.273 +	 */
   8.274  
   8.275  	POSTCODE(START_ALL_APS_POST);
   8.276  
   8.277  	mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
   8.278 -
   8.279 +#if 0
   8.280  	/* install the AP 1st level boot code */
   8.281  	install_ap_tramp();
   8.282  
   8.283  	/* save the current value of the warm-start vector */
   8.284  	mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
   8.285 -#ifndef PC98
   8.286 -	outb(CMOS_REG, BIOS_RESET);
   8.287 -	mpbiosreason = inb(CMOS_DATA);
   8.288 -#endif
   8.289 +
   8.290  
   8.291  	/* set up temporary P==V mapping for AP boot */
   8.292  	/* XXX this is a hack, we should boot the AP on its own stack/PTD */
   8.293 @@ -640,7 +732,7 @@ start_all_aps(void)
   8.294  		PTD[i] = (pd_entry_t)(PG_V | PG_RW |
   8.295  		    ((kptbase + i * PAGE_SIZE) & PG_FRAME));
   8.296  	invltlb();
   8.297 -
   8.298 +#endif
   8.299  	/* start each AP */
   8.300  	for (cpu = 0, apic_id = 0; apic_id < MAXCPU; apic_id++) {
   8.301  		if (!cpu_info[apic_id].cpu_present ||
   8.302 @@ -650,7 +742,7 @@ start_all_aps(void)
   8.303  
   8.304  		/* save APIC ID for this logical ID */
   8.305  		cpu_apic_ids[cpu] = apic_id;
   8.306 -
   8.307 +#if 0
   8.308  		/* first page of AP's private space */
   8.309  		pg = cpu * i386_btop(sizeof(struct privatespace));
   8.310  
   8.311 @@ -665,11 +757,14 @@ start_all_aps(void)
   8.312  		for (i = 0; i < KSTACK_PAGES; i++)
   8.313  			SMPpt[pg + 1 + i] = (pt_entry_t)
   8.314  			    (PG_V | PG_RW | vtophys(PAGE_SIZE * i + stack));
   8.315 +#endif
   8.316 +		pc = &SMP_prvspace[cpu].pcpu;
   8.317  
   8.318  		/* prime data page for it to use */
   8.319  		pcpu_init(pc, cpu, sizeof(struct pcpu));
   8.320  		pc->pc_apic_id = apic_id;
   8.321  
   8.322 +#if 0
   8.323  		/* setup a vector to our boot code */
   8.324  		*((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
   8.325  		*((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
   8.326 @@ -677,7 +772,7 @@ start_all_aps(void)
   8.327  		outb(CMOS_REG, BIOS_RESET);
   8.328  		outb(CMOS_DATA, BIOS_WARM);	/* 'warm-start' */
   8.329  #endif
   8.330 -
   8.331 +#endif
   8.332  		bootSTK = &SMP_prvspace[cpu].idlekstack[KSTACK_PAGES *
   8.333  		    PAGE_SIZE];
   8.334  		bootAP = cpu;
   8.335 @@ -700,13 +795,10 @@ start_all_aps(void)
   8.336  	/* build our map of 'other' CPUs */
   8.337  	PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
   8.338  
   8.339 +#if 0
   8.340  	/* restore the warmstart vector */
   8.341  	*(u_long *) WARMBOOT_OFF = mpbioswarmvec;
   8.342 -#ifndef PC98
   8.343 -	outb(CMOS_REG, BIOS_RESET);
   8.344 -	outb(CMOS_DATA, mpbiosreason);
   8.345  #endif
   8.346 -
   8.347  	/*
   8.348  	 * Set up the idle context for the BSP.  Similar to above except
   8.349  	 * that some was done by locore, some by pmap.c and some is implicit
   8.350 @@ -739,7 +831,7 @@ extern void bootDataSeg(void);
   8.351  extern void MPentry(void);
   8.352  extern u_int MP_GDT;
   8.353  extern u_int mp_gdtbase;
   8.354 -
   8.355 +#if 0
   8.356  static void
   8.357  install_ap_tramp(void)
   8.358  {
   8.359 @@ -791,6 +883,21 @@ install_ap_tramp(void)
   8.360  	*dst16 = (u_int) boot_address & 0xffff;
   8.361  	*dst8 = ((u_int) boot_address >> 16) & 0xff;
   8.362  }
   8.363 +#endif
   8.364 +
   8.365 +static int 
   8.366 +cpu_mp_trap_init(trap_info_t *trap_ctxt)
   8.367 +{
   8.368 +
   8.369 +        trap_info_t *t = trap_table;
   8.370 +
   8.371 +        for (t = trap_table; t->address; t++) {
   8.372 +                trap_ctxt[t->vector].flags = t->flags;
   8.373 +                trap_ctxt[t->vector].cs = t->cs;
   8.374 +                trap_ctxt[t->vector].address = t->address;
   8.375 +        }
   8.376 +        return 0x80 /*SYSCALL_VECTOR*/;
   8.377 +}
   8.378  
   8.379  /*
   8.380   * This function starts the AP (application processor) identified
   8.381 @@ -802,8 +909,25 @@ install_ap_tramp(void)
   8.382  static int
   8.383  start_ap(int apic_id)
   8.384  {
   8.385 -	int vector, ms;
   8.386 -	int cpus;
   8.387 +	int vector, ms, i;
   8.388 +	int cpus, boot_error;
   8.389 +	vcpu_guest_context_t ctxt;
   8.390 +
   8.391 +	/* 
   8.392 +	 * This is the FreeBSD equivalent to do_boot_cpu(apicid) in
   8.393 +	 * smpboot.c. 
   8.394 +	 * its initialization sequence consists of:
   8.395 +	 * - fork_idle(cpu) to create separate idle context
   8.396 +	 * - initialization of idle's context to start_secondary
   8.397 +	 * - initialization of cpu ctxt to start in startup_32_smp
   8.398 +	 * - then we call HYPERVISOR_boot_vcpu with the cpu index and
   8.399 +	 *   a pointer to the context.
   8.400 +	 * - on boot success we:
   8.401 +	 *   - set ourselves in the callout_map
   8.402 +	 *   - wait up to 5 seconds for us to be set in the callin map
   8.403 +	 * - set x86_cpu_to_apicid[cpu] = apicid;
   8.404 +	 *
   8.405 +	 */
   8.406  
   8.407  	POSTCODE(START_AP_POST);
   8.408  
   8.409 @@ -813,6 +937,55 @@ start_ap(int apic_id)
   8.410  	/* used as a watchpoint to signal AP startup */
   8.411  	cpus = mp_naps;
   8.412  
   8.413 +	memset(&ctxt, 0, sizeof(ctxt));
   8.414 +
   8.415 +	ctxt.user_regs.ds = GSEL(GDATA_SEL, SEL_KPL);
   8.416 +	ctxt.user_regs.es = GSEL(GDATA_SEL, SEL_KPL);
   8.417 +	ctxt.user_regs.fs = 0;
   8.418 +	ctxt.user_regs.gs = 0;
   8.419 +	ctxt.user_regs.ss = __KERNEL_DS;
   8.420 +	ctxt.user_regs.cs = __KERNEL_CS;
   8.421 +	ctxt.user_regs.eip = (unsigned long)init_secondary;
   8.422 +	ctxt.user_regs.esp = (unsigned long)bootSTK;
   8.423 +#ifdef notyet
   8.424 +	ctxt.user_regs.eflags = (1<<9) | (1<<2) | (idle->thread.io_pl<<12);
   8.425 +#else
   8.426 +	ctxt.user_regs.eflags = (1<<9) | (1<<2);
   8.427 +#endif
   8.428 +	/* FPU is set up to default initial state. */
   8.429 +	memset(&ctxt.fpu_ctxt, 0, sizeof(ctxt.fpu_ctxt));
   8.430 +
   8.431 +	/* Virtual IDT is empty at start-of-day. */
   8.432 +	for ( i = 0; i < 256; i++ )
   8.433 +	{
   8.434 +		ctxt.trap_ctxt[i].vector = i;
   8.435 +		ctxt.trap_ctxt[i].cs     = FLAT_KERNEL_CS;
   8.436 +	}
   8.437 +	ctxt.fast_trap_idx = cpu_mp_trap_init(ctxt.trap_ctxt);
   8.438 +
   8.439 +	/* No LDT. */
   8.440 +	ctxt.ldt_ents = 0;
   8.441 +
   8.442 +	/* Ring 1 stack is the initial stack. */
   8.443 +	ctxt.kernel_ss = __KERNEL_DS;
   8.444 +	ctxt.kernel_sp = (unsigned long)bootSTK;
   8.445 +
   8.446 +	/* Callback handlers. */
   8.447 +	ctxt.event_callback_cs     = __KERNEL_CS;
   8.448 +	ctxt.event_callback_eip    = (unsigned long)Xhypervisor_callback;
   8.449 +	ctxt.failsafe_callback_cs  = __KERNEL_CS;
   8.450 +	ctxt.failsafe_callback_eip = (unsigned long)failsafe_callback;
   8.451 +
   8.452 +	ctxt.pt_base = (vm_paddr_t)IdlePTD;
   8.453 +
   8.454 +	boot_error = HYPERVISOR_boot_vcpu(bootAP, &ctxt);
   8.455 +
   8.456 +	
   8.457 +	if (boot_error) 
   8.458 +		printk("Houston we have a problem\n");
   8.459 +	else
   8.460 +		printk("boot_vcpu succeeded\n");
   8.461 +#if 0
   8.462  	/*
   8.463  	 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
   8.464  	 * and running the target CPU. OR this INIT IPI might be latched (P5
   8.465 @@ -862,6 +1035,7 @@ start_ap(int apic_id)
   8.466  	    APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
   8.467  	    vector, apic_id);
   8.468  	lapic_ipi_wait(-1);
   8.469 +#endif
   8.470  	DELAY(200);		/* wait ~200uS */
   8.471  
   8.472  	/* Wait up to 5 seconds for it to start. */

     9.1 --- a/freebsd-5.3-xen-sparse/i386-xen/i386-xen/pmap.c	Tue May 03 14:42:00 2005 +0000
     9.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/pmap.c	Tue May 10 08:49:59 2005 +0000
     9.3 @@ -1374,7 +1374,6 @@ static u_int *lazymask;
     9.4  static u_int lazyptd;
     9.5  static volatile u_int lazywait;
     9.6  
     9.7 -void pmap_lazyfix_action(void);
     9.8  
     9.9  void
    9.10  pmap_lazyfix_action(void)

    10.1 --- a/freebsd-5.3-xen-sparse/i386-xen/i386-xen/xen_machdep.c	Tue May 03 14:42:00 2005 +0000
    10.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/i386-xen/xen_machdep.c	Tue May 10 08:49:59 2005 +0000
    10.3 @@ -380,8 +380,6 @@ printk(const char *fmt, ...)
    10.4          (void)HYPERVISOR_console_write(buf, ret);
    10.5  }
    10.6  
    10.7 -#define PANIC_IF(exp) if (unlikely(exp)) {printk("%s failed\n",#exp); panic("%s: %s:%d", #exp, __FILE__, __LINE__);} 
    10.8 -
    10.9  
   10.10  #define XPQUEUE_SIZE 128
   10.11  #ifdef SMP

    11.1 --- a/freebsd-5.3-xen-sparse/i386-xen/include/hypervisor.h	Tue May 03 14:42:00 2005 +0000
    11.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/include/hypervisor.h	Tue May 10 08:49:59 2005 +0000
    11.3 @@ -441,4 +441,20 @@ HYPERVISOR_vm_assist(unsigned int cmd, u
    11.4      return ret;
    11.5  }
    11.6  
    11.7 +static inline int
    11.8 +HYPERVISOR_boot_vcpu(
    11.9 +    unsigned long vcpu, vcpu_guest_context_t *ctxt)
   11.10 +{
   11.11 +    int ret;
   11.12 +    unsigned long ign1, ign2;
   11.13 +
   11.14 +    __asm__ __volatile__ (
   11.15 +        TRAP_INSTR
   11.16 +        : "=a" (ret), "=b" (ign1), "=c" (ign2)
   11.17 +	: "0" (__HYPERVISOR_boot_vcpu), "1" (vcpu), "2" (ctxt)
   11.18 +	: "memory");
   11.19 +
   11.20 +    return ret;
   11.21 +}
   11.22 +
   11.23  #endif /* __HYPERVISOR_H__ */

    12.1 --- a/freebsd-5.3-xen-sparse/i386-xen/include/pcpu.h	Tue May 03 14:42:00 2005 +0000
    12.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/include/pcpu.h	Tue May 10 08:49:59 2005 +0000
    12.3 @@ -53,7 +53,12 @@
    12.4          int     *pc_ipi_to_evtchn;                                      \
    12.5          int     *pc_virq_to_irq;                                        \
    12.6          u_int   pc_cr2;                                                 \
    12.7 -        u_int   pc_pdir                                        
    12.8 +        u_int   pc_pdir;                                                \
    12.9 +        u_int   pc_lazypmap;                                            \
   12.10 +        u_int   pc_rendezvous;                                          \
   12.11 +        u_int   pc_cpuast;                                              \
   12.12 +        u_int   pc_time_irq;                                              \
   12.13 +        uint64_t pc_processed_system_time;  
   12.14  
   12.15  #if defined(lint)
   12.16   

    13.1 --- a/freebsd-5.3-xen-sparse/i386-xen/include/pmap.h	Tue May 03 14:42:00 2005 +0000
    13.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/include/pmap.h	Tue May 10 08:49:59 2005 +0000
    13.3 @@ -343,6 +343,7 @@ void	pmap_set_pg(void);
    13.4  void	pmap_invalidate_page(pmap_t, vm_offset_t);
    13.5  void	pmap_invalidate_range(pmap_t, vm_offset_t, vm_offset_t);
    13.6  void	pmap_invalidate_all(pmap_t);
    13.7 +void    pmap_lazyfix_action(void);
    13.8  
    13.9  void pmap_map_readonly(pmap_t pmap, vm_offset_t va, int len);
   13.10  void pmap_map_readwrite(pmap_t pmap, vm_offset_t va, int len);

    14.1 --- a/freebsd-5.3-xen-sparse/i386-xen/include/xenfunc.h	Tue May 03 14:42:00 2005 +0000
    14.2 +++ b/freebsd-5.3-xen-sparse/i386-xen/include/xenfunc.h	Tue May 10 08:49:59 2005 +0000
    14.3 @@ -61,6 +61,9 @@ void load_cr3(uint32_t val);
    14.4  void xen_machphys_update(unsigned long, unsigned long);
    14.5  void xen_update_descriptor(union descriptor *, union descriptor *);
    14.6  void lldt(u_short sel);
    14.7 +void ap_cpu_initclocks(void);
    14.8 +
    14.9 +
   14.10  /*
   14.11   * Invalidate a patricular VA on all cpus
   14.12   *
   14.13 @@ -79,5 +82,6 @@ invltlb(void)
   14.14  	
   14.15  }
   14.16  
   14.17 +#define PANIC_IF(exp) if (unlikely(exp)) {printk("%s failed\n",#exp); panic("%s: %s:%d", #exp, __FILE__, __LINE__);} 
   14.18  
   14.19  #endif /* _XEN_XENFUNC_H_ */

    15.1 --- a/linux-2.4.29-xen-sparse/mkbuildtree	Tue May 03 14:42:00 2005 +0000
    15.2 +++ b/linux-2.4.29-xen-sparse/mkbuildtree	Tue May 10 08:49:59 2005 +0000
    15.3 @@ -66,7 +66,7 @@ relative_lndir ()
    15.4      (
    15.5      cd $i
    15.6      pref=`echo $i | sed -e 's#/[^/]*#../#g' -e 's#^\.##'`
    15.7 -    for j in `find . -type f -o -type l -maxdepth 1`; do
    15.8 +    for j in `find . -maxdepth 1 -type f -o -type l`; do
    15.9        ln -sf ${pref}${REAL_DIR}/$i/$j ${SYMLINK_DIR}/$i/$j
   15.10      done
   15.11      )
   15.12 @@ -232,7 +232,6 @@ ln -sf ../../../${LINUX_26}/arch/xen/ker
   15.13  ln -sf ../../../${LINUX_26}/arch/xen/kernel/gnttab.c
   15.14  ln -sf ../../../${LINUX_26}/arch/xen/kernel/reboot.c
   15.15  ln -sf ../../../${LINUX_26}/arch/xen/kernel/skbuff.c
   15.16 -ln -sf ../../../${LINUX_26}/arch/xen/i386/kernel/pci-dma.c
   15.17  
   15.18  cd ${AD}/arch/xen/lib
   15.19  ln -sf ../../i386/lib/checksum.S 

    16.1 --- a/linux-2.6.11-xen-sparse/arch/xen/Kconfig.drivers	Tue May 03 14:42:00 2005 +0000
    16.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/Kconfig.drivers	Tue May 10 08:49:59 2005 +0000
    16.3 @@ -49,9 +49,46 @@ source "drivers/infiniband/Kconfig"
    16.4  endif
    16.5  
    16.6  if !XEN_PHYSDEV_ACCESS
    16.7 +
    16.8 +menu "Character devices"
    16.9 +
   16.10  config UNIX98_PTYS
   16.11  	bool
   16.12  	default y
   16.13 +
   16.14 +config LEGACY_PTYS
   16.15 +	bool "Legacy (BSD) PTY support"
   16.16 +	default y
   16.17 +	---help---
   16.18 +	  A pseudo terminal (PTY) is a software device consisting of two
   16.19 +	  halves: a master and a slave. The slave device behaves identical to
   16.20 +	  a physical terminal; the master device is used by a process to
   16.21 +	  read data from and write data to the slave, thereby emulating a
   16.22 +	  terminal. Typical programs for the master side are telnet servers
   16.23 +	  and xterms.
   16.24 +
   16.25 +	  Linux has traditionally used the BSD-like names /dev/ptyxx
   16.26 +	  for masters and /dev/ttyxx for slaves of pseudo
   16.27 +	  terminals. This scheme has a number of problems, including
   16.28 +	  security.  This option enables these legacy devices; on most
   16.29 +	  systems, it is safe to say N.
   16.30 +
   16.31 +
   16.32 +config LEGACY_PTY_COUNT
   16.33 +	int "Maximum number of legacy PTY in use"
   16.34 +	depends on LEGACY_PTYS
   16.35 +	range 1 256
   16.36 +	default "256"
   16.37 +	---help---
   16.38 +	  The maximum number of legacy PTYs that can be used at any one time.
   16.39 +	  The default is 256, and should be more than enough.  Embedded
   16.40 +	  systems may want to reduce this to save memory.
   16.41 +
   16.42 +	  When not in use, each legacy PTY occupies 12 bytes on 32-bit
   16.43 +	  architectures and 24 bytes on 64-bit architectures.
   16.44 +
   16.45 +endmenu
   16.46 +
   16.47  endif
   16.48  
   16.49  endmenu

    17.1 --- a/linux-2.6.11-xen-sparse/arch/xen/configs/xen0_defconfig_x86_32	Tue May 03 14:42:00 2005 +0000
    17.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/configs/xen0_defconfig_x86_32	Tue May 10 08:49:59 2005 +0000
    17.3 @@ -1,7 +1,7 @@
    17.4  #
    17.5  # Automatically generated make config: don't edit
    17.6  # Linux kernel version: 2.6.11-xen0
    17.7 -# Tue May  3 13:25:48 2005
    17.8 +# Wed May  4 17:11:56 2005
    17.9  #
   17.10  CONFIG_XEN=y
   17.11  CONFIG_ARCH_XEN=y
   17.12 @@ -146,7 +146,7 @@ CONFIG_PCI=y
   17.13  # CONFIG_PCI_GOMMCONFIG is not set
   17.14  # CONFIG_PCI_GODIRECT is not set
   17.15  CONFIG_PCI_GOANY=y
   17.16 -CONFIG_PCI_BIOS=y
   17.17 +# CONFIG_PCI_BIOS is not set
   17.18  CONFIG_PCI_DIRECT=y
   17.19  # CONFIG_PCIEPORTBUS is not set
   17.20  # CONFIG_PCI_MSI is not set
   17.21 @@ -176,16 +176,22 @@ CONFIG_PCMCIA_PROBE=y
   17.22  # Kernel hacking
   17.23  #
   17.24  CONFIG_DEBUG_KERNEL=y
   17.25 +CONFIG_MAGIC_SYSRQ=y
   17.26 +# CONFIG_SCHEDSTATS is not set
   17.27 +# CONFIG_DEBUG_SLAB is not set
   17.28 +# CONFIG_DEBUG_PREEMPT is not set
   17.29 +# CONFIG_DEBUG_SPINLOCK is not set
   17.30 +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
   17.31 +# CONFIG_DEBUG_KOBJECT is not set
   17.32 +CONFIG_DEBUG_BUGVERBOSE=y
   17.33 +# CONFIG_DEBUG_INFO is not set
   17.34 +# CONFIG_DEBUG_FS is not set
   17.35 +# CONFIG_FRAME_POINTER is not set
   17.36  CONFIG_EARLY_PRINTK=y
   17.37  # CONFIG_DEBUG_STACKOVERFLOW is not set
   17.38 +# CONFIG_KPROBES is not set
   17.39  # CONFIG_DEBUG_STACK_USAGE is not set
   17.40 -# CONFIG_DEBUG_SLAB is not set
   17.41 -CONFIG_MAGIC_SYSRQ=y
   17.42 -# CONFIG_DEBUG_SPINLOCK is not set
   17.43  # CONFIG_DEBUG_PAGEALLOC is not set
   17.44 -# CONFIG_DEBUG_INFO is not set
   17.45 -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
   17.46 -# CONFIG_FRAME_POINTER is not set
   17.47  # CONFIG_4KSTACKS is not set
   17.48  CONFIG_X86_FIND_SMP_CONFIG=y
   17.49  CONFIG_X86_MPPARSE=y

    18.1 --- a/linux-2.6.11-xen-sparse/arch/xen/configs/xenU_defconfig_x86_32	Tue May 03 14:42:00 2005 +0000
    18.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/configs/xenU_defconfig_x86_32	Tue May 10 08:49:59 2005 +0000
    18.3 @@ -1,7 +1,7 @@
    18.4  #
    18.5  # Automatically generated make config: don't edit
    18.6  # Linux kernel version: 2.6.11-xenU
    18.7 -# Wed Apr  6 09:20:09 2005
    18.8 +# Wed May  4 17:14:10 2005
    18.9  #
   18.10  CONFIG_XEN=y
   18.11  CONFIG_ARCH_XEN=y
   18.12 @@ -132,16 +132,22 @@ CONFIG_HAVE_DEC_LOCK=y
   18.13  # Kernel hacking
   18.14  #
   18.15  CONFIG_DEBUG_KERNEL=y
   18.16 +CONFIG_MAGIC_SYSRQ=y
   18.17 +# CONFIG_SCHEDSTATS is not set
   18.18 +# CONFIG_DEBUG_SLAB is not set
   18.19 +# CONFIG_DEBUG_PREEMPT is not set
   18.20 +# CONFIG_DEBUG_SPINLOCK is not set
   18.21 +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
   18.22 +# CONFIG_DEBUG_KOBJECT is not set
   18.23 +CONFIG_DEBUG_BUGVERBOSE=y
   18.24 +# CONFIG_DEBUG_INFO is not set
   18.25 +# CONFIG_DEBUG_FS is not set
   18.26 +# CONFIG_FRAME_POINTER is not set
   18.27  CONFIG_EARLY_PRINTK=y
   18.28  # CONFIG_DEBUG_STACKOVERFLOW is not set
   18.29 +# CONFIG_KPROBES is not set
   18.30  # CONFIG_DEBUG_STACK_USAGE is not set
   18.31 -# CONFIG_DEBUG_SLAB is not set
   18.32 -CONFIG_MAGIC_SYSRQ=y
   18.33 -# CONFIG_DEBUG_SPINLOCK is not set
   18.34  # CONFIG_DEBUG_PAGEALLOC is not set
   18.35 -# CONFIG_DEBUG_INFO is not set
   18.36 -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
   18.37 -# CONFIG_FRAME_POINTER is not set
   18.38  # CONFIG_4KSTACKS is not set
   18.39  CONFIG_GENERIC_HARDIRQS=y
   18.40  CONFIG_GENERIC_IRQ_PROBE=y
   18.41 @@ -334,6 +340,12 @@ CONFIG_NETDEVICES=y
   18.42  # CONFIG_SHAPER is not set
   18.43  # CONFIG_NETCONSOLE is not set
   18.44  CONFIG_UNIX98_PTYS=y
   18.45 +CONFIG_LEGACY_PTYS=y
   18.46 +CONFIG_LEGACY_PTY_COUNT=256
   18.47 +
   18.48 +#
   18.49 +# Character devices
   18.50 +#
   18.51  
   18.52  #
   18.53  # File systems

    19.1 --- a/linux-2.6.11-xen-sparse/arch/xen/configs/xenU_defconfig_x86_64	Tue May 03 14:42:00 2005 +0000
    19.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/configs/xenU_defconfig_x86_64	Tue May 10 08:49:59 2005 +0000
    19.3 @@ -316,6 +316,12 @@ CONFIG_NETDEVICES=y
    19.4  # CONFIG_SHAPER is not set
    19.5  # CONFIG_NETCONSOLE is not set
    19.6  CONFIG_UNIX98_PTYS=y
    19.7 +CONFIG_LEGACY_PTYS=y
    19.8 +CONFIG_LEGACY_PTY_COUNT=256
    19.9 +
   19.10 +#
   19.11 +# Character devices
   19.12 +#
   19.13  
   19.14  #
   19.15  # File systems

    20.1 --- a/linux-2.6.11-xen-sparse/arch/xen/i386/Kconfig	Tue May 03 14:42:00 2005 +0000
    20.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/i386/Kconfig	Tue May 10 08:49:59 2005 +0000
    20.3 @@ -12,6 +12,11 @@ config XENARCH
    20.4  config X86
    20.5  	bool
    20.6  	default y
    20.7 +	help
    20.8 +	  This is Linux's home port.  Linux was originally native to the Intel
    20.9 +	  386, and runs on all the later x86 processors including the Intel
   20.10 +	  486, 586, Pentiums, and various instruction-set-compatible chips by
   20.11 +	  AMD, Cyrix, and others.
   20.12  
   20.13  config MMU
   20.14  	bool
   20.15 @@ -782,13 +787,19 @@ endchoice
   20.16  config PCI_BIOS
   20.17  	bool
   20.18  	depends on !X86_VISWS && PCI && (PCI_GOBIOS || PCI_GOANY)
   20.19 -	default n
   20.20 +	default y
   20.21  
   20.22  config PCI_DIRECT
   20.23  	bool
   20.24   	depends on PCI && ((PCI_GODIRECT || PCI_GOANY) || X86_VISWS)
   20.25  	default y
   20.26  
   20.27 +config PCI_MMCONFIG
   20.28 +	bool
   20.29 +	depends on PCI && (PCI_GOMMCONFIG || (PCI_GOANY && ACPI))
   20.30 +	select ACPI_BOOT
   20.31 +	default y
   20.32 +
   20.33  source "drivers/pci/pcie/Kconfig"
   20.34  
   20.35  source "drivers/pci/Kconfig"
   20.36 @@ -856,129 +867,7 @@ endmenu
   20.37  
   20.38  endif
   20.39  
   20.40 -menu "Kernel hacking"
   20.41 -
   20.42 -config DEBUG_KERNEL
   20.43 -	bool "Kernel debugging"
   20.44 -	help
   20.45 -	  Say Y here if you are developing drivers or trying to debug and
   20.46 -	  identify kernel problems.
   20.47 -
   20.48 -config EARLY_PRINTK
   20.49 -	bool "Early printk" if EMBEDDED
   20.50 -	default y
   20.51 -	help
   20.52 -	  Write kernel log output directly into the VGA buffer or to a serial
   20.53 -	  port.
   20.54 -
   20.55 -	  This is useful for kernel debugging when your machine crashes very
   20.56 -	  early before the console code is initialized. For normal operation
   20.57 -	  it is not recommended because it looks ugly and doesn't cooperate
   20.58 -	  with klogd/syslogd or the X server. You should normally N here,
   20.59 -	  unless you want to debug such a crash.
   20.60 -
   20.61 -config DEBUG_STACKOVERFLOW
   20.62 -	bool "Check for stack overflows"
   20.63 -	depends on DEBUG_KERNEL
   20.64 -
   20.65 -config DEBUG_STACK_USAGE
   20.66 -	bool "Stack utilization instrumentation"
   20.67 -	depends on DEBUG_KERNEL
   20.68 -	help
   20.69 -	  Enables the display of the minimum amount of free stack which each
   20.70 -	  task has ever had available in the sysrq-T and sysrq-P debug output.
   20.71 -
   20.72 -	  This option will slow down process creation somewhat.
   20.73 -
   20.74 -config DEBUG_SLAB
   20.75 -	bool "Debug memory allocations"
   20.76 -	depends on DEBUG_KERNEL
   20.77 -	help
   20.78 -	  Say Y here to have the kernel do limited verification on memory
   20.79 -	  allocation as well as poisoning memory on free to catch use of freed
   20.80 -	  memory.
   20.81 -
   20.82 -config MAGIC_SYSRQ
   20.83 -	bool "Magic SysRq key"
   20.84 -	depends on DEBUG_KERNEL
   20.85 -	help
   20.86 -	  If you say Y here, you will have some control over the system even
   20.87 -	  if the system crashes for example during kernel debugging (e.g., you
   20.88 -	  will be able to flush the buffer cache to disk, reboot the system
   20.89 -	  immediately or dump some status information). This is accomplished
   20.90 -	  by pressing various keys while holding SysRq (Alt+PrintScreen). It
   20.91 -	  also works on a serial console (on PC hardware at least), if you
   20.92 -	  send a BREAK and then within 5 seconds a command keypress. The
   20.93 -	  keys are documented in <file:Documentation/sysrq.txt>. Don't say Y
   20.94 -	  unless you really know what this hack does.
   20.95 -
   20.96 -config DEBUG_SPINLOCK
   20.97 -	bool "Spinlock debugging"
   20.98 -	depends on DEBUG_KERNEL
   20.99 -	help
  20.100 -	  Say Y here and build SMP to catch missing spinlock initialization
  20.101 -	  and certain other kinds of spinlock errors commonly made.  This is
  20.102 -	  best used in conjunction with the NMI watchdog so that spinlock
  20.103 -	  deadlocks are also debuggable.
  20.104 -
  20.105 -config DEBUG_PAGEALLOC
  20.106 -	bool "Page alloc debugging"
  20.107 -	depends on DEBUG_KERNEL
  20.108 -	help
  20.109 -	  Unmap pages from the kernel linear mapping after free_pages().
  20.110 -	  This results in a large slowdown, but helps to find certain types
  20.111 -	  of memory corruptions.
  20.112 -
  20.113 -config DEBUG_HIGHMEM
  20.114 -	bool "Highmem debugging"
  20.115 -	depends on DEBUG_KERNEL && HIGHMEM
  20.116 -	help
  20.117 -	  This options enables addition error checking for high memory systems.
  20.118 -	  Disable for production systems.
  20.119 -
  20.120 -config DEBUG_INFO
  20.121 -	bool "Compile the kernel with debug info"
  20.122 -	depends on DEBUG_KERNEL
  20.123 -	help
  20.124 -          If you say Y here the resulting kernel image will include
  20.125 -	  debugging info resulting in a larger kernel image.
  20.126 -	  Say Y here only if you plan to use gdb to debug the kernel.
  20.127 -	  If you don't debug the kernel, you can say N.
  20.128 -	  
  20.129 -config DEBUG_SPINLOCK_SLEEP
  20.130 -	bool "Sleep-inside-spinlock checking"
  20.131 -	help
  20.132 -	  If you say Y here, various routines which may sleep will become very
  20.133 -	  noisy if they are called with a spinlock held.	
  20.134 -
  20.135 -config FRAME_POINTER
  20.136 -	bool "Compile the kernel with frame pointers"
  20.137 -	help
  20.138 -	  If you say Y here the resulting kernel image will be slightly larger
  20.139 -	  and slower, but it will give very useful debugging information.
  20.140 -	  If you don't debug the kernel, you can say N, but we may not be able
  20.141 -	  to solve problems without frame pointers.
  20.142 -
  20.143 -config 4KSTACKS
  20.144 -	bool "Use 4Kb for kernel stacks instead of 8Kb"
  20.145 -	help
  20.146 -	  If you say Y here the kernel will use a 4Kb stacksize for the
  20.147 -	  kernel stack attached to each process/thread. This facilitates
  20.148 -	  running more threads on a system and also reduces the pressure
  20.149 -	  on the VM subsystem for higher order allocations. This option
  20.150 -	  will also use IRQ stacks to compensate for the reduced stackspace.
  20.151 -
  20.152 -config X86_FIND_SMP_CONFIG
  20.153 -	bool
  20.154 -	depends on X86_LOCAL_APIC || X86_VOYAGER
  20.155 -	default n
  20.156 -
  20.157 -config X86_MPPARSE
  20.158 -	bool
  20.159 -	depends on X86_LOCAL_APIC && !X86_VISWS
  20.160 -	default y
  20.161 -
  20.162 -endmenu
  20.163 +source "arch/i386/Kconfig.debug"
  20.164  
  20.165  #
  20.166  # Use the generic interrupt handling code in kernel/irq/:

    21.1 --- a/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/Makefile	Tue May 03 14:42:00 2005 +0000
    21.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/Makefile	Tue May 10 08:49:59 2005 +0000
    21.3 @@ -20,7 +20,7 @@ s-obj-y	:=
    21.4  
    21.5  obj-y				+= cpu/
    21.6  obj-y				+= timers/
    21.7 -c-obj-$(CONFIG_ACPI_BOOT)	+= acpi/
    21.8 +obj-$(CONFIG_ACPI_BOOT)		+= acpi/
    21.9  #c-obj-$(CONFIG_X86_BIOS_REBOOT)	+= reboot.o
   21.10  c-obj-$(CONFIG_MCA)		+= mca.o
   21.11  c-obj-$(CONFIG_X86_MSR)		+= msr.o
   21.12 @@ -29,10 +29,10 @@ obj-$(CONFIG_MICROCODE)		+= microcode.o
   21.13  c-obj-$(CONFIG_APM)		+= apm.o
   21.14  obj-$(CONFIG_X86_SMP)		+= smp.o smpboot.o
   21.15  #obj-$(CONFIG_X86_TRAMPOLINE)	+= trampoline.o
   21.16 -c-obj-$(CONFIG_X86_MPPARSE)	+= mpparse.o
   21.17 +obj-$(CONFIG_X86_MPPARSE)	+= mpparse.o
   21.18  obj-$(CONFIG_X86_LOCAL_APIC)	+= apic.o
   21.19  c-obj-$(CONFIG_X86_LOCAL_APIC)	+= nmi.o
   21.20 -c-obj-$(CONFIG_X86_IO_APIC)	+= io_apic.o
   21.21 +obj-$(CONFIG_X86_IO_APIC)	+= io_apic.o
   21.22  c-obj-$(CONFIG_X86_NUMAQ)	+= numaq.o
   21.23  c-obj-$(CONFIG_X86_SUMMIT_NUMA)	+= summit.o
   21.24  c-obj-$(CONFIG_MODULES)		+= module.o

    22.1 --- a/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/acpi/Makefile	Tue May 03 14:42:00 2005 +0000
    22.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/acpi/Makefile	Tue May 10 08:49:59 2005 +0000
    22.3 @@ -7,3 +7,7 @@ c-link                                  
    22.4  $(patsubst %.o,$(obj)/%.c,$(c-obj-y) $(c-link)):
    22.5  	@ln -fsn $(srctree)/arch/i386/kernel/acpi/$(notdir $@) $@
    22.6  
    22.7 +obj-y	+= $(c-obj-y) $(s-obj-y)
    22.8 +
    22.9 +clean-files += $(patsubst %.o,%.c,$(c-obj-y) $(c-obj-) $(c-link))
   22.10 +clean-files += $(patsubst %.o,%.S,$(s-obj-y) $(s-obj-) $(s-link))

    23.1 --- a/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/acpi/boot.c	Tue May 03 14:42:00 2005 +0000
    23.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/acpi/boot.c	Tue May 10 08:49:59 2005 +0000
    23.3 @@ -109,17 +109,17 @@ enum acpi_irq_model_id		acpi_irq_model =
    23.4  
    23.5  char *__acpi_map_table(unsigned long phys_addr, unsigned long size)
    23.6  {
    23.7 -        unsigned int i,j;
    23.8 +	unsigned int i,j;
    23.9  
   23.10 -        j = PAGE_ALIGN(size) >> PAGE_SHIFT;
   23.11 -        for (i = 0; (i < FIX_ACPI_PAGES) && j ; i++, j--) {
   23.12 -                __set_fixmap_ma(FIX_ACPI_END - i,
   23.13 -                                (phys_addr & PAGE_MASK) + (i << PAGE_SHIFT),
   23.14 -                                PAGE_KERNEL);
   23.15 -        }
   23.16 +	j = PAGE_ALIGN(size) >> PAGE_SHIFT;
   23.17 +	for (i = 0; (i < FIX_ACPI_PAGES) && j ; i++, j--) {
   23.18 +		set_fixmap(FIX_ACPI_END - i,
   23.19 +			   (phys_addr & PAGE_MASK) + (i << PAGE_SHIFT));
   23.20 +	}
   23.21  
   23.22 -        return (char *) __fix_to_virt(FIX_ACPI_END) + (phys_addr & ~PAGE_MASK);
   23.23 +	return (char *) __fix_to_virt(FIX_ACPI_END) + (phys_addr & ~PAGE_MASK);
   23.24  }
   23.25 +
   23.26  #else
   23.27  #ifdef	CONFIG_X86_64
   23.28  
   23.29 @@ -523,7 +523,7 @@ acpi_scan_rsdp (
   23.30  {
   23.31  	unsigned long		offset = 0;
   23.32  	unsigned long		sig_len = sizeof("RSD PTR ") - 1;
   23.33 -        unsigned long           vstart = isa_bus_to_virt(start);
   23.34 +	unsigned long		vstart = (unsigned long)isa_bus_to_virt(start);
   23.35  
   23.36  	/*
   23.37  	 * Scan all 16-byte boundaries of the physical memory region for the
   23.38 @@ -649,16 +649,15 @@ acpi_find_rsdp (void)
   23.39  		else if (efi.acpi)
   23.40  			return __pa(efi.acpi);
   23.41  	}
   23.42 -
   23.43  	/*
   23.44  	 * Scan memory looking for the RSDP signature. First search EBDA (low
   23.45  	 * memory) paragraphs and then search upper memory (E0000-FFFFF).
   23.46  	 */
   23.47  	rsdp_phys = acpi_scan_rsdp (0, 0x400);
   23.48  	if (!rsdp_phys)
   23.49 -		rsdp_phys = acpi_scan_rsdp (0xE0000, 0xFFFFF);
   23.50 +		rsdp_phys = acpi_scan_rsdp (0xE0000, 0x20000);
   23.51  
   23.52 -        __set_fixmap_ma(FIX_ACPI_RSDP_PAGE, rsdp_phys, PAGE_KERNEL);
   23.53 +	set_fixmap(FIX_ACPI_RSDP_PAGE, rsdp_phys);
   23.54  
   23.55  	return rsdp_phys;
   23.56  }
   23.57 @@ -673,10 +672,6 @@ acpi_parse_madt_lapic_entries(void)
   23.58  {
   23.59  	int count;
   23.60  
   23.61 -#ifdef CONFIG_XEN
   23.62 -        return 0;
   23.63 -#endif
   23.64 -
   23.65  	/* 
   23.66  	 * Note that the LAPIC address is obtained from the MADT (32-bit value)
   23.67  	 * and (optionally) overriden by a LAPIC_ADDR_OVR entry (64-bit value).
   23.68 @@ -872,7 +867,7 @@ acpi_boot_table_init(void)
   23.69  	}
   23.70  
   23.71  #ifdef __i386__
   23.72 -	//check_acpi_pci();
   23.73 +	check_acpi_pci();
   23.74  #endif
   23.75  
   23.76  	acpi_table_parse(ACPI_BOOT, acpi_parse_sbf);

    24.1 --- a/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/apic.c	Tue May 03 14:42:00 2005 +0000
    24.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/apic.c	Tue May 10 08:49:59 2005 +0000
    24.3 @@ -16,8 +16,32 @@
    24.4  
    24.5  #include <linux/config.h>
    24.6  #include <linux/init.h>
    24.7 -#include <asm/apic.h>
    24.8 +
    24.9 +#include <linux/mm.h>
   24.10 +#include <linux/irq.h>
   24.11 +#include <linux/delay.h>
   24.12 +#include <linux/bootmem.h>
   24.13 +#include <linux/smp_lock.h>
   24.14 +#include <linux/interrupt.h>
   24.15 +#include <linux/mc146818rtc.h>
   24.16 +#include <linux/kernel_stat.h>
   24.17 +#include <linux/sysdev.h>
   24.18  
   24.19 +#include <asm/atomic.h>
   24.20 +#include <asm/smp.h>
   24.21 +#include <asm/mtrr.h>
   24.22 +#include <asm/mpspec.h>
   24.23 +#include <asm/desc.h>
   24.24 +#include <asm/arch_hooks.h>
   24.25 +#include <asm/hpet.h>
   24.26 +
   24.27 +#include <mach_apic.h>
   24.28 +
   24.29 +#include "io_ports.h"
   24.30 +
   24.31 +/*
   24.32 + * Debug level
   24.33 + */
   24.34  int apic_verbosity;
   24.35  
   24.36  int get_physical_broadcast(void)
   24.37 @@ -49,5 +73,11 @@ void ack_bad_irq(unsigned int irq)
   24.38   */
   24.39  int __init APIC_init_uniprocessor (void)
   24.40  {
   24.41 +#ifdef CONFIG_X86_IO_APIC
   24.42 +	if (smp_found_config)
   24.43 +		if (!skip_ioapic_setup && nr_ioapics)
   24.44 +			setup_IO_APIC();
   24.45 +#endif
   24.46 +
   24.47  	return 0;
   24.48  }

    25.1 --- a/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/io_apic.c	Tue May 03 14:42:00 2005 +0000
    25.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/io_apic.c	Tue May 10 08:49:59 2005 +0000
    25.3 @@ -37,19 +37,56 @@
    25.4  #include <asm/smp.h>
    25.5  #include <asm/desc.h>
    25.6  #include <asm/timer.h>
    25.7 -#include <asm/io_apic.h>
    25.8 -#include <asm/apic.h>
    25.9  
   25.10  #include <mach_apic.h>
   25.11  
   25.12  #include "io_ports.h"
   25.13  
   25.14 +#ifdef CONFIG_XEN
   25.15 +
   25.16 +#include <asm-xen/xen-public/xen.h>
   25.17 +#include <asm-xen/xen-public/physdev.h>
   25.18 +
   25.19 +/* Fake i8259 */
   25.20 +#define make_8259A_irq(_irq)     (io_apic_irqs &= ~(1UL<<(_irq)))
   25.21 +#define disable_8259A_irq(_irq)  ((void)0)
   25.22 +#define i8259A_irq_pending(_irq) (0)
   25.23 +
   25.24 +unsigned long io_apic_irqs;
   25.25 +
   25.26 +static inline unsigned int xen_io_apic_read(unsigned int apic, unsigned int reg)
   25.27 +{
   25.28 +	physdev_op_t op;
   25.29 +	int ret;
   25.30 +
   25.31 +	op.cmd = PHYSDEVOP_APIC_READ;
   25.32 +	op.u.apic_op.apic = mp_ioapics[apic].mpc_apicid;
   25.33 +	op.u.apic_op.offset = reg;
   25.34 +	ret = HYPERVISOR_physdev_op(&op);
   25.35 +	if (ret)
   25.36 +		return ret;
   25.37 +	return op.u.apic_op.value;
   25.38 +}
   25.39 +
   25.40 +static inline void xen_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
   25.41 +{
   25.42 +	physdev_op_t op;
   25.43 +
   25.44 +	op.cmd = PHYSDEVOP_APIC_WRITE;
   25.45 +	op.u.apic_op.apic = mp_ioapics[apic].mpc_apicid;
   25.46 +	op.u.apic_op.offset = reg;
   25.47 +	op.u.apic_op.value = value;
   25.48 +	HYPERVISOR_physdev_op(&op);
   25.49 +}
   25.50 +
   25.51 +#define io_apic_read(a,r)    xen_io_apic_read(a,r)
   25.52 +#define io_apic_write(a,r,v) xen_io_apic_write(a,r,v)
   25.53 +
   25.54 +#endif /* CONFIG_XEN */
   25.55 +
   25.56  int (*ioapic_renumber_irq)(int ioapic, int irq);
   25.57  atomic_t irq_mis_count;
   25.58  
   25.59 -unsigned long io_apic_irqs;
   25.60 -int skip_ioapic_setup;
   25.61 -
   25.62  static DEFINE_SPINLOCK(ioapic_lock);
   25.63  
   25.64  /*
   25.65 @@ -89,24 +126,6 @@ int vector_irq[NR_VECTORS] = { [0 ... NR
   25.66  #define vector_to_irq(vector)	(vector)
   25.67  #endif
   25.68  
   25.69 -
   25.70 -#ifndef CONFIG_SMP
   25.71 -void fastcall send_IPI_self(int vector)
   25.72 -{
   25.73 -     return; 
   25.74 -}
   25.75 -#endif
   25.76 -
   25.77 -int irqbalance_disable(char *str)
   25.78 -{
   25.79 -     return 0; 
   25.80 -}
   25.81 -
   25.82 -void print_IO_APIC(void)
   25.83 -{
   25.84 -     return; 
   25.85 -}
   25.86 -
   25.87  /*
   25.88   * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
   25.89   * shared ISA-space IRQs, so we have to support them. We are super
   25.90 @@ -130,6 +149,583 @@ static void add_pin_to_irq(unsigned int 
   25.91  	entry->pin = pin;
   25.92  }
   25.93  
   25.94 +#ifndef CONFIG_XEN
   25.95 +/*
   25.96 + * Reroute an IRQ to a different pin.
   25.97 + */
   25.98 +static void __init replace_pin_at_irq(unsigned int irq,
   25.99 +				      int oldapic, int oldpin,
  25.100 +				      int newapic, int newpin)
  25.101 +{
  25.102 +	struct irq_pin_list *entry = irq_2_pin + irq;
  25.103 +
  25.104 +	while (1) {
  25.105 +		if (entry->apic == oldapic && entry->pin == oldpin) {
  25.106 +			entry->apic = newapic;
  25.107 +			entry->pin = newpin;
  25.108 +		}
  25.109 +		if (!entry->next)
  25.110 +			break;
  25.111 +		entry = irq_2_pin + entry->next;
  25.112 +	}
  25.113 +}
  25.114 +
  25.115 +static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
  25.116 +{
  25.117 +	struct irq_pin_list *entry = irq_2_pin + irq;
  25.118 +	unsigned int pin, reg;
  25.119 +
  25.120 +	for (;;) {
  25.121 +		pin = entry->pin;
  25.122 +		if (pin == -1)
  25.123 +			break;
  25.124 +		reg = io_apic_read(entry->apic, 0x10 + pin*2);
  25.125 +		reg &= ~disable;
  25.126 +		reg |= enable;
  25.127 +		io_apic_modify(entry->apic, 0x10 + pin*2, reg);
  25.128 +		if (!entry->next)
  25.129 +			break;
  25.130 +		entry = irq_2_pin + entry->next;
  25.131 +	}
  25.132 +}
  25.133 +
  25.134 +/* mask = 1 */
  25.135 +static void __mask_IO_APIC_irq (unsigned int irq)
  25.136 +{
  25.137 +	__modify_IO_APIC_irq(irq, 0x00010000, 0);
  25.138 +}
  25.139 +
  25.140 +/* mask = 0 */
  25.141 +static void __unmask_IO_APIC_irq (unsigned int irq)
  25.142 +{
  25.143 +	__modify_IO_APIC_irq(irq, 0, 0x00010000);
  25.144 +}
  25.145 +
  25.146 +/* mask = 1, trigger = 0 */
  25.147 +static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
  25.148 +{
  25.149 +	__modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
  25.150 +}
  25.151 +
  25.152 +/* mask = 0, trigger = 1 */
  25.153 +static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
  25.154 +{
  25.155 +	__modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
  25.156 +}
  25.157 +
  25.158 +static void mask_IO_APIC_irq (unsigned int irq)
  25.159 +{
  25.160 +	unsigned long flags;
  25.161 +
  25.162 +	spin_lock_irqsave(&ioapic_lock, flags);
  25.163 +	__mask_IO_APIC_irq(irq);
  25.164 +	spin_unlock_irqrestore(&ioapic_lock, flags);
  25.165 +}
  25.166 +
  25.167 +static void unmask_IO_APIC_irq (unsigned int irq)
  25.168 +{
  25.169 +	unsigned long flags;
  25.170 +
  25.171 +	spin_lock_irqsave(&ioapic_lock, flags);
  25.172 +	__unmask_IO_APIC_irq(irq);
  25.173 +	spin_unlock_irqrestore(&ioapic_lock, flags);
  25.174 +}
  25.175 +
  25.176 +void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
  25.177 +{
  25.178 +	struct IO_APIC_route_entry entry;
  25.179 +	unsigned long flags;
  25.180 +	
  25.181 +	/* Check delivery_mode to be sure we're not clearing an SMI pin */
  25.182 +	spin_lock_irqsave(&ioapic_lock, flags);
  25.183 +	*(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
  25.184 +	*(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
  25.185 +	spin_unlock_irqrestore(&ioapic_lock, flags);
  25.186 +	if (entry.delivery_mode == dest_SMI)
  25.187 +		return;
  25.188 +
  25.189 +	/*
  25.190 +	 * Disable it in the IO-APIC irq-routing table:
  25.191 +	 */
  25.192 +	memset(&entry, 0, sizeof(entry));
  25.193 +	entry.mask = 1;
  25.194 +	spin_lock_irqsave(&ioapic_lock, flags);
  25.195 +	io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
  25.196 +	io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
  25.197 +	spin_unlock_irqrestore(&ioapic_lock, flags);
  25.198 +}
  25.199 +
  25.200 +static void clear_IO_APIC (void)
  25.201 +{
  25.202 +	int apic, pin;
  25.203 +
  25.204 +	for (apic = 0; apic < nr_ioapics; apic++)
  25.205 +		for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
  25.206 +			clear_IO_APIC_pin(apic, pin);
  25.207 +}
  25.208 +
  25.209 +static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
  25.210 +{
  25.211 +	unsigned long flags;
  25.212 +	int pin;
  25.213 +	struct irq_pin_list *entry = irq_2_pin + irq;
  25.214 +	unsigned int apicid_value;
  25.215 +	
  25.216 +	apicid_value = cpu_mask_to_apicid(cpumask);
  25.217 +	/* Prepare to do the io_apic_write */
  25.218 +	apicid_value = apicid_value << 24;
  25.219 +	spin_lock_irqsave(&ioapic_lock, flags);
  25.220 +	for (;;) {
  25.221 +		pin = entry->pin;
  25.222 +		if (pin == -1)
  25.223 +			break;
  25.224 +		io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
  25.225 +		if (!entry->next)
  25.226 +			break;
  25.227 +		entry = irq_2_pin + entry->next;
  25.228 +	}
  25.229 +	spin_unlock_irqrestore(&ioapic_lock, flags);
  25.230 +}
  25.231 +#else
  25.232 +#define clear_IO_APIC() ((void)0)
  25.233 +#endif
  25.234 +
  25.235 +#if defined(CONFIG_IRQBALANCE)
  25.236 +# include <asm/processor.h>	/* kernel_thread() */
  25.237 +# include <linux/kernel_stat.h>	/* kstat */
  25.238 +# include <linux/slab.h>		/* kmalloc() */
  25.239 +# include <linux/timer.h>	/* time_after() */
  25.240 + 
  25.241 +# ifdef CONFIG_BALANCED_IRQ_DEBUG
  25.242 +#  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
  25.243 +#  define Dprintk(x...) do { TDprintk(x); } while (0)
  25.244 +# else
  25.245 +#  define TDprintk(x...) 
  25.246 +#  define Dprintk(x...) 
  25.247 +# endif
  25.248 +
  25.249 +cpumask_t __cacheline_aligned pending_irq_balance_cpumask[NR_IRQS];
  25.250 +
  25.251 +#define IRQBALANCE_CHECK_ARCH -999
  25.252 +static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
  25.253 +static int physical_balance = 0;
  25.254 +
  25.255 +struct irq_cpu_info {
  25.256 +	unsigned long * last_irq;
  25.257 +	unsigned long * irq_delta;
  25.258 +	unsigned long irq;
  25.259 +} irq_cpu_data[NR_CPUS];
  25.260 +
  25.261 +#define CPU_IRQ(cpu)		(irq_cpu_data[cpu].irq)
  25.262 +#define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
  25.263 +#define IRQ_DELTA(cpu,irq) 	(irq_cpu_data[cpu].irq_delta[irq])
  25.264 +
  25.265 +#define IDLE_ENOUGH(cpu,now) \
  25.266 +		(idle_cpu(cpu) && ((now) - irq_stat[(cpu)].idle_timestamp > 1))
  25.267 +
  25.268 +#define IRQ_ALLOWED(cpu, allowed_mask)	cpu_isset(cpu, allowed_mask)
  25.269 +
  25.270 +#define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
  25.271 +
  25.272 +#define MAX_BALANCED_IRQ_INTERVAL	(5*HZ)
  25.273 +#define MIN_BALANCED_IRQ_INTERVAL	(HZ/2)
  25.274 +#define BALANCED_IRQ_MORE_DELTA		(HZ/10)
  25.275 +#define BALANCED_IRQ_LESS_DELTA		(HZ)
  25.276 +
  25.277 +long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
  25.278 +
  25.279 +static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
  25.280 +			unsigned long now, int direction)
  25.281 +{
  25.282 +	int search_idle = 1;
  25.283 +	int cpu = curr_cpu;
  25.284 +
  25.285 +	goto inside;
  25.286 +
  25.287 +	do {
  25.288 +		if (unlikely(cpu == curr_cpu))
  25.289 +			search_idle = 0;
  25.290 +inside:
  25.291 +		if (direction == 1) {
  25.292 +			cpu++;
  25.293 +			if (cpu >= NR_CPUS)
  25.294 +				cpu = 0;
  25.295 +		} else {
  25.296 +			cpu--;
  25.297 +			if (cpu == -1)
  25.298 +				cpu = NR_CPUS-1;
  25.299 +		}
  25.300 +	} while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
  25.301 +			(search_idle && !IDLE_ENOUGH(cpu,now)));
  25.302 +
  25.303 +	return cpu;
  25.304 +}
  25.305 +
  25.306 +static inline void balance_irq(int cpu, int irq)
  25.307 +{
  25.308 +	unsigned long now = jiffies;
  25.309 +	cpumask_t allowed_mask;
  25.310 +	unsigned int new_cpu;
  25.311 +		
  25.312 +	if (irqbalance_disabled)
  25.313 +		return; 
  25.314 +
  25.315 +	cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
  25.316 +	new_cpu = move(cpu, allowed_mask, now, 1);
  25.317 +	if (cpu != new_cpu) {
  25.318 +		irq_desc_t *desc = irq_desc + irq;
  25.319 +		unsigned long flags;
  25.320 +
  25.321 +		spin_lock_irqsave(&desc->lock, flags);
  25.322 +		pending_irq_balance_cpumask[irq] = cpumask_of_cpu(new_cpu);
  25.323 +		spin_unlock_irqrestore(&desc->lock, flags);
  25.324 +	}
  25.325 +}
  25.326 +
  25.327 +static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
  25.328 +{
  25.329 +	int i, j;
  25.330 +	Dprintk("Rotating IRQs among CPUs.\n");
  25.331 +	for (i = 0; i < NR_CPUS; i++) {
  25.332 +		for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
  25.333 +			if (!irq_desc[j].action)
  25.334 +				continue;
  25.335 +			/* Is it a significant load ?  */
  25.336 +			if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
  25.337 +						useful_load_threshold)
  25.338 +				continue;
  25.339 +			balance_irq(i, j);
  25.340 +		}
  25.341 +	}
  25.342 +	balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
  25.343 +		balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);	
  25.344 +	return;
  25.345 +}
  25.346 +
  25.347 +static void do_irq_balance(void)
  25.348 +{
  25.349 +	int i, j;
  25.350 +	unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
  25.351 +	unsigned long move_this_load = 0;
  25.352 +	int max_loaded = 0, min_loaded = 0;
  25.353 +	int load;
  25.354 +	unsigned long useful_load_threshold = balanced_irq_interval + 10;
  25.355 +	int selected_irq;
  25.356 +	int tmp_loaded, first_attempt = 1;
  25.357 +	unsigned long tmp_cpu_irq;
  25.358 +	unsigned long imbalance = 0;
  25.359 +	cpumask_t allowed_mask, target_cpu_mask, tmp;
  25.360 +
  25.361 +	for (i = 0; i < NR_CPUS; i++) {
  25.362 +		int package_index;
  25.363 +		CPU_IRQ(i) = 0;
  25.364 +		if (!cpu_online(i))
  25.365 +			continue;
  25.366 +		package_index = CPU_TO_PACKAGEINDEX(i);
  25.367 +		for (j = 0; j < NR_IRQS; j++) {
  25.368 +			unsigned long value_now, delta;
  25.369 +			/* Is this an active IRQ? */
  25.370 +			if (!irq_desc[j].action)
  25.371 +				continue;
  25.372 +			if ( package_index == i )
  25.373 +				IRQ_DELTA(package_index,j) = 0;
  25.374 +			/* Determine the total count per processor per IRQ */
  25.375 +			value_now = (unsigned long) kstat_cpu(i).irqs[j];
  25.376 +
  25.377 +			/* Determine the activity per processor per IRQ */
  25.378 +			delta = value_now - LAST_CPU_IRQ(i,j);
  25.379 +
  25.380 +			/* Update last_cpu_irq[][] for the next time */
  25.381 +			LAST_CPU_IRQ(i,j) = value_now;
  25.382 +
  25.383 +			/* Ignore IRQs whose rate is less than the clock */
  25.384 +			if (delta < useful_load_threshold)
  25.385 +				continue;
  25.386 +			/* update the load for the processor or package total */
  25.387 +			IRQ_DELTA(package_index,j) += delta;
  25.388 +
  25.389 +			/* Keep track of the higher numbered sibling as well */
  25.390 +			if (i != package_index)
  25.391 +				CPU_IRQ(i) += delta;
  25.392 +			/*
  25.393 +			 * We have sibling A and sibling B in the package
  25.394 +			 *
  25.395 +			 * cpu_irq[A] = load for cpu A + load for cpu B
  25.396 +			 * cpu_irq[B] = load for cpu B
  25.397 +			 */
  25.398 +			CPU_IRQ(package_index) += delta;
  25.399 +		}
  25.400 +	}
  25.401 +	/* Find the least loaded processor package */
  25.402 +	for (i = 0; i < NR_CPUS; i++) {
  25.403 +		if (!cpu_online(i))
  25.404 +			continue;
  25.405 +		if (i != CPU_TO_PACKAGEINDEX(i))
  25.406 +			continue;
  25.407 +		if (min_cpu_irq > CPU_IRQ(i)) {
  25.408 +			min_cpu_irq = CPU_IRQ(i);
  25.409 +			min_loaded = i;
  25.410 +		}
  25.411 +	}
  25.412 +	max_cpu_irq = ULONG_MAX;
  25.413 +
  25.414 +tryanothercpu:
  25.415 +	/* Look for heaviest loaded processor.
  25.416 +	 * We may come back to get the next heaviest loaded processor.
  25.417 +	 * Skip processors with trivial loads.
  25.418 +	 */
  25.419 +	tmp_cpu_irq = 0;
  25.420 +	tmp_loaded = -1;
  25.421 +	for (i = 0; i < NR_CPUS; i++) {
  25.422 +		if (!cpu_online(i))
  25.423 +			continue;
  25.424 +		if (i != CPU_TO_PACKAGEINDEX(i))
  25.425 +			continue;
  25.426 +		if (max_cpu_irq <= CPU_IRQ(i)) 
  25.427 +			continue;
  25.428 +		if (tmp_cpu_irq < CPU_IRQ(i)) {
  25.429 +			tmp_cpu_irq = CPU_IRQ(i);
  25.430 +			tmp_loaded = i;
  25.431 +		}
  25.432 +	}
  25.433 +
  25.434 +	if (tmp_loaded == -1) {
  25.435 + 	 /* In the case of small number of heavy interrupt sources, 
  25.436 +	  * loading some of the cpus too much. We use Ingo's original 
  25.437 +	  * approach to rotate them around.
  25.438 +	  */
  25.439 +		if (!first_attempt && imbalance >= useful_load_threshold) {
  25.440 +			rotate_irqs_among_cpus(useful_load_threshold);
  25.441 +			return;
  25.442 +		}
  25.443 +		goto not_worth_the_effort;
  25.444 +	}
  25.445 +	
  25.446 +	first_attempt = 0;		/* heaviest search */
  25.447 +	max_cpu_irq = tmp_cpu_irq;	/* load */
  25.448 +	max_loaded = tmp_loaded;	/* processor */
  25.449 +	imbalance = (max_cpu_irq - min_cpu_irq) / 2;
  25.450 +	
  25.451 +	Dprintk("max_loaded cpu = %d\n", max_loaded);
  25.452 +	Dprintk("min_loaded cpu = %d\n", min_loaded);
  25.453 +	Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
  25.454 +	Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
  25.455 +	Dprintk("load imbalance = %lu\n", imbalance);
  25.456 +
  25.457 +	/* if imbalance is less than approx 10% of max load, then
  25.458 +	 * observe diminishing returns action. - quit
  25.459 +	 */
  25.460 +	if (imbalance < (max_cpu_irq >> 3)) {
  25.461 +		Dprintk("Imbalance too trivial\n");
  25.462 +		goto not_worth_the_effort;
  25.463 +	}
  25.464 +
  25.465 +tryanotherirq:
  25.466 +	/* if we select an IRQ to move that can't go where we want, then
  25.467 +	 * see if there is another one to try.
  25.468 +	 */
  25.469 +	move_this_load = 0;
  25.470 +	selected_irq = -1;
  25.471 +	for (j = 0; j < NR_IRQS; j++) {
  25.472 +		/* Is this an active IRQ? */
  25.473 +		if (!irq_desc[j].action)
  25.474 +			continue;
  25.475 +		if (imbalance <= IRQ_DELTA(max_loaded,j))
  25.476 +			continue;
  25.477 +		/* Try to find the IRQ that is closest to the imbalance
  25.478 +		 * without going over.
  25.479 +		 */
  25.480 +		if (move_this_load < IRQ_DELTA(max_loaded,j)) {
  25.481 +			move_this_load = IRQ_DELTA(max_loaded,j);
  25.482 +			selected_irq = j;
  25.483 +		}
  25.484 +	}
  25.485 +	if (selected_irq == -1) {
  25.486 +		goto tryanothercpu;
  25.487 +	}
  25.488 +
  25.489 +	imbalance = move_this_load;
  25.490 +	
  25.491 +	/* For physical_balance case, we accumlated both load
  25.492 +	 * values in the one of the siblings cpu_irq[],
  25.493 +	 * to use the same code for physical and logical processors
  25.494 +	 * as much as possible. 
  25.495 +	 *
  25.496 +	 * NOTE: the cpu_irq[] array holds the sum of the load for
  25.497 +	 * sibling A and sibling B in the slot for the lowest numbered
  25.498 +	 * sibling (A), _AND_ the load for sibling B in the slot for
  25.499 +	 * the higher numbered sibling.
  25.500 +	 *
  25.501 +	 * We seek the least loaded sibling by making the comparison
  25.502 +	 * (A+B)/2 vs B
  25.503 +	 */
  25.504 +	load = CPU_IRQ(min_loaded) >> 1;
  25.505 +	for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
  25.506 +		if (load > CPU_IRQ(j)) {
  25.507 +			/* This won't change cpu_sibling_map[min_loaded] */
  25.508 +			load = CPU_IRQ(j);
  25.509 +			min_loaded = j;
  25.510 +		}
  25.511 +	}
  25.512 +
  25.513 +	cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
  25.514 +	target_cpu_mask = cpumask_of_cpu(min_loaded);
  25.515 +	cpus_and(tmp, target_cpu_mask, allowed_mask);
  25.516 +
  25.517 +	if (!cpus_empty(tmp)) {
  25.518 +		irq_desc_t *desc = irq_desc + selected_irq;
  25.519 +		unsigned long flags;
  25.520 +
  25.521 +		Dprintk("irq = %d moved to cpu = %d\n",
  25.522 +				selected_irq, min_loaded);
  25.523 +		/* mark for change destination */
  25.524 +		spin_lock_irqsave(&desc->lock, flags);
  25.525 +		pending_irq_balance_cpumask[selected_irq] =
  25.526 +					cpumask_of_cpu(min_loaded);
  25.527 +		spin_unlock_irqrestore(&desc->lock, flags);
  25.528 +		/* Since we made a change, come back sooner to 
  25.529 +		 * check for more variation.
  25.530 +		 */
  25.531 +		balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
  25.532 +			balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);	
  25.533 +		return;
  25.534 +	}
  25.535 +	goto tryanotherirq;
  25.536 +
  25.537 +not_worth_the_effort:
  25.538 +	/*
  25.539 +	 * if we did not find an IRQ to move, then adjust the time interval
  25.540 +	 * upward
  25.541 +	 */
  25.542 +	balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
  25.543 +		balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);	
  25.544 +	Dprintk("IRQ worth rotating not found\n");
  25.545 +	return;
  25.546 +}
  25.547 +
  25.548 +static int balanced_irq(void *unused)
  25.549 +{
  25.550 +	int i;
  25.551 +	unsigned long prev_balance_time = jiffies;
  25.552 +	long time_remaining = balanced_irq_interval;
  25.553 +
  25.554 +	daemonize("kirqd");
  25.555 +	
  25.556 +	/* push everything to CPU 0 to give us a starting point.  */
  25.557 +	for (i = 0 ; i < NR_IRQS ; i++) {
  25.558 +		pending_irq_balance_cpumask[i] = cpumask_of_cpu(0);
  25.559 +	}
  25.560 +
  25.561 +	for ( ; ; ) {
  25.562 +		set_current_state(TASK_INTERRUPTIBLE);
  25.563 +		time_remaining = schedule_timeout(time_remaining);
  25.564 +		try_to_freeze(PF_FREEZE);
  25.565 +		if (time_after(jiffies,
  25.566 +				prev_balance_time+balanced_irq_interval)) {
  25.567 +			do_irq_balance();
  25.568 +			prev_balance_time = jiffies;
  25.569 +			time_remaining = balanced_irq_interval;
  25.570 +		}
  25.571 +	}
  25.572 +	return 0;
  25.573 +}
  25.574 +
  25.575 +static int __init balanced_irq_init(void)
  25.576 +{
  25.577 +	int i;
  25.578 +	struct cpuinfo_x86 *c;
  25.579 +	cpumask_t tmp;
  25.580 +
  25.581 +	cpus_shift_right(tmp, cpu_online_map, 2);
  25.582 +        c = &boot_cpu_data;
  25.583 +	/* When not overwritten by the command line ask subarchitecture. */
  25.584 +	if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
  25.585 +		irqbalance_disabled = NO_BALANCE_IRQ;
  25.586 +	if (irqbalance_disabled)
  25.587 +		return 0;
  25.588 +	
  25.589 +	 /* disable irqbalance completely if there is only one processor online */
  25.590 +	if (num_online_cpus() < 2) {
  25.591 +		irqbalance_disabled = 1;
  25.592 +		return 0;
  25.593 +	}
  25.594 +	/*
  25.595 +	 * Enable physical balance only if more than 1 physical processor
  25.596 +	 * is present
  25.597 +	 */
  25.598 +	if (smp_num_siblings > 1 && !cpus_empty(tmp))
  25.599 +		physical_balance = 1;
  25.600 +
  25.601 +	for (i = 0; i < NR_CPUS; i++) {
  25.602 +		if (!cpu_online(i))
  25.603 +			continue;
  25.604 +		irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
  25.605 +		irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
  25.606 +		if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
  25.607 +			printk(KERN_ERR "balanced_irq_init: out of memory");
  25.608 +			goto failed;
  25.609 +		}
  25.610 +		memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
  25.611 +		memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
  25.612 +	}
  25.613 +	
  25.614 +	printk(KERN_INFO "Starting balanced_irq\n");
  25.615 +	if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0) 
  25.616 +		return 0;
  25.617 +	else 
  25.618 +		printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
  25.619 +failed:
  25.620 +	for (i = 0; i < NR_CPUS; i++) {
  25.621 +		if(irq_cpu_data[i].irq_delta)
  25.622 +			kfree(irq_cpu_data[i].irq_delta);
  25.623 +		if(irq_cpu_data[i].last_irq)
  25.624 +			kfree(irq_cpu_data[i].last_irq);
  25.625 +	}
  25.626 +	return 0;
  25.627 +}
  25.628 +
  25.629 +int __init irqbalance_disable(char *str)
  25.630 +{
  25.631 +	irqbalance_disabled = 1;
  25.632 +	return 0;
  25.633 +}
  25.634 +
  25.635 +__setup("noirqbalance", irqbalance_disable);
  25.636 +
  25.637 +static inline void move_irq(int irq)
  25.638 +{
  25.639 +	/* note - we hold the desc->lock */
  25.640 +	if (unlikely(!cpus_empty(pending_irq_balance_cpumask[irq]))) {
  25.641 +		set_ioapic_affinity_irq(irq, pending_irq_balance_cpumask[irq]);
  25.642 +		cpus_clear(pending_irq_balance_cpumask[irq]);
  25.643 +	}
  25.644 +}
  25.645 +
  25.646 +late_initcall(balanced_irq_init);
  25.647 +
  25.648 +#else /* !CONFIG_IRQBALANCE */
  25.649 +static inline void move_irq(int irq) { }
  25.650 +#endif /* CONFIG_IRQBALANCE */
  25.651 +
  25.652 +#ifndef CONFIG_SMP
  25.653 +void fastcall send_IPI_self(int vector)
  25.654 +{
  25.655 +#ifndef CONFIG_XEN
  25.656 +	unsigned int cfg;
  25.657 +
  25.658 +	/*
  25.659 +	 * Wait for idle.
  25.660 +	 */
  25.661 +	apic_wait_icr_idle();
  25.662 +	cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
  25.663 +	/*
  25.664 +	 * Send the IPI. The write to APIC_ICR fires this off.
  25.665 +	 */
  25.666 +	apic_write_around(APIC_ICR, cfg);
  25.667 +#endif
  25.668 +}
  25.669 +#endif /* !CONFIG_SMP */
  25.670 +
  25.671  /*
  25.672   * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
  25.673   * specific CPU-side IRQs.
  25.674 @@ -138,6 +734,88 @@ static void add_pin_to_irq(unsigned int 
  25.675  #define MAX_PIRQS 8
  25.676  int pirq_entries [MAX_PIRQS];
  25.677  int pirqs_enabled;
  25.678 +int skip_ioapic_setup;
  25.679 +
  25.680 +static int __init ioapic_setup(char *str)
  25.681 +{
  25.682 +	skip_ioapic_setup = 1;
  25.683 +	return 1;
  25.684 +}
  25.685 +
  25.686 +__setup("noapic", ioapic_setup);
  25.687 +
  25.688 +static int __init ioapic_pirq_setup(char *str)
  25.689 +{
  25.690 +	int i, max;
  25.691 +	int ints[MAX_PIRQS+1];
  25.692 +
  25.693 +	get_options(str, ARRAY_SIZE(ints), ints);
  25.694 +
  25.695 +	for (i = 0; i < MAX_PIRQS; i++)
  25.696 +		pirq_entries[i] = -1;
  25.697 +
  25.698 +	pirqs_enabled = 1;
  25.699 +	apic_printk(APIC_VERBOSE, KERN_INFO
  25.700 +			"PIRQ redirection, working around broken MP-BIOS.\n");
  25.701 +	max = MAX_PIRQS;
  25.702 +	if (ints[0] < MAX_PIRQS)
  25.703 +		max = ints[0];
  25.704 +
  25.705 +	for (i = 0; i < max; i++) {
  25.706 +		apic_printk(APIC_VERBOSE, KERN_DEBUG
  25.707 +				"... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
  25.708 +		/*
  25.709 +		 * PIRQs are mapped upside down, usually.
  25.710 +		 */
  25.711 +		pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
  25.712 +	}
  25.713 +	return 1;
  25.714 +}
  25.715 +
  25.716 +__setup("pirq=", ioapic_pirq_setup);
  25.717 +
  25.718 +/*
  25.719 + * Find the IRQ entry number of a certain pin.
  25.720 + */
  25.721 +static int find_irq_entry(int apic, int pin, int type)
  25.722 +{
  25.723 +	int i;
  25.724 +
  25.725 +	for (i = 0; i < mp_irq_entries; i++)
  25.726 +		if (mp_irqs[i].mpc_irqtype == type &&
  25.727 +		    (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
  25.728 +		     mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
  25.729 +		    mp_irqs[i].mpc_dstirq == pin)
  25.730 +			return i;
  25.731 +
  25.732 +	return -1;
  25.733 +}
  25.734 +
  25.735 +#ifndef CONFIG_XEN
  25.736 +/*
  25.737 + * Find the pin to which IRQ[irq] (ISA) is connected
  25.738 + */
  25.739 +static int find_isa_irq_pin(int irq, int type)
  25.740 +{
  25.741 +	int i;
  25.742 +
  25.743 +	for (i = 0; i < mp_irq_entries; i++) {
  25.744 +		int lbus = mp_irqs[i].mpc_srcbus;
  25.745 +
  25.746 +		if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
  25.747 +		     mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
  25.748 +		     mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
  25.749 +		     mp_bus_id_to_type[lbus] == MP_BUS_NEC98
  25.750 +		    ) &&
  25.751 +		    (mp_irqs[i].mpc_irqtype == type) &&
  25.752 +		    (mp_irqs[i].mpc_srcbusirq == irq))
  25.753 +
  25.754 +			return mp_irqs[i].mpc_dstirq;
  25.755 +	}
  25.756 +	return -1;
  25.757 +}
  25.758 +#endif
  25.759 +
  25.760  /*
  25.761   * Find a specific PCI IRQ entry.
  25.762   * Not an __init, possibly needed by modules
  25.763 @@ -184,6 +862,236 @@ int IO_APIC_get_PCI_irq_vector(int bus, 
  25.764  	return best_guess;
  25.765  }
  25.766  
  25.767 +#ifndef CONFIG_XEN
  25.768 +/*
  25.769 + * This function currently is only a helper for the i386 smp boot process where 
  25.770 + * we need to reprogram the ioredtbls to cater for the cpus which have come online
  25.771 + * so mask in all cases should simply be TARGET_CPUS
  25.772 + */
  25.773 +void __init setup_ioapic_dest(void)
  25.774 +{
  25.775 +	int pin, ioapic, irq, irq_entry;
  25.776 +
  25.777 +	if (skip_ioapic_setup == 1)
  25.778 +		return;
  25.779 +
  25.780 +	for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
  25.781 +		for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
  25.782 +			irq_entry = find_irq_entry(ioapic, pin, mp_INT);
  25.783 +			if (irq_entry == -1)
  25.784 +				continue;
  25.785 +			irq = pin_2_irq(irq_entry, ioapic, pin);
  25.786 +			set_ioapic_affinity_irq(irq, TARGET_CPUS);
  25.787 +		}
  25.788 +
  25.789 +	}
  25.790 +}
  25.791 +#endif /* !CONFIG_XEN */
  25.792 +
  25.793 +/*
  25.794 + * EISA Edge/Level control register, ELCR
  25.795 + */
  25.796 +static int EISA_ELCR(unsigned int irq)
  25.797 +{
  25.798 +	if (irq < 16) {
  25.799 +		unsigned int port = 0x4d0 + (irq >> 3);
  25.800 +		return (inb(port) >> (irq & 7)) & 1;
  25.801 +	}
  25.802 +	apic_printk(APIC_VERBOSE, KERN_INFO
  25.803 +			"Broken MPtable reports ISA irq %d\n", irq);
  25.804 +	return 0;
  25.805 +}
  25.806 +
  25.807 +/* EISA interrupts are always polarity zero and can be edge or level
  25.808 + * trigger depending on the ELCR value.  If an interrupt is listed as
  25.809 + * EISA conforming in the MP table, that means its trigger type must
  25.810 + * be read in from the ELCR */
  25.811 +
  25.812 +#define default_EISA_trigger(idx)	(EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
  25.813 +#define default_EISA_polarity(idx)	(0)
  25.814 +
  25.815 +/* ISA interrupts are always polarity zero edge triggered,
  25.816 + * when listed as conforming in the MP table. */
  25.817 +
  25.818 +#define default_ISA_trigger(idx)	(0)
  25.819 +#define default_ISA_polarity(idx)	(0)
  25.820 +
  25.821 +/* PCI interrupts are always polarity one level triggered,
  25.822 + * when listed as conforming in the MP table. */
  25.823 +
  25.824 +#define default_PCI_trigger(idx)	(1)
  25.825 +#define default_PCI_polarity(idx)	(1)
  25.826 +
  25.827 +/* MCA interrupts are always polarity zero level triggered,
  25.828 + * when listed as conforming in the MP table. */
  25.829 +
  25.830 +#define default_MCA_trigger(idx)	(1)
  25.831 +#define default_MCA_polarity(idx)	(0)
  25.832 +
  25.833 +/* NEC98 interrupts are always polarity zero edge triggered,
  25.834 + * when listed as conforming in the MP table. */
  25.835 +
  25.836 +#define default_NEC98_trigger(idx)     (0)
  25.837 +#define default_NEC98_polarity(idx)    (0)
  25.838 +
  25.839 +static int __init MPBIOS_polarity(int idx)
  25.840 +{
  25.841 +	int bus = mp_irqs[idx].mpc_srcbus;
  25.842 +	int polarity;
  25.843 +
  25.844 +	/*
  25.845 +	 * Determine IRQ line polarity (high active or low active):
  25.846 +	 */
  25.847 +	switch (mp_irqs[idx].mpc_irqflag & 3)
  25.848 +	{
  25.849 +		case 0: /* conforms, ie. bus-type dependent polarity */
  25.850 +		{
  25.851 +			switch (mp_bus_id_to_type[bus])
  25.852 +			{
  25.853 +				case MP_BUS_ISA: /* ISA pin */
  25.854 +				{
  25.855 +					polarity = default_ISA_polarity(idx);
  25.856 +					break;
  25.857 +				}
  25.858 +				case MP_BUS_EISA: /* EISA pin */
  25.859 +				{
  25.860 +					polarity = default_EISA_polarity(idx);
  25.861 +					break;
  25.862 +				}
  25.863 +				case MP_BUS_PCI: /* PCI pin */
  25.864 +				{
  25.865 +					polarity = default_PCI_polarity(idx);
  25.866 +					break;
  25.867 +				}
  25.868 +				case MP_BUS_MCA: /* MCA pin */
  25.869 +				{
  25.870 +					polarity = default_MCA_polarity(idx);
  25.871 +					break;
  25.872 +				}
  25.873 +				case MP_BUS_NEC98: /* NEC 98 pin */
  25.874 +				{
  25.875 +					polarity = default_NEC98_polarity(idx);
  25.876 +					break;
  25.877 +				}
  25.878 +				default:
  25.879 +				{
  25.880 +					printk(KERN_WARNING "broken BIOS!!\n");
  25.881 +					polarity = 1;
  25.882 +					break;
  25.883 +				}
  25.884 +			}
  25.885 +			break;
  25.886 +		}
  25.887 +		case 1: /* high active */
  25.888 +		{
  25.889 +			polarity = 0;
  25.890 +			break;
  25.891 +		}
  25.892 +		case 2: /* reserved */
  25.893 +		{
  25.894 +			printk(KERN_WARNING "broken BIOS!!\n");
  25.895 +			polarity = 1;
  25.896 +			break;
  25.897 +		}
  25.898 +		case 3: /* low active */
  25.899 +		{
  25.900 +			polarity = 1;
  25.901 +			break;
  25.902 +		}
  25.903 +		default: /* invalid */
  25.904 +		{
  25.905 +			printk(KERN_WARNING "broken BIOS!!\n");
  25.906 +			polarity = 1;
  25.907 +			break;
  25.908 +		}
  25.909 +	}
  25.910 +	return polarity;
  25.911 +}
  25.912 +
  25.913 +static int MPBIOS_trigger(int idx)
  25.914 +{
  25.915 +	int bus = mp_irqs[idx].mpc_srcbus;
  25.916 +	int trigger;
  25.917 +
  25.918 +	/*
  25.919 +	 * Determine IRQ trigger mode (edge or level sensitive):
  25.920 +	 */
  25.921 +	switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
  25.922 +	{
  25.923 +		case 0: /* conforms, ie. bus-type dependent */
  25.924 +		{
  25.925 +			switch (mp_bus_id_to_type[bus])
  25.926 +			{
  25.927 +				case MP_BUS_ISA: /* ISA pin */
  25.928 +				{
  25.929 +					trigger = default_ISA_trigger(idx);
  25.930 +					break;
  25.931 +				}
  25.932 +				case MP_BUS_EISA: /* EISA pin */
  25.933 +				{
  25.934 +					trigger = default_EISA_trigger(idx);
  25.935 +					break;
  25.936 +				}
  25.937 +				case MP_BUS_PCI: /* PCI pin */
  25.938 +				{
  25.939 +					trigger = default_PCI_trigger(idx);
  25.940 +					break;
  25.941 +				}
  25.942 +				case MP_BUS_MCA: /* MCA pin */
  25.943 +				{
  25.944 +					trigger = default_MCA_trigger(idx);
  25.945 +					break;
  25.946 +				}
  25.947 +				case MP_BUS_NEC98: /* NEC 98 pin */
  25.948 +				{
  25.949 +					trigger = default_NEC98_trigger(idx);
  25.950 +					break;
  25.951 +				}
  25.952 +				default:
  25.953 +				{
  25.954 +					printk(KERN_WARNING "broken BIOS!!\n");
  25.955 +					trigger = 1;
  25.956 +					break;
  25.957 +				}
  25.958 +			}
  25.959 +			break;
  25.960 +		}
  25.961 +		case 1: /* edge */
  25.962 +		{
  25.963 +			trigger = 0;
  25.964 +			break;
  25.965 +		}
  25.966 +		case 2: /* reserved */
  25.967 +		{
  25.968 +			printk(KERN_WARNING "broken BIOS!!\n");
  25.969 +			trigger = 1;
  25.970 +			break;
  25.971 +		}
  25.972 +		case 3: /* level */
  25.973 +		{
  25.974 +			trigger = 1;
  25.975 +			break;
  25.976 +		}
  25.977 +		default: /* invalid */
  25.978 +		{
  25.979 +			printk(KERN_WARNING "broken BIOS!!\n");
  25.980 +			trigger = 0;
  25.981 +			break;
  25.982 +		}
  25.983 +	}
  25.984 +	return trigger;
  25.985 +}
  25.986 +
  25.987 +static inline int irq_polarity(int idx)
  25.988 +{
  25.989 +	return MPBIOS_polarity(idx);
  25.990 +}
  25.991 +
  25.992 +static inline int irq_trigger(int idx)
  25.993 +{
  25.994 +	return MPBIOS_trigger(idx);
  25.995 +}
  25.996 +
  25.997  static int pin_2_irq(int idx, int apic, int pin)
  25.998  {
  25.999  	int irq, i;
 25.1000 @@ -250,26 +1158,41 @@ static int pin_2_irq(int idx, int apic, 
 25.1001  	return irq;
 25.1002  }
 25.1003  
 25.1004 +static inline int IO_APIC_irq_trigger(int irq)
 25.1005 +{
 25.1006 +	int apic, idx, pin;
 25.1007 +
 25.1008 +	for (apic = 0; apic < nr_ioapics; apic++) {
 25.1009 +		for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 25.1010 +			idx = find_irq_entry(apic,pin,mp_INT);
 25.1011 +			if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 25.1012 +				return irq_trigger(idx);
 25.1013 +		}
 25.1014 +	}
 25.1015 +	/*
 25.1016 +	 * nonexistent IRQs are edge default
 25.1017 +	 */
 25.1018 +	return 0;
 25.1019 +}
 25.1020 +
 25.1021  /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 25.1022 -u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
 25.1023 +u8 irq_vector[NR_IRQ_VECTORS]; /* = { FIRST_DEVICE_VECTOR , 0 }; */
 25.1024  
 25.1025  int assign_irq_vector(int irq)
 25.1026  {
 25.1027  	static int current_vector = FIRST_DEVICE_VECTOR;
 25.1028 -        physdev_op_t op;
 25.1029 -        int ret;
 25.1030 +	physdev_op_t op;
 25.1031  
 25.1032  	BUG_ON(irq >= NR_IRQ_VECTORS);
 25.1033  	if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
 25.1034  		return IO_APIC_VECTOR(irq);
 25.1035  
 25.1036 -        op.cmd = PHYSDEVOP_ASSIGN_VECTOR;
 25.1037 -        op.u.irq_op.irq = irq;
 25.1038 -        ret = HYPERVISOR_physdev_op(&op);
 25.1039 -        if (ret)
 25.1040 -            return -ENOSPC;
 25.1041 +	op.cmd = PHYSDEVOP_ASSIGN_VECTOR;
 25.1042 +	op.u.irq_op.irq = irq;
 25.1043 +	if (HYPERVISOR_physdev_op(&op))
 25.1044 +		return -ENOSPC;
 25.1045 +	current_vector = op.u.irq_op.vector;
 25.1046  
 25.1047 -        current_vector = op.u.irq_op.vector;
 25.1048  	vector_irq[current_vector] = irq;
 25.1049  	if (irq != AUTO_ASSIGN)
 25.1050  		IO_APIC_VECTOR(irq) = current_vector;
 25.1051 @@ -277,12 +1200,1268 @@ int assign_irq_vector(int irq)
 25.1052  	return current_vector;
 25.1053  }
 25.1054  
 25.1055 +#ifndef CONFIG_XEN
 25.1056 +static struct hw_interrupt_type ioapic_level_type;
 25.1057 +static struct hw_interrupt_type ioapic_edge_type;
 25.1058 +
 25.1059 +#define IOAPIC_AUTO	-1
 25.1060 +#define IOAPIC_EDGE	0
 25.1061 +#define IOAPIC_LEVEL	1
 25.1062 +
 25.1063 +static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 25.1064 +{
 25.1065 +	if (use_pci_vector() && !platform_legacy_irq(irq)) {
 25.1066 +		if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 25.1067 +				trigger == IOAPIC_LEVEL)
 25.1068 +			irq_desc[vector].handler = &ioapic_level_type;
 25.1069 +		else
 25.1070 +			irq_desc[vector].handler = &ioapic_edge_type;
 25.1071 +		set_intr_gate(vector, interrupt[vector]);
 25.1072 +	} else	{
 25.1073 +		if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 25.1074 +				trigger == IOAPIC_LEVEL)
 25.1075 +			irq_desc[irq].handler = &ioapic_level_type;
 25.1076 +		else
 25.1077 +			irq_desc[irq].handler = &ioapic_edge_type;
 25.1078 +		set_intr_gate(vector, interrupt[irq]);
 25.1079 +	}
 25.1080 +}
 25.1081 +#else
 25.1082 +#define ioapic_register_intr(_irq,_vector,_trigger) ((void)0)
 25.1083 +#endif
 25.1084 +
 25.1085 +void __init setup_IO_APIC_irqs(void)
 25.1086 +{
 25.1087 +	struct IO_APIC_route_entry entry;
 25.1088 +	int apic, pin, idx, irq, first_notcon = 1, vector;
 25.1089 +	unsigned long flags;
 25.1090 +
 25.1091 +	apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 25.1092 +
 25.1093 +	for (apic = 0; apic < nr_ioapics; apic++) {
 25.1094 +	for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 25.1095 +
 25.1096 +		/*
 25.1097 +		 * add it to the IO-APIC irq-routing table:
 25.1098 +		 */
 25.1099 +		memset(&entry,0,sizeof(entry));
 25.1100 +
 25.1101 +		entry.delivery_mode = INT_DELIVERY_MODE;
 25.1102 +		entry.dest_mode = INT_DEST_MODE;
 25.1103 +		entry.mask = 0;				/* enable IRQ */
 25.1104 +		entry.dest.logical.logical_dest = 
 25.1105 +					cpu_mask_to_apicid(TARGET_CPUS);
 25.1106 +
 25.1107 +		idx = find_irq_entry(apic,pin,mp_INT);
 25.1108 +		if (idx == -1) {
 25.1109 +			if (first_notcon) {
 25.1110 +				apic_printk(APIC_VERBOSE, KERN_DEBUG
 25.1111 +						" IO-APIC (apicid-pin) %d-%d",
 25.1112 +						mp_ioapics[apic].mpc_apicid,
 25.1113 +						pin);
 25.1114 +				first_notcon = 0;
 25.1115 +			} else
 25.1116 +				apic_printk(APIC_VERBOSE, ", %d-%d",
 25.1117 +					mp_ioapics[apic].mpc_apicid, pin);
 25.1118 +			continue;
 25.1119 +		}
 25.1120 +
 25.1121 +		entry.trigger = irq_trigger(idx);
 25.1122 +		entry.polarity = irq_polarity(idx);
 25.1123 +
 25.1124 +		if (irq_trigger(idx)) {
 25.1125 +			entry.trigger = 1;
 25.1126 +			entry.mask = 1;
 25.1127 +		}
 25.1128 +
 25.1129 +		irq = pin_2_irq(idx, apic, pin);
 25.1130 +		/*
 25.1131 +		 * skip adding the timer int on secondary nodes, which causes
 25.1132 +		 * a small but painful rift in the time-space continuum
 25.1133 +		 */
 25.1134 +		if (multi_timer_check(apic, irq))
 25.1135 +			continue;
 25.1136 +		else
 25.1137 +			add_pin_to_irq(irq, apic, pin);
 25.1138 +
 25.1139 +		if (/*!apic &&*/ !IO_APIC_IRQ(irq))
 25.1140 +			continue;
 25.1141 +
 25.1142 +		if (IO_APIC_IRQ(irq)) {
 25.1143 +			vector = assign_irq_vector(irq);
 25.1144 +			entry.vector = vector;
 25.1145 +			ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 25.1146 +		
 25.1147 +			if (!apic && (irq < 16))
 25.1148 +				disable_8259A_irq(irq);
 25.1149 +		}
 25.1150 +		spin_lock_irqsave(&ioapic_lock, flags);
 25.1151 +		io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 25.1152 +		io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 25.1153 +		spin_unlock_irqrestore(&ioapic_lock, flags);
 25.1154 +	}
 25.1155 +	}
 25.1156 +
 25.1157 +	if (!first_notcon)
 25.1158 +		apic_printk(APIC_VERBOSE, " not connected.\n");
 25.1159 +}
 25.1160 +
 25.1161 +/*
 25.1162 + * Set up the 8259A-master output pin:
 25.1163 + */
 25.1164 +#ifndef CONFIG_XEN
 25.1165 +void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
 25.1166 +{
 25.1167 +	struct IO_APIC_route_entry entry;
 25.1168 +	unsigned long flags;
 25.1169 +
 25.1170 +	memset(&entry,0,sizeof(entry));
 25.1171 +
 25.1172 +	disable_8259A_irq(0);
 25.1173 +
 25.1174 +	/* mask LVT0 */
 25.1175 +	apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 25.1176 +
 25.1177 +	/*
 25.1178 +	 * We use logical delivery to get the timer IRQ
 25.1179 +	 * to the first CPU.
 25.1180 +	 */
 25.1181 +	entry.dest_mode = INT_DEST_MODE;
 25.1182 +	entry.mask = 0;					/* unmask IRQ now */
 25.1183 +	entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 25.1184 +	entry.delivery_mode = INT_DELIVERY_MODE;
 25.1185 +	entry.polarity = 0;
 25.1186 +	entry.trigger = 0;
 25.1187 +	entry.vector = vector;
 25.1188 +
 25.1189 +	/*
 25.1190 +	 * The timer IRQ doesn't have to know that behind the
 25.1191 +	 * scene we have a 8259A-master in AEOI mode ...
 25.1192 +	 */
 25.1193 +	irq_desc[0].handler = &ioapic_edge_type;
 25.1194 +
 25.1195 +	/*
 25.1196 +	 * Add it to the IO-APIC irq-routing table:
 25.1197 +	 */
 25.1198 +	spin_lock_irqsave(&ioapic_lock, flags);
 25.1199 +	io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
 25.1200 +	io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
 25.1201 +	spin_unlock_irqrestore(&ioapic_lock, flags);
 25.1202 +
 25.1203 +	enable_8259A_irq(0);
 25.1204 +}
 25.1205 +
 25.1206 +static inline void UNEXPECTED_IO_APIC(void)
 25.1207 +{
 25.1208 +}
 25.1209 +
 25.1210 +void __init print_IO_APIC(void)
 25.1211 +{
 25.1212 +	int apic, i;
 25.1213 +	union IO_APIC_reg_00 reg_00;
 25.1214 +	union IO_APIC_reg_01 reg_01;
 25.1215 +	union IO_APIC_reg_02 reg_02;
 25.1216 +	union IO_APIC_reg_03 reg_03;
 25.1217 +	unsigned long flags;
 25.1218 +
 25.1219 +	if (apic_verbosity == APIC_QUIET)
 25.1220 +		return;
 25.1221 +
 25.1222 + 	printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 25.1223 +	for (i = 0; i < nr_ioapics; i++)
 25.1224 +		printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 25.1225 +		       mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 25.1226 +
 25.1227 +	/*
 25.1228 +	 * We are a bit conservative about what we expect.  We have to
 25.1229 +	 * know about every hardware change ASAP.
 25.1230 +	 */
 25.1231 +	printk(KERN_INFO "testing the IO APIC.......................\n");
 25.1232 +
 25.1233 +	for (apic = 0; apic < nr_ioapics; apic++) {
 25.1234 +
 25.1235 +	spin_lock_irqsave(&ioapic_lock, flags);
 25.1236 +	reg_00.raw = io_apic_read(apic, 0);
 25.1237 +	reg_01.raw = io_apic_read(apic, 1);
 25.1238 +	if (reg_01.bits.version >= 0x10)
 25.1239 +		reg_02.raw = io_apic_read(apic, 2);
 25.1240 +	if (reg_01.bits.version >= 0x20)
 25.1241 +		reg_03.raw = io_apic_read(apic, 3);
 25.1242 +	spin_unlock_irqrestore(&ioapic_lock, flags);
 25.1243 +
 25.1244 +	printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 25.1245 +	printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 25.1246 +	printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 25.1247 +	printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
 25.1248 +	printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
 25.1249 +	if (reg_00.bits.ID >= get_physical_broadcast())
 25.1250 +		UNEXPECTED_IO_APIC();
 25.1251 +	if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 25.1252 +		UNEXPECTED_IO_APIC();
 25.1253 +
 25.1254 +	printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
 25.1255 +	printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 25.1256 +	if (	(reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 25.1257 +		(reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 25.1258 +		(reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 25.1259 +		(reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 25.1260 +		(reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 25.1261 +		(reg_01.bits.entries != 0x2E) &&
 25.1262 +		(reg_01.bits.entries != 0x3F)
 25.1263 +	)
 25.1264 +		UNEXPECTED_IO_APIC();
 25.1265 +
 25.1266 +	printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 25.1267 +	printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 25.1268 +	if (	(reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 25.1269 +		(reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 25.1270 +		(reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 25.1271 +		(reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 25.1272 +		(reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 25.1273 +	)
 25.1274 +		UNEXPECTED_IO_APIC();
 25.1275 +	if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 25.1276 +		UNEXPECTED_IO_APIC();
 25.1277 +
 25.1278 +	/*
 25.1279 +	 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
 25.1280 +	 * but the value of reg_02 is read as the previous read register
 25.1281 +	 * value, so ignore it if reg_02 == reg_01.
 25.1282 +	 */
 25.1283 +	if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
 25.1284 +		printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 25.1285 +		printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 25.1286 +		if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 25.1287 +			UNEXPECTED_IO_APIC();
 25.1288 +	}
 25.1289 +
 25.1290 +	/*
 25.1291 +	 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
 25.1292 +	 * or reg_03, but the value of reg_0[23] is read as the previous read
 25.1293 +	 * register value, so ignore it if reg_03 == reg_0[12].
 25.1294 +	 */
 25.1295 +	if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
 25.1296 +	    reg_03.raw != reg_01.raw) {
 25.1297 +		printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
 25.1298 +		printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
 25.1299 +		if (reg_03.bits.__reserved_1)
 25.1300 +			UNEXPECTED_IO_APIC();
 25.1301 +	}
 25.1302 +
 25.1303 +	printk(KERN_DEBUG ".... IRQ redirection table:\n");
 25.1304 +
 25.1305 +	printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
 25.1306 +			  " Stat Dest Deli Vect:   \n");
 25.1307 +
 25.1308 +	for (i = 0; i <= reg_01.bits.entries; i++) {
 25.1309 +		struct IO_APIC_route_entry entry;
 25.1310 +
 25.1311 +		spin_lock_irqsave(&ioapic_lock, flags);
 25.1312 +		*(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
 25.1313 +		*(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
 25.1314 +		spin_unlock_irqrestore(&ioapic_lock, flags);
 25.1315 +
 25.1316 +		printk(KERN_DEBUG " %02x %03X %02X  ",
 25.1317 +			i,
 25.1318 +			entry.dest.logical.logical_dest,
 25.1319 +			entry.dest.physical.physical_dest
 25.1320 +		);
 25.1321 +
 25.1322 +		printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
 25.1323 +			entry.mask,
 25.1324 +			entry.trigger,
 25.1325 +			entry.irr,
 25.1326 +			entry.polarity,
 25.1327 +			entry.delivery_status,
 25.1328 +			entry.dest_mode,
 25.1329 +			entry.delivery_mode,
 25.1330 +			entry.vector
 25.1331 +		);
 25.1332 +	}
 25.1333 +	}
 25.1334 +	if (use_pci_vector())
 25.1335 +		printk(KERN_INFO "Using vector-based indexing\n");
 25.1336 +	printk(KERN_DEBUG "IRQ to pin mappings:\n");
 25.1337 +	for (i = 0; i < NR_IRQS; i++) {
 25.1338 +		struct irq_pin_list *entry = irq_2_pin + i;
 25.1339 +		if (entry->pin < 0)
 25.1340 +			continue;
 25.1341 + 		if (use_pci_vector() && !platform_legacy_irq(i))
 25.1342 +			printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
 25.1343 +		else
 25.1344 +			printk(KERN_DEBUG "IRQ%d ", i);
 25.1345 +		for (;;) {
 25.1346 +			printk("-> %d:%d", entry->apic, entry->pin);
 25.1347 +			if (!entry->next)
 25.1348 +				break;
 25.1349 +			entry = irq_2_pin + entry->next;
 25.1350 +		}
 25.1351 +		printk("\n");
 25.1352 +	}
 25.1353 +
 25.1354 +	printk(KERN_INFO ".................................... done.\n");
 25.1355 +
 25.1356 +	return;
 25.1357 +}
 25.1358 +
 25.1359 +static void print_APIC_bitfield (int base)
 25.1360 +{
 25.1361 +	unsigned int v;
 25.1362 +	int i, j;
 25.1363 +
 25.1364 +	if (apic_verbosity == APIC_QUIET)
 25.1365 +		return;
 25.1366 +
 25.1367 +	printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
 25.1368 +	for (i = 0; i < 8; i++) {
 25.1369 +		v = apic_read(base + i*0x10);
 25.1370 +		for (j = 0; j < 32; j++) {
 25.1371 +			if (v & (1<<j))
 25.1372 +				printk("1");
 25.1373 +			else
 25.1374 +				printk("0");
 25.1375 +		}
 25.1376 +		printk("\n");
 25.1377 +	}
 25.1378 +}
 25.1379 +
 25.1380 +void /*__init*/ print_local_APIC(void * dummy)
 25.1381 +{
 25.1382 +	unsigned int v, ver, maxlvt;
 25.1383 +
 25.1384 +	if (apic_verbosity == APIC_QUIET)
 25.1385 +		return;
 25.1386 +
 25.1387 +	printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
 25.1388 +		smp_processor_id(), hard_smp_processor_id());
 25.1389 +	v = apic_read(APIC_ID);
 25.1390 +	printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
 25.1391 +	v = apic_read(APIC_LVR);
 25.1392 +	printk(KERN_INFO "... APIC VERSION: %08x\n", v);
 25.1393 +	ver = GET_APIC_VERSION(v);
 25.1394 +	maxlvt = get_maxlvt();
 25.1395 +
 25.1396 +	v = apic_read(APIC_TASKPRI);
 25.1397 +	printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
 25.1398 +
 25.1399 +	if (APIC_INTEGRATED(ver)) {			/* !82489DX */
 25.1400 +		v = apic_read(APIC_ARBPRI);
 25.1401 +		printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
 25.1402 +			v & APIC_ARBPRI_MASK);
 25.1403 +		v = apic_read(APIC_PROCPRI);
 25.1404 +		printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
 25.1405 +	}
 25.1406 +
 25.1407 +	v = apic_read(APIC_EOI);
 25.1408 +	printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
 25.1409 +	v = apic_read(APIC_RRR);
 25.1410 +	printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
 25.1411 +	v = apic_read(APIC_LDR);
 25.1412 +	printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
 25.1413 +	v = apic_read(APIC_DFR);
 25.1414 +	printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
 25.1415 +	v = apic_read(APIC_SPIV);
 25.1416 +	printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
 25.1417 +
 25.1418 +	printk(KERN_DEBUG "... APIC ISR field:\n");
 25.1419 +	print_APIC_bitfield(APIC_ISR);
 25.1420 +	printk(KERN_DEBUG "... APIC TMR field:\n");
 25.1421 +	print_APIC_bitfield(APIC_TMR);
 25.1422 +	printk(KERN_DEBUG "... APIC IRR field:\n");
 25.1423 +	print_APIC_bitfield(APIC_IRR);
 25.1424 +
 25.1425 +	if (APIC_INTEGRATED(ver)) {		/* !82489DX */
 25.1426 +		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */
 25.1427 +			apic_write(APIC_ESR, 0);
 25.1428 +		v = apic_read(APIC_ESR);
 25.1429 +		printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
 25.1430 +	}
 25.1431 +
 25.1432 +	v = apic_read(APIC_ICR);
 25.1433 +	printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
 25.1434 +	v = apic_read(APIC_ICR2);
 25.1435 +	printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
 25.1436 +
 25.1437 +	v = apic_read(APIC_LVTT);
 25.1438 +	printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
 25.1439 +
 25.1440 +	if (maxlvt > 3) {                       /* PC is LVT#4. */
 25.1441 +		v = apic_read(APIC_LVTPC);
 25.1442 +		printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
 25.1443 +	}
 25.1444 +	v = apic_read(APIC_LVT0);
 25.1445 +	printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
 25.1446 +	v = apic_read(APIC_LVT1);
 25.1447 +	printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
 25.1448 +
 25.1449 +	if (maxlvt > 2) {			/* ERR is LVT#3. */
 25.1450 +		v = apic_read(APIC_LVTERR);
 25.1451 +		printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
 25.1452 +	}
 25.1453 +
 25.1454 +	v = apic_read(APIC_TMICT);
 25.1455 +	printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
 25.1456 +	v = apic_read(APIC_TMCCT);
 25.1457 +	printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
 25.1458 +	v = apic_read(APIC_TDCR);
 25.1459 +	printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
 25.1460 +	printk("\n");
 25.1461 +}
 25.1462 +
 25.1463 +void print_all_local_APICs (void)
 25.1464 +{
 25.1465 +	on_each_cpu(print_local_APIC, NULL, 1, 1);
 25.1466 +}
 25.1467 +
 25.1468 +void /*__init*/ print_PIC(void)
 25.1469 +{
 25.1470 +	extern spinlock_t i8259A_lock;
 25.1471 +	unsigned int v;
 25.1472 +	unsigned long flags;
 25.1473 +
 25.1474 +	if (apic_verbosity == APIC_QUIET)
 25.1475 +		return;
 25.1476 +
 25.1477 +	printk(KERN_DEBUG "\nprinting PIC contents\n");
 25.1478 +
 25.1479 +	spin_lock_irqsave(&i8259A_lock, flags);
 25.1480 +
 25.1481 +	v = inb(0xa1) << 8 | inb(0x21);
 25.1482 +	printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
 25.1483 +
 25.1484 +	v = inb(0xa0) << 8 | inb(0x20);
 25.1485 +	printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
 25.1486 +
 25.1487 +	outb(0x0b,0xa0);
 25.1488 +	outb(0x0b,0x20);
 25.1489 +	v = inb(0xa0) << 8 | inb(0x20);
 25.1490 +	outb(0x0a,0xa0);
 25.1491 +	outb(0x0a,0x20);
 25.1492 +
 25.1493 +	spin_unlock_irqrestore(&i8259A_lock, flags);
 25.1494 +
 25.1495 +	printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
 25.1496 +
 25.1497 +	v = inb(0x4d1) << 8 | inb(0x4d0);
 25.1498 +	printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
 25.1499 +}
 25.1500 +#else
 25.1501 +void __init print_IO_APIC(void) { }
 25.1502 +#endif /* !CONFIG_XEN */
 25.1503 +
 25.1504 +static void __init enable_IO_APIC(void)
 25.1505 +{
 25.1506 +	union IO_APIC_reg_01 reg_01;
 25.1507 +	int i;
 25.1508 +	unsigned long flags;
 25.1509 +
 25.1510 +	for (i = 0; i < PIN_MAP_SIZE; i++) {
 25.1511 +		irq_2_pin[i].pin = -1;
 25.1512 +		irq_2_pin[i].next = 0;
 25.1513 +	}
 25.1514 +	if (!pirqs_enabled)
 25.1515 +		for (i = 0; i < MAX_PIRQS; i++)
 25.1516 +			pirq_entries[i] = -1;
 25.1517 +
 25.1518 +	/*
 25.1519 +	 * The number of IO-APIC IRQ registers (== #pins):
 25.1520 +	 */
 25.1521 +	for (i = 0; i < nr_ioapics; i++) {
 25.1522 +		spin_lock_irqsave(&ioapic_lock, flags);
 25.1523 +		reg_01.raw = io_apic_read(i, 1);
 25.1524 +		spin_unlock_irqrestore(&ioapic_lock, flags);
 25.1525 +		nr_ioapic_registers[i] = reg_01.bits.entries+1;
 25.1526 +	}
 25.1527 +
 25.1528 +	/*
 25.1529 +	 * Do not trust the IO-APIC being empty at bootup
 25.1530 +	 */
 25.1531 +	clear_IO_APIC();
 25.1532 +}
 25.1533 +
 25.1534 +/*
 25.1535 + * Not an __init, needed by the reboot code
 25.1536 + */
 25.1537 +void disable_IO_APIC(void)
 25.1538 +{
 25.1539 +	/*
 25.1540 +	 * Clear the IO-APIC before rebooting:
 25.1541 +	 */
 25.1542 +	clear_IO_APIC();
 25.1543 +
 25.1544 +#ifndef CONFIG_XEN
 25.1545 +	disconnect_bsp_APIC();
 25.1546 +#endif
 25.1547 +}
 25.1548 +
 25.1549 +/*
 25.1550 + * function to set the IO-APIC physical IDs based on the
 25.1551 + * values stored in the MPC table.
 25.1552 + *
 25.1553 + * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
 25.1554 + */
 25.1555 +
 25.1556 +#if !defined(CONFIG_XEN) && !defined(CONFIG_X86_NUMAQ)
 25.1557 +static void __init setup_ioapic_ids_from_mpc(void)
 25.1558 +{
 25.1559 +	union IO_APIC_reg_00 reg_00;
 25.1560 +	physid_mask_t phys_id_present_map;
 25.1561 +	int apic;
 25.1562 +	int i;
 25.1563 +	unsigned char old_id;
 25.1564 +	unsigned long flags;
 25.1565 +
 25.1566 +	/*
 25.1567 +	 * This is broken; anything with a real cpu count has to
 25.1568 +	 * circumvent this idiocy regardless.
 25.1569 +	 */
 25.1570 +	phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
 25.1571 +
 25.1572 +	/*
 25.1573 +	 * Set the IOAPIC ID to the value stored in the MPC table.
 25.1574 +	 */
 25.1575 +	for (apic = 0; apic < nr_ioapics; apic++) {
 25.1576 +
 25.1577 +		/* Read the register 0 value */
 25.1578 +		spin_lock_irqsave(&ioapic_lock, flags);
 25.1579 +		reg_00.raw = io_apic_read(apic, 0);
 25.1580 +		spin_unlock_irqrestore(&ioapic_lock, flags);
 25.1581 +		
 25.1582 +		old_id = mp_ioapics[apic].mpc_apicid;
 25.1583 +
 25.1584 +		if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
 25.1585 +			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
 25.1586 +				apic, mp_ioapics[apic].mpc_apicid);
 25.1587 +			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
 25.1588 +				reg_00.bits.ID);
 25.1589 +			mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
 25.1590 +		}
 25.1591 +
 25.1592 +		/* Don't check I/O APIC IDs for some xAPIC systems.  They have
 25.1593 +		 * no meaning without the serial APIC bus. */
 25.1594 +		if (NO_IOAPIC_CHECK)
 25.1595 +			continue;
 25.1596 +		/*
 25.1597 +		 * Sanity check, is the ID really free? Every APIC in a
 25.1598 +		 * system must have a unique ID or we get lots of nice
 25.1599 +		 * 'stuck on smp_invalidate_needed IPI wait' messages.
 25.1600 +		 */
 25.1601 +		if (check_apicid_used(phys_id_present_map,
 25.1602 +					mp_ioapics[apic].mpc_apicid)) {
 25.1603 +			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
 25.1604 +				apic, mp_ioapics[apic].mpc_apicid);
 25.1605 +			for (i = 0; i < get_physical_broadcast(); i++)
 25.1606 +				if (!physid_isset(i, phys_id_present_map))
 25.1607 +					break;
 25.1608 +			if (i >= get_physical_broadcast())
 25.1609 +				panic("Max APIC ID exceeded!\n");
 25.1610 +			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
 25.1611 +				i);
 25.1612 +			physid_set(i, phys_id_present_map);
 25.1613 +			mp_ioapics[apic].mpc_apicid = i;
 25.1614 +		} else {
 25.1615 +			physid_mask_t tmp;
 25.1616 +			tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
 25.1617 +			apic_printk(APIC_VERBOSE, "Setting %d in the "
 25.1618 +					"phys_id_present_map\n",
 25.1619 +					mp_ioapics[apic].mpc_apicid);
 25.1620 +			physids_or(phys_id_present_map, phys_id_present_map, tmp);
 25.1621 +		}
 25.1622 +
 25.1623 +
 25.1624 +		/*
 25.1625 +		 * We need to adjust the IRQ routing table
 25.1626 +		 * if the ID changed.
 25.1627 +		 */
 25.1628 +		if (old_id != mp_ioapics[apic].mpc_apicid)
 25.1629 +			for (i = 0; i < mp_irq_entries; i++)
 25.1630 +				if (mp_irqs[i].mpc_dstapic == old_id)
 25.1631 +					mp_irqs[i].mpc_dstapic
 25.1632 +						= mp_ioapics[apic].mpc_apicid;
 25.1633 +
 25.1634 +		/*
 25.1635 +		 * Read the right value from the MPC table and
 25.1636 +		 * write it into the ID register.
 25.1637 +	 	 */
 25.1638 +		apic_printk(APIC_VERBOSE, KERN_INFO
 25.1639 +			"...changing IO-APIC physical APIC ID to %d ...",
 25.1640 +			mp_ioapics[apic].mpc_apicid);
 25.1641 +
 25.1642 +		reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
 25.1643 +		spin_lock_irqsave(&ioapic_lock, flags);
 25.1644 +		io_apic_write(apic, 0, reg_00.raw);
 25.1645 +		spin_unlock_irqrestore(&ioapic_lock, flags);
 25.1646 +
 25.1647 +		/*
 25.1648 +		 * Sanity check
 25.1649 +		 */
 25.1650 +		spin_lock_irqsave(&ioapic_lock, flags);
 25.1651 +		reg_00.raw = io_apic_read(apic, 0);
 25.1652 +		spin_unlock_irqrestore(&ioapic_lock, flags);
 25.1653 +		if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
 25.1654 +			printk("could not set ID!\n");
 25.1655 +		else
 25.1656 +			apic_printk(APIC_VERBOSE, " ok.\n");
 25.1657 +	}
 25.1658 +}
 25.1659 +#else
 25.1660 +static void __init setup_ioapic_ids_from_mpc(void) { }
 25.1661 +#endif
 25.1662 +
 25.1663 +#ifndef CONFIG_XEN
 25.1664 +/*
 25.1665 + * There is a nasty bug in some older SMP boards, their mptable lies
 25.1666 + * about the timer IRQ. We do the following to work around the situation:
 25.1667 + *
 25.1668 + *	- timer IRQ defaults to IO-APIC IRQ
 25.1669 + *	- if this function detects that timer IRQs are defunct, then we fall
 25.1670 + *	  back to ISA timer IRQs
 25.1671 + */
 25.1672 +static int __init timer_irq_works(void)
 25.1673 +{
 25.1674 +	unsigned long t1 = jiffies;
 25.1675 +
 25.1676 +	local_irq_enable();
 25.1677 +	/* Let ten ticks pass... */
 25.1678 +	mdelay((10 * 1000) / HZ);
 25.1679 +
 25.1680 +	/*
 25.1681 +	 * Expect a few ticks at least, to be sure some possible
 25.1682 +	 * glue logic does not lock up after one or two first
 25.1683 +	 * ticks in a non-ExtINT mode.  Also the local APIC
 25.1684 +	 * might have cached one ExtINT interrupt.  Finally, at
 25.1685 +	 * least one tick may be lost due to delays.
 25.1686 +	 */
 25.1687 +	if (jiffies - t1 > 4)
 25.1688 +		return 1;
 25.1689 +
 25.1690 +	return 0;
 25.1691 +}
 25.1692 +
 25.1693 +/*
 25.1694 + * In the SMP+IOAPIC case it might happen that there are an unspecified
 25.1695 + * number of pending IRQ events unhandled. These cases are very rare,
 25.1696 + * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
 25.1697 + * better to do it this way as thus we do not have to be aware of
 25.1698 + * 'pending' interrupts in the IRQ path, except at this point.
 25.1699 + */
 25.1700 +/*
 25.1701 + * Edge triggered needs to resend any interrupt
 25.1702 + * that was delayed but this is now handled in the device
 25.1703 + * independent code.
 25.1704 + */
 25.1705 +
 25.1706 +/*
 25.1707 + * Starting up a edge-triggered IO-APIC interrupt is
 25.1708 + * nasty - we need to make sure that we get the edge.
 25.1709 + * If it is already asserted for some reason, we need
 25.1710 + * return 1 to indicate that is was pending.
 25.1711 + *
 25.1712 + * This is not complete - we should be able to fake
 25.1713 + * an edge even if it isn't on the 8259A...
 25.1714 + */
 25.1715 +static unsigned int startup_edge_ioapic_irq(unsigned int irq)
 25.1716 +{
 25.1717 +	int was_pending = 0;
 25.1718 +	unsigned long flags;
 25.1719 +
 25.1720 +	spin_lock_irqsave(&ioapic_lock, flags);
 25.1721 +	if (irq < 16) {
 25.1722 +		disable_8259A_irq(irq);
 25.1723 +		if (i8259A_irq_pending(irq))
 25.1724 +			was_pending = 1;
 25.1725 +	}
 25.1726 +	__unmask_IO_APIC_irq(irq);
 25.1727 +	spin_unlock_irqrestore(&ioapic_lock, flags);
 25.1728 +
 25.1729 +	return was_pending;
 25.1730 +}
 25.1731 +
 25.1732 +/*
 25.1733 + * Once we have recorded IRQ_PENDING already, we can mask the
 25.1734 + * interrupt for real. This prevents IRQ storms from unhandled
 25.1735 + * devices.
 25.1736 + */
 25.1737 +static void ack_edge_ioapic_irq(unsigned int irq)
 25.1738 +{
 25.1739 +	move_irq(irq);
 25.1740 +	if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
 25.1741 +					== (IRQ_PENDING | IRQ_DISABLED))
 25.1742 +		mask_IO_APIC_irq(irq);
 25.1743 +	ack_APIC_irq();
 25.1744 +}
 25.1745 +
 25.1746 +/*
 25.1747 + * Level triggered interrupts can just be masked,
 25.1748 + * and shutting down and starting up the interrupt
 25.1749 + * is the same as enabling and disabling them -- except
 25.1750 + * with a startup need to return a "was pending" value.
 25.1751 + *
 25.1752 + * Level triggered interrupts are special because we
 25.1753 + * do not touch any IO-APIC register while handling
 25.1754 + * them. We ack the APIC in the end-IRQ handler, not
 25.1755 + * in the start-IRQ-handler. Protection against reentrance
 25.1756 + * from the same interrupt is still provided, both by the
 25.1757 + * generic IRQ layer and by the fact that an unacked local
 25.1758 + * APIC does not accept IRQs.
 25.1759 + */
 25.1760 +static unsigned int startup_level_ioapic_irq (unsigned int irq)
 25.1761 +{
 25.1762 +	unmask_IO_APIC_irq(irq);
 25.1763 +
 25.1764 +	return 0; /* don't check for pending */
 25.1765 +}
 25.1766 +
 25.1767 +static void end_level_ioapic_irq (unsigned int irq)
 25.1768 +{
 25.1769 +	unsigned long v;
 25.1770 +	int i;
 25.1771 +
 25.1772 +	move_irq(irq);
 25.1773 +/*
 25.1774 + * It appears there is an erratum which affects at least version 0x11
 25.1775 + * of I/O APIC (that's the 82093AA and cores integrated into various
 25.1776 + * chipsets).  Under certain conditions a level-triggered interrupt is
 25.1777 + * erroneously delivered as edge-triggered one but the respective IRR
 25.1778 + * bit gets set nevertheless.  As a result the I/O unit expects an EOI
 25.1779 + * message but it will never arrive and further interrupts are blocked
 25.1780 + * from the source.  The exact reason is so far unknown, but the
 25.1781 + * phenomenon was observed when two consecutive interrupt requests
 25.1782 + * from a given source get delivered to the same CPU and the source is
 25.1783 + * temporarily disabled in between.
 25.1784 + *
 25.1785 + * A workaround is to simulate an EOI message manually.  We achieve it
 25.1786 + * by setting the trigger mode to edge and then to level when the edge
 25.1787 + * trigger mode gets detected in the TMR of a local APIC for a
 25.1788 + * level-triggered interrupt.  We mask the source for the time of the
 25.1789 + * operation to prevent an edge-triggered interrupt escaping meanwhile.
 25.1790 + * The idea is from Manfred Spraul.  --macro
 25.1791 + */
 25.1792 +	i = IO_APIC_VECTOR(irq);
 25.1793 +
 25.1794 +	v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
 25.1795 +
 25.1796 +	ack_APIC_irq();
 25.1797 +
 25.1798 +	if (!(v & (1 << (i & 0x1f)))) {
 25.1799 +		atomic_inc(&irq_mis_count);
 25.1800 +		spin_lock(&ioapic_lock);
 25.1801 +		__mask_and_edge_IO_APIC_irq(irq);
 25.1802 +		__unmask_and_level_IO_APIC_irq(irq);
 25.1803 +		spin_unlock(&ioapic_lock);
 25.1804 +	}
 25.1805 +}
 25.1806 +
 25.1807 +#ifdef CONFIG_PCI_MSI
 25.1808 +static unsigned int startup_edge_ioapic_vector(unsigned int vector)
 25.1809 +{
 25.1810 +	int irq = vector_to_irq(vector);
 25.1811 +
 25.1812 +	return startup_edge_ioapic_irq(irq);
 25.1813 +}
 25.1814 +
 25.1815 +static void ack_edge_ioapic_vector(unsigned int vector)
 25.1816 +{
 25.1817 +	int irq = vector_to_irq(vector);
 25.1818 +
 25.1819 +	ack_edge_ioapic_irq(irq);
 25.1820 +}
 25.1821 +
 25.1822 +static unsigned int startup_level_ioapic_vector (unsigned int vector)
 25.1823 +{
 25.1824 +	int irq = vector_to_irq(vector);
 25.1825 +
 25.1826 +	return startup_level_ioapic_irq (irq);
 25.1827 +}
 25.1828 +
 25.1829 +static void end_level_ioapic_vector (unsigned int vector)
 25.1830 +{
 25.1831 +	int irq = vector_to_irq(vector);
 25.1832 +
 25.1833 +	end_level_ioapic_irq(irq);
 25.1834 +}
 25.1835 +
 25.1836 +static void mask_IO_APIC_vector (unsigned int vector)
 25.1837 +{
 25.1838 +	int irq = vector_to_irq(vector);
 25.1839 +
 25.1840 +	mask_IO_APIC_irq(irq);
 25.1841 +}
 25.1842 +
 25.1843 +static void unmask_IO_APIC_vector (unsigned int vector)
 25.1844 +{
 25.1845 +	int irq = vector_to_irq(vector);
 25.1846 +
 25.1847 +	unmask_IO_APIC_irq(irq);
 25.1848 +}
 25.1849 +
 25.1850 +static void set_ioapic_affinity_vector (unsigned int vector,
 25.1851 +					cpumask_t cpu_mask)
 25.1852 +{
 25.1853 +	int irq = vector_to_irq(vector);
 25.1854 +
 25.1855 +	set_ioapic_affinity_irq(irq, cpu_mask);
 25.1856 +}
 25.1857 +#endif
 25.1858 +
 25.1859 +/*
 25.1860 + * Level and edge triggered IO-APIC interrupts need different handling,
 25.1861 + * so we use two separate IRQ descriptors. Edge triggered IRQs can be
 25.1862 + * handled with the level-triggered descriptor, but that one has slightly
 25.1863 + * more overhead. Level-triggered interrupts cannot be handled with the
 25.1864 + * edge-triggered handler, without risking IRQ storms and other ugly
 25.1865 + * races.
 25.1866 + */
 25.1867 +static struct hw_interrupt_type ioapic_edge_type = {
 25.1868 +	.typename 	= "IO-APIC-edge",
 25.1869 +	.startup 	= startup_edge_ioapic,
 25.1870 +	.shutdown 	= shutdown_edge_ioapic,
 25.1871 +	.enable 	= enable_edge_ioapic,
 25.1872 +	.disable 	= disable_edge_ioapic,
 25.1873 +	.ack 		= ack_edge_ioapic,
 25.1874 +	.end 		= end_edge_ioapic,
 25.1875 +	.set_affinity 	= set_ioapic_affinity,
 25.1876 +};
 25.1877 +
 25.1878 +static struct hw_interrupt_type ioapic_level_type = {
 25.1879 +	.typename 	= "IO-APIC-level",
 25.1880 +	.startup 	= startup_level_ioapic,
 25.1881 +	.shutdown 	= shutdown_level_ioapic,
 25.1882 +	.enable 	= enable_level_ioapic,
 25.1883 +	.disable 	= disable_level_ioapic,
 25.1884 +	.ack 		= mask_and_ack_level_ioapic,
 25.1885 +	.end 		= end_level_ioapic,
 25.1886 +	.set_affinity 	= set_ioapic_affinity,
 25.1887 +};
 25.1888 +#endif /* !CONFIG_XEN */
 25.1889 +
 25.1890 +static inline void init_IO_APIC_traps(void)
 25.1891 +{
 25.1892 +	int irq;
 25.1893 +
 25.1894 +	/*
 25.1895 +	 * NOTE! The local APIC isn't very good at handling
 25.1896 +	 * multiple interrupts at the same interrupt level.
 25.1897 +	 * As the interrupt level is determined by taking the
 25.1898 +	 * vector number and shifting that right by 4, we
 25.1899 +	 * want to spread these out a bit so that they don't
 25.1900 +	 * all fall in the same interrupt level.
 25.1901 +	 *
 25.1902 +	 * Also, we've got to be careful not to trash gate
 25.1903 +	 * 0x80, because int 0x80 is hm, kind of importantish. ;)
 25.1904 +	 */
 25.1905 +	for (irq = 0; irq < NR_IRQS ; irq++) {
 25.1906 +		int tmp = irq;
 25.1907 +		if (use_pci_vector()) {
 25.1908 +			if (!platform_legacy_irq(tmp))
 25.1909 +				if ((tmp = vector_to_irq(tmp)) == -1)
 25.1910 +					continue;
 25.1911 +		}
 25.1912 +		if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
 25.1913 +			/*
 25.1914 +			 * Hmm.. We don't have an entry for this,
 25.1915 +			 * so default to an old-fashioned 8259
 25.1916 +			 * interrupt if we can..
 25.1917 +			 */
 25.1918 +			if (irq < 16)
 25.1919 +				make_8259A_irq(irq);
 25.1920 +#ifndef CONFIG_XEN
 25.1921 +			else
 25.1922 +				/* Strange. Oh, well.. */
 25.1923 +				irq_desc[irq].handler = &no_irq_type;
 25.1924 +#endif
 25.1925 +		}
 25.1926 +	}
 25.1927 +}
 25.1928 +
 25.1929 +#ifndef CONFIG_XEN
 25.1930 +static void enable_lapic_irq (unsigned int irq)
 25.1931 +{
 25.1932 +	unsigned long v;
 25.1933 +
 25.1934 +	v = apic_read(APIC_LVT0);
 25.1935 +	apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
 25.1936 +}
 25.1937 +
 25.1938 +static void disable_lapic_irq (unsigned int irq)
 25.1939 +{
 25.1940 +	unsigned long v;
 25.1941 +
 25.1942 +	v = apic_read(APIC_LVT0);
 25.1943 +	apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
 25.1944 +}
 25.1945 +
 25.1946 +static void ack_lapic_irq (unsigned int irq)
 25.1947 +{
 25.1948 +	ack_APIC_irq();
 25.1949 +}
 25.1950 +
 25.1951 +static void end_lapic_irq (unsigned int i) { /* nothing */ }
 25.1952 +
 25.1953 +static struct hw_interrupt_type lapic_irq_type = {
 25.1954 +	.typename 	= "local-APIC-edge",
 25.1955 +	.startup 	= NULL, /* startup_irq() not used for IRQ0 */
 25.1956 +	.shutdown 	= NULL, /* shutdown_irq() not used for IRQ0 */
 25.1957 +	.enable 	= enable_lapic_irq,
 25.1958 +	.disable 	= disable_lapic_irq,
 25.1959 +	.ack 		= ack_lapic_irq,
 25.1960 +	.end 		= end_lapic_irq
 25.1961 +};
 25.1962 +
 25.1963 +static void setup_nmi (void)
 25.1964 +{
 25.1965 +	/*
 25.1966 + 	 * Dirty trick to enable the NMI watchdog ...
 25.1967 +	 * We put the 8259A master into AEOI mode and
 25.1968 +	 * unmask on all local APICs LVT0 as NMI.
 25.1969 +	 *
 25.1970 +	 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
 25.1971 +	 * is from Maciej W. Rozycki - so we do not have to EOI from
 25.1972 +	 * the NMI handler or the timer interrupt.
 25.1973 +	 */ 
 25.1974 +	apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
 25.1975 +
 25.1976 +	on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
 25.1977 +
 25.1978 +	apic_printk(APIC_VERBOSE, " done.\n");
 25.1979 +}
 25.1980 +
 25.1981 +/*
 25.1982 + * This looks a bit hackish but it's about the only one way of sending
 25.1983 + * a few INTA cycles to 8259As and any associated glue logic.  ICR does
 25.1984 + * not support the ExtINT mode, unfortunately.  We need to send these
 25.1985 + * cycles as some i82489DX-based boards have glue logic that keeps the
 25.1986 + * 8259A interrupt line asserted until INTA.  --macro
 25.1987 + */
 25.1988 +static inline void unlock_ExtINT_logic(void)
 25.1989 +{
 25.1990 +	int pin, i;
 25.1991 +	struct IO_APIC_route_entry entry0, entry1;
 25.1992 +	unsigned char save_control, save_freq_select;
 25.1993 +	unsigned long flags;
 25.1994 +
 25.1995 +	pin = find_isa_irq_pin(8, mp_INT);
 25.1996 +	if (pin == -1)
 25.1997 +		return;
 25.1998 +
 25.1999 +	spin_lock_irqsave(&ioapic_lock, flags);
 25.2000 +	*(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
 25.2001 +	*(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
 25.2002 +	spin_unlock_irqrestore(&ioapic_lock, flags);
 25.2003 +	clear_IO_APIC_pin(0, pin);
 25.2004 +
 25.2005 +	memset(&entry1, 0, sizeof(entry1));
 25.2006 +
 25.2007 +	entry1.dest_mode = 0;			/* physical delivery */
 25.2008 +	entry1.mask = 0;			/* unmask IRQ now */
 25.2009 +	entry1.dest.physical.physical_dest = hard_smp_processor_id();
 25.2010 +	entry1.delivery_mode = dest_ExtINT;
 25.2011 +	entry1.polarity = entry0.polarity;
 25.2012 +	entry1.trigger = 0;
 25.2013 +	entry1.vector = 0;
 25.2014 +
 25.2015 +	spin_lock_irqsave(&ioapic_lock, flags);
 25.2016 +	io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
 25.2017 +	io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
 25.2018 +	spin_unlock_irqrestore(&ioapic_lock, flags);
 25.2019 +
 25.2020 +	save_control = CMOS_READ(RTC_CONTROL);
 25.2021 +	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
 25.2022 +	CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
 25.2023 +		   RTC_FREQ_SELECT);
 25.2024 +	CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
 25.2025 +
 25.2026 +	i = 100;
 25.2027 +	while (i-- > 0) {
 25.2028 +		mdelay(10);
 25.2029 +		if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
 25.2030 +			i -= 10;
 25.2031 +	}
 25.2032 +
 25.2033 +	CMOS_WRITE(save_control, RTC_CONTROL);
 25.2034 +	CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
 25.2035 +	clear_IO_APIC_pin(0, pin);
 25.2036 +
 25.2037 +	spin_lock_irqsave(&ioapic_lock, flags);
 25.2038 +	io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
 25.2039 +	io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
 25.2040 +	spin_unlock_irqrestore(&ioapic_lock, flags);
 25.2041 +}
 25.2042 +
 25.2043 +/*
 25.2044 + * This code may look a bit paranoid, but it's supposed to cooperate with
 25.2045 + * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
 25.2046 + * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
 25.2047 + * fanatically on his truly buggy board.
 25.2048 + */
 25.2049 +static inline void check_timer(void)
 25.2050 +{
 25.2051 +	int pin1, pin2;
 25.2052 +	int vector;
 25.2053 +
 25.2054 +	/*
 25.2055 +	 * get/set the timer IRQ vector:
 25.2056 +	 */
 25.2057 +	disable_8259A_irq(0);
 25.2058 +	vector = assign_irq_vector(0);
 25.2059 +	set_intr_gate(vector, interrupt[0]);
 25.2060 +
 25.2061 +	/*
 25.2062 +	 * Subtle, code in do_timer_interrupt() expects an AEOI
 25.2063 +	 * mode for the 8259A whenever interrupts are routed
 25.2064 +	 * through I/O APICs.  Also IRQ0 has to be enabled in
 25.2065 +	 * the 8259A which implies the virtual wire has to be
 25.2066 +	 * disabled in the local APIC.
 25.2067 +	 */
 25.2068 +	apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 25.2069 +	init_8259A(1);
 25.2070 +	timer_ack = 1;
 25.2071 +	enable_8259A_irq(0);
 25.2072 +
 25.2073 +	pin1 = find_isa_irq_pin(0, mp_INT);
 25.2074 +	pin2 = find_isa_irq_pin(0, mp_ExtINT);
 25.2075 +
 25.2076 +	printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
 25.2077 +
 25.2078 +	if (pin1 != -1) {
 25.2079 +		/*
 25.2080 +		 * Ok, does IRQ0 through the IOAPIC work?
 25.2081 +		 */
 25.2082 +		unmask_IO_APIC_irq(0);
 25.2083 +		if (timer_irq_works()) {
 25.2084 +			if (nmi_watchdog == NMI_IO_APIC) {
 25.2085 +				disable_8259A_irq(0);
 25.2086 +				setup_nmi();
 25.2087 +				enable_8259A_irq(0);
 25.2088 +				check_nmi_watchdog();
 25.2089 +			}
 25.2090 +			return;
 25.2091 +		}
 25.2092 +		clear_IO_APIC_pin(0, pin1);
 25.2093 +		printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
 25.2094 +	}
 25.2095 +
 25.2096 +	printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
 25.2097 +	if (pin2 != -1) {
 25.2098 +		printk("\n..... (found pin %d) ...", pin2);
 25.2099 +		/*
 25.2100 +		 * legacy devices should be connected to IO APIC #0
 25.2101 +		 */
 25.2102 +		setup_ExtINT_IRQ0_pin(pin2, vector);
 25.2103 +		if (timer_irq_works()) {
 25.2104 +			printk("works.\n");
 25.2105 +			if (pin1 != -1)
 25.2106 +				replace_pin_at_irq(0, 0, pin1, 0, pin2);
 25.2107 +			else
 25.2108 +				add_pin_to_irq(0, 0, pin2);
 25.2109 +			if (nmi_watchdog == NMI_IO_APIC) {
 25.2110 +				setup_nmi();
 25.2111 +				check_nmi_watchdog();
 25.2112 +			}
 25.2113 +			return;
 25.2114 +		}
 25.2115 +		/*
 25.2116 +		 * Cleanup, just in case ...
 25.2117 +		 */
 25.2118 +		clear_IO_APIC_pin(0, pin2);
 25.2119 +	}
 25.2120 +	printk(" failed.\n");
 25.2121 +
 25.2122 +	if (nmi_watchdog == NMI_IO_APIC) {
 25.2123 +		printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
 25.2124 +		nmi_watchdog = 0;
 25.2125 +	}
 25.2126 +
 25.2127 +	printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
 25.2128 +
 25.2129 +	disable_8259A_irq(0);
 25.2130 +	irq_desc[0].handler = &lapic_irq_type;
 25.2131 +	apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);	/* Fixed mode */
 25.2132 +	enable_8259A_irq(0);
 25.2133 +
 25.2134 +	if (timer_irq_works()) {
 25.2135 +		printk(" works.\n");
 25.2136 +		return;
 25.2137 +	}
 25.2138 +	apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
 25.2139 +	printk(" failed.\n");
 25.2140 +
 25.2141 +	printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
 25.2142 +
 25.2143 +	timer_ack = 0;
 25.2144 +	init_8259A(0);
 25.2145 +	make_8259A_irq(0);
 25.2146 +	apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
 25.2147 +
 25.2148 +	unlock_ExtINT_logic();
 25.2149 +
 25.2150 +	if (timer_irq_works()) {
 25.2151 +		printk(" works.\n");
 25.2152 +		return;
 25.2153 +	}
 25.2154 +	printk(" failed :(.\n");
 25.2155 +	panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
 25.2156 +		"report.  Then try booting with the 'noapic' option");
 25.2157 +}
 25.2158 +#else
 25.2159 +#define check_timer() ((void)0)
 25.2160 +#endif
 25.2161 +
 25.2162 +/*
 25.2163 + *
 25.2164 + * IRQ's that are handled by the PIC in the MPS IOAPIC case.
 25.2165 + * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
 25.2166 + *   Linux doesn't really care, as it's not actually used
 25.2167 + *   for any interrupt handling anyway.
 25.2168 + */
 25.2169 +#define PIC_IRQS	(1 << PIC_CASCADE_IR)
 25.2170 +
 25.2171 +void __init setup_IO_APIC(void)
 25.2172 +{
 25.2173 +	enable_IO_APIC();
 25.2174 +
 25.2175 +	if (acpi_ioapic)
 25.2176 +		io_apic_irqs = ~0;	/* all IRQs go through IOAPIC */
 25.2177 +	else
 25.2178 +		io_apic_irqs = ~PIC_IRQS;
 25.2179 +
 25.2180 +	printk("ENABLING IO-APIC IRQs\n");
 25.2181 +
 25.2182 +	/*
 25.2183 +	 * Set up IO-APIC IRQ routing.
 25.2184 +	 */
 25.2185 +	if (!acpi_ioapic)
 25.2186 +		setup_ioapic_ids_from_mpc();
 25.2187 +#ifndef CONFIG_XEN
 25.2188 +	sync_Arb_IDs();
 25.2189 +#endif
 25.2190 +	setup_IO_APIC_irqs();
 25.2191 +	init_IO_APIC_traps();
 25.2192 +	check_timer();
 25.2193 +	if (!acpi_ioapic)
 25.2194 +		print_IO_APIC();
 25.2195 +}
 25.2196 +
 25.2197 +/*
 25.2198 + *	Called after all the initialization is done. If we didnt find any
 25.2199 + *	APIC bugs then we can allow the modify fast path
 25.2200 + */
 25.2201 + 
 25.2202 +static int __init io_apic_bug_finalize(void)
 25.2203 +{
 25.2204 +	if(sis_apic_bug == -1)
 25.2205 +		sis_apic_bug = 0;
 25.2206 +	return 0;
 25.2207 +}
 25.2208 +
 25.2209 +late_initcall(io_apic_bug_finalize);
 25.2210 +
 25.2211 +struct sysfs_ioapic_data {
 25.2212 +	struct sys_device dev;
 25.2213 +	struct IO_APIC_route_entry entry[0];
 25.2214 +};
 25.2215 +static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
 25.2216 +
 25.2217 +static int ioapic_suspend(struct sys_device *dev, u32 state)
 25.2218 +{
 25.2219 +	struct IO_APIC_route_entry *entry;
 25.2220 +	struct sysfs_ioapic_data *data;
 25.2221 +	unsigned long flags;
 25.2222 +	int i;
 25.2223 +	
 25.2224 +	data = container_of(dev, struct sysfs_ioapic_data, dev);
 25.2225 +	entry = data->entry;
 25.2226 +	spin_lock_irqsave(&ioapic_lock, flags);
 25.2227 +	for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
 25.2228 +		*(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
 25.2229 +		*(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
 25.2230 +	}
 25.2231 +	spin_unlock_irqrestore(&ioapic_lock, flags);
 25.2232 +
 25.2233 +	return 0;
 25.2234 +}
 25.2235 +
 25.2236 +static int ioapic_resume(struct sys_device *dev)
 25.2237 +{
 25.2238 +	struct IO_APIC_route_entry *entry;
 25.2239 +	struct sysfs_ioapic_data *data;
 25.2240 +	unsigned long flags;
 25.2241 +	union IO_APIC_reg_00 reg_00;
 25.2242 +	int i;
 25.2243 +	
 25.2244 +	data = container_of(dev, struct sysfs_ioapic_data, dev);
 25.2245 +	entry = data->entry;
 25.2246 +
 25.2247 +	spin_lock_irqsave(&ioapic_lock, flags);
 25.2248 +	reg_00.raw = io_apic_read(dev->id, 0);
 25.2249 +	if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
 25.2250 +		reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
 25.2251 +		io_apic_write(dev->id, 0, reg_00.raw);
 25.2252 +	}
 25.2253 +	for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
 25.2254 +		io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
 25.2255 +		io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
 25.2256 +	}
 25.2257 +	spin_unlock_irqrestore(&ioapic_lock, flags);
 25.2258 +
 25.2259 +	return 0;
 25.2260 +}
 25.2261 +
 25.2262 +static struct sysdev_class ioapic_sysdev_class = {
 25.2263 +	set_kset_name("ioapic"),
 25.2264 +	.suspend = ioapic_suspend,
 25.2265 +	.resume = ioapic_resume,
 25.2266 +};
 25.2267 +
 25.2268 +static int __init ioapic_init_sysfs(void)
 25.2269 +{
 25.2270 +	struct sys_device * dev;
 25.2271 +	int i, size, error = 0;
 25.2272 +
 25.2273 +	error = sysdev_class_register(&ioapic_sysdev_class);
 25.2274 +	if (error)
 25.2275 +		return error;
 25.2276 +
 25.2277 +	for (i = 0; i < nr_ioapics; i++ ) {
 25.2278 +		size = sizeof(struct sys_device) + nr_ioapic_registers[i] 
 25.2279 +			* sizeof(struct IO_APIC_route_entry);
 25.2280 +		mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
 25.2281 +		if (!mp_ioapic_data[i]) {
 25.2282 +			printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
 25.2283 +			continue;
 25.2284 +		}
 25.2285 +		memset(mp_ioapic_data[i], 0, size);
 25.2286 +		dev = &mp_ioapic_data[i]->dev;
 25.2287 +		dev->id = i; 
 25.2288 +		dev->cls = &ioapic_sysdev_class;
 25.2289 +		error = sysdev_register(dev);
 25.2290 +		if (error) {
 25.2291 +			kfree(mp_ioapic_data[i]);
 25.2292 +			mp_ioapic_data[i] = NULL;
 25.2293 +			printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
 25.2294 +			continue;
 25.2295 +		}
 25.2296 +	}
 25.2297 +
 25.2298 +	return 0;
 25.2299 +}
 25.2300 +
 25.2301 +device_initcall(ioapic_init_sysfs);
 25.2302 +
 25.2303 +/* --------------------------------------------------------------------------
 25.2304 +                          ACPI-based IOAPIC Configuration
 25.2305 +   -------------------------------------------------------------------------- */
 25.2306 +
 25.2307  #ifdef CONFIG_ACPI_BOOT
 25.2308 +
 25.2309  int __init io_apic_get_unique_id (int ioapic, int apic_id)
 25.2310  {
 25.2311 +#ifndef CONFIG_XEN
 25.2312  	union IO_APIC_reg_00 reg_00;
 25.2313  	static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
 25.2314 +	physid_mask_t tmp;
 25.2315  	unsigned long flags;
 25.2316 +	int i = 0;
 25.2317  
 25.2318  	/*
 25.2319  	 * The P4 platform supports up to 256 APIC IDs on two separate APIC 
 25.2320 @@ -306,8 +2485,45 @@ int __init io_apic_get_unique_id (int io
 25.2321  		apic_id = reg_00.bits.ID;
 25.2322  	}
 25.2323  
 25.2324 +	/*
 25.2325 +	 * Every APIC in a system must have a unique ID or we get lots of nice 
 25.2326 +	 * 'stuck on smp_invalidate_needed IPI wait' messages.
 25.2327 +	 */
 25.2328 +	if (check_apicid_used(apic_id_map, apic_id)) {
 25.2329 +
 25.2330 +		for (i = 0; i < get_physical_broadcast(); i++) {
 25.2331 +			if (!check_apicid_used(apic_id_map, i))
 25.2332 +				break;
 25.2333 +		}
 25.2334 +
 25.2335 +		if (i == get_physical_broadcast())
 25.2336 +			panic("Max apic_id exceeded!\n");
 25.2337 +
 25.2338 +		printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
 25.2339 +			"trying %d\n", ioapic, apic_id, i);
 25.2340 +
 25.2341 +		apic_id = i;
 25.2342 +	} 
 25.2343 +
 25.2344 +	tmp = apicid_to_cpu_present(apic_id);
 25.2345 +	physids_or(apic_id_map, apic_id_map, tmp);
 25.2346 +
 25.2347 +	if (reg_00.bits.ID != apic_id) {
 25.2348 +		reg_00.bits.ID = apic_id;
 25.2349 +
 25.2350 +		spin_lock_irqsave(&ioapic_lock, flags);
 25.2351 +		io_apic_write(ioapic, 0, reg_00.raw);
 25.2352 +		reg_00.raw = io_apic_read(ioapic, 0);
 25.2353 +		spin_unlock_irqrestore(&ioapic_lock, flags);
 25.2354 +
 25.2355 +		/* Sanity check */
 25.2356 +		if (reg_00.bits.ID != apic_id)
 25.2357 +			panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
 25.2358 +	}
 25.2359 +
 25.2360  	apic_printk(APIC_VERBOSE, KERN_INFO
 25.2361  			"IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
 25.2362 +#endif /* !CONFIG_XEN */
 25.2363  
 25.2364  	return apic_id;
 25.2365  }
 25.2366 @@ -338,6 +2554,7 @@ int __init io_apic_get_redir_entries (in
 25.2367  	return reg_01.bits.entries;
 25.2368  }
 25.2369  
 25.2370 +
 25.2371  int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
 25.2372  {
 25.2373  	struct IO_APIC_route_entry entry;
 25.2374 @@ -377,12 +2594,10 @@ int io_apic_set_pci_routing (int ioapic,
 25.2375  		mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
 25.2376  		edge_level, active_high_low);
 25.2377  
 25.2378 -#ifndef CONFIG_XEN
 25.2379  	ioapic_register_intr(irq, entry.vector, edge_level);
 25.2380  
 25.2381  	if (!ioapic && (irq < 16))
 25.2382  		disable_8259A_irq(irq);
 25.2383 -#endif
 25.2384  
 25.2385  	spin_lock_irqsave(&ioapic_lock, flags);
 25.2386  	io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
 25.2387 @@ -391,4 +2606,5 @@ int io_apic_set_pci_routing (int ioapic,
 25.2388  
 25.2389  	return 0;
 25.2390  }
 25.2391 +
 25.2392  #endif /*CONFIG_ACPI_BOOT*/

    26.1 --- a/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/mpparse.c	Tue May 03 14:42:00 2005 +0000
    26.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/mpparse.c	Tue May 10 08:49:59 2005 +0000
    26.3 @@ -109,7 +109,7 @@ static int MP_valid_apicid(int apicid, i
    26.4  {
    26.5  	return hweight_long(apicid & 0xf) == 1 && (apicid >> 4) != 0xf;
    26.6  }
    26.7 -#else
    26.8 +#elif !defined(CONFIG_XEN)
    26.9  static int MP_valid_apicid(int apicid, int version)
   26.10  {
   26.11  	if (version >= 0x14)
   26.12 @@ -119,6 +119,7 @@ static int MP_valid_apicid(int apicid, i
   26.13  }
   26.14  #endif
   26.15  
   26.16 +#ifndef CONFIG_XEN
   26.17  void __init MP_processor_info (struct mpc_config_processor *m)
   26.18  {
   26.19   	int ver, apicid;
   26.20 @@ -217,6 +218,12 @@ void __init MP_processor_info (struct mp
   26.21  	apic_version[m->mpc_apicid] = ver;
   26.22  	bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
   26.23  }
   26.24 +#else
   26.25 +void __init MP_processor_info (struct mpc_config_processor *m)
   26.26 +{
   26.27 +	num_processors++;
   26.28 +}
   26.29 +#endif /* CONFIG_XEN */
   26.30  
   26.31  static void __init MP_bus_info (struct mpc_config_bus *m)
   26.32  {
   26.33 @@ -690,7 +697,7 @@ void __init get_smp_config (void)
   26.34  		 * Read the physical hardware table.  Anything here will
   26.35  		 * override the defaults.
   26.36  		 */
   26.37 -		if (!smp_read_mpc((void *)mpf->mpf_physptr)) {
   26.38 +		if (!smp_read_mpc(isa_bus_to_virt(mpf->mpf_physptr))) {
   26.39  			smp_found_config = 0;
   26.40  			printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
   26.41  			printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
   26.42 @@ -743,7 +750,6 @@ static int __init smp_scan_config (unsig
   26.43  			smp_found_config = 1;
   26.44  			printk(KERN_INFO "found SMP MP-table at %08lx\n",
   26.45  						virt_to_phys(mpf));
   26.46 -			reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE);
   26.47  			if (mpf->mpf_physptr) {
   26.48  				/*
   26.49  				 * We cannot access to MPC table to compute
   26.50 @@ -817,12 +823,14 @@ void __init find_smp_config (void)
   26.51  void __init mp_register_lapic_address (
   26.52  	u64			address)
   26.53  {
   26.54 +#ifndef CONFIG_XEN
   26.55  	mp_lapic_addr = (unsigned long) address;
   26.56  
   26.57  	if (boot_cpu_physical_apicid == -1U)
   26.58  		boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
   26.59  
   26.60  	Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
   26.61 +#endif
   26.62  }
   26.63  
   26.64  
   26.65 @@ -842,6 +850,7 @@ void __init mp_register_lapic (
   26.66  	if (id == boot_cpu_physical_apicid)
   26.67  		boot_cpu = 1;
   26.68  
   26.69 +#ifndef CONFIG_XEN
   26.70  	processor.mpc_type = MP_PROCESSOR;
   26.71  	processor.mpc_apicid = id;
   26.72  	processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
   26.73 @@ -852,6 +861,7 @@ void __init mp_register_lapic (
   26.74  	processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
   26.75  	processor.mpc_reserved[0] = 0;
   26.76  	processor.mpc_reserved[1] = 0;
   26.77 +#endif
   26.78  
   26.79  	MP_processor_info(&processor);
   26.80  }

    27.1 --- a/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/setup.c	Tue May 03 14:42:00 2005 +0000
    27.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/i386/kernel/setup.c	Tue May 10 08:49:59 2005 +0000
    27.3 @@ -779,7 +779,7 @@ static void __init parse_cmdline_early (
    27.4  			noexec_setup(from + 7);
    27.5  
    27.6  
    27.7 -#ifdef  CONFIG_X86_SMP
    27.8 +#ifdef  CONFIG_X86_MPPARSE
    27.9  		/*
   27.10  		 * If the BIOS enumerates physical processors before logical,
   27.11  		 * maxcpus=N at enumeration-time can be used to disable HT.
   27.12 @@ -1133,12 +1133,6 @@ static unsigned long __init setup_memory
   27.13  	 */
   27.14  	acpi_reserve_bootmem();
   27.15  #endif
   27.16 -#ifdef CONFIG_X86_FIND_SMP_CONFIG
   27.17 -	/*
   27.18 -	 * Find and reserve possible boot-time SMP configuration:
   27.19 -	 */
   27.20 -	find_smp_config();
   27.21 -#endif
   27.22  
   27.23  #ifdef CONFIG_BLK_DEV_INITRD
   27.24  	if (xen_start_info.mod_start) {
   27.25 @@ -1503,6 +1497,13 @@ void __init setup_arch(char **cmdline_p)
   27.26  #endif
   27.27  	paging_init();
   27.28  
   27.29 +#ifdef CONFIG_X86_FIND_SMP_CONFIG
   27.30 +	/*
   27.31 +	 * Find and reserve possible boot-time SMP configuration:
   27.32 +	 */
   27.33 +	find_smp_config();
   27.34 +#endif
   27.35 +
   27.36  	/* Make sure we have a correctly sized P->M table. */
   27.37  	if (max_pfn != xen_start_info.nr_pages) {
   27.38  		phys_to_machine_mapping = alloc_bootmem_low_pages(
   27.39 @@ -1566,6 +1567,10 @@ void __init setup_arch(char **cmdline_p)
   27.40  	if (efi_enabled)
   27.41  		efi_map_memmap();
   27.42  
   27.43 +	op.cmd             = PHYSDEVOP_SET_IOPL;
   27.44 +	op.u.set_iopl.iopl = current->thread.io_pl = 1;
   27.45 +	HYPERVISOR_physdev_op(&op);
   27.46 +
   27.47  	/*
   27.48  	 * Parse the ACPI tables for possible boot-time SMP configuration.
   27.49  	 */
   27.50 @@ -1583,10 +1588,6 @@ void __init setup_arch(char **cmdline_p)
   27.51  
   27.52  	register_memory();
   27.53  
   27.54 -	op.cmd             = PHYSDEVOP_SET_IOPL;
   27.55 -	op.u.set_iopl.iopl = current->thread.io_pl = 1;
   27.56 -	HYPERVISOR_physdev_op(&op);
   27.57 -
   27.58  	if (xen_start_info.flags & SIF_INITDOMAIN) {
   27.59  		if (!(xen_start_info.flags & SIF_PRIVILEGED))
   27.60  			panic("Xen granted us console access "

    28.1 --- a/linux-2.6.11-xen-sparse/arch/xen/i386/mm/init.c	Tue May 03 14:42:00 2005 +0000
    28.2 +++ b/linux-2.6.11-xen-sparse/arch/xen/i386/mm/init.c	Tue May 10 08:49:59 2005 +0000
    28.3 @@ -361,6 +361,7 @@ static void __init pagetable_init (void)
    28.4  	make_page_writable(old_pgd);
    28.5  	__flush_tlb_all();
    28.6  	free_bootmem(__pa(old_pgd), PAGE_SIZE);
    28.7 +	init_mm.context.pinned = 1;
    28.8  
    28.9  	kernel_physical_mapping_init(pgd_base);
   28.10  	remap_numa_kva();
   28.11 @@ -562,7 +563,7 @@ void __init paging_init(void)
   28.12  	zone_sizes_init();
   28.13  
   28.14  	/* Switch to the real shared_info page, and clear the dummy page. */
   28.15 -	set_fixmap_ma(FIX_SHARED_INFO, xen_start_info.shared_info);
   28.16 +	set_fixmap(FIX_SHARED_INFO, xen_start_info.shared_info);
   28.17  	HYPERVISOR_shared_info = (shared_info_t *)fix_to_virt(FIX_SHARED_INFO);
   28.18  	memset(empty_zero_page, 0, sizeof(empty_zero_page));
   28.19  
   28.20 @@ -570,10 +571,11 @@ void __init paging_init(void)
   28.21  	/* Setup mapping of lower 1st MB */
   28.22  	for (i = 0; i < NR_FIX_ISAMAPS; i++)
   28.23  		if (xen_start_info.flags & SIF_PRIVILEGED)
   28.24 -			set_fixmap_ma(FIX_ISAMAP_BEGIN - i, i * PAGE_SIZE);
   28.25 +			set_fixmap(FIX_ISAMAP_BEGIN - i, i * PAGE_SIZE);
   28.26  		else
   28.27 -			set_fixmap_ma_ro(FIX_ISAMAP_BEGIN - i,
   28.28 -					 virt_to_machine(empty_zero_page));
   28.29 +			__set_fixmap(FIX_ISAMAP_BEGIN - i,
   28.30 +				     virt_to_machine(empty_zero_page),
   28.31 +				     PAGE_KERNEL_RO);
   28.32  #endif
   28.33  }
   28.34