1.1 --- a/.rootkeys	Mon May 09 14:34:59 2005 +0000
     1.2 +++ b/.rootkeys	Mon May 09 17:50:11 2005 +0000
     1.3 @@ -1185,7 +1185,7 @@ 421098b6lY2JzrV1oFDbrt7XQhtElg xen/arch/
     1.4  427664f5eygrc3nEhI3RKf0Y37PzyA xen/arch/ia64/xentime.c
     1.5  3ddb79bcZbRBzT3elFWSX7u6NtMagQ xen/arch/x86/Makefile
     1.6  3ddb79bcBQF85CfLS4i1WGZ4oLLaCA xen/arch/x86/Rules.mk
     1.7 -3e5636e5FAYZ5_vQnmgwFJfSdmO5Mw xen/arch/x86/acpi.c
     1.8 +3e5636e5FAYZ5_vQnmgwFJfSdmO5Mw xen/arch/x86/acpi/boot.c
     1.9  3ddb79bcsjinG9k1KcvbVBuas1R2dA xen/arch/x86/apic.c
    1.10  42360b3244-Q6BpEKhR_A1YtG1wPNQ xen/arch/x86/audit.c
    1.11  3ddb79c4yGZ7_22QAFFwPzqP4NSHwA xen/arch/x86/boot/mkelf32.c
    1.12 @@ -1247,6 +1247,7 @@ 40e96d3akN3Hu_J5Bk-WXD8OGscrYQ xen/arch/
    1.13  422f27c8J9DQfCpegccMid59XhSmGA xen/arch/x86/x86_emulate.c
    1.14  3ddb79bdff-gj-jFGKjOejeHLqL8Lg xen/common/Makefile
    1.15  3e397e66AyyD5fYraAySWuwi9uqSXg xen/common/ac_timer.c
    1.16 +427fa2d0J0LU2s5oKbsM0nTZ2iyd2Q xen/common/bitmap.c
    1.17  3ddb79bdLX_P6iB7ILiblRLWvebapg xen/common/dom0_ops.c
    1.18  3e6377e4i0c9GtKN65e99OtRbw3AZw xen/common/dom_mem_ops.c
    1.19  3ddb79bdYO5D8Av12NHqPeSviav7cg xen/common/domain.c
    1.20 @@ -1341,13 +1342,33 @@ 3ddb79c3TMDjkxVndKFKnGiwY0HzDg xen/inclu
    1.21  4204e7acwXDo-5iAAiO2eQbtDeYZXA xen/include/asm-x86/init.h
    1.22  3ddb79c3fQ_O3o5NHK2N8AJdk0Ea4Q xen/include/asm-x86/io.h
    1.23  3ddb79c2TKeScYHQZreTdHqYNLbehQ xen/include/asm-x86/io_apic.h
    1.24 -42605109qxLSrHVE2SRhGXmgk907iw xen/include/asm-x86/io_ports.h
    1.25  3ddb79c2L7rTlFzazOLW1XuSZefpFw xen/include/asm-x86/irq.h
    1.26  404f1b93OjLO4bFfBXYNaJdIqlNz-Q xen/include/asm-x86/ldt.h
    1.27 -4260510aYPj2kr6rMbBfMxcvvmXndQ xen/include/asm-x86/mach_apic.h
    1.28 +427fa2d0m8MOSSXT13zgb-q0fGA_Dw xen/include/asm-x86/mach-default/apm.h
    1.29 +427fa2d0suK9Av7vsAXhsQxZjqpc_Q xen/include/asm-x86/mach-default/bios_ebda.h
    1.30 +427fa2d0yC3KzLozoeK3Xa3uGVfIdw xen/include/asm-x86/mach-default/do_timer.h
    1.31 +427fa2d0bWQkR1mW5OBYxn07AN-bDw xen/include/asm-x86/mach-default/entry_arch.h
    1.32 +427fa2d0-SWcuwbdSypo4953bc2JdQ xen/include/asm-x86/mach-default/io_ports.h
    1.33 +427fa2d0eyAl7LAeO-SVV4IW7lZPGQ xen/include/asm-x86/mach-default/irq_vectors.h
    1.34 +427fa2d0df7VWG4KKpnKbKR2Cbd1_w xen/include/asm-x86/mach-default/irq_vectors_limits.h
    1.35 +4260510aYPj2kr6rMbBfMxcvvmXndQ xen/include/asm-x86/mach-default/mach_apic.h
    1.36 +427fa2d0I3FWjE2tWdOhlEOJn7stcg xen/include/asm-x86/mach-default/mach_apicdef.h
    1.37 +427fa2d093fDS2gOBLcl7Yndzl7HmA xen/include/asm-x86/mach-default/mach_ipi.h
    1.38 +427fa2d0Y7bD35d-FvDAeiJDIdRw2A xen/include/asm-x86/mach-default/mach_mpparse.h
    1.39 +427fa2d0aLQgE9e1GY9ZP5jrMOC8pQ xen/include/asm-x86/mach-default/mach_mpspec.h
    1.40 +427fa2d0fJ5nNn5ydJuOaZIL6F2fjQ xen/include/asm-x86/mach-default/mach_reboot.h
    1.41 +427fa2d0VlN555TE68TjKMsrOoFXNA xen/include/asm-x86/mach-default/mach_time.h
    1.42 +427fa2d0C0jWTKYjy7WJjGKeujSpSg xen/include/asm-x86/mach-default/mach_timer.h
    1.43 +427fa2d0UXLiS1scpNrK26ZT6Oes3g xen/include/asm-x86/mach-default/mach_traps.h
    1.44 +427fa2d0OfglYyfpDTD5DII4M0uZRw xen/include/asm-x86/mach-default/mach_wakecpu.h
    1.45 +427fa2d0_OBPxdi5Qo04JWgZhz7BFA xen/include/asm-x86/mach-default/pci-functions.h
    1.46 +427fa2d0mrTtXrliqDfLuJc5LLVXaA xen/include/asm-x86/mach-default/setup_arch_post.h
    1.47 +427fa2d0Uoo7gC61Kep6Yy7Os367Hg xen/include/asm-x86/mach-default/setup_arch_pre.h
    1.48 +427fa2d1EKnA8zCq2QLHiGOUqOgszg xen/include/asm-x86/mach-default/smpboot_hooks.h
    1.49  3ddb79c3I98vWcQR8xEo34JMJ4Ahyw xen/include/asm-x86/mc146818rtc.h
    1.50  40ec25fd7cSvbP7Biw91zaU_g0xsEQ xen/include/asm-x86/mm.h
    1.51  3ddb79c3n_UbPuxlkNxvvLycClIkxA xen/include/asm-x86/mpspec.h
    1.52 +427fa2d1eJRenftJJnRyLsHKl1ghtA xen/include/asm-x86/mpspec_def.h
    1.53  3ddb79c2wa0dA_LGigxOelSGbJ284Q xen/include/asm-x86/msr.h
    1.54  41aaf567Mi3OishhvrCtET1y-mxQBg xen/include/asm-x86/mtrr.h
    1.55  41a61536MFhNalgbVmYGXAhQsPTZNw xen/include/asm-x86/multicall.h
    1.56 @@ -1409,11 +1430,14 @@ 4266bd01Ul-pC01ZVvBkhBnv5eqzvw xen/inclu
    1.57  3ddb79c25UE59iu4JJcbRalx95mvcg xen/include/public/xen.h
    1.58  3e397e66m2tO3s-J8Jnr7Ws_tGoPTg xen/include/xen/ac_timer.h
    1.59  40715b2epYl2jBbxzz9CI2rgIca7Zg xen/include/xen/acpi.h
    1.60 +427fa2d1wyoVbvCyZRLposYjA_D_4g xen/include/xen/bitmap.h
    1.61 +427fa2d1ItcC_yWuBUkhc7adedP5ow xen/include/xen/bitops.h
    1.62  3ddb79c0c0cX_DZE209-Bb-Rx1v-Aw xen/include/xen/cache.h
    1.63  41f2cea7Yna7xc0X9fyavIjoSFFeVg xen/include/xen/compile.h.in
    1.64  3f840f12CkbYSlwMrY2S11Mpyxg7Nw xen/include/xen/compiler.h
    1.65  3ddb79c259jh8hE7vre_8NuE7nwNSA xen/include/xen/config.h
    1.66  3eb165e0eawr3R-p2ZQtSdLWtLRN_A xen/include/xen/console.h
    1.67 +427fa2d1bQCWgEQqTTh5MjG4MPEH9g xen/include/xen/cpumask.h
    1.68  3ddb79c1V44RD26YqCUm-kqIupM37A xen/include/xen/ctype.h
    1.69  3ddb79c05DdHQ0UxX_jKsXdR4QlMCA xen/include/xen/delay.h
    1.70  40f2b4a2hC3HtChu-ArD8LyojxWMjg xen/include/xen/domain.h

     2.1 --- a/xen/arch/x86/Makefile	Mon May 09 14:34:59 2005 +0000
     2.2 +++ b/xen/arch/x86/Makefile	Mon May 09 17:50:11 2005 +0000
     2.3 @@ -3,6 +3,7 @@ include $(BASEDIR)/Rules.mk
     2.4  
     2.5  OBJS += $(patsubst %.S,%.o,$(wildcard $(TARGET_SUBARCH)/*.S))
     2.6  OBJS += $(patsubst %.c,%.o,$(wildcard $(TARGET_SUBARCH)/*.c))
     2.7 +OBJS += $(patsubst %.c,%.o,$(wildcard acpi/*.c))
     2.8  OBJS += $(patsubst %.c,%.o,$(wildcard mtrr/*.c))
     2.9  
    2.10  OBJS := $(subst $(TARGET_SUBARCH)/asm-offsets.o,,$(OBJS))

     3.1 --- a/xen/arch/x86/Rules.mk	Mon May 09 14:34:59 2005 +0000
     3.2 +++ b/xen/arch/x86/Rules.mk	Mon May 09 17:50:11 2005 +0000
     3.3 @@ -2,8 +2,8 @@
     3.4  # x86-specific definitions
     3.5  
     3.6  CFLAGS  += -nostdinc -fno-builtin -fno-common -fno-strict-aliasing
     3.7 -CFLAGS  += -iwithprefix include -Wall -Werror -pipe
     3.8 -CFLAGS  += -I$(BASEDIR)/include -Wno-pointer-arith -Wredundant-decls
     3.9 +CFLAGS  += -iwithprefix include -Wall -Werror -Wno-pointer-arith -pipe
    3.10 +CFLAGS  += -I$(BASEDIR)/include -I$(BASEDIR)/include/asm-x86/mach-default
    3.11  
    3.12  ifeq ($(optimize),y)
    3.13  CFLAGS  += -O3 -fomit-frame-pointer

     4.1 --- a/xen/arch/x86/acpi.c	Mon May 09 14:34:59 2005 +0000
     4.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.3 @@ -1,729 +0,0 @@
     4.4 -/*
     4.5 - *  acpi.c - Architecture-Specific Low-Level ACPI Support
     4.6 - *
     4.7 - *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
     4.8 - *  Copyright (C) 2001 Jun Nakajima <jun.nakajima@intel.com>
     4.9 - *  Copyright (C) 2001 Patrick Mochel <mochel@osdl.org>
    4.10 - *
    4.11 - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    4.12 - *
    4.13 - *  This program is free software; you can redistribute it and/or modify
    4.14 - *  it under the terms of the GNU General Public License as published by
    4.15 - *  the Free Software Foundation; either version 2 of the License, or
    4.16 - *  (at your option) any later version.
    4.17 - *
    4.18 - *  This program is distributed in the hope that it will be useful,
    4.19 - *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    4.20 - *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    4.21 - *  GNU General Public License for more details.
    4.22 - *
    4.23 - *  You should have received a copy of the GNU General Public License
    4.24 - *  along with this program; if not, write to the Free Software
    4.25 - *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
    4.26 - *
    4.27 - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    4.28 - */
    4.29 -
    4.30 -#include <xen/config.h>
    4.31 -#include <xen/kernel.h>
    4.32 -#include <xen/init.h>
    4.33 -#include <xen/types.h>
    4.34 -#include <xen/slab.h>
    4.35 -#include <xen/pci.h>
    4.36 -#include <xen/irq.h>
    4.37 -#include <xen/acpi.h>
    4.38 -#include <asm/mpspec.h>
    4.39 -#include <asm/io.h>
    4.40 -#include <asm/apic.h>
    4.41 -#include <asm/apicdef.h>
    4.42 -#include <asm/page.h>
    4.43 -#include <asm/io_apic.h>
    4.44 -#include <asm/acpi.h>
    4.45 -#include <asm/smpboot.h>
    4.46 -
    4.47 -
    4.48 -#define PREFIX			"ACPI: "
    4.49 -
    4.50 -int acpi_lapic;
    4.51 -int acpi_ioapic;
    4.52 -int acpi_strict;
    4.53 -
    4.54 -acpi_interrupt_flags acpi_sci_flags __initdata;
    4.55 -int acpi_sci_override_gsi __initdata;
    4.56 -/* --------------------------------------------------------------------------
    4.57 -                              Boot-time Configuration
    4.58 -   -------------------------------------------------------------------------- */
    4.59 -
    4.60 -int acpi_noirq __initdata = 0;  /* skip ACPI IRQ initialization */
    4.61 -int acpi_ht __initdata = 1;     /* enable HT */
    4.62 -
    4.63 -enum acpi_irq_model_id		acpi_irq_model;
    4.64 -
    4.65 -
    4.66 -/*
    4.67 - * Temporarily use the virtual area starting from FIX_IO_APIC_BASE_END,
    4.68 - * to map the target physical address. The problem is that set_fixmap()
    4.69 - * provides a single page, and it is possible that the page is not
    4.70 - * sufficient.
    4.71 - * By using this area, we can map up to MAX_IO_APICS pages temporarily,
    4.72 - * i.e. until the next __va_range() call.
    4.73 - *
    4.74 - * Important Safety Note:  The fixed I/O APIC page numbers are *subtracted*
    4.75 - * from the fixed base.  That's why we start at FIX_IO_APIC_BASE_END and
    4.76 - * count idx down while incrementing the phys address.
    4.77 - */
    4.78 -char *__acpi_map_table(unsigned long phys, unsigned long size)
    4.79 -{
    4.80 -	unsigned long base, offset, mapped_size;
    4.81 -	int idx;
    4.82 -
    4.83 -	if (phys + size < 8*1024*1024) 
    4.84 -		return __va(phys); 
    4.85 -
    4.86 -	offset = phys & (PAGE_SIZE - 1);
    4.87 -	mapped_size = PAGE_SIZE - offset;
    4.88 -	set_fixmap(FIX_ACPI_END, phys);
    4.89 -	base = fix_to_virt(FIX_ACPI_END);
    4.90 -
    4.91 -	/*
    4.92 -	 * Most cases can be covered by the below.
    4.93 -	 */
    4.94 -	idx = FIX_ACPI_END;
    4.95 -	while (mapped_size < size) {
    4.96 -		if (--idx < FIX_ACPI_BEGIN)
    4.97 -			return 0;	/* cannot handle this */
    4.98 -		phys += PAGE_SIZE;
    4.99 -		set_fixmap(idx, phys);
   4.100 -		mapped_size += PAGE_SIZE;
   4.101 -	}
   4.102 -
   4.103 -	return ((char *) base + offset);
   4.104 -}
   4.105 -
   4.106 -
   4.107 -#ifdef CONFIG_X86_LOCAL_APIC
   4.108 -
   4.109 -static u64 acpi_lapic_addr __initdata = APIC_DEFAULT_PHYS_BASE;
   4.110 -
   4.111 -
   4.112 -static int __init
   4.113 -acpi_parse_madt (
   4.114 -	unsigned long		phys_addr,
   4.115 -	unsigned long		size)
   4.116 -{
   4.117 -	struct acpi_table_madt	*madt = NULL;
   4.118 -
   4.119 -	if (!phys_addr || !size)
   4.120 -		return -EINVAL;
   4.121 -
   4.122 -	madt = (struct acpi_table_madt *) __acpi_map_table(phys_addr, size);
   4.123 -	if (!madt) {
   4.124 -		printk(KERN_WARNING PREFIX "Unable to map MADT\n");
   4.125 -		return -ENODEV;
   4.126 -	}
   4.127 -
   4.128 -	if (madt->lapic_address)
   4.129 -		acpi_lapic_addr = (u64) madt->lapic_address;
   4.130 -
   4.131 -	printk(KERN_INFO PREFIX "Local APIC address 0x%08x\n",
   4.132 -		madt->lapic_address);
   4.133 -
   4.134 -	detect_clustered_apic(madt->header.oem_id, madt->header.oem_table_id);
   4.135 -
   4.136 -	return 0;
   4.137 -}
   4.138 -
   4.139 -
   4.140 -static int __init
   4.141 -acpi_parse_lapic (
   4.142 -	acpi_table_entry_header *header)
   4.143 -{
   4.144 -	struct acpi_table_lapic	*processor = NULL;
   4.145 -
   4.146 -	processor = (struct acpi_table_lapic*) header;
   4.147 -	if (!processor)
   4.148 -		return -EINVAL;
   4.149 -
   4.150 -	acpi_table_print_madt_entry(header);
   4.151 -
   4.152 -	mp_register_lapic (
   4.153 -		processor->id,					   /* APIC ID */
   4.154 -		processor->flags.enabled);			  /* Enabled? */
   4.155 -
   4.156 -	return 0;
   4.157 -}
   4.158 -
   4.159 -
   4.160 -static int __init
   4.161 -acpi_parse_lapic_addr_ovr (
   4.162 -	acpi_table_entry_header *header)
   4.163 -{
   4.164 -	struct acpi_table_lapic_addr_ovr *lapic_addr_ovr = NULL;
   4.165 -
   4.166 -	lapic_addr_ovr = (struct acpi_table_lapic_addr_ovr*) header;
   4.167 -	if (!lapic_addr_ovr)
   4.168 -		return -EINVAL;
   4.169 -
   4.170 -	acpi_lapic_addr = lapic_addr_ovr->address;
   4.171 -
   4.172 -	return 0;
   4.173 -}
   4.174 -
   4.175 -static int __init
   4.176 -acpi_parse_lapic_nmi (
   4.177 -	acpi_table_entry_header *header)
   4.178 -{
   4.179 -	struct acpi_table_lapic_nmi *lapic_nmi = NULL;
   4.180 -
   4.181 -	lapic_nmi = (struct acpi_table_lapic_nmi*) header;
   4.182 -	if (!lapic_nmi)
   4.183 -		return -EINVAL;
   4.184 -
   4.185 -	acpi_table_print_madt_entry(header);
   4.186 -
   4.187 -	if (lapic_nmi->lint != 1)
   4.188 -		printk(KERN_WARNING PREFIX "NMI not connected to LINT 1!\n");
   4.189 -
   4.190 -	return 0;
   4.191 -}
   4.192 -
   4.193 -#endif /*CONFIG_X86_LOCAL_APIC*/
   4.194 -
   4.195 -#if defined(CONFIG_X86_IO_APIC) /*&& defined(CONFIG_ACPI_INTERPRETER)*/
   4.196 -
   4.197 -static int __init
   4.198 -acpi_parse_ioapic (
   4.199 -	acpi_table_entry_header *header)
   4.200 -{
   4.201 -	struct acpi_table_ioapic *ioapic = NULL;
   4.202 -
   4.203 -	ioapic = (struct acpi_table_ioapic*) header;
   4.204 -	if (!ioapic)
   4.205 -		return -EINVAL;
   4.206 - 
   4.207 -	acpi_table_print_madt_entry(header);
   4.208 -
   4.209 -	mp_register_ioapic (
   4.210 -		ioapic->id,
   4.211 -		ioapic->address,
   4.212 -		ioapic->global_irq_base);
   4.213 - 
   4.214 -	return 0;
   4.215 -}
   4.216 -
   4.217 -#ifdef CONFIG_ACPI_INTERPRETER
   4.218 -/*
   4.219 - * Parse Interrupt Source Override for the ACPI SCI
   4.220 - */
   4.221 -static void
   4.222 -acpi_sci_ioapic_setup(u32 gsi, u16 polarity, u16 trigger)
   4.223 -{
   4.224 -	if (trigger == 0)	/* compatible SCI trigger is level */
   4.225 -		trigger = 3;
   4.226 -
   4.227 -	if (polarity == 0)	/* compatible SCI polarity is low */
   4.228 -		polarity = 3;
   4.229 -
   4.230 -	/* Command-line over-ride via acpi_sci= */
   4.231 -	if (acpi_sci_flags.trigger)
   4.232 -		trigger = acpi_sci_flags.trigger;
   4.233 -
   4.234 -	if (acpi_sci_flags.polarity)
   4.235 -		polarity = acpi_sci_flags.polarity;
   4.236 -
   4.237 -	/*
   4.238 - 	 * mp_config_acpi_legacy_irqs() already setup IRQs < 16
   4.239 -	 * If GSI is < 16, this will update its flags,
   4.240 -	 * else it will create a new mp_irqs[] entry.
   4.241 -	 */
   4.242 -	mp_override_legacy_irq(gsi, polarity, trigger, gsi);
   4.243 -
   4.244 -	/*
   4.245 -	 * stash over-ride to indicate we've been here
   4.246 -	 * and for later update of acpi_fadt
   4.247 -	 */
   4.248 -	acpi_sci_override_gsi = gsi;
   4.249 -	return;
   4.250 -}
   4.251 -#endif
   4.252 -
   4.253 -static int __init
   4.254 -acpi_parse_fadt(unsigned long phys, unsigned long size)
   4.255 -{
   4.256 -        struct fadt_descriptor_rev2 *fadt =0;
   4.257 -
   4.258 -        fadt = (struct fadt_descriptor_rev2*) __acpi_map_table(phys,size);
   4.259 -        if (!fadt) {
   4.260 -                printk(KERN_WARNING PREFIX "Unable to map FADT\n");
   4.261 -                return 0;
   4.262 -        }
   4.263 -
   4.264 -#ifdef  CONFIG_ACPI_INTERPRETER
   4.265 -        /* initialize sci_int early for INT_SRC_OVR MADT parsing */
   4.266 -        acpi_fadt.sci_int = fadt->sci_int;
   4.267 -#endif
   4.268 -
   4.269 -        return 0;
   4.270 -}
   4.271 -
   4.272 -
   4.273 -static int __init
   4.274 -acpi_parse_int_src_ovr (
   4.275 -	acpi_table_entry_header *header)
   4.276 -{
   4.277 -	struct acpi_table_int_src_ovr *intsrc = NULL;
   4.278 -
   4.279 -	intsrc = (struct acpi_table_int_src_ovr*) header;
   4.280 -	if (!intsrc)
   4.281 -		return -EINVAL;
   4.282 -
   4.283 -	acpi_table_print_madt_entry(header);
   4.284 -
   4.285 -#ifdef CONFIG_ACPI_INTERPRETER
   4.286 -	if (intsrc->bus_irq == acpi_fadt.sci_int) {
   4.287 -		acpi_sci_ioapic_setup(intsrc->global_irq,
   4.288 -			intsrc->flags.polarity, intsrc->flags.trigger);
   4.289 -		return 0;
   4.290 -	}
   4.291 -#endif
   4.292 -
   4.293 -	mp_override_legacy_irq (
   4.294 -		intsrc->bus_irq,
   4.295 -		intsrc->flags.polarity,
   4.296 -		intsrc->flags.trigger,
   4.297 -		intsrc->global_irq);
   4.298 -
   4.299 -	return 0;
   4.300 -}
   4.301 -
   4.302 -
   4.303 -static int __init
   4.304 -acpi_parse_nmi_src (
   4.305 -	acpi_table_entry_header *header)
   4.306 -{
   4.307 -	struct acpi_table_nmi_src *nmi_src = NULL;
   4.308 -
   4.309 -	nmi_src = (struct acpi_table_nmi_src*) header;
   4.310 -	if (!nmi_src)
   4.311 -		return -EINVAL;
   4.312 -
   4.313 -	acpi_table_print_madt_entry(header);
   4.314 -
   4.315 -	/* TBD: Support nimsrc entries? */
   4.316 -
   4.317 -	return 0;
   4.318 -}
   4.319 -
   4.320 -#endif /*CONFIG_X86_IO_APIC && CONFIG_ACPI_INTERPRETER*/
   4.321 -
   4.322 -
   4.323 -static unsigned long __init
   4.324 -acpi_scan_rsdp (
   4.325 -	unsigned long		start,
   4.326 -	unsigned long		length)
   4.327 -{
   4.328 -	unsigned long		offset = 0;
   4.329 -	unsigned long		sig_len = sizeof("RSD PTR ") - 1;
   4.330 -
   4.331 -	/*
   4.332 -	 * Scan all 16-byte boundaries of the physical memory region for the
   4.333 -	 * RSDP signature.
   4.334 -	 */
   4.335 -	for (offset = 0; offset < length; offset += 16) {
   4.336 -		if (strncmp((char *) (start + offset), "RSD PTR ", sig_len))
   4.337 -			continue;
   4.338 -		return (start + offset);
   4.339 -	}
   4.340 -
   4.341 -	return 0;
   4.342 -}
   4.343 -
   4.344 -
   4.345 -unsigned long __init
   4.346 -acpi_find_rsdp (void)
   4.347 -{
   4.348 -	unsigned long		rsdp_phys = 0;
   4.349 -
   4.350 -	/*
   4.351 -	 * Scan memory looking for the RSDP signature. First search EBDA (low
   4.352 -	 * memory) paragraphs and then search upper memory (E0000-FFFFF).
   4.353 -	 */
   4.354 -	rsdp_phys = acpi_scan_rsdp (0, 0x400);
   4.355 -	if (!rsdp_phys)
   4.356 -		rsdp_phys = acpi_scan_rsdp (0xE0000, 0x20000);
   4.357 -
   4.358 -	return rsdp_phys;
   4.359 -}
   4.360 -
   4.361 -
   4.362 -/*
   4.363 - * acpi_boot_init()
   4.364 - *  called from setup_arch(), always.
   4.365 - *	1. maps ACPI tables for later use
   4.366 - *	2. enumerates lapics
   4.367 - *	3. enumerates io-apics
   4.368 - *
   4.369 - * side effects:
   4.370 - * 	acpi_lapic = 1 if LAPIC found
   4.371 - *	acpi_ioapic = 1 if IOAPIC found
   4.372 - *	if (acpi_lapic && acpi_ioapic) smp_found_config = 1;
   4.373 - *	if acpi_blacklisted() disable_acpi()
   4.374 - *	acpi_irq_model=...
   4.375 - *	...
   4.376 - *
   4.377 - * return value: (currently ignored)
   4.378 - *	0: success
   4.379 - *	!0: failure
   4.380 - */
   4.381 -int __init
   4.382 -acpi_boot_init (void)
   4.383 -{
   4.384 -	int			result = 0;
   4.385 -
   4.386 -	if (acpi_disabled && !acpi_ht)
   4.387 -		return(1);
   4.388 -
   4.389 -	/*
   4.390 -	 * The default interrupt routing model is PIC (8259).  This gets
   4.391 -	 * overriden if IOAPICs are enumerated (below).
   4.392 -	 */
   4.393 -	acpi_irq_model = ACPI_IRQ_MODEL_PIC;
   4.394 -
   4.395 -	/* 
   4.396 -	 * Initialize the ACPI boot-time table parser.
   4.397 -	 */
   4.398 -	result = acpi_table_init();
   4.399 -	if (result) {
   4.400 -		disable_acpi();
   4.401 -		return result;
   4.402 -	}
   4.403 -
   4.404 -	result = acpi_blacklisted();
   4.405 -	if (result) {
   4.406 -		printk(KERN_NOTICE PREFIX "BIOS listed in blacklist, disabling ACPI support\n");
   4.407 -		disable_acpi();
   4.408 -		return result;
   4.409 -	}
   4.410 -
   4.411 -#ifdef CONFIG_X86_LOCAL_APIC
   4.412 -
   4.413 -	/* 
   4.414 -	 * MADT
   4.415 -	 * ----
   4.416 -	 * Parse the Multiple APIC Description Table (MADT), if exists.
   4.417 -	 * Note that this table provides platform SMP configuration 
   4.418 -	 * information -- the successor to MPS tables.
   4.419 -	 */
   4.420 -
   4.421 -	result = acpi_table_parse(ACPI_APIC, acpi_parse_madt);
   4.422 -	if (!result) {
   4.423 -		return 0;
   4.424 -	}
   4.425 -	else if (result < 0) {
   4.426 -		printk(KERN_ERR PREFIX "Error parsing MADT\n");
   4.427 -		return result;
   4.428 -	}
   4.429 -	else if (result > 1) 
   4.430 -		printk(KERN_WARNING PREFIX "Multiple MADT tables exist\n");
   4.431 -
   4.432 -	/* 
   4.433 -	 * Local APIC
   4.434 -	 * ----------
   4.435 -	 * Note that the LAPIC address is obtained from the MADT (32-bit value)
   4.436 -	 * and (optionally) overriden by a LAPIC_ADDR_OVR entry (64-bit value).
   4.437 -	 */
   4.438 -
   4.439 -	result = acpi_table_parse_madt(ACPI_MADT_LAPIC_ADDR_OVR, acpi_parse_lapic_addr_ovr);
   4.440 -	if (result < 0) {
   4.441 -		printk(KERN_ERR PREFIX "Error parsing LAPIC address override entry\n");
   4.442 -		return result;
   4.443 -	}
   4.444 -
   4.445 -	mp_register_lapic_address(acpi_lapic_addr);
   4.446 -
   4.447 -	result = acpi_table_parse_madt(ACPI_MADT_LAPIC, acpi_parse_lapic);
   4.448 -	if (!result) { 
   4.449 -		printk(KERN_ERR PREFIX "No LAPIC entries present\n");
   4.450 -		/* TBD: Cleanup to allow fallback to MPS */
   4.451 -		return -ENODEV;
   4.452 -	}
   4.453 -	else if (result < 0) {
   4.454 -		printk(KERN_ERR PREFIX "Error parsing LAPIC entry\n");
   4.455 -		/* TBD: Cleanup to allow fallback to MPS */
   4.456 -		return result;
   4.457 -	}
   4.458 -
   4.459 -	result = acpi_table_parse_madt(ACPI_MADT_LAPIC_NMI, acpi_parse_lapic_nmi);
   4.460 -	if (result < 0) {
   4.461 -		printk(KERN_ERR PREFIX "Error parsing LAPIC NMI entry\n");
   4.462 -		/* TBD: Cleanup to allow fallback to MPS */
   4.463 -		return result;
   4.464 -	}
   4.465 -
   4.466 -	acpi_lapic = 1;
   4.467 -
   4.468 -#endif /*CONFIG_X86_LOCAL_APIC*/
   4.469 -
   4.470 -#if defined(CONFIG_X86_IO_APIC) /*&& defined(CONFIG_ACPI_INTERPRETER)*/
   4.471 -
   4.472 -	/* 
   4.473 -	 * I/O APIC 
   4.474 -	 * --------
   4.475 -	 */
   4.476 -
   4.477 -#if 0
   4.478 -	/*
   4.479 -	 * ACPI interpreter is required to complete interrupt setup,
   4.480 -	 * so if it is off, don't enumerate the io-apics with ACPI.
   4.481 -	 * If MPS is present, it will handle them,
   4.482 -	 * otherwise the system will stay in PIC mode
   4.483 -	 */
   4.484 -	if (acpi_disabled || acpi_noirq) {
   4.485 -		return 1;
   4.486 -	}
   4.487 -#endif
   4.488 -
   4.489 -	/*
   4.490 -	 * if "noapic" boot option, don't look for IO-APICs
   4.491 -	 */
   4.492 -	if (ioapic_setup_disabled()) {
   4.493 -		printk(KERN_INFO PREFIX "Skipping IOAPIC probe "
   4.494 -			"due to 'noapic' option.\n");
   4.495 -		return 1;
   4.496 -        }
   4.497 -
   4.498 -
   4.499 -	result = acpi_table_parse_madt(ACPI_MADT_IOAPIC, acpi_parse_ioapic);
   4.500 -	if (!result) { 
   4.501 -		printk(KERN_ERR PREFIX "No IOAPIC entries present\n");
   4.502 -		return -ENODEV;
   4.503 -	}
   4.504 -	else if (result < 0) {
   4.505 -		printk(KERN_ERR PREFIX "Error parsing IOAPIC entry\n");
   4.506 -		return result;
   4.507 -	}
   4.508 -
   4.509 -	/* Build a default routing table for legacy (ISA) interrupts. */
   4.510 -	mp_config_acpi_legacy_irqs();
   4.511 -
   4.512 -	/* Record sci_int for use when looking for MADT sci_int override */
   4.513 -	acpi_table_parse(ACPI_FADT, acpi_parse_fadt);
   4.514 -
   4.515 -	result = acpi_table_parse_madt(ACPI_MADT_INT_SRC_OVR, acpi_parse_int_src_ovr);
   4.516 -	if (result < 0) {
   4.517 -		printk(KERN_ERR PREFIX "Error parsing interrupt source overrides entry\n");
   4.518 -		/* TBD: Cleanup to allow fallback to MPS */
   4.519 -		return result;
   4.520 -	}
   4.521 -
   4.522 -#ifdef CONFIG_ACPI_INTERPRETER
   4.523 -	/*
   4.524 -	 * If BIOS did not supply an INT_SRC_OVR for the SCI
   4.525 -	 * pretend we got one so we can set the SCI flags.
   4.526 -	 */
   4.527 -	if (!acpi_sci_override_gsi)
   4.528 -		acpi_sci_ioapic_setup(acpi_fadt.sci_int, 0, 0);
   4.529 -#endif
   4.530 -
   4.531 -	result = acpi_table_parse_madt(ACPI_MADT_NMI_SRC, acpi_parse_nmi_src);
   4.532 -	if (result < 0) {
   4.533 -		printk(KERN_ERR PREFIX "Error parsing NMI SRC entry\n");
   4.534 -		/* TBD: Cleanup to allow fallback to MPS */
   4.535 -		return result;
   4.536 -	}
   4.537 -
   4.538 -	acpi_irq_model = ACPI_IRQ_MODEL_IOAPIC;
   4.539 -
   4.540 -	acpi_irq_balance_set(NULL);
   4.541 -
   4.542 -	acpi_ioapic = 1;
   4.543 -
   4.544 -	if (acpi_lapic && acpi_ioapic)
   4.545 -		smp_found_config = 1;
   4.546 -
   4.547 -#endif /*CONFIG_X86_IO_APIC && CONFIG_ACPI_INTERPRETER*/
   4.548 -
   4.549 -	return 0;
   4.550 -}
   4.551 -
   4.552 -
   4.553 -#ifdef	CONFIG_ACPI_BUS
   4.554 -/*
   4.555 - * acpi_pic_sci_set_trigger()
   4.556 - *
   4.557 - * use ELCR to set PIC-mode trigger type for SCI
   4.558 - *
   4.559 - * If a PIC-mode SCI is not recognized or gives spurious IRQ7's
   4.560 - * it may require Edge Trigger -- use "acpi_sci=edge"
   4.561 - *
   4.562 - * Port 0x4d0-4d1 are ECLR1 and ECLR2, the Edge/Level Control Registers
   4.563 - * for the 8259 PIC.  bit[n] = 1 means irq[n] is Level, otherwise Edge.
   4.564 - * ECLR1 is IRQ's 0-7 (IRQ 0, 1, 2 must be 0)
   4.565 - * ECLR2 is IRQ's 8-15 (IRQ 8, 13 must be 0)
   4.566 - */
   4.567 -
   4.568 -void __init
   4.569 -acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger)
   4.570 -{
   4.571 -	unsigned char mask = 1 << (irq & 7);
   4.572 -	unsigned int port = 0x4d0 + (irq >> 3);
   4.573 -	unsigned char val = inb(port);
   4.574 -
   4.575 -
   4.576 -	printk(PREFIX "IRQ%d SCI:", irq);
   4.577 -	if (!(val & mask)) {
   4.578 -		printk(" Edge");
   4.579 -
   4.580 -		if (trigger == 3) {
   4.581 -			printk(" set to Level");
   4.582 -			outb(val | mask, port);
   4.583 -		}
   4.584 -	} else {
   4.585 -		printk(" Level");
   4.586 -
   4.587 -		if (trigger == 1) {
   4.588 -			printk(" set to Edge");
   4.589 -			outb(val & ~mask, port);
   4.590 -		}
   4.591 -	}
   4.592 -	printk(" Trigger.\n");
   4.593 -}
   4.594 -
   4.595 -#endif /* CONFIG_ACPI_BUS */
   4.596 -
   4.597 -
   4.598 -/* --------------------------------------------------------------------------
   4.599 -                              Low-Level Sleep Support
   4.600 -   -------------------------------------------------------------------------- */
   4.601 -
   4.602 -#ifdef CONFIG_ACPI_SLEEP
   4.603 -
   4.604 -#define DEBUG
   4.605 -
   4.606 -#ifdef DEBUG
   4.607 -#include <xen/serial.h>
   4.608 -#endif
   4.609 -
   4.610 -/* address in low memory of the wakeup routine. */
   4.611 -unsigned long acpi_wakeup_address = 0;
   4.612 -
   4.613 -/* new page directory that we will be using */
   4.614 -static pmd_t *pmd;
   4.615 -
   4.616 -/* saved page directory */
   4.617 -static pmd_t saved_pmd;
   4.618 -
   4.619 -/* page which we'll use for the new page directory */
   4.620 -static pte_t *ptep;
   4.621 -
   4.622 -extern unsigned long FASTCALL(acpi_copy_wakeup_routine(unsigned long));
   4.623 -
   4.624 -/*
   4.625 - * acpi_create_identity_pmd
   4.626 - *
   4.627 - * Create a new, identity mapped pmd.
   4.628 - *
   4.629 - * Do this by creating new page directory, and marking all the pages as R/W
   4.630 - * Then set it as the new Page Middle Directory.
   4.631 - * And, of course, flush the TLB so it takes effect.
   4.632 - *
   4.633 - * We save the address of the old one, for later restoration.
   4.634 - */
   4.635 -static void acpi_create_identity_pmd (void)
   4.636 -{
   4.637 -	pgd_t *pgd;
   4.638 -	int i;
   4.639 -
   4.640 -	ptep = (pte_t*)__get_free_page(GFP_KERNEL);
   4.641 -
   4.642 -	/* fill page with low mapping */
   4.643 -	for (i = 0; i < PTRS_PER_PTE; i++)
   4.644 -		set_pte(ptep + i, mk_pte_phys(i << PAGE_SHIFT, PAGE_SHARED));
   4.645 -
   4.646 -	pgd = pgd_offset(current->active_mm, 0);
   4.647 -	pmd = pmd_alloc(current->mm,pgd, 0);
   4.648 -
   4.649 -	/* save the old pmd */
   4.650 -	saved_pmd = *pmd;
   4.651 -
   4.652 -	/* set the new one */
   4.653 -	set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(ptep)));
   4.654 -
   4.655 -	/* flush the TLB */
   4.656 -	local_flush_tlb();
   4.657 -}
   4.658 -
   4.659 -/*
   4.660 - * acpi_restore_pmd
   4.661 - *
   4.662 - * Restore the old pmd saved by acpi_create_identity_pmd and
   4.663 - * free the page that said function alloc'd
   4.664 - */
   4.665 -static void acpi_restore_pmd (void)
   4.666 -{
   4.667 -	set_pmd(pmd, saved_pmd);
   4.668 -	local_flush_tlb();
   4.669 -	free_page((unsigned long)ptep);
   4.670 -}
   4.671 -
   4.672 -/**
   4.673 - * acpi_save_state_mem - save kernel state
   4.674 - *
   4.675 - * Create an identity mapped page table and copy the wakeup routine to
   4.676 - * low memory.
   4.677 - */
   4.678 -int acpi_save_state_mem (void)
   4.679 -{
   4.680 -	acpi_create_identity_pmd();
   4.681 -	acpi_copy_wakeup_routine(acpi_wakeup_address);
   4.682 -
   4.683 -	return 0;
   4.684 -}
   4.685 -
   4.686 -/**
   4.687 - * acpi_save_state_disk - save kernel state to disk
   4.688 - *
   4.689 - */
   4.690 -int acpi_save_state_disk (void)
   4.691 -{
   4.692 -	return 1;
   4.693 -}
   4.694 -
   4.695 -/*
   4.696 - * acpi_restore_state
   4.697 - */
   4.698 -void acpi_restore_state_mem (void)
   4.699 -{
   4.700 -	acpi_restore_pmd();
   4.701 -}
   4.702 -
   4.703 -/**
   4.704 - * acpi_reserve_bootmem - do _very_ early ACPI initialisation
   4.705 - *
   4.706 - * We allocate a page in low memory for the wakeup
   4.707 - * routine for when we come back from a sleep state. The
   4.708 - * runtime allocator allows specification of <16M pages, but not
   4.709 - * <1M pages.
   4.710 - */
   4.711 -void __init acpi_reserve_bootmem(void)
   4.712 -{
   4.713 -	acpi_wakeup_address = (unsigned long)alloc_bootmem_low(PAGE_SIZE);
   4.714 -	if (!acpi_wakeup_address)
   4.715 -		printk(KERN_ERR "ACPI: Cannot allocate lowmem, S3 disabled.\n");
   4.716 -}
   4.717 -
   4.718 -void do_suspend_lowlevel_s4bios(int resume)
   4.719 -{
   4.720 -	if (!resume) {
   4.721 -		save_processor_context();
   4.722 -		acpi_save_register_state((unsigned long)&&acpi_sleep_done);
   4.723 -		acpi_enter_sleep_state_s4bios();
   4.724 -		return;
   4.725 -	}
   4.726 -acpi_sleep_done:
   4.727 -	restore_processor_context();
   4.728 -}
   4.729 -
   4.730 -
   4.731 -#endif /*CONFIG_ACPI_SLEEP*/
   4.732 -

     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/xen/arch/x86/acpi/boot.c	Mon May 09 17:50:11 2005 +0000
     5.3 @@ -0,0 +1,912 @@
     5.4 +/*
     5.5 + *  boot.c - Architecture-Specific Low-Level ACPI Boot Support
     5.6 + *
     5.7 + *  Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
     5.8 + *  Copyright (C) 2001 Jun Nakajima <jun.nakajima@intel.com>
     5.9 + *
    5.10 + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    5.11 + *
    5.12 + *  This program is free software; you can redistribute it and/or modify
    5.13 + *  it under the terms of the GNU General Public License as published by
    5.14 + *  the Free Software Foundation; either version 2 of the License, or
    5.15 + *  (at your option) any later version.
    5.16 + *
    5.17 + *  This program is distributed in the hope that it will be useful,
    5.18 + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    5.19 + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    5.20 + *  GNU General Public License for more details.
    5.21 + *
    5.22 + *  You should have received a copy of the GNU General Public License
    5.23 + *  along with this program; if not, write to the Free Software
    5.24 + *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
    5.25 + *
    5.26 + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    5.27 + */
    5.28 +
    5.29 +#include <xen/config.h>
    5.30 +#include <xen/errno.h>
    5.31 +#include <xen/init.h>
    5.32 +#include <xen/acpi.h>
    5.33 +#include <xen/irq.h>
    5.34 +#include <xen/sched.h>
    5.35 +#include <asm/page.h>
    5.36 +#include <asm/apic.h>
    5.37 +#include <asm/io_apic.h>
    5.38 +#include <asm/apic.h>
    5.39 +#include <asm/io.h>
    5.40 +#include <asm/irq.h>
    5.41 +#include <asm/mpspec.h>
    5.42 +
    5.43 +int sbf_port; /* XXX XEN */
    5.44 +
    5.45 +#ifdef	CONFIG_X86_64
    5.46 +
    5.47 +static inline void  acpi_madt_oem_check(char *oem_id, char *oem_table_id) { }
    5.48 +extern void __init clustered_apic_check(void);
    5.49 +static inline int ioapic_setup_disabled(void) { return 0; }
    5.50 +#include <asm/proto.h>
    5.51 +
    5.52 +#else	/* X86 */
    5.53 +
    5.54 +#ifdef	CONFIG_X86_LOCAL_APIC
    5.55 +#include <mach_apic.h>
    5.56 +#include <mach_mpparse.h>
    5.57 +#endif	/* CONFIG_X86_LOCAL_APIC */
    5.58 +
    5.59 +#endif	/* X86 */
    5.60 +
    5.61 +#define BAD_MADT_ENTRY(entry, end) (					    \
    5.62 +		(!entry) || (unsigned long)entry + sizeof(*entry) > end ||  \
    5.63 +		((acpi_table_entry_header *)entry)->length != sizeof(*entry))
    5.64 +
    5.65 +#define PREFIX			"ACPI: "
    5.66 +
    5.67 +#ifdef CONFIG_ACPI_PCI
    5.68 +int acpi_noirq __initdata;	/* skip ACPI IRQ initialization */
    5.69 +int acpi_pci_disabled __initdata; /* skip ACPI PCI scan and IRQ initialization */
    5.70 +#else
    5.71 +int acpi_noirq __initdata = 1;
    5.72 +int acpi_pci_disabled __initdata = 1;
    5.73 +#endif
    5.74 +int acpi_ht __initdata = 1;	/* enable HT */
    5.75 +
    5.76 +int acpi_lapic;
    5.77 +int acpi_ioapic;
    5.78 +int acpi_strict;
    5.79 +EXPORT_SYMBOL(acpi_strict);
    5.80 +
    5.81 +acpi_interrupt_flags acpi_sci_flags __initdata;
    5.82 +int acpi_sci_override_gsi __initdata;
    5.83 +int acpi_skip_timer_override __initdata;
    5.84 +
    5.85 +#ifdef CONFIG_X86_LOCAL_APIC
    5.86 +static u64 acpi_lapic_addr __initdata = APIC_DEFAULT_PHYS_BASE;
    5.87 +#endif
    5.88 +
    5.89 +#ifndef __HAVE_ARCH_CMPXCHG
    5.90 +#warning ACPI uses CMPXCHG, i486 and later hardware
    5.91 +#endif
    5.92 +
    5.93 +#define MAX_MADT_ENTRIES	256
    5.94 +u8 x86_acpiid_to_apicid[MAX_MADT_ENTRIES] =
    5.95 +			{ [0 ... MAX_MADT_ENTRIES-1] = 0xff };
    5.96 +EXPORT_SYMBOL(x86_acpiid_to_apicid);
    5.97 +
    5.98 +/* --------------------------------------------------------------------------
    5.99 +                              Boot-time Configuration
   5.100 +   -------------------------------------------------------------------------- */
   5.101 +
   5.102 +/*
   5.103 + * The default interrupt routing model is PIC (8259).  This gets
   5.104 + * overriden if IOAPICs are enumerated (below).
   5.105 + */
   5.106 +enum acpi_irq_model_id		acpi_irq_model = ACPI_IRQ_MODEL_PIC;
   5.107 +
   5.108 +#ifdef	CONFIG_X86_64
   5.109 +
   5.110 +/* rely on all ACPI tables being in the direct mapping */
   5.111 +char *__acpi_map_table(unsigned long phys_addr, unsigned long size)
   5.112 +{
   5.113 +	if (!phys_addr || !size)
   5.114 +	return NULL;
   5.115 +
   5.116 +	if (phys_addr < (end_pfn_map << PAGE_SHIFT))
   5.117 +		return __va(phys_addr);
   5.118 +
   5.119 +	return NULL;
   5.120 +}
   5.121 +
   5.122 +#else
   5.123 +
   5.124 +/*
   5.125 + * Temporarily use the virtual area starting from FIX_IO_APIC_BASE_END,
   5.126 + * to map the target physical address. The problem is that set_fixmap()
   5.127 + * provides a single page, and it is possible that the page is not
   5.128 + * sufficient.
   5.129 + * By using this area, we can map up to MAX_IO_APICS pages temporarily,
   5.130 + * i.e. until the next __va_range() call.
   5.131 + *
   5.132 + * Important Safety Note:  The fixed I/O APIC page numbers are *subtracted*
   5.133 + * from the fixed base.  That's why we start at FIX_IO_APIC_BASE_END and
   5.134 + * count idx down while incrementing the phys address.
   5.135 + */
   5.136 +char *__acpi_map_table(unsigned long phys, unsigned long size)
   5.137 +{
   5.138 +	unsigned long base, offset, mapped_size;
   5.139 +	int idx;
   5.140 +
   5.141 +	if (phys + size < 8*1024*1024) 
   5.142 +		return __va(phys); 
   5.143 +
   5.144 +	offset = phys & (PAGE_SIZE - 1);
   5.145 +	mapped_size = PAGE_SIZE - offset;
   5.146 +	set_fixmap(FIX_ACPI_END, phys);
   5.147 +	base = fix_to_virt(FIX_ACPI_END);
   5.148 +
   5.149 +	/*
   5.150 +	 * Most cases can be covered by the below.
   5.151 +	 */
   5.152 +	idx = FIX_ACPI_END;
   5.153 +	while (mapped_size < size) {
   5.154 +		if (--idx < FIX_ACPI_BEGIN)
   5.155 +			return NULL;	/* cannot handle this */
   5.156 +		phys += PAGE_SIZE;
   5.157 +		set_fixmap(idx, phys);
   5.158 +		mapped_size += PAGE_SIZE;
   5.159 +	}
   5.160 +
   5.161 +	return ((unsigned char *) base + offset);
   5.162 +}
   5.163 +#endif
   5.164 +
   5.165 +#ifdef CONFIG_PCI_MMCONFIG
   5.166 +static int __init acpi_parse_mcfg(unsigned long phys_addr, unsigned long size)
   5.167 +{
   5.168 +	struct acpi_table_mcfg *mcfg;
   5.169 +
   5.170 +	if (!phys_addr || !size)
   5.171 +		return -EINVAL;
   5.172 +
   5.173 +	mcfg = (struct acpi_table_mcfg *) __acpi_map_table(phys_addr, size);
   5.174 +	if (!mcfg) {
   5.175 +		printk(KERN_WARNING PREFIX "Unable to map MCFG\n");
   5.176 +		return -ENODEV;
   5.177 +	}
   5.178 +
   5.179 +	if (mcfg->base_reserved) {
   5.180 +		printk(KERN_ERR PREFIX "MMCONFIG not in low 4GB of memory\n");
   5.181 +		return -ENODEV;
   5.182 +	}
   5.183 +
   5.184 +	pci_mmcfg_base_addr = mcfg->base_address;
   5.185 +
   5.186 +	return 0;
   5.187 +}
   5.188 +#else
   5.189 +#define	acpi_parse_mcfg NULL
   5.190 +#endif /* !CONFIG_PCI_MMCONFIG */
   5.191 +
   5.192 +#ifdef CONFIG_X86_LOCAL_APIC
   5.193 +static int __init
   5.194 +acpi_parse_madt (
   5.195 +	unsigned long		phys_addr,
   5.196 +	unsigned long		size)
   5.197 +{
   5.198 +	struct acpi_table_madt	*madt = NULL;
   5.199 +
   5.200 +	if (!phys_addr || !size)
   5.201 +		return -EINVAL;
   5.202 +
   5.203 +	madt = (struct acpi_table_madt *) __acpi_map_table(phys_addr, size);
   5.204 +	if (!madt) {
   5.205 +		printk(KERN_WARNING PREFIX "Unable to map MADT\n");
   5.206 +		return -ENODEV;
   5.207 +	}
   5.208 +
   5.209 +	if (madt->lapic_address) {
   5.210 +		acpi_lapic_addr = (u64) madt->lapic_address;
   5.211 +
   5.212 +		printk(KERN_DEBUG PREFIX "Local APIC address 0x%08x\n",
   5.213 +			madt->lapic_address);
   5.214 +	}
   5.215 +
   5.216 +	acpi_madt_oem_check(madt->header.oem_id, madt->header.oem_table_id);
   5.217 +	
   5.218 +	return 0;
   5.219 +}
   5.220 +
   5.221 +
   5.222 +static int __init
   5.223 +acpi_parse_lapic (
   5.224 +	acpi_table_entry_header *header, const unsigned long end)
   5.225 +{
   5.226 +	struct acpi_table_lapic	*processor = NULL;
   5.227 +
   5.228 +	processor = (struct acpi_table_lapic*) header;
   5.229 +
   5.230 +	if (BAD_MADT_ENTRY(processor, end))
   5.231 +		return -EINVAL;
   5.232 +
   5.233 +	acpi_table_print_madt_entry(header);
   5.234 +
   5.235 +	/* no utility in registering a disabled processor */
   5.236 +	if (processor->flags.enabled == 0)
   5.237 +		return 0;
   5.238 +
   5.239 +	x86_acpiid_to_apicid[processor->acpi_id] = processor->id;
   5.240 +
   5.241 +	mp_register_lapic (
   5.242 +		processor->id,					   /* APIC ID */
   5.243 +		processor->flags.enabled);			  /* Enabled? */
   5.244 +
   5.245 +	return 0;
   5.246 +}
   5.247 +
   5.248 +static int __init
   5.249 +acpi_parse_lapic_addr_ovr (
   5.250 +	acpi_table_entry_header *header, const unsigned long end)
   5.251 +{
   5.252 +	struct acpi_table_lapic_addr_ovr *lapic_addr_ovr = NULL;
   5.253 +
   5.254 +	lapic_addr_ovr = (struct acpi_table_lapic_addr_ovr*) header;
   5.255 +
   5.256 +	if (BAD_MADT_ENTRY(lapic_addr_ovr, end))
   5.257 +		return -EINVAL;
   5.258 +
   5.259 +	acpi_lapic_addr = lapic_addr_ovr->address;
   5.260 +
   5.261 +	return 0;
   5.262 +}
   5.263 +
   5.264 +static int __init
   5.265 +acpi_parse_lapic_nmi (
   5.266 +	acpi_table_entry_header *header, const unsigned long end)
   5.267 +{
   5.268 +	struct acpi_table_lapic_nmi *lapic_nmi = NULL;
   5.269 +
   5.270 +	lapic_nmi = (struct acpi_table_lapic_nmi*) header;
   5.271 +
   5.272 +	if (BAD_MADT_ENTRY(lapic_nmi, end))
   5.273 +		return -EINVAL;
   5.274 +
   5.275 +	acpi_table_print_madt_entry(header);
   5.276 +
   5.277 +	if (lapic_nmi->lint != 1)
   5.278 +		printk(KERN_WARNING PREFIX "NMI not connected to LINT 1!\n");
   5.279 +
   5.280 +	return 0;
   5.281 +}
   5.282 +
   5.283 +
   5.284 +#endif /*CONFIG_X86_LOCAL_APIC*/
   5.285 +
   5.286 +#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_ACPI_INTERPRETER)
   5.287 +
   5.288 +static int __init
   5.289 +acpi_parse_ioapic (
   5.290 +	acpi_table_entry_header *header, const unsigned long end)
   5.291 +{
   5.292 +	struct acpi_table_ioapic *ioapic = NULL;
   5.293 +
   5.294 +	ioapic = (struct acpi_table_ioapic*) header;
   5.295 +
   5.296 +	if (BAD_MADT_ENTRY(ioapic, end))
   5.297 +		return -EINVAL;
   5.298 + 
   5.299 +	acpi_table_print_madt_entry(header);
   5.300 +
   5.301 +	mp_register_ioapic (
   5.302 +		ioapic->id,
   5.303 +		ioapic->address,
   5.304 +		ioapic->global_irq_base);
   5.305 + 
   5.306 +	return 0;
   5.307 +}
   5.308 +
   5.309 +/*
   5.310 + * Parse Interrupt Source Override for the ACPI SCI
   5.311 + */
   5.312 +static void
   5.313 +acpi_sci_ioapic_setup(u32 gsi, u16 polarity, u16 trigger)
   5.314 +{
   5.315 +	if (trigger == 0)	/* compatible SCI trigger is level */
   5.316 +		trigger = 3;
   5.317 +
   5.318 +	if (polarity == 0)	/* compatible SCI polarity is low */
   5.319 +		polarity = 3;
   5.320 +
   5.321 +	/* Command-line over-ride via acpi_sci= */
   5.322 +	if (acpi_sci_flags.trigger)
   5.323 +		trigger = acpi_sci_flags.trigger;
   5.324 +
   5.325 +	if (acpi_sci_flags.polarity)
   5.326 +		polarity = acpi_sci_flags.polarity;
   5.327 +
   5.328 +	/*
   5.329 + 	 * mp_config_acpi_legacy_irqs() already setup IRQs < 16
   5.330 +	 * If GSI is < 16, this will update its flags,
   5.331 +	 * else it will create a new mp_irqs[] entry.
   5.332 +	 */
   5.333 +	mp_override_legacy_irq(gsi, polarity, trigger, gsi);
   5.334 +
   5.335 +	/*
   5.336 +	 * stash over-ride to indicate we've been here
   5.337 +	 * and for later update of acpi_fadt
   5.338 +	 */
   5.339 +	acpi_sci_override_gsi = gsi;
   5.340 +	return;
   5.341 +}
   5.342 +
   5.343 +static int __init
   5.344 +acpi_parse_int_src_ovr (
   5.345 +	acpi_table_entry_header *header, const unsigned long end)
   5.346 +{
   5.347 +	struct acpi_table_int_src_ovr *intsrc = NULL;
   5.348 +
   5.349 +	intsrc = (struct acpi_table_int_src_ovr*) header;
   5.350 +
   5.351 +	if (BAD_MADT_ENTRY(intsrc, end))
   5.352 +		return -EINVAL;
   5.353 +
   5.354 +	acpi_table_print_madt_entry(header);
   5.355 +
   5.356 +	if (intsrc->bus_irq == acpi_fadt.sci_int) {
   5.357 +		acpi_sci_ioapic_setup(intsrc->global_irq,
   5.358 +			intsrc->flags.polarity, intsrc->flags.trigger);
   5.359 +		return 0;
   5.360 +	}
   5.361 +
   5.362 +	if (acpi_skip_timer_override &&
   5.363 +		intsrc->bus_irq == 0 && intsrc->global_irq == 2) {
   5.364 +			printk(PREFIX "BIOS IRQ0 pin2 override ignored.\n");
   5.365 +			return 0;
   5.366 +	}
   5.367 +
   5.368 +	mp_override_legacy_irq (
   5.369 +		intsrc->bus_irq,
   5.370 +		intsrc->flags.polarity,
   5.371 +		intsrc->flags.trigger,
   5.372 +		intsrc->global_irq);
   5.373 +
   5.374 +	return 0;
   5.375 +}
   5.376 +
   5.377 +
   5.378 +static int __init
   5.379 +acpi_parse_nmi_src (
   5.380 +	acpi_table_entry_header *header, const unsigned long end)
   5.381 +{
   5.382 +	struct acpi_table_nmi_src *nmi_src = NULL;
   5.383 +
   5.384 +	nmi_src = (struct acpi_table_nmi_src*) header;
   5.385 +
   5.386 +	if (BAD_MADT_ENTRY(nmi_src, end))
   5.387 +		return -EINVAL;
   5.388 +
   5.389 +	acpi_table_print_madt_entry(header);
   5.390 +
   5.391 +	/* TBD: Support nimsrc entries? */
   5.392 +
   5.393 +	return 0;
   5.394 +}
   5.395 +
   5.396 +#endif /* CONFIG_X86_IO_APIC */
   5.397 +
   5.398 +#ifdef	CONFIG_ACPI_BUS
   5.399 +
   5.400 +/*
   5.401 + * acpi_pic_sci_set_trigger()
   5.402 + * 
   5.403 + * use ELCR to set PIC-mode trigger type for SCI
   5.404 + *
   5.405 + * If a PIC-mode SCI is not recognized or gives spurious IRQ7's
   5.406 + * it may require Edge Trigger -- use "acpi_sci=edge"
   5.407 + *
   5.408 + * Port 0x4d0-4d1 are ECLR1 and ECLR2, the Edge/Level Control Registers
   5.409 + * for the 8259 PIC.  bit[n] = 1 means irq[n] is Level, otherwise Edge.
   5.410 + * ECLR1 is IRQ's 0-7 (IRQ 0, 1, 2 must be 0)
   5.411 + * ECLR2 is IRQ's 8-15 (IRQ 8, 13 must be 0)
   5.412 + */
   5.413 +
   5.414 +void __init
   5.415 +acpi_pic_sci_set_trigger(unsigned int irq, u16 trigger)
   5.416 +{
   5.417 +	unsigned int mask = 1 << irq;
   5.418 +	unsigned int old, new;
   5.419 +
   5.420 +	/* Real old ELCR mask */
   5.421 +	old = inb(0x4d0) | (inb(0x4d1) << 8);
   5.422 +
   5.423 +	/*
   5.424 +	 * If we use ACPI to set PCI irq's, then we should clear ELCR
   5.425 +	 * since we will set it correctly as we enable the PCI irq
   5.426 +	 * routing.
   5.427 +	 */
   5.428 +	new = acpi_noirq ? old : 0;
   5.429 +
   5.430 +	/*
   5.431 +	 * Update SCI information in the ELCR, it isn't in the PCI
   5.432 +	 * routing tables..
   5.433 +	 */
   5.434 +	switch (trigger) {
   5.435 +	case 1:	/* Edge - clear */
   5.436 +		new &= ~mask;
   5.437 +		break;
   5.438 +	case 3: /* Level - set */
   5.439 +		new |= mask;
   5.440 +		break;
   5.441 +	}
   5.442 +
   5.443 +	if (old == new)
   5.444 +		return;
   5.445 +
   5.446 +	printk(PREFIX "setting ELCR to %04x (from %04x)\n", new, old);
   5.447 +	outb(new, 0x4d0);
   5.448 +	outb(new >> 8, 0x4d1);
   5.449 +}
   5.450 +
   5.451 +
   5.452 +#endif /* CONFIG_ACPI_BUS */
   5.453 +
   5.454 +int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
   5.455 +{
   5.456 +#ifdef CONFIG_X86_IO_APIC
   5.457 +	if (use_pci_vector() && !platform_legacy_irq(gsi))
   5.458 + 		*irq = IO_APIC_VECTOR(gsi);
   5.459 +	else
   5.460 +#endif
   5.461 +		*irq = gsi;
   5.462 +	return 0;
   5.463 +}
   5.464 +
   5.465 +unsigned int acpi_register_gsi(u32 gsi, int edge_level, int active_high_low)
   5.466 +{
   5.467 +	unsigned int irq;
   5.468 +	unsigned int plat_gsi = gsi;
   5.469 +
   5.470 +#ifdef CONFIG_PCI
   5.471 +	/*
   5.472 +	 * Make sure all (legacy) PCI IRQs are set as level-triggered.
   5.473 +	 */
   5.474 +	if (acpi_irq_model == ACPI_IRQ_MODEL_PIC) {
   5.475 +		extern void eisa_set_level_irq(unsigned int irq);
   5.476 +
   5.477 +		if (edge_level == ACPI_LEVEL_SENSITIVE)
   5.478 +				eisa_set_level_irq(gsi);
   5.479 +	}
   5.480 +#endif
   5.481 +
   5.482 +#ifdef CONFIG_X86_IO_APIC
   5.483 +	if (acpi_irq_model == ACPI_IRQ_MODEL_IOAPIC) {
   5.484 +		plat_gsi = mp_register_gsi(gsi, edge_level, active_high_low);
   5.485 +	}
   5.486 +#endif
   5.487 +	acpi_gsi_to_irq(plat_gsi, &irq);
   5.488 +	return irq;
   5.489 +}
   5.490 +EXPORT_SYMBOL(acpi_register_gsi);
   5.491 +
   5.492 +/*
   5.493 + *  ACPI based hotplug support for CPU
   5.494 + */
   5.495 +#ifdef CONFIG_ACPI_HOTPLUG_CPU
   5.496 +int
   5.497 +acpi_map_lsapic(acpi_handle handle, int *pcpu)
   5.498 +{
   5.499 +	/* TBD */
   5.500 +	return -EINVAL;
   5.501 +}
   5.502 +EXPORT_SYMBOL(acpi_map_lsapic);
   5.503 +
   5.504 +
   5.505 +int
   5.506 +acpi_unmap_lsapic(int cpu)
   5.507 +{
   5.508 +	/* TBD */
   5.509 +	return -EINVAL;
   5.510 +}
   5.511 +EXPORT_SYMBOL(acpi_unmap_lsapic);
   5.512 +#endif /* CONFIG_ACPI_HOTPLUG_CPU */
   5.513 +
   5.514 +static unsigned long __init
   5.515 +acpi_scan_rsdp (
   5.516 +	unsigned long		start,
   5.517 +	unsigned long		length)
   5.518 +{
   5.519 +	unsigned long		offset = 0;
   5.520 +	unsigned long		sig_len = sizeof("RSD PTR ") - 1;
   5.521 +
   5.522 +	/*
   5.523 +	 * Scan all 16-byte boundaries of the physical memory region for the
   5.524 +	 * RSDP signature.
   5.525 +	 */
   5.526 +	for (offset = 0; offset < length; offset += 16) {
   5.527 +		if (strncmp((char *) (start + offset), "RSD PTR ", sig_len))
   5.528 +			continue;
   5.529 +		return (start + offset);
   5.530 +	}
   5.531 +
   5.532 +	return 0;
   5.533 +}
   5.534 +
   5.535 +static int __init acpi_parse_sbf(unsigned long phys_addr, unsigned long size)
   5.536 +{
   5.537 +	struct acpi_table_sbf *sb;
   5.538 +
   5.539 +	if (!phys_addr || !size)
   5.540 +	return -EINVAL;
   5.541 +
   5.542 +	sb = (struct acpi_table_sbf *) __acpi_map_table(phys_addr, size);
   5.543 +	if (!sb) {
   5.544 +		printk(KERN_WARNING PREFIX "Unable to map SBF\n");
   5.545 +		return -ENODEV;
   5.546 +	}
   5.547 +
   5.548 +	sbf_port = sb->sbf_cmos; /* Save CMOS port */
   5.549 +
   5.550 +	return 0;
   5.551 +}
   5.552 +
   5.553 +
   5.554 +#ifdef CONFIG_HPET_TIMER
   5.555 +
   5.556 +static int __init acpi_parse_hpet(unsigned long phys, unsigned long size)
   5.557 +{
   5.558 +	struct acpi_table_hpet *hpet_tbl;
   5.559 +
   5.560 +	if (!phys || !size)
   5.561 +		return -EINVAL;
   5.562 +
   5.563 +	hpet_tbl = (struct acpi_table_hpet *) __acpi_map_table(phys, size);
   5.564 +	if (!hpet_tbl) {
   5.565 +		printk(KERN_WARNING PREFIX "Unable to map HPET\n");
   5.566 +		return -ENODEV;
   5.567 +	}
   5.568 +
   5.569 +	if (hpet_tbl->addr.space_id != ACPI_SPACE_MEM) {
   5.570 +		printk(KERN_WARNING PREFIX "HPET timers must be located in "
   5.571 +		       "memory.\n");
   5.572 +		return -1;
   5.573 +	}
   5.574 +
   5.575 +#ifdef	CONFIG_X86_64
   5.576 +        vxtime.hpet_address = hpet_tbl->addr.addrl |
   5.577 +                ((long) hpet_tbl->addr.addrh << 32);
   5.578 +
   5.579 +        printk(KERN_INFO PREFIX "HPET id: %#x base: %#lx\n",
   5.580 +               hpet_tbl->id, vxtime.hpet_address);
   5.581 +#else	/* X86 */
   5.582 +	{
   5.583 +		extern unsigned long hpet_address;
   5.584 +
   5.585 +		hpet_address = hpet_tbl->addr.addrl;
   5.586 +		printk(KERN_INFO PREFIX "HPET id: %#x base: %#lx\n",
   5.587 +			hpet_tbl->id, hpet_address);
   5.588 +	}
   5.589 +#endif	/* X86 */
   5.590 +
   5.591 +	return 0;
   5.592 +}
   5.593 +#else
   5.594 +#define	acpi_parse_hpet	NULL
   5.595 +#endif
   5.596 +
   5.597 +#ifdef CONFIG_X86_PM_TIMER
   5.598 +extern u32 pmtmr_ioport;
   5.599 +#endif
   5.600 +
   5.601 +static int __init acpi_parse_fadt(unsigned long phys, unsigned long size)
   5.602 +{
   5.603 +	struct fadt_descriptor_rev2 *fadt = NULL;
   5.604 +
   5.605 +	fadt = (struct fadt_descriptor_rev2*) __acpi_map_table(phys,size);
   5.606 +	if(!fadt) {
   5.607 +		printk(KERN_WARNING PREFIX "Unable to map FADT\n");
   5.608 +		return 0;
   5.609 +	}
   5.610 +
   5.611 +#ifdef	CONFIG_ACPI_INTERPRETER
   5.612 +	/* initialize sci_int early for INT_SRC_OVR MADT parsing */
   5.613 +	acpi_fadt.sci_int = fadt->sci_int;
   5.614 +#endif
   5.615 +
   5.616 +#ifdef CONFIG_X86_PM_TIMER
   5.617 +	/* detect the location of the ACPI PM Timer */
   5.618 +	if (fadt->revision >= FADT2_REVISION_ID) {
   5.619 +		/* FADT rev. 2 */
   5.620 +		if (fadt->xpm_tmr_blk.address_space_id != ACPI_ADR_SPACE_SYSTEM_IO)
   5.621 +			return 0;
   5.622 +
   5.623 +		pmtmr_ioport = fadt->xpm_tmr_blk.address;
   5.624 +	} else {
   5.625 +		/* FADT rev. 1 */
   5.626 +		pmtmr_ioport = fadt->V1_pm_tmr_blk;
   5.627 +	}
   5.628 +	if (pmtmr_ioport)
   5.629 +		printk(KERN_INFO PREFIX "PM-Timer IO Port: %#x\n", pmtmr_ioport);
   5.630 +#endif
   5.631 +	return 0;
   5.632 +}
   5.633 +
   5.634 +
   5.635 +unsigned long __init
   5.636 +acpi_find_rsdp (void)
   5.637 +{
   5.638 +	unsigned long		rsdp_phys = 0;
   5.639 +
   5.640 +#if 0
   5.641 +	if (efi_enabled) {
   5.642 +		if (efi.acpi20)
   5.643 +			return __pa(efi.acpi20);
   5.644 +		else if (efi.acpi)
   5.645 +			return __pa(efi.acpi);
   5.646 +	}
   5.647 +#endif
   5.648 +	/*
   5.649 +	 * Scan memory looking for the RSDP signature. First search EBDA (low
   5.650 +	 * memory) paragraphs and then search upper memory (E0000-FFFFF).
   5.651 +	 */
   5.652 +	rsdp_phys = acpi_scan_rsdp (0, 0x400);
   5.653 +	if (!rsdp_phys)
   5.654 +		rsdp_phys = acpi_scan_rsdp (0xE0000, 0xFFFFF);
   5.655 +
   5.656 +	return rsdp_phys;
   5.657 +}
   5.658 +
   5.659 +#ifdef	CONFIG_X86_LOCAL_APIC
   5.660 +/*
   5.661 + * Parse LAPIC entries in MADT
   5.662 + * returns 0 on success, < 0 on error
   5.663 + */
   5.664 +static int __init
   5.665 +acpi_parse_madt_lapic_entries(void)
   5.666 +{
   5.667 +	int count;
   5.668 +
   5.669 +	/* 
   5.670 +	 * Note that the LAPIC address is obtained from the MADT (32-bit value)
   5.671 +	 * and (optionally) overriden by a LAPIC_ADDR_OVR entry (64-bit value).
   5.672 +	 */
   5.673 +
   5.674 +	count = acpi_table_parse_madt(ACPI_MADT_LAPIC_ADDR_OVR, acpi_parse_lapic_addr_ovr, 0);
   5.675 +	if (count < 0) {
   5.676 +		printk(KERN_ERR PREFIX "Error parsing LAPIC address override entry\n");
   5.677 +		return count;
   5.678 +	}
   5.679 +
   5.680 +	mp_register_lapic_address(acpi_lapic_addr);
   5.681 +
   5.682 +	count = acpi_table_parse_madt(ACPI_MADT_LAPIC, acpi_parse_lapic,
   5.683 +				       MAX_APICS);
   5.684 +	if (!count) { 
   5.685 +		printk(KERN_ERR PREFIX "No LAPIC entries present\n");
   5.686 +		/* TBD: Cleanup to allow fallback to MPS */
   5.687 +		return -ENODEV;
   5.688 +	}
   5.689 +	else if (count < 0) {
   5.690 +		printk(KERN_ERR PREFIX "Error parsing LAPIC entry\n");
   5.691 +		/* TBD: Cleanup to allow fallback to MPS */
   5.692 +		return count;
   5.693 +	}
   5.694 +
   5.695 +	count = acpi_table_parse_madt(ACPI_MADT_LAPIC_NMI, acpi_parse_lapic_nmi, 0);
   5.696 +	if (count < 0) {
   5.697 +		printk(KERN_ERR PREFIX "Error parsing LAPIC NMI entry\n");
   5.698 +		/* TBD: Cleanup to allow fallback to MPS */
   5.699 +		return count;
   5.700 +	}
   5.701 +	return 0;
   5.702 +}
   5.703 +#endif /* CONFIG_X86_LOCAL_APIC */
   5.704 +
   5.705 +#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_ACPI_INTERPRETER)
   5.706 +/*
   5.707 + * Parse IOAPIC related entries in MADT
   5.708 + * returns 0 on success, < 0 on error
   5.709 + */
   5.710 +static int __init
   5.711 +acpi_parse_madt_ioapic_entries(void)
   5.712 +{
   5.713 +	int count;
   5.714 +
   5.715 +	/*
   5.716 +	 * ACPI interpreter is required to complete interrupt setup,
   5.717 +	 * so if it is off, don't enumerate the io-apics with ACPI.
   5.718 +	 * If MPS is present, it will handle them,
   5.719 +	 * otherwise the system will stay in PIC mode
   5.720 +	 */
   5.721 +	if (acpi_disabled || acpi_noirq) {
   5.722 +		return -ENODEV;
   5.723 +        }
   5.724 +
   5.725 +	/*
   5.726 + 	 * if "noapic" boot option, don't look for IO-APICs
   5.727 +	 */
   5.728 +	if (skip_ioapic_setup) {
   5.729 +		printk(KERN_INFO PREFIX "Skipping IOAPIC probe "
   5.730 +			"due to 'noapic' option.\n");
   5.731 +		return -ENODEV;
   5.732 +	}
   5.733 +
   5.734 +	count = acpi_table_parse_madt(ACPI_MADT_IOAPIC, acpi_parse_ioapic, MAX_IO_APICS);
   5.735 +	if (!count) {
   5.736 +		printk(KERN_ERR PREFIX "No IOAPIC entries present\n");
   5.737 +		return -ENODEV;
   5.738 +	}
   5.739 +	else if (count < 0) {
   5.740 +		printk(KERN_ERR PREFIX "Error parsing IOAPIC entry\n");
   5.741 +		return count;
   5.742 +	}
   5.743 +
   5.744 +	count = acpi_table_parse_madt(ACPI_MADT_INT_SRC_OVR, acpi_parse_int_src_ovr, NR_IRQ_VECTORS);
   5.745 +	if (count < 0) {
   5.746 +		printk(KERN_ERR PREFIX "Error parsing interrupt source overrides entry\n");
   5.747 +		/* TBD: Cleanup to allow fallback to MPS */
   5.748 +		return count;
   5.749 +	}
   5.750 +
   5.751 +	/*
   5.752 +	 * If BIOS did not supply an INT_SRC_OVR for the SCI
   5.753 +	 * pretend we got one so we can set the SCI flags.
   5.754 +	 */
   5.755 +	if (!acpi_sci_override_gsi)
   5.756 +		acpi_sci_ioapic_setup(acpi_fadt.sci_int, 0, 0);
   5.757 +
   5.758 +	/* Fill in identity legacy mapings where no override */
   5.759 +	mp_config_acpi_legacy_irqs();
   5.760 +
   5.761 +	count = acpi_table_parse_madt(ACPI_MADT_NMI_SRC, acpi_parse_nmi_src, NR_IRQ_VECTORS);
   5.762 +	if (count < 0) {
   5.763 +		printk(KERN_ERR PREFIX "Error parsing NMI SRC entry\n");
   5.764 +		/* TBD: Cleanup to allow fallback to MPS */
   5.765 +		return count;
   5.766 +	}
   5.767 +
   5.768 +	return 0;
   5.769 +}
   5.770 +#else
   5.771 +static inline int acpi_parse_madt_ioapic_entries(void)
   5.772 +{
   5.773 +	return -1;
   5.774 +}
   5.775 +#endif /* !(CONFIG_X86_IO_APIC && CONFIG_ACPI_INTERPRETER) */
   5.776 +
   5.777 +
   5.778 +static void __init
   5.779 +acpi_process_madt(void)
   5.780 +{
   5.781 +#ifdef CONFIG_X86_LOCAL_APIC
   5.782 +	int count, error;
   5.783 +
   5.784 +	count = acpi_table_parse(ACPI_APIC, acpi_parse_madt);
   5.785 +	if (count >= 1) {
   5.786 +
   5.787 +		/*
   5.788 +		 * Parse MADT LAPIC entries
   5.789 +		 */
   5.790 +		error = acpi_parse_madt_lapic_entries();
   5.791 +		if (!error) {
   5.792 +			acpi_lapic = 1;
   5.793 +
   5.794 +			/*
   5.795 +			 * Parse MADT IO-APIC entries
   5.796 +			 */
   5.797 +			error = acpi_parse_madt_ioapic_entries();
   5.798 +			if (!error) {
   5.799 +				acpi_irq_model = ACPI_IRQ_MODEL_IOAPIC;
   5.800 +				acpi_irq_balance_set(NULL);
   5.801 +				acpi_ioapic = 1;
   5.802 +
   5.803 +				smp_found_config = 1;
   5.804 +				clustered_apic_check();
   5.805 +			}
   5.806 +		}
   5.807 +		if (error == -EINVAL) {
   5.808 +			/*
   5.809 +			 * Dell Precision Workstation 410, 610 come here.
   5.810 +			 */
   5.811 +			printk(KERN_ERR PREFIX "Invalid BIOS MADT, disabling ACPI\n");
   5.812 +			disable_acpi();
   5.813 +		}
   5.814 +	}
   5.815 +#endif
   5.816 +	return;
   5.817 +}
   5.818 +
   5.819 +/*
   5.820 + * acpi_boot_table_init() and acpi_boot_init()
   5.821 + *  called from setup_arch(), always.
   5.822 + *	1. checksums all tables
   5.823 + *	2. enumerates lapics
   5.824 + *	3. enumerates io-apics
   5.825 + *
   5.826 + * acpi_table_init() is separate to allow reading SRAT without
   5.827 + * other side effects.
   5.828 + *
   5.829 + * side effects of acpi_boot_init:
   5.830 + *	acpi_lapic = 1 if LAPIC found
   5.831 + *	acpi_ioapic = 1 if IOAPIC found
   5.832 + *	if (acpi_lapic && acpi_ioapic) smp_found_config = 1;
   5.833 + *	if acpi_blacklisted() acpi_disabled = 1;
   5.834 + *	acpi_irq_model=...
   5.835 + *	...
   5.836 + *
   5.837 + * return value: (currently ignored)
   5.838 + *	0: success
   5.839 + *	!0: failure
   5.840 + */
   5.841 +
   5.842 +int __init
   5.843 +acpi_boot_table_init(void)
   5.844 +{
   5.845 +	int error;
   5.846 +
   5.847 +	/*
   5.848 +	 * If acpi_disabled, bail out
   5.849 +	 * One exception: acpi=ht continues far enough to enumerate LAPICs
   5.850 +	 */
   5.851 +	if (acpi_disabled && !acpi_ht)
   5.852 +		 return 1;
   5.853 +
   5.854 +	/* 
   5.855 +	 * Initialize the ACPI boot-time table parser.
   5.856 +	 */
   5.857 +	error = acpi_table_init();
   5.858 +	if (error) {
   5.859 +		disable_acpi();
   5.860 +		return error;
   5.861 +	}
   5.862 +
   5.863 +#if 0 /*def __i386__*/
   5.864 +	check_acpi_pci();
   5.865 +#endif
   5.866 +
   5.867 +	acpi_table_parse(ACPI_BOOT, acpi_parse_sbf);
   5.868 +
   5.869 +	/*
   5.870 +	 * blacklist may disable ACPI entirely
   5.871 +	 */
   5.872 +	error = acpi_blacklisted();
   5.873 +	if (error) {
   5.874 +		extern int acpi_force;
   5.875 +
   5.876 +		if (acpi_force) {
   5.877 +			printk(KERN_WARNING PREFIX "acpi=force override\n");
   5.878 +		} else {
   5.879 +			printk(KERN_WARNING PREFIX "Disabling ACPI support\n");
   5.880 +			disable_acpi();
   5.881 +			return error;
   5.882 +		}
   5.883 +	}
   5.884 +
   5.885 +	return 0;
   5.886 +}
   5.887 +
   5.888 +
   5.889 +int __init acpi_boot_init(void)
   5.890 +{
   5.891 +	/*
   5.892 +	 * If acpi_disabled, bail out
   5.893 +	 * One exception: acpi=ht continues far enough to enumerate LAPICs
   5.894 +	 */
   5.895 +	if (acpi_disabled && !acpi_ht)
   5.896 +		 return 1;
   5.897 +
   5.898 +	acpi_table_parse(ACPI_BOOT, acpi_parse_sbf);
   5.899 +
   5.900 +	/*
   5.901 +	 * set sci_int and PM timer address
   5.902 +	 */
   5.903 +	acpi_table_parse(ACPI_FADT, acpi_parse_fadt);
   5.904 +
   5.905 +	/*
   5.906 +	 * Process the Multiple APIC Description Table (MADT), if present
   5.907 +	 */
   5.908 +	acpi_process_madt();
   5.909 +
   5.910 +	acpi_table_parse(ACPI_HPET, acpi_parse_hpet);
   5.911 +	acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg);
   5.912 +
   5.913 +	return 0;
   5.914 +}
   5.915 +

     6.1 --- a/xen/arch/x86/apic.c	Mon May 09 14:34:59 2005 +0000
     6.2 +++ b/xen/arch/x86/apic.c	Mon May 09 17:50:11 2005 +0000
     6.3 @@ -34,14 +34,27 @@
     6.4  #include <asm/hardirq.h>
     6.5  #include <asm/apic.h>
     6.6  #include <asm/io_apic.h>
     6.7 -#include <asm/mach_apic.h>
     6.8 -#include <asm/io_ports.h>
     6.9 +#include <mach_apic.h>
    6.10 +#include <io_ports.h>
    6.11  
    6.12  /* Using APIC to generate smp_local_timer_interrupt? */
    6.13  int using_apic_timer = 0;
    6.14  
    6.15 +int apic_verbosity;
    6.16 +
    6.17  static int enabled_via_apicbase;
    6.18  
    6.19 +int get_physical_broadcast(void)
    6.20 +{
    6.21 +    unsigned int lvr, version;
    6.22 +    lvr = apic_read(APIC_LVR);
    6.23 +    version = GET_APIC_VERSION(lvr);
    6.24 +    if (!APIC_INTEGRATED(version) || version >= 0x14)
    6.25 +        return 0xff;
    6.26 +    else
    6.27 +        return 0xf;
    6.28 +}
    6.29 +
    6.30  int get_maxlvt(void)
    6.31  {
    6.32      unsigned int v, ver, maxlvt;
    6.33 @@ -907,7 +920,7 @@ int __init APIC_init_uniprocessor (void)
    6.34  #ifdef CONFIG_SMP
    6.35      cpu_online_map = 1;
    6.36  #endif
    6.37 -    phys_cpu_present_map = 1;
    6.38 +    phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
    6.39      apic_write_around(APIC_ID, boot_cpu_physical_apicid);
    6.40  
    6.41      setup_local_APIC();

     7.1 --- a/xen/arch/x86/i8259.c	Mon May 09 14:34:59 2005 +0000
     7.2 +++ b/xen/arch/x86/i8259.c	Mon May 09 17:50:11 2005 +0000
     7.3 @@ -45,7 +45,7 @@ BUILD_COMMON_IRQ()
     7.4  
     7.5  /*
     7.6   * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
     7.7 - * (these are usually mapped to vectors 0x30-0x3f)
     7.8 + * (these are usually mapped to vectors 0x20-0x2f)
     7.9   */
    7.10  BUILD_16_IRQS(0x0)
    7.11  
    7.12 @@ -58,7 +58,7 @@ BUILD_16_IRQS(0x0)
    7.13   * of these. Plus, more powerful systems might have more than 64
    7.14   * IO-APIC registers.
    7.15   *
    7.16 - * (these are usually mapped into the 0x30-0xff vector range)
    7.17 + * (these are usually mapped into the 0x20-0xff vector range)
    7.18   */
    7.19  BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
    7.20  BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
    7.21 @@ -101,7 +101,7 @@ BUILD_SMP_INTERRUPT(spurious_interrupt,S
    7.22  	IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
    7.23  	IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
    7.24  
    7.25 -    void *interrupt[NR_IRQS] = {
    7.26 +    void (*interrupt[NR_IRQS])(void) = {
    7.27  	IRQLIST_16(0x0),
    7.28  
    7.29  #ifdef CONFIG_X86_IO_APIC
    7.30 @@ -341,7 +341,7 @@ void __init init_8259A(int auto_eoi)
    7.31       * outb_p - this has to work on a wide range of PC hardware.
    7.32       */
    7.33      outb_p(0x11, 0x20);	/* ICW1: select 8259A-1 init */
    7.34 -    outb_p(0x30 + 0, 0x21);	/* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 */
    7.35 +    outb_p(0x20 + 0, 0x21);	/* ICW2: 8259A-1 IR0-7 mapped to 0x20-0x27 */
    7.36      outb_p(0x04, 0x21);	/* 8259A-1 (the master) has a slave on IR2 */
    7.37      if (auto_eoi)
    7.38          outb_p(0x03, 0x21);	/* master does Auto EOI */
    7.39 @@ -349,7 +349,7 @@ void __init init_8259A(int auto_eoi)
    7.40          outb_p(0x01, 0x21);	/* master expects normal EOI */
    7.41  
    7.42      outb_p(0x11, 0xA0);	/* ICW1: select 8259A-2 init */
    7.43 -    outb_p(0x30 + 8, 0xA1);	/* ICW2: 8259A-2 IR0-7 mapped to 0x38-0x3f */
    7.44 +    outb_p(0x20 + 8, 0xA1);	/* ICW2: 8259A-2 IR0-7 mapped to 0x28-0x2f */
    7.45      outb_p(0x02, 0xA1);	/* 8259A-2 is a slave on master's IR2 */
    7.46      outb_p(0x01, 0xA1);	/* (slave's support for AEOI in flat mode
    7.47                             is to be investigated) */

     8.1 --- a/xen/arch/x86/io_apic.c	Mon May 09 14:34:59 2005 +0000
     8.2 +++ b/xen/arch/x86/io_apic.c	Mon May 09 17:50:11 2005 +0000
     8.3 @@ -25,26 +25,20 @@
     8.4  #include <xen/irq.h>
     8.5  #include <xen/delay.h>
     8.6  #include <xen/sched.h>
     8.7 -#include <xen/config.h>
     8.8 -#include <asm/mc146818rtc.h>
     8.9 +#include <xen/acpi.h>
    8.10  #include <asm/io.h>
    8.11 -#include <asm/mpspec.h>
    8.12 -#include <asm/io_apic.h>
    8.13 +#include <asm/mc146818rtc.h>
    8.14  #include <asm/smp.h>
    8.15  #include <asm/desc.h>
    8.16 -#include <asm/smpboot.h>
    8.17 -
    8.18 -#ifdef CONFIG_X86_IO_APIC
    8.19 -
    8.20 -#undef APIC_LOCKUP_DEBUG
    8.21 +#include <mach_apic.h>
    8.22 +#include <io_ports.h>
    8.23  
    8.24 -#define APIC_LOCKUP_DEBUG
    8.25 -
    8.26 -static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
    8.27 +int (*ioapic_renumber_irq)(int ioapic, int irq);
    8.28 +atomic_t irq_mis_count;
    8.29  
    8.30 -unsigned int int_dest_addr_mode = APIC_DEST_LOGICAL;
    8.31 -unsigned char int_delivery_mode = dest_LowestPrio;
    8.32 +static DEFINE_SPINLOCK(ioapic_lock);
    8.33  
    8.34 +int skip_ioapic_setup;
    8.35  
    8.36  /*
    8.37   * # of IRQ routing registers
    8.38 @@ -69,12 +63,20 @@ static struct irq_pin_list {
    8.39  	int apic, pin, next;
    8.40  } irq_2_pin[PIN_MAP_SIZE];
    8.41  
    8.42 +int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
    8.43 +#ifdef CONFIG_PCI_MSI
    8.44 +#define vector_to_irq(vector) 	\
    8.45 +	(platform_legacy_irq(vector) ? vector : vector_irq[vector])
    8.46 +#else
    8.47 +#define vector_to_irq(vector)	(vector)
    8.48 +#endif
    8.49 +
    8.50  /*
    8.51   * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
    8.52   * shared ISA-space IRQs, so we have to support them. We are super
    8.53   * fast in the common case, and fast for shared ISA-space IRQs.
    8.54   */
    8.55 -static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
    8.56 +static void add_pin_to_irq(unsigned int irq, int apic, int pin)
    8.57  {
    8.58  	static int first_free_entry = NR_IRQS;
    8.59  	struct irq_pin_list *entry = irq_2_pin + irq;
    8.60 @@ -112,36 +114,48 @@ static void __init replace_pin_at_irq(un
    8.61  	}
    8.62  }
    8.63  
    8.64 -#define __DO_ACTION(R, ACTION, FINAL)					\
    8.65 -									\
    8.66 -{									\
    8.67 -	int pin;							\
    8.68 -	struct irq_pin_list *entry = irq_2_pin + irq;			\
    8.69 -									\
    8.70 -	for (;;) {							\
    8.71 -		unsigned int reg;					\
    8.72 -		pin = entry->pin;					\
    8.73 -		if (pin == -1)						\
    8.74 -			break;						\
    8.75 -		reg = io_apic_read(entry->apic, 0x10 + R + pin*2);	\
    8.76 -		reg ACTION;						\
    8.77 -		io_apic_write(entry->apic, 0x10 + R + pin*2, reg);	\
    8.78 -		if (!entry->next)					\
    8.79 -			break;						\
    8.80 -		entry = irq_2_pin + entry->next;			\
    8.81 -	}								\
    8.82 -	FINAL;								\
    8.83 +static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
    8.84 +{
    8.85 +	struct irq_pin_list *entry = irq_2_pin + irq;
    8.86 +	unsigned int pin, reg;
    8.87 +
    8.88 +	for (;;) {
    8.89 +		pin = entry->pin;
    8.90 +		if (pin == -1)
    8.91 +			break;
    8.92 +		reg = io_apic_read(entry->apic, 0x10 + pin*2);
    8.93 +		reg &= ~disable;
    8.94 +		reg |= enable;
    8.95 +		io_apic_modify(entry->apic, 0x10 + pin*2, reg);
    8.96 +		if (!entry->next)
    8.97 +			break;
    8.98 +		entry = irq_2_pin + entry->next;
    8.99 +	}
   8.100  }
   8.101  
   8.102 -#define DO_ACTION(name,R,ACTION, FINAL)					\
   8.103 -									\
   8.104 -	static void name##_IO_APIC_irq (unsigned int irq)		\
   8.105 -	__DO_ACTION(R, ACTION, FINAL)
   8.106 +/* mask = 1 */
   8.107 +static void __mask_IO_APIC_irq (unsigned int irq)
   8.108 +{
   8.109 +	__modify_IO_APIC_irq(irq, 0x00010000, 0);
   8.110 +}
   8.111 +
   8.112 +/* mask = 0 */
   8.113 +static void __unmask_IO_APIC_irq (unsigned int irq)
   8.114 +{
   8.115 +	__modify_IO_APIC_irq(irq, 0, 0x00010000);
   8.116 +}
   8.117  
   8.118 -DO_ACTION( __mask,    0, |= 0x00010000, io_apic_sync(entry->apic) )
   8.119 -DO_ACTION( __unmask,  0, &= 0xfffeffff, )
   8.120 -DO_ACTION( __edge,    0, &= 0xffff7fff, )
   8.121 -DO_ACTION( __level,   0, |= 0x00008000, )
   8.122 +/* mask = 1, trigger = 0 */
   8.123 +static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
   8.124 +{
   8.125 +	__modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
   8.126 +}
   8.127 +
   8.128 +/* mask = 0, trigger = 1 */
   8.129 +static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
   8.130 +{
   8.131 +	__modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
   8.132 +}
   8.133  
   8.134  static void mask_IO_APIC_irq (unsigned int irq)
   8.135  {
   8.136 @@ -165,7 +179,7 @@ void clear_IO_APIC_pin(unsigned int apic
   8.137  {
   8.138  	struct IO_APIC_route_entry entry;
   8.139  	unsigned long flags;
   8.140 -
   8.141 +	
   8.142  	/* Check delivery_mode to be sure we're not clearing an SMI pin */
   8.143  	spin_lock_irqsave(&ioapic_lock, flags);
   8.144  	*(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
   8.145 @@ -194,85 +208,467 @@ static void clear_IO_APIC (void)
   8.146  			clear_IO_APIC_pin(apic, pin);
   8.147  }
   8.148  
   8.149 -static void set_ioapic_affinity (unsigned int irq, unsigned long mask)
   8.150 +static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
   8.151  {
   8.152  	unsigned long flags;
   8.153 -
   8.154 -	/*
   8.155 -	 * Only the first 8 bits are valid.
   8.156 -	 */
   8.157 -	mask = mask << 24;
   8.158 +	int pin;
   8.159 +	struct irq_pin_list *entry = irq_2_pin + irq;
   8.160 +	unsigned int apicid_value;
   8.161 +	
   8.162 +	apicid_value = cpu_mask_to_apicid(cpumask);
   8.163 +	/* Prepare to do the io_apic_write */
   8.164 +	apicid_value = apicid_value << 24;
   8.165  	spin_lock_irqsave(&ioapic_lock, flags);
   8.166 -	__DO_ACTION(1, = mask, )
   8.167 +	for (;;) {
   8.168 +		pin = entry->pin;
   8.169 +		if (pin == -1)
   8.170 +			break;
   8.171 +		io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
   8.172 +		if (!entry->next)
   8.173 +			break;
   8.174 +		entry = irq_2_pin + entry->next;
   8.175 +	}
   8.176  	spin_unlock_irqrestore(&ioapic_lock, flags);
   8.177  }
   8.178  
   8.179 -#define balance_irq(_irq) ((void)0)
   8.180 +#if defined(CONFIG_IRQBALANCE)
   8.181 +# include <asm/processor.h>	/* kernel_thread() */
   8.182 +# include <xen/kernel_stat.h>	/* kstat */
   8.183 +# include <xen/slab.h>		/* kmalloc() */
   8.184 +# include <xen/timer.h>	/* time_after() */
   8.185 + 
   8.186 +# ifdef CONFIG_BALANCED_IRQ_DEBUG
   8.187 +#  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
   8.188 +#  define Dprintk(x...) do { TDprintk(x); } while (0)
   8.189 +# else
   8.190 +#  define TDprintk(x...) 
   8.191 +#  define Dprintk(x...) 
   8.192 +# endif
   8.193 +
   8.194 +cpumask_t __cacheline_aligned pending_irq_balance_cpumask[NR_IRQS];
   8.195  
   8.196 -/*
   8.197 - * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
   8.198 - * specific CPU-side IRQs.
   8.199 - */
   8.200 +#define IRQBALANCE_CHECK_ARCH -999
   8.201 +static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
   8.202 +static int physical_balance = 0;
   8.203 +
   8.204 +struct irq_cpu_info {
   8.205 +	unsigned long * last_irq;
   8.206 +	unsigned long * irq_delta;
   8.207 +	unsigned long irq;
   8.208 +} irq_cpu_data[NR_CPUS];
   8.209 +
   8.210 +#define CPU_IRQ(cpu)		(irq_cpu_data[cpu].irq)
   8.211 +#define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
   8.212 +#define IRQ_DELTA(cpu,irq) 	(irq_cpu_data[cpu].irq_delta[irq])
   8.213 +
   8.214 +#define IDLE_ENOUGH(cpu,now) \
   8.215 +		(idle_cpu(cpu) && ((now) - irq_stat[(cpu)].idle_timestamp > 1))
   8.216 +
   8.217 +#define IRQ_ALLOWED(cpu, allowed_mask)	cpu_isset(cpu, allowed_mask)
   8.218  
   8.219 -#define MAX_PIRQS 8
   8.220 -int pirq_entries [MAX_PIRQS];
   8.221 -int pirqs_enabled;
   8.222 +#define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
   8.223 +
   8.224 +#define MAX_BALANCED_IRQ_INTERVAL	(5*HZ)
   8.225 +#define MIN_BALANCED_IRQ_INTERVAL	(HZ/2)
   8.226 +#define BALANCED_IRQ_MORE_DELTA		(HZ/10)
   8.227 +#define BALANCED_IRQ_LESS_DELTA		(HZ)
   8.228 +
   8.229 +long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
   8.230 +
   8.231 +static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
   8.232 +			unsigned long now, int direction)
   8.233 +{
   8.234 +	int search_idle = 1;
   8.235 +	int cpu = curr_cpu;
   8.236 +
   8.237 +	goto inside;
   8.238  
   8.239 -int skip_ioapic_setup;
   8.240 -#if 0
   8.241 +	do {
   8.242 +		if (unlikely(cpu == curr_cpu))
   8.243 +			search_idle = 0;
   8.244 +inside:
   8.245 +		if (direction == 1) {
   8.246 +			cpu++;
   8.247 +			if (cpu >= NR_CPUS)
   8.248 +				cpu = 0;
   8.249 +		} else {
   8.250 +			cpu--;
   8.251 +			if (cpu == -1)
   8.252 +				cpu = NR_CPUS-1;
   8.253 +		}
   8.254 +	} while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
   8.255 +			(search_idle && !IDLE_ENOUGH(cpu,now)));
   8.256  
   8.257 -static int __init noioapic_setup(char *str)
   8.258 -{
   8.259 -	skip_ioapic_setup = 1;
   8.260 -	return 1;
   8.261 +	return cpu;
   8.262  }
   8.263  
   8.264 -__setup("noapic", noioapic_setup);
   8.265 +static inline void balance_irq(int cpu, int irq)
   8.266 +{
   8.267 +	unsigned long now = jiffies;
   8.268 +	cpumask_t allowed_mask;
   8.269 +	unsigned int new_cpu;
   8.270 +		
   8.271 +	if (irqbalance_disabled)
   8.272 +		return; 
   8.273 +
   8.274 +	cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
   8.275 +	new_cpu = move(cpu, allowed_mask, now, 1);
   8.276 +	if (cpu != new_cpu) {
   8.277 +		irq_desc_t *desc = irq_desc + irq;
   8.278 +		unsigned long flags;
   8.279  
   8.280 -static int __init ioapic_setup(char *str)
   8.281 +		spin_lock_irqsave(&desc->lock, flags);
   8.282 +		pending_irq_balance_cpumask[irq] = cpumask_of_cpu(new_cpu);
   8.283 +		spin_unlock_irqrestore(&desc->lock, flags);
   8.284 +	}
   8.285 +}
   8.286 +
   8.287 +static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
   8.288  {
   8.289 -	skip_ioapic_setup = 0;
   8.290 -	return 1;
   8.291 +	int i, j;
   8.292 +	Dprintk("Rotating IRQs among CPUs.\n");
   8.293 +	for (i = 0; i < NR_CPUS; i++) {
   8.294 +		for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
   8.295 +			if (!irq_desc[j].action)
   8.296 +				continue;
   8.297 +			/* Is it a significant load ?  */
   8.298 +			if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
   8.299 +						useful_load_threshold)
   8.300 +				continue;
   8.301 +			balance_irq(i, j);
   8.302 +		}
   8.303 +	}
   8.304 +	balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
   8.305 +		balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);	
   8.306 +	return;
   8.307  }
   8.308  
   8.309 -__setup("apic", ioapic_setup);
   8.310 -
   8.311 -
   8.312 -
   8.313 -static int __init ioapic_pirq_setup(char *str)
   8.314 +static void do_irq_balance(void)
   8.315  {
   8.316 -	int i, max;
   8.317 -	int ints[MAX_PIRQS+1];
   8.318 +	int i, j;
   8.319 +	unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
   8.320 +	unsigned long move_this_load = 0;
   8.321 +	int max_loaded = 0, min_loaded = 0;
   8.322 +	int load;
   8.323 +	unsigned long useful_load_threshold = balanced_irq_interval + 10;
   8.324 +	int selected_irq;
   8.325 +	int tmp_loaded, first_attempt = 1;
   8.326 +	unsigned long tmp_cpu_irq;
   8.327 +	unsigned long imbalance = 0;
   8.328 +	cpumask_t allowed_mask, target_cpu_mask, tmp;
   8.329 +
   8.330 +	for (i = 0; i < NR_CPUS; i++) {
   8.331 +		int package_index;
   8.332 +		CPU_IRQ(i) = 0;
   8.333 +		if (!cpu_online(i))
   8.334 +			continue;
   8.335 +		package_index = CPU_TO_PACKAGEINDEX(i);
   8.336 +		for (j = 0; j < NR_IRQS; j++) {
   8.337 +			unsigned long value_now, delta;
   8.338 +			/* Is this an active IRQ? */
   8.339 +			if (!irq_desc[j].action)
   8.340 +				continue;
   8.341 +			if ( package_index == i )
   8.342 +				IRQ_DELTA(package_index,j) = 0;
   8.343 +			/* Determine the total count per processor per IRQ */
   8.344 +			value_now = (unsigned long) kstat_cpu(i).irqs[j];
   8.345 +
   8.346 +			/* Determine the activity per processor per IRQ */
   8.347 +			delta = value_now - LAST_CPU_IRQ(i,j);
   8.348 +
   8.349 +			/* Update last_cpu_irq[][] for the next time */
   8.350 +			LAST_CPU_IRQ(i,j) = value_now;
   8.351 +
   8.352 +			/* Ignore IRQs whose rate is less than the clock */
   8.353 +			if (delta < useful_load_threshold)
   8.354 +				continue;
   8.355 +			/* update the load for the processor or package total */
   8.356 +			IRQ_DELTA(package_index,j) += delta;
   8.357  
   8.358 -	get_options(str, ARRAY_SIZE(ints), ints);
   8.359 +			/* Keep track of the higher numbered sibling as well */
   8.360 +			if (i != package_index)
   8.361 +				CPU_IRQ(i) += delta;
   8.362 +			/*
   8.363 +			 * We have sibling A and sibling B in the package
   8.364 +			 *
   8.365 +			 * cpu_irq[A] = load for cpu A + load for cpu B
   8.366 +			 * cpu_irq[B] = load for cpu B
   8.367 +			 */
   8.368 +			CPU_IRQ(package_index) += delta;
   8.369 +		}
   8.370 +	}
   8.371 +	/* Find the least loaded processor package */
   8.372 +	for (i = 0; i < NR_CPUS; i++) {
   8.373 +		if (!cpu_online(i))
   8.374 +			continue;
   8.375 +		if (i != CPU_TO_PACKAGEINDEX(i))
   8.376 +			continue;
   8.377 +		if (min_cpu_irq > CPU_IRQ(i)) {
   8.378 +			min_cpu_irq = CPU_IRQ(i);
   8.379 +			min_loaded = i;
   8.380 +		}
   8.381 +	}
   8.382 +	max_cpu_irq = ULONG_MAX;
   8.383  
   8.384 -	for (i = 0; i < MAX_PIRQS; i++)
   8.385 -		pirq_entries[i] = -1;
   8.386 +tryanothercpu:
   8.387 +	/* Look for heaviest loaded processor.
   8.388 +	 * We may come back to get the next heaviest loaded processor.
   8.389 +	 * Skip processors with trivial loads.
   8.390 +	 */
   8.391 +	tmp_cpu_irq = 0;
   8.392 +	tmp_loaded = -1;
   8.393 +	for (i = 0; i < NR_CPUS; i++) {
   8.394 +		if (!cpu_online(i))
   8.395 +			continue;
   8.396 +		if (i != CPU_TO_PACKAGEINDEX(i))
   8.397 +			continue;
   8.398 +		if (max_cpu_irq <= CPU_IRQ(i)) 
   8.399 +			continue;
   8.400 +		if (tmp_cpu_irq < CPU_IRQ(i)) {
   8.401 +			tmp_cpu_irq = CPU_IRQ(i);
   8.402 +			tmp_loaded = i;
   8.403 +		}
   8.404 +	}
   8.405  
   8.406 -	pirqs_enabled = 1;
   8.407 -	printk(KERN_INFO "PIRQ redirection, working around broken MP-BIOS.\n");
   8.408 -	max = MAX_PIRQS;
   8.409 -	if (ints[0] < MAX_PIRQS)
   8.410 -		max = ints[0];
   8.411 +	if (tmp_loaded == -1) {
   8.412 + 	 /* In the case of small number of heavy interrupt sources, 
   8.413 +	  * loading some of the cpus too much. We use Ingo's original 
   8.414 +	  * approach to rotate them around.
   8.415 +	  */
   8.416 +		if (!first_attempt && imbalance >= useful_load_threshold) {
   8.417 +			rotate_irqs_among_cpus(useful_load_threshold);
   8.418 +			return;
   8.419 +		}
   8.420 +		goto not_worth_the_effort;
   8.421 +	}
   8.422 +	
   8.423 +	first_attempt = 0;		/* heaviest search */
   8.424 +	max_cpu_irq = tmp_cpu_irq;	/* load */
   8.425 +	max_loaded = tmp_loaded;	/* processor */
   8.426 +	imbalance = (max_cpu_irq - min_cpu_irq) / 2;
   8.427 +	
   8.428 +	Dprintk("max_loaded cpu = %d\n", max_loaded);
   8.429 +	Dprintk("min_loaded cpu = %d\n", min_loaded);
   8.430 +	Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
   8.431 +	Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
   8.432 +	Dprintk("load imbalance = %lu\n", imbalance);
   8.433 +
   8.434 +	/* if imbalance is less than approx 10% of max load, then
   8.435 +	 * observe diminishing returns action. - quit
   8.436 +	 */
   8.437 +	if (imbalance < (max_cpu_irq >> 3)) {
   8.438 +		Dprintk("Imbalance too trivial\n");
   8.439 +		goto not_worth_the_effort;
   8.440 +	}
   8.441 +
   8.442 +tryanotherirq:
   8.443 +	/* if we select an IRQ to move that can't go where we want, then
   8.444 +	 * see if there is another one to try.
   8.445 +	 */
   8.446 +	move_this_load = 0;
   8.447 +	selected_irq = -1;
   8.448 +	for (j = 0; j < NR_IRQS; j++) {
   8.449 +		/* Is this an active IRQ? */
   8.450 +		if (!irq_desc[j].action)
   8.451 +			continue;
   8.452 +		if (imbalance <= IRQ_DELTA(max_loaded,j))
   8.453 +			continue;
   8.454 +		/* Try to find the IRQ that is closest to the imbalance
   8.455 +		 * without going over.
   8.456 +		 */
   8.457 +		if (move_this_load < IRQ_DELTA(max_loaded,j)) {
   8.458 +			move_this_load = IRQ_DELTA(max_loaded,j);
   8.459 +			selected_irq = j;
   8.460 +		}
   8.461 +	}
   8.462 +	if (selected_irq == -1) {
   8.463 +		goto tryanothercpu;
   8.464 +	}
   8.465  
   8.466 -	for (i = 0; i < max; i++) {
   8.467 -		printk(KERN_DEBUG "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
   8.468 -		/*
   8.469 -		 * PIRQs are mapped upside down, usually.
   8.470 +	imbalance = move_this_load;
   8.471 +	
   8.472 +	/* For physical_balance case, we accumlated both load
   8.473 +	 * values in the one of the siblings cpu_irq[],
   8.474 +	 * to use the same code for physical and logical processors
   8.475 +	 * as much as possible. 
   8.476 +	 *
   8.477 +	 * NOTE: the cpu_irq[] array holds the sum of the load for
   8.478 +	 * sibling A and sibling B in the slot for the lowest numbered
   8.479 +	 * sibling (A), _AND_ the load for sibling B in the slot for
   8.480 +	 * the higher numbered sibling.
   8.481 +	 *
   8.482 +	 * We seek the least loaded sibling by making the comparison
   8.483 +	 * (A+B)/2 vs B
   8.484 +	 */
   8.485 +	load = CPU_IRQ(min_loaded) >> 1;
   8.486 +	for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
   8.487 +		if (load > CPU_IRQ(j)) {
   8.488 +			/* This won't change cpu_sibling_map[min_loaded] */
   8.489 +			load = CPU_IRQ(j);
   8.490 +			min_loaded = j;
   8.491 +		}
   8.492 +	}
   8.493 +
   8.494 +	cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
   8.495 +	target_cpu_mask = cpumask_of_cpu(min_loaded);
   8.496 +	cpus_and(tmp, target_cpu_mask, allowed_mask);
   8.497 +
   8.498 +	if (!cpus_empty(tmp)) {
   8.499 +		irq_desc_t *desc = irq_desc + selected_irq;
   8.500 +		unsigned long flags;
   8.501 +
   8.502 +		Dprintk("irq = %d moved to cpu = %d\n",
   8.503 +				selected_irq, min_loaded);
   8.504 +		/* mark for change destination */
   8.505 +		spin_lock_irqsave(&desc->lock, flags);
   8.506 +		pending_irq_balance_cpumask[selected_irq] =
   8.507 +					cpumask_of_cpu(min_loaded);
   8.508 +		spin_unlock_irqrestore(&desc->lock, flags);
   8.509 +		/* Since we made a change, come back sooner to 
   8.510 +		 * check for more variation.
   8.511  		 */
   8.512 -		pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
   8.513 +		balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
   8.514 +			balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);	
   8.515 +		return;
   8.516  	}
   8.517 -	return 1;
   8.518 +	goto tryanotherirq;
   8.519 +
   8.520 +not_worth_the_effort:
   8.521 +	/*
   8.522 +	 * if we did not find an IRQ to move, then adjust the time interval
   8.523 +	 * upward
   8.524 +	 */
   8.525 +	balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
   8.526 +		balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);	
   8.527 +	Dprintk("IRQ worth rotating not found\n");
   8.528 +	return;
   8.529  }
   8.530  
   8.531 -__setup("pirq=", ioapic_pirq_setup);
   8.532 +static int balanced_irq(void *unused)
   8.533 +{
   8.534 +	int i;
   8.535 +	unsigned long prev_balance_time = jiffies;
   8.536 +	long time_remaining = balanced_irq_interval;
   8.537 +
   8.538 +	daemonize("kirqd");
   8.539 +	
   8.540 +	/* push everything to CPU 0 to give us a starting point.  */
   8.541 +	for (i = 0 ; i < NR_IRQS ; i++) {
   8.542 +		pending_irq_balance_cpumask[i] = cpumask_of_cpu(0);
   8.543 +	}
   8.544 +
   8.545 +	for ( ; ; ) {
   8.546 +		set_current_state(TASK_INTERRUPTIBLE);
   8.547 +		time_remaining = schedule_timeout(time_remaining);
   8.548 +		try_to_freeze(PF_FREEZE);
   8.549 +		if (time_after(jiffies,
   8.550 +				prev_balance_time+balanced_irq_interval)) {
   8.551 +			do_irq_balance();
   8.552 +			prev_balance_time = jiffies;
   8.553 +			time_remaining = balanced_irq_interval;
   8.554 +		}
   8.555 +	}
   8.556 +	return 0;
   8.557 +}
   8.558 +
   8.559 +static int __init balanced_irq_init(void)
   8.560 +{
   8.561 +	int i;
   8.562 +	struct cpuinfo_x86 *c;
   8.563 +	cpumask_t tmp;
   8.564 +
   8.565 +	cpus_shift_right(tmp, cpu_online_map, 2);
   8.566 +        c = &boot_cpu_data;
   8.567 +	/* When not overwritten by the command line ask subarchitecture. */
   8.568 +	if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
   8.569 +		irqbalance_disabled = NO_BALANCE_IRQ;
   8.570 +	if (irqbalance_disabled)
   8.571 +		return 0;
   8.572 +	
   8.573 +	 /* disable irqbalance completely if there is only one processor online */
   8.574 +	if (num_online_cpus() < 2) {
   8.575 +		irqbalance_disabled = 1;
   8.576 +		return 0;
   8.577 +	}
   8.578 +	/*
   8.579 +	 * Enable physical balance only if more than 1 physical processor
   8.580 +	 * is present
   8.581 +	 */
   8.582 +	if (smp_num_siblings > 1 && !cpus_empty(tmp))
   8.583 +		physical_balance = 1;
   8.584  
   8.585 -#endif
   8.586 +	for (i = 0; i < NR_CPUS; i++) {
   8.587 +		if (!cpu_online(i))
   8.588 +			continue;
   8.589 +		irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
   8.590 +		irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
   8.591 +		if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
   8.592 +			printk(KERN_ERR "balanced_irq_init: out of memory");
   8.593 +			goto failed;
   8.594 +		}
   8.595 +		memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
   8.596 +		memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
   8.597 +	}
   8.598 +	
   8.599 +	printk(KERN_INFO "Starting balanced_irq\n");
   8.600 +	if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0) 
   8.601 +		return 0;
   8.602 +	else 
   8.603 +		printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
   8.604 +failed:
   8.605 +	for (i = 0; i < NR_CPUS; i++) {
   8.606 +		if(irq_cpu_data[i].irq_delta)
   8.607 +			kfree(irq_cpu_data[i].irq_delta);
   8.608 +		if(irq_cpu_data[i].last_irq)
   8.609 +			kfree(irq_cpu_data[i].last_irq);
   8.610 +	}
   8.611 +	return 0;
   8.612 +}
   8.613 +
   8.614 +int __init irqbalance_disable(char *str)
   8.615 +{
   8.616 +	irqbalance_disabled = 1;
   8.617 +	return 0;
   8.618 +}
   8.619 +
   8.620 +__setup("noirqbalance", irqbalance_disable);
   8.621 +
   8.622 +static inline void move_irq(int irq)
   8.623 +{
   8.624 +	/* note - we hold the desc->lock */
   8.625 +	if (unlikely(!cpus_empty(pending_irq_balance_cpumask[irq]))) {
   8.626 +		set_ioapic_affinity_irq(irq, pending_irq_balance_cpumask[irq]);
   8.627 +		cpus_clear(pending_irq_balance_cpumask[irq]);
   8.628 +	}
   8.629 +}
   8.630 +
   8.631 +late_initcall(balanced_irq_init);
   8.632 +
   8.633 +#else /* !CONFIG_IRQBALANCE */
   8.634 +static inline void move_irq(int irq) { }
   8.635 +#endif /* CONFIG_IRQBALANCE */
   8.636 +
   8.637 +#ifndef CONFIG_SMP
   8.638 +void fastcall send_IPI_self(int vector)
   8.639 +{
   8.640 +	unsigned int cfg;
   8.641 +
   8.642 +	/*
   8.643 +	 * Wait for idle.
   8.644 +	 */
   8.645 +	apic_wait_icr_idle();
   8.646 +	cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
   8.647 +	/*
   8.648 +	 * Send the IPI. The write to APIC_ICR fires this off.
   8.649 +	 */
   8.650 +	apic_write_around(APIC_ICR, cfg);
   8.651 +}
   8.652 +#endif /* !CONFIG_SMP */
   8.653  
   8.654  /*
   8.655   * Find the IRQ entry number of a certain pin.
   8.656   */
   8.657 -static int __init find_irq_entry(int apic, int pin, int type)
   8.658 +static int find_irq_entry(int apic, int pin, int type)
   8.659  {
   8.660  	int i;
   8.661  
   8.662 @@ -289,7 +685,7 @@ static int __init find_irq_entry(int api
   8.663  /*
   8.664   * Find the pin to which IRQ[irq] (ISA) is connected
   8.665   */
   8.666 -static int __init find_isa_irq_pin(int irq, int type)
   8.667 +static int find_isa_irq_pin(int irq, int type)
   8.668  {
   8.669  	int i;
   8.670  
   8.671 @@ -298,7 +694,9 @@ static int __init find_isa_irq_pin(int i
   8.672  
   8.673  		if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
   8.674  		     mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
   8.675 -		     mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
   8.676 +		     mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
   8.677 +		     mp_bus_id_to_type[lbus] == MP_BUS_NEC98
   8.678 +		    ) &&
   8.679  		    (mp_irqs[i].mpc_irqtype == type) &&
   8.680  		    (mp_irqs[i].mpc_srcbusirq == irq))
   8.681  
   8.682 @@ -313,16 +711,81 @@ static int __init find_isa_irq_pin(int i
   8.683   */
   8.684  static int pin_2_irq(int idx, int apic, int pin);
   8.685  
   8.686 +int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
   8.687 +{
   8.688 +	int apic, i, best_guess = -1;
   8.689 +
   8.690 +	apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
   8.691 +		"slot:%d, pin:%d.\n", bus, slot, pin);
   8.692 +	if (mp_bus_id_to_pci_bus[bus] == -1) {
   8.693 +		printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
   8.694 +		return -1;
   8.695 +	}
   8.696 +	for (i = 0; i < mp_irq_entries; i++) {
   8.697 +		int lbus = mp_irqs[i].mpc_srcbus;
   8.698 +
   8.699 +		for (apic = 0; apic < nr_ioapics; apic++)
   8.700 +			if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
   8.701 +			    mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
   8.702 +				break;
   8.703 +
   8.704 +		if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
   8.705 +		    !mp_irqs[i].mpc_irqtype &&
   8.706 +		    (bus == lbus) &&
   8.707 +		    (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
   8.708 +			int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
   8.709 +
   8.710 +			if (!(apic || IO_APIC_IRQ(irq)))
   8.711 +				continue;
   8.712 +
   8.713 +			if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
   8.714 +				return irq;
   8.715 +			/*
   8.716 +			 * Use the first all-but-pin matching entry as a
   8.717 +			 * best-guess fuzzy result for broken mptables.
   8.718 +			 */
   8.719 +			if (best_guess < 0)
   8.720 +				best_guess = irq;
   8.721 +		}
   8.722 +	}
   8.723 +	return best_guess;
   8.724 +}
   8.725 +
   8.726 +/*
   8.727 + * This function currently is only a helper for the i386 smp boot process where 
   8.728 + * we need to reprogram the ioredtbls to cater for the cpus which have come online
   8.729 + * so mask in all cases should simply be TARGET_CPUS
   8.730 + */
   8.731 +void __init setup_ioapic_dest(void)
   8.732 +{
   8.733 +	int pin, ioapic, irq, irq_entry;
   8.734 +
   8.735 +	if (skip_ioapic_setup == 1)
   8.736 +		return;
   8.737 +
   8.738 +	for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
   8.739 +		for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
   8.740 +			irq_entry = find_irq_entry(ioapic, pin, mp_INT);
   8.741 +			if (irq_entry == -1)
   8.742 +				continue;
   8.743 +			irq = pin_2_irq(irq_entry, ioapic, pin);
   8.744 +			set_ioapic_affinity_irq(irq, TARGET_CPUS);
   8.745 +		}
   8.746 +
   8.747 +	}
   8.748 +}
   8.749 +
   8.750  /*
   8.751   * EISA Edge/Level control register, ELCR
   8.752   */
   8.753 -static int __init EISA_ELCR(unsigned int irq)
   8.754 +static int EISA_ELCR(unsigned int irq)
   8.755  {
   8.756  	if (irq < 16) {
   8.757  		unsigned int port = 0x4d0 + (irq >> 3);
   8.758  		return (inb(port) >> (irq & 7)) & 1;
   8.759  	}
   8.760 -	printk(KERN_INFO "Broken MPtable reports ISA irq %d\n", irq);
   8.761 +	apic_printk(APIC_VERBOSE, KERN_INFO
   8.762 +			"Broken MPtable reports ISA irq %d\n", irq);
   8.763  	return 0;
   8.764  }
   8.765  
   8.766 @@ -352,6 +815,12 @@ static int __init EISA_ELCR(unsigned int
   8.767  #define default_MCA_trigger(idx)	(1)
   8.768  #define default_MCA_polarity(idx)	(0)
   8.769  
   8.770 +/* NEC98 interrupts are always polarity zero edge triggered,
   8.771 + * when listed as conforming in the MP table. */
   8.772 +
   8.773 +#define default_NEC98_trigger(idx)     (0)
   8.774 +#define default_NEC98_polarity(idx)    (0)
   8.775 +
   8.776  static int __init MPBIOS_polarity(int idx)
   8.777  {
   8.778  	int bus = mp_irqs[idx].mpc_srcbus;
   8.779 @@ -386,6 +855,11 @@ static int __init MPBIOS_polarity(int id
   8.780  					polarity = default_MCA_polarity(idx);
   8.781  					break;
   8.782  				}
   8.783 +				case MP_BUS_NEC98: /* NEC 98 pin */
   8.784 +				{
   8.785 +					polarity = default_NEC98_polarity(idx);
   8.786 +					break;
   8.787 +				}
   8.788  				default:
   8.789  				{
   8.790  					printk(KERN_WARNING "broken BIOS!!\n");
   8.791 @@ -421,7 +895,7 @@ static int __init MPBIOS_polarity(int id
   8.792  	return polarity;
   8.793  }
   8.794  
   8.795 -static int __init MPBIOS_trigger(int idx)
   8.796 +static int MPBIOS_trigger(int idx)
   8.797  {
   8.798  	int bus = mp_irqs[idx].mpc_srcbus;
   8.799  	int trigger;
   8.800 @@ -455,6 +929,11 @@ static int __init MPBIOS_trigger(int idx
   8.801  					trigger = default_MCA_trigger(idx);
   8.802  					break;
   8.803  				}
   8.804 +				case MP_BUS_NEC98: /* NEC 98 pin */
   8.805 +				{
   8.806 +					trigger = default_NEC98_trigger(idx);
   8.807 +					break;
   8.808 +				}
   8.809  				default:
   8.810  				{
   8.811  					printk(KERN_WARNING "broken BIOS!!\n");
   8.812 @@ -516,6 +995,7 @@ static int pin_2_irq(int idx, int apic, 
   8.813  		case MP_BUS_ISA: /* ISA pin */
   8.814  		case MP_BUS_EISA:
   8.815  		case MP_BUS_MCA:
   8.816 +		case MP_BUS_NEC98:
   8.817  		{
   8.818  			irq = mp_irqs[idx].mpc_srcbusirq;
   8.819  			break;
   8.820 @@ -529,6 +1009,13 @@ static int pin_2_irq(int idx, int apic, 
   8.821  			while (i < apic)
   8.822  				irq += nr_ioapic_registers[i++];
   8.823  			irq += pin;
   8.824 +
   8.825 +			/*
   8.826 +			 * For MPS mode, so far only needed by ES7000 platform
   8.827 +			 */
   8.828 +			if (ioapic_renumber_irq)
   8.829 +				irq = ioapic_renumber_irq(apic, irq);
   8.830 +
   8.831  			break;
   8.832  		}
   8.833  		default:
   8.834 @@ -539,20 +1026,6 @@ static int pin_2_irq(int idx, int apic, 
   8.835  		}
   8.836  	}
   8.837  
   8.838 -	/*
   8.839 -	 * PCI IRQ command line redirection. Yes, limits are hardcoded.
   8.840 -	 */
   8.841 -	if ((pin >= 16) && (pin <= 23)) {
   8.842 -		if (pirq_entries[pin-16] != -1) {
   8.843 -			if (!pirq_entries[pin-16]) {
   8.844 -				printk(KERN_DEBUG "disabling PIRQ%d\n", pin-16);
   8.845 -			} else {
   8.846 -				irq = pirq_entries[pin-16];
   8.847 -				printk(KERN_DEBUG "using PIRQ%d -> IRQ %d\n",
   8.848 -						pin-16, irq);
   8.849 -			}
   8.850 -		}
   8.851 -	}
   8.852  	return irq;
   8.853  }
   8.854  
   8.855 @@ -573,90 +1046,74 @@ static inline int IO_APIC_irq_trigger(in
   8.856  	return 0;
   8.857  }
   8.858  
   8.859 -int irq_vector[NR_IRQS] = { FIRST_DEVICE_VECTOR , 0 };
   8.860 -
   8.861 -int vector_irq[256];
   8.862 +/* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
   8.863 +u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
   8.864  
   8.865  int assign_irq_vector(int irq)
   8.866  {
   8.867  	static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
   8.868 -	if (IO_APIC_VECTOR(irq) > 0)
   8.869 +
   8.870 +	BUG_ON(irq >= NR_IRQ_VECTORS);
   8.871 +	if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
   8.872  		return IO_APIC_VECTOR(irq);
   8.873  next:
   8.874  	current_vector += 8;
   8.875  
   8.876 -        /* Skip the hypercall vector. */
   8.877 -	if (current_vector == HYPERCALL_VECTOR) goto next;
   8.878 -        /* Skip the Linux/BSD fast-trap vector. */
   8.879 -        if (current_vector == 0x80) goto next;
   8.880 +	/* Skip the hypercall vector. */
   8.881 +	if (current_vector == HYPERCALL_VECTOR)
   8.882 +		goto next;
   8.883  
   8.884 -	if (current_vector > FIRST_SYSTEM_VECTOR) {
   8.885 +	/* Skip the Linux/BSD fast-trap vector. */
   8.886 +	if (current_vector == 0x80)
   8.887 +		goto next;
   8.888 +
   8.889 +	if (current_vector >= FIRST_SYSTEM_VECTOR) {
   8.890  		offset++;
   8.891 +		if (!(offset%8))
   8.892 +			return -ENOSPC;
   8.893  		current_vector = FIRST_DEVICE_VECTOR + offset;
   8.894  	}
   8.895  
   8.896 -	if (current_vector == FIRST_SYSTEM_VECTOR)
   8.897 -		panic("ran out of interrupt sources!");
   8.898 -
   8.899 -	IO_APIC_VECTOR(irq) = current_vector;
   8.900 -
   8.901 -        vector_irq[current_vector] = irq;
   8.902 +	vector_irq[current_vector] = irq;
   8.903 +	if (irq != AUTO_ASSIGN)
   8.904 +		IO_APIC_VECTOR(irq) = current_vector;
   8.905  
   8.906  	return current_vector;
   8.907  }
   8.908  
   8.909 -extern void (*interrupt[NR_IRQS])(void);
   8.910 +static struct hw_interrupt_type ioapic_level_type;
   8.911 +static struct hw_interrupt_type ioapic_edge_type;
   8.912  
   8.913 -/*
   8.914 - * Level and edge triggered IO-APIC interrupts need different handling,
   8.915 - * so we use two separate IRQ descriptors. Edge triggered IRQs can be
   8.916 - * handled with the level-triggered descriptor, but that one has slightly
   8.917 - * more overhead. Level-triggered interrupts cannot be handled with the
   8.918 - * edge-triggered handler, without risking IRQ storms and other ugly
   8.919 - * races.
   8.920 - */
   8.921 +#define IOAPIC_AUTO	-1
   8.922 +#define IOAPIC_EDGE	0
   8.923 +#define IOAPIC_LEVEL	1
   8.924  
   8.925 -static unsigned int startup_edge_ioapic_irq(unsigned int irq);
   8.926 -#define shutdown_edge_ioapic_irq  disable_edge_ioapic_irq
   8.927 -#define enable_edge_ioapic_irq    unmask_IO_APIC_irq
   8.928 -static void disable_edge_ioapic_irq (unsigned int irq);
   8.929 -static void ack_edge_ioapic_irq(unsigned int irq);
   8.930 -static void end_edge_ioapic_irq (unsigned int i);
   8.931 -static struct hw_interrupt_type ioapic_edge_irq_type = {
   8.932 -	"IO-APIC-edge",
   8.933 -	startup_edge_ioapic_irq,
   8.934 -	shutdown_edge_ioapic_irq,
   8.935 -	enable_edge_ioapic_irq,
   8.936 -	disable_edge_ioapic_irq,
   8.937 -	ack_edge_ioapic_irq,
   8.938 -	end_edge_ioapic_irq,
   8.939 -	set_ioapic_affinity,
   8.940 -};
   8.941 -
   8.942 -static unsigned int startup_level_ioapic_irq (unsigned int irq);
   8.943 -#define shutdown_level_ioapic_irq mask_IO_APIC_irq
   8.944 -#define enable_level_ioapic_irq   unmask_IO_APIC_irq
   8.945 -#define disable_level_ioapic_irq  mask_IO_APIC_irq
   8.946 -static void mask_and_ack_level_ioapic_irq (unsigned int irq);
   8.947 -static void end_level_ioapic_irq (unsigned int irq);
   8.948 -static struct hw_interrupt_type ioapic_level_irq_type = {
   8.949 -	"IO-APIC-level",
   8.950 -	startup_level_ioapic_irq,
   8.951 -	shutdown_level_ioapic_irq,
   8.952 -	enable_level_ioapic_irq,
   8.953 -	disable_level_ioapic_irq,
   8.954 -	mask_and_ack_level_ioapic_irq,
   8.955 -	end_level_ioapic_irq,
   8.956 -	set_ioapic_affinity,
   8.957 -};
   8.958 +static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
   8.959 +{
   8.960 +	if (use_pci_vector() && !platform_legacy_irq(irq)) {
   8.961 +		if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
   8.962 +				trigger == IOAPIC_LEVEL)
   8.963 +			irq_desc[vector].handler = &ioapic_level_type;
   8.964 +		else
   8.965 +			irq_desc[vector].handler = &ioapic_edge_type;
   8.966 +		set_intr_gate(vector, interrupt[vector]);
   8.967 +	} else	{
   8.968 +		if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
   8.969 +				trigger == IOAPIC_LEVEL)
   8.970 +			irq_desc[irq].handler = &ioapic_level_type;
   8.971 +		else
   8.972 +			irq_desc[irq].handler = &ioapic_edge_type;
   8.973 +		set_intr_gate(vector, interrupt[irq]);
   8.974 +	}
   8.975 +}
   8.976  
   8.977  void __init setup_IO_APIC_irqs(void)
   8.978  {
   8.979  	struct IO_APIC_route_entry entry;
   8.980 -	int apic, pin, idx, irq, vector;
   8.981 +	int apic, pin, idx, irq, first_notcon = 1, vector;
   8.982  	unsigned long flags;
   8.983  
   8.984 -	printk(KERN_DEBUG "init IO_APIC IRQs\n");
   8.985 +	apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
   8.986  
   8.987  	for (apic = 0; apic < nr_ioapics; apic++) {
   8.988  	for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
   8.989 @@ -667,13 +1124,24 @@ void __init setup_IO_APIC_irqs(void)
   8.990  		memset(&entry,0,sizeof(entry));
   8.991  
   8.992  		entry.delivery_mode = INT_DELIVERY_MODE;
   8.993 -		entry.dest_mode = (INT_DEST_ADDR_MODE != 0);
   8.994 +		entry.dest_mode = INT_DEST_MODE;
   8.995  		entry.mask = 0;				/* enable IRQ */
   8.996 -		entry.dest.logical.logical_dest = target_cpus();
   8.997 +		entry.dest.logical.logical_dest = 
   8.998 +					cpu_mask_to_apicid(TARGET_CPUS);
   8.999  
  8.1000  		idx = find_irq_entry(apic,pin,mp_INT);
  8.1001 -		if (idx == -1)
  8.1002 +		if (idx == -1) {
  8.1003 +			if (first_notcon) {
  8.1004 +				apic_printk(APIC_VERBOSE, KERN_DEBUG
  8.1005 +						" IO-APIC (apicid-pin) %d-%d",
  8.1006 +						mp_ioapics[apic].mpc_apicid,
  8.1007 +						pin);
  8.1008 +				first_notcon = 0;
  8.1009 +			} else
  8.1010 +				apic_printk(APIC_VERBOSE, ", %d-%d",
  8.1011 +					mp_ioapics[apic].mpc_apicid, pin);
  8.1012  			continue;
  8.1013 +		}
  8.1014  
  8.1015  		entry.trigger = irq_trigger(idx);
  8.1016  		entry.polarity = irq_polarity(idx);
  8.1017 @@ -688,8 +1156,7 @@ void __init setup_IO_APIC_irqs(void)
  8.1018  		 * skip adding the timer int on secondary nodes, which causes
  8.1019  		 * a small but painful rift in the time-space continuum
  8.1020  		 */
  8.1021 -		if ((clustered_apic_mode == CLUSTERED_APIC_NUMAQ) 
  8.1022 -			&& (apic != 0) && (irq == 0))
  8.1023 +		if (multi_timer_check(apic, irq))
  8.1024  			continue;
  8.1025  		else
  8.1026  			add_pin_to_irq(irq, apic, pin);
  8.1027 @@ -700,13 +1167,7 @@ void __init setup_IO_APIC_irqs(void)
  8.1028  		if (IO_APIC_IRQ(irq)) {
  8.1029  			vector = assign_irq_vector(irq);
  8.1030  			entry.vector = vector;
  8.1031 -
  8.1032 -			if (IO_APIC_irq_trigger(irq))
  8.1033 -				irq_desc[irq].handler = &ioapic_level_irq_type;
  8.1034 -			else
  8.1035 -				irq_desc[irq].handler = &ioapic_edge_irq_type;
  8.1036 -
  8.1037 -			set_intr_gate(vector, interrupt[irq]);
  8.1038 +			ioapic_register_intr(irq, vector, IOAPIC_AUTO);
  8.1039  		
  8.1040  			if (!apic && (irq < 16))
  8.1041  				disable_8259A_irq(irq);
  8.1042 @@ -717,11 +1178,13 @@ void __init setup_IO_APIC_irqs(void)
  8.1043  		spin_unlock_irqrestore(&ioapic_lock, flags);
  8.1044  	}
  8.1045  	}
  8.1046 +
  8.1047 +	if (!first_notcon)
  8.1048 +		apic_printk(APIC_VERBOSE, " not connected.\n");
  8.1049  }
  8.1050  
  8.1051  /*
  8.1052 - * Set up the 8259A-master output pin as broadcast to all
  8.1053 - * CPUs.
  8.1054 + * Set up the 8259A-master output pin:
  8.1055   */
  8.1056  void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
  8.1057  {
  8.1058 @@ -739,9 +1202,9 @@ void __init setup_ExtINT_IRQ0_pin(unsign
  8.1059  	 * We use logical delivery to get the timer IRQ
  8.1060  	 * to the first CPU.
  8.1061  	 */
  8.1062 -	entry.dest_mode = (INT_DEST_ADDR_MODE != 0);
  8.1063 +	entry.dest_mode = INT_DEST_MODE;
  8.1064  	entry.mask = 0;					/* unmask IRQ now */
  8.1065 -	entry.dest.logical.logical_dest = target_cpus();
  8.1066 +	entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
  8.1067  	entry.delivery_mode = INT_DELIVERY_MODE;
  8.1068  	entry.polarity = 0;
  8.1069  	entry.trigger = 0;
  8.1070 @@ -751,7 +1214,7 @@ void __init setup_ExtINT_IRQ0_pin(unsign
  8.1071  	 * The timer IRQ doesn't have to know that behind the
  8.1072  	 * scene we have a 8259A-master in AEOI mode ...
  8.1073  	 */
  8.1074 -	irq_desc[0].handler = &ioapic_edge_irq_type;
  8.1075 +	irq_desc[0].handler = &ioapic_edge_type;
  8.1076  
  8.1077  	/*
  8.1078  	 * Add it to the IO-APIC irq-routing table:
  8.1079 @@ -764,23 +1227,23 @@ void __init setup_ExtINT_IRQ0_pin(unsign
  8.1080  	enable_8259A_irq(0);
  8.1081  }
  8.1082  
  8.1083 -void __init UNEXPECTED_IO_APIC(void)
  8.1084 +static inline void UNEXPECTED_IO_APIC(void)
  8.1085  {
  8.1086 -	printk(KERN_WARNING 
  8.1087 -		"An unexpected IO-APIC was found. If this kernel release is less than\n"
  8.1088 -		"three months old please report this to linux-smp@vger.kernel.org\n");
  8.1089  }
  8.1090  
  8.1091  void __init print_IO_APIC(void)
  8.1092  {
  8.1093 -#ifdef VERBOSE
  8.1094 +#ifndef NDEBUG
  8.1095  	int apic, i;
  8.1096 -	struct IO_APIC_reg_00 reg_00;
  8.1097 -	struct IO_APIC_reg_01 reg_01;
  8.1098 -	struct IO_APIC_reg_02 reg_02;
  8.1099 -	struct IO_APIC_reg_03 reg_03;
  8.1100 +	union IO_APIC_reg_00 reg_00;
  8.1101 +	union IO_APIC_reg_01 reg_01;
  8.1102 +	union IO_APIC_reg_02 reg_02;
  8.1103 +	union IO_APIC_reg_03 reg_03;
  8.1104  	unsigned long flags;
  8.1105  
  8.1106 +	if (apic_verbosity == APIC_QUIET)
  8.1107 +		return;
  8.1108 +
  8.1109   	printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
  8.1110  	for (i = 0; i < nr_ioapics; i++)
  8.1111  		printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
  8.1112 @@ -795,47 +1258,46 @@ void __init print_IO_APIC(void)
  8.1113  	for (apic = 0; apic < nr_ioapics; apic++) {
  8.1114  
  8.1115  	spin_lock_irqsave(&ioapic_lock, flags);
  8.1116 -	*(int *)&reg_00 = io_apic_read(apic, 0);
  8.1117 -	*(int *)&reg_01 = io_apic_read(apic, 1);
  8.1118 -	if (reg_01.version >= 0x10)
  8.1119 -		*(int *)&reg_02 = io_apic_read(apic, 2);
  8.1120 -	if (reg_01.version >= 0x20)
  8.1121 -		*(int *)&reg_03 = io_apic_read(apic, 3);
  8.1122 +	reg_00.raw = io_apic_read(apic, 0);
  8.1123 +	reg_01.raw = io_apic_read(apic, 1);
  8.1124 +	if (reg_01.bits.version >= 0x10)
  8.1125 +		reg_02.raw = io_apic_read(apic, 2);
  8.1126 +	if (reg_01.bits.version >= 0x20)
  8.1127 +		reg_03.raw = io_apic_read(apic, 3);
  8.1128  	spin_unlock_irqrestore(&ioapic_lock, flags);
  8.1129  
  8.1130 -	printk("\n");
  8.1131  	printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
  8.1132 -	printk(KERN_DEBUG ".... register #00: %08X\n", *(int *)&reg_00);
  8.1133 -	printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.ID);
  8.1134 -	printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.delivery_type);
  8.1135 -	printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.LTS);
  8.1136 -	if (reg_00.__reserved_0 || reg_00.__reserved_1 || reg_00.__reserved_2)
  8.1137 +	printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
  8.1138 +	printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
  8.1139 +	printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
  8.1140 +	printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
  8.1141 +	if (reg_00.bits.ID >= get_physical_broadcast())
  8.1142 +		UNEXPECTED_IO_APIC();
  8.1143 +	if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
  8.1144  		UNEXPECTED_IO_APIC();
  8.1145  
  8.1146 -	printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
  8.1147 -	printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.entries);
  8.1148 -	if (	(reg_01.entries != 0x0f) && /* older (Neptune) boards */
  8.1149 -		(reg_01.entries != 0x17) && /* typical ISA+PCI boards */
  8.1150 -		(reg_01.entries != 0x1b) && /* Compaq Proliant boards */
  8.1151 -		(reg_01.entries != 0x1f) && /* dual Xeon boards */
  8.1152 -		(reg_01.entries != 0x22) && /* bigger Xeon boards */
  8.1153 -		(reg_01.entries != 0x2E) &&
  8.1154 -		(reg_01.entries != 0x3F)
  8.1155 +	printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
  8.1156 +	printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
  8.1157 +	if (	(reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
  8.1158 +		(reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
  8.1159 +		(reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
  8.1160 +		(reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
  8.1161 +		(reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
  8.1162 +		(reg_01.bits.entries != 0x2E) &&
  8.1163 +		(reg_01.bits.entries != 0x3F)
  8.1164  	)
  8.1165  		UNEXPECTED_IO_APIC();
  8.1166  
  8.1167 -	printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.PRQ);
  8.1168 -	printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.version);
  8.1169 -	if (	(reg_01.version != 0x01) && /* 82489DX IO-APICs */
  8.1170 -		(reg_01.version != 0x02) && /* VIA */
  8.1171 -		(reg_01.version != 0x03) && /* later VIA */
  8.1172 -		(reg_01.version != 0x10) && /* oldest IO-APICs */
  8.1173 -		(reg_01.version != 0x11) && /* Pentium/Pro IO-APICs */
  8.1174 -		(reg_01.version != 0x13) && /* Xeon IO-APICs */
  8.1175 -		(reg_01.version != 0x20)    /* Intel P64H (82806 AA) */
  8.1176 +	printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
  8.1177 +	printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
  8.1178 +	if (	(reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
  8.1179 +		(reg_01.bits.version != 0x10) && /* oldest IO-APICs */
  8.1180 +		(reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
  8.1181 +		(reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
  8.1182 +		(reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
  8.1183  	)
  8.1184  		UNEXPECTED_IO_APIC();
  8.1185 -	if (reg_01.__reserved_1 || reg_01.__reserved_2)
  8.1186 +	if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
  8.1187  		UNEXPECTED_IO_APIC();
  8.1188  
  8.1189  	/*
  8.1190 @@ -843,10 +1305,10 @@ void __init print_IO_APIC(void)
  8.1191  	 * but the value of reg_02 is read as the previous read register
  8.1192  	 * value, so ignore it if reg_02 == reg_01.
  8.1193  	 */
  8.1194 -	if (reg_01.version >= 0x10 && *(int *)&reg_02 != *(int *)&reg_01) {
  8.1195 -		printk(KERN_DEBUG ".... register #02: %08X\n", *(int *)&reg_02);
  8.1196 -		printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.arbitration);
  8.1197 -		if (reg_02.__reserved_1 || reg_02.__reserved_2)
  8.1198 +	if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
  8.1199 +		printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
  8.1200 +		printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
  8.1201 +		if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
  8.1202  			UNEXPECTED_IO_APIC();
  8.1203  	}
  8.1204  
  8.1205 @@ -855,11 +1317,11 @@ void __init print_IO_APIC(void)
  8.1206  	 * or reg_03, but the value of reg_0[23] is read as the previous read
  8.1207  	 * register value, so ignore it if reg_03 == reg_0[12].
  8.1208  	 */
  8.1209 -	if (reg_01.version >= 0x20 && *(int *)&reg_03 != *(int *)&reg_02 &&
  8.1210 -	    *(int *)&reg_03 != *(int *)&reg_01) {
  8.1211 -		printk(KERN_DEBUG ".... register #03: %08X\n", *(int *)&reg_03);
  8.1212 -		printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.boot_DT);
  8.1213 -		if (reg_03.__reserved_1)
  8.1214 +	if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
  8.1215 +	    reg_03.raw != reg_01.raw) {
  8.1216 +		printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
  8.1217 +		printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
  8.1218 +		if (reg_03.bits.__reserved_1)
  8.1219  			UNEXPECTED_IO_APIC();
  8.1220  	}
  8.1221  
  8.1222 @@ -868,7 +1330,7 @@ void __init print_IO_APIC(void)
  8.1223  	printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
  8.1224  			  " Stat Dest Deli Vect:   \n");
  8.1225  
  8.1226 -	for (i = 0; i <= reg_01.entries; i++) {
  8.1227 +	for (i = 0; i <= reg_01.bits.entries; i++) {
  8.1228  		struct IO_APIC_route_entry entry;
  8.1229  
  8.1230  		spin_lock_irqsave(&ioapic_lock, flags);
  8.1231 @@ -894,12 +1356,17 @@ void __init print_IO_APIC(void)
  8.1232  		);
  8.1233  	}
  8.1234  	}
  8.1235 +	if (use_pci_vector())
  8.1236 +		printk(KERN_INFO "Using vector-based indexing\n");
  8.1237  	printk(KERN_DEBUG "IRQ to pin mappings:\n");
  8.1238  	for (i = 0; i < NR_IRQS; i++) {
  8.1239  		struct irq_pin_list *entry = irq_2_pin + i;
  8.1240  		if (entry->pin < 0)
  8.1241  			continue;
  8.1242 -		printk(KERN_DEBUG "IRQ%d ", i);
  8.1243 + 		if (use_pci_vector() && !platform_legacy_irq(i))
  8.1244 +			printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
  8.1245 +		else
  8.1246 +			printk(KERN_DEBUG "IRQ%d ", i);
  8.1247  		for (;;) {
  8.1248  			printk("-> %d:%d", entry->apic, entry->pin);
  8.1249  			if (!entry->next)
  8.1250 @@ -910,152 +1377,13 @@ void __init print_IO_APIC(void)
  8.1251  	}
  8.1252  
  8.1253  	printk(KERN_INFO ".................................... done.\n");
  8.1254 -#endif
  8.1255 -}
  8.1256 -
  8.1257 -
  8.1258 -#if 0 /* Maybe useful for debugging, but not currently used anywhere. */
  8.1259 -
  8.1260 -static void print_APIC_bitfield (int base)
  8.1261 -{
  8.1262 -	unsigned int v;
  8.1263 -	int i, j;
  8.1264 -
  8.1265 -	printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
  8.1266 -	for (i = 0; i < 8; i++) {
  8.1267 -		v = apic_read(base + i*0x10);
  8.1268 -		for (j = 0; j < 32; j++) {
  8.1269 -			if (v & (1<<j))
  8.1270 -				printk("1");
  8.1271 -			else
  8.1272 -				printk("0");
  8.1273 -		}
  8.1274 -		printk("\n");
  8.1275 -	}
  8.1276 +#endif /* !NDEBUG */
  8.1277 +	return;
  8.1278  }
  8.1279  
  8.1280 -
  8.1281 -void /*__init*/ print_local_APIC(void * dummy)
  8.1282 -{
  8.1283 -	unsigned int v, ver, maxlvt;
  8.1284 -
  8.1285 -	printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
  8.1286 -		smp_processor_id(), hard_smp_processor_id());
  8.1287 -	v = apic_read(APIC_ID);
  8.1288 -	printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
  8.1289 -	v = apic_read(APIC_LVR);
  8.1290 -	printk(KERN_INFO "... APIC VERSION: %08x\n", v);
  8.1291 -	ver = GET_APIC_VERSION(v);
  8.1292 -	maxlvt = get_maxlvt();
  8.1293 -
  8.1294 -	v = apic_read(APIC_TASKPRI);
  8.1295 -	printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
  8.1296 -
  8.1297 -	if (APIC_INTEGRATED(ver)) {			/* !82489DX */
  8.1298 -		v = apic_read(APIC_ARBPRI);
  8.1299 -		printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
  8.1300 -			v & APIC_ARBPRI_MASK);
  8.1301 -		v = apic_read(APIC_PROCPRI);
  8.1302 -		printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
  8.1303 -	}
  8.1304 -
  8.1305 -	v = apic_read(APIC_EOI);
  8.1306 -	printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
  8.1307 -	v = apic_read(APIC_RRR);
  8.1308 -	printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
  8.1309 -	v = apic_read(APIC_LDR);
  8.1310 -	printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
  8.1311 -	v = apic_read(APIC_DFR);
  8.1312 -	printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
  8.1313 -	v = apic_read(APIC_SPIV);
  8.1314 -	printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
  8.1315 -
  8.1316 -	printk(KERN_DEBUG "... APIC ISR field:\n");
  8.1317 -	print_APIC_bitfield(APIC_ISR);
  8.1318 -	printk(KERN_DEBUG "... APIC TMR field:\n");
  8.1319 -	print_APIC_bitfield(APIC_TMR);
  8.1320 -	printk(KERN_DEBUG "... APIC IRR field:\n");
  8.1321 -	print_APIC_bitfield(APIC_IRR);
  8.1322 -
  8.1323 -	if (APIC_INTEGRATED(ver)) {		/* !82489DX */
  8.1324 -		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */
  8.1325 -			apic_write(APIC_ESR, 0);
  8.1326 -		v = apic_read(APIC_ESR);
  8.1327 -		printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
  8.1328 -	}
  8.1329 -
  8.1330 -	v = apic_read(APIC_ICR);
  8.1331 -	printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
  8.1332 -	v = apic_read(APIC_ICR2);
  8.1333 -	printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
  8.1334 -
  8.1335 -	v = apic_read(APIC_LVTT);
  8.1336 -	printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
  8.1337 -
  8.1338 -	if (maxlvt > 3) {                       /* PC is LVT#4. */
  8.1339 -		v = apic_read(APIC_LVTPC);
  8.1340 -		printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
  8.1341 -	}
  8.1342 -	v = apic_read(APIC_LVT0);
  8.1343 -	printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
  8.1344 -	v = apic_read(APIC_LVT1);
  8.1345 -	printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
  8.1346 -
  8.1347 -	if (maxlvt > 2) {			/* ERR is LVT#3. */
  8.1348 -		v = apic_read(APIC_LVTERR);
  8.1349 -		printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
  8.1350 -	}
  8.1351 -
  8.1352 -	v = apic_read(APIC_TMICT);
  8.1353 -	printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
  8.1354 -	v = apic_read(APIC_TMCCT);
  8.1355 -	printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
  8.1356 -	v = apic_read(APIC_TDCR);
  8.1357 -	printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
  8.1358 -	printk("\n");
  8.1359 -}
  8.1360 -
  8.1361 -void print_all_local_APICs (void)
  8.1362 -{
  8.1363 -	smp_call_function(print_local_APIC, NULL, 1, 1);
  8.1364 -	print_local_APIC(NULL);
  8.1365 -}
  8.1366 -
  8.1367 -void /*__init*/ print_PIC(void)
  8.1368 -{
  8.1369 -	extern spinlock_t i8259A_lock;
  8.1370 -	unsigned int v, flags;
  8.1371 -
  8.1372 -	printk(KERN_DEBUG "\nprinting PIC contents\n");
  8.1373 -
  8.1374 -	spin_lock_irqsave(&i8259A_lock, flags);
  8.1375 -
  8.1376 -	v = inb(0xa1) << 8 | inb(0x21);
  8.1377 -	printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
  8.1378 -
  8.1379 -	v = inb(0xa0) << 8 | inb(0x20);
  8.1380 -	printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
  8.1381 -
  8.1382 -	outb(0x0b,0xa0);
  8.1383 -	outb(0x0b,0x20);
  8.1384 -	v = inb(0xa0) << 8 | inb(0x20);
  8.1385 -	outb(0x0a,0xa0);
  8.1386 -	outb(0x0a,0x20);
  8.1387 -
  8.1388 -	spin_unlock_irqrestore(&i8259A_lock, flags);
  8.1389 -
  8.1390 -	printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
  8.1391 -
  8.1392 -	v = inb(0x4d1) << 8 | inb(0x4d0);
  8.1393 -	printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
  8.1394 -}
  8.1395 -
  8.1396 -#endif /* 0 */
  8.1397 -
  8.1398 -
  8.1399  static void __init enable_IO_APIC(void)
  8.1400  {
  8.1401 -	struct IO_APIC_reg_01 reg_01;
  8.1402 +	union IO_APIC_reg_01 reg_01;
  8.1403  	int i;
  8.1404  	unsigned long flags;
  8.1405  
  8.1406 @@ -1063,18 +1391,15 @@ static void __init enable_IO_APIC(void)
  8.1407  		irq_2_pin[i].pin = -1;
  8.1408  		irq_2_pin[i].next = 0;
  8.1409  	}
  8.1410 -	if (!pirqs_enabled)
  8.1411 -		for (i = 0; i < MAX_PIRQS; i++)
  8.1412 -			pirq_entries[i] = -1;
  8.1413  
  8.1414  	/*
  8.1415  	 * The number of IO-APIC IRQ registers (== #pins):
  8.1416  	 */
  8.1417  	for (i = 0; i < nr_ioapics; i++) {
  8.1418  		spin_lock_irqsave(&ioapic_lock, flags);
  8.1419 -		*(int *)&reg_01 = io_apic_read(i, 1);
  8.1420 +		reg_01.raw = io_apic_read(i, 1);
  8.1421  		spin_unlock_irqrestore(&ioapic_lock, flags);
  8.1422 -		nr_ioapic_registers[i] = reg_01.entries+1;
  8.1423 +		nr_ioapic_registers[i] = reg_01.bits.entries+1;
  8.1424  	}
  8.1425  
  8.1426  	/*
  8.1427 @@ -1103,18 +1428,22 @@ void disable_IO_APIC(void)
  8.1428   * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
  8.1429   */
  8.1430  
  8.1431 -static void __init setup_ioapic_ids_from_mpc (void)
  8.1432 +#ifndef CONFIG_X86_NUMAQ
  8.1433 +static void __init setup_ioapic_ids_from_mpc(void)
  8.1434  {
  8.1435 -	struct IO_APIC_reg_00 reg_00;
  8.1436 -	unsigned long phys_id_present_map = phys_cpu_present_map;
  8.1437 +	union IO_APIC_reg_00 reg_00;
  8.1438 +	physid_mask_t phys_id_present_map;
  8.1439  	int apic;
  8.1440  	int i;
  8.1441  	unsigned char old_id;
  8.1442  	unsigned long flags;
  8.1443  
  8.1444 -	if (clustered_apic_mode)
  8.1445 -		/* We don't have a good way to do this yet - hack */
  8.1446 -		phys_id_present_map = (u_long) 0xf;
  8.1447 +	/*
  8.1448 +	 * This is broken; anything with a real cpu count has to
  8.1449 +	 * circumvent this idiocy regardless.
  8.1450 +	 */
  8.1451 +	phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
  8.1452 +
  8.1453  	/*
  8.1454  	 * Set the IOAPIC ID to the value stored in the MPC table.
  8.1455  	 */
  8.1456 @@ -1122,41 +1451,48 @@ static void __init setup_ioapic_ids_from
  8.1457  
  8.1458  		/* Read the register 0 value */
  8.1459  		spin_lock_irqsave(&ioapic_lock, flags);
  8.1460 -		*(int *)&reg_00 = io_apic_read(apic, 0);
  8.1461 +		reg_00.raw = io_apic_read(apic, 0);
  8.1462  		spin_unlock_irqrestore(&ioapic_lock, flags);
  8.1463  		
  8.1464  		old_id = mp_ioapics[apic].mpc_apicid;
  8.1465  
  8.1466 -		if (mp_ioapics[apic].mpc_apicid >= apic_broadcast_id) {
  8.1467 +		if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
  8.1468  			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
  8.1469  				apic, mp_ioapics[apic].mpc_apicid);
  8.1470  			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
  8.1471 -				reg_00.ID);
  8.1472 -			mp_ioapics[apic].mpc_apicid = reg_00.ID;
  8.1473 +				reg_00.bits.ID);
  8.1474 +			mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
  8.1475  		}
  8.1476  
  8.1477 +		/* Don't check I/O APIC IDs for some xAPIC systems.  They have
  8.1478 +		 * no meaning without the serial APIC bus. */
  8.1479 +		if (NO_IOAPIC_CHECK)
  8.1480 +			continue;
  8.1481  		/*
  8.1482  		 * Sanity check, is the ID really free? Every APIC in a
  8.1483  		 * system must have a unique ID or we get lots of nice
  8.1484  		 * 'stuck on smp_invalidate_needed IPI wait' messages.
  8.1485 -		 * I/O APIC IDs no longer have any meaning for xAPICs and SAPICs.
  8.1486  		 */
  8.1487 -		if ((clustered_apic_mode != CLUSTERED_APIC_XAPIC) &&
  8.1488 -		    (phys_id_present_map & (1 << mp_ioapics[apic].mpc_apicid))) {
  8.1489 +		if (check_apicid_used(phys_id_present_map,
  8.1490 +					mp_ioapics[apic].mpc_apicid)) {
  8.1491  			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
  8.1492  				apic, mp_ioapics[apic].mpc_apicid);
  8.1493 -			for (i = 0; i < 0xf; i++)
  8.1494 -				if (!(phys_id_present_map & (1 << i)))
  8.1495 +			for (i = 0; i < get_physical_broadcast(); i++)
  8.1496 +				if (!physid_isset(i, phys_id_present_map))
  8.1497  					break;
  8.1498 -			if (i >= apic_broadcast_id)
  8.1499 +			if (i >= get_physical_broadcast())
  8.1500  				panic("Max APIC ID exceeded!\n");
  8.1501  			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
  8.1502  				i);
  8.1503 -			phys_id_present_map |= 1 << i;
  8.1504 +			physid_set(i, phys_id_present_map);
  8.1505  			mp_ioapics[apic].mpc_apicid = i;
  8.1506  		} else {
  8.1507 -			printk("Setting %d in the phys_id_present_map\n", mp_ioapics[apic].mpc_apicid);
  8.1508 -			phys_id_present_map |= 1 << mp_ioapics[apic].mpc_apicid;
  8.1509 +			physid_mask_t tmp;
  8.1510 +			tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
  8.1511 +			apic_printk(APIC_VERBOSE, "Setting %d in the "
  8.1512 +					"phys_id_present_map\n",
  8.1513 +					mp_ioapics[apic].mpc_apicid);
  8.1514 +			physids_or(phys_id_present_map, phys_id_present_map, tmp);
  8.1515  		}
  8.1516  
  8.1517  
  8.1518 @@ -1174,26 +1510,30 @@ static void __init setup_ioapic_ids_from
  8.1519  		 * Read the right value from the MPC table and
  8.1520  		 * write it into the ID register.
  8.1521  	 	 */
  8.1522 -		printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
  8.1523 -					mp_ioapics[apic].mpc_apicid);
  8.1524 +		apic_printk(APIC_VERBOSE, KERN_INFO
  8.1525 +			"...changing IO-APIC physical APIC ID to %d ...",
  8.1526 +			mp_ioapics[apic].mpc_apicid);
  8.1527  
  8.1528 -		reg_00.ID = mp_ioapics[apic].mpc_apicid;
  8.1529 +		reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
  8.1530  		spin_lock_irqsave(&ioapic_lock, flags);
  8.1531 -		io_apic_write(apic, 0, *(int *)&reg_00);
  8.1532 +		io_apic_write(apic, 0, reg_00.raw);
  8.1533  		spin_unlock_irqrestore(&ioapic_lock, flags);
  8.1534  
  8.1535  		/*
  8.1536  		 * Sanity check
  8.1537  		 */
  8.1538  		spin_lock_irqsave(&ioapic_lock, flags);
  8.1539 -		*(int *)&reg_00 = io_apic_read(apic, 0);
  8.1540 +		reg_00.raw = io_apic_read(apic, 0);
  8.1541  		spin_unlock_irqrestore(&ioapic_lock, flags);
  8.1542 -		if (reg_00.ID != mp_ioapics[apic].mpc_apicid)
  8.1543 -			panic("could not set ID!\n");
  8.1544 +		if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
  8.1545 +			printk("could not set ID!\n");
  8.1546  		else
  8.1547 -			printk(" ok.\n");
  8.1548 +			apic_printk(APIC_VERBOSE, " ok.\n");
  8.1549  	}
  8.1550  }
  8.1551 +#else
  8.1552 +static void __init setup_ioapic_ids_from_mpc(void) { }
  8.1553 +#endif
  8.1554  
  8.1555  /*
  8.1556   * There is a nasty bug in some older SMP boards, their mptable lies
  8.1557 @@ -1205,9 +1545,9 @@ static void __init setup_ioapic_ids_from
  8.1558   */
  8.1559  static int __init timer_irq_works(void)
  8.1560  {
  8.1561 -	unsigned int t1 = jiffies;
  8.1562 +	unsigned long t1 = jiffies;
  8.1563  
  8.1564 -	__sti();
  8.1565 +	local_irq_enable();
  8.1566  	/* Let ten ticks pass... */
  8.1567  	mdelay((10 * 1000) / HZ);
  8.1568  
  8.1569 @@ -1224,7 +1564,18 @@ static int __init timer_irq_works(void)
  8.1570  	return 0;
  8.1571  }
  8.1572  
  8.1573 -static void disable_edge_ioapic_irq (unsigned int irq) { /* nothing */ }
  8.1574 +/*
  8.1575 + * In the SMP+IOAPIC case it might happen that there are an unspecified
  8.1576 + * number of pending IRQ events unhandled. These cases are very rare,
  8.1577 + * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
  8.1578 + * better to do it this way as thus we do not have to be aware of
  8.1579 + * 'pending' interrupts in the IRQ path, except at this point.
  8.1580 + */
  8.1581 +/*
  8.1582 + * Edge triggered needs to resend any interrupt
  8.1583 + * that was delayed but this is now handled in the device
  8.1584 + * independent code.
  8.1585 + */
  8.1586  
  8.1587  /*
  8.1588   * Starting up a edge-triggered IO-APIC interrupt is
  8.1589 @@ -1235,7 +1586,6 @@ static void disable_edge_ioapic_irq (uns
  8.1590   * This is not complete - we should be able to fake
  8.1591   * an edge even if it isn't on the 8259A...
  8.1592   */
  8.1593 -
  8.1594  static unsigned int startup_edge_ioapic_irq(unsigned int irq)
  8.1595  {
  8.1596  	int was_pending = 0;
  8.1597 @@ -1260,16 +1610,13 @@ static unsigned int startup_edge_ioapic_
  8.1598   */
  8.1599  static void ack_edge_ioapic_irq(unsigned int irq)
  8.1600  {
  8.1601 -	balance_irq(irq);
  8.1602 +	move_irq(irq);
  8.1603  	if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
  8.1604  					== (IRQ_PENDING | IRQ_DISABLED))
  8.1605  		mask_IO_APIC_irq(irq);
  8.1606  	ack_APIC_irq();
  8.1607  }
  8.1608  
  8.1609 -static void end_edge_ioapic_irq (unsigned int i) { /* nothing */ }
  8.1610 -
  8.1611 -
  8.1612  /*
  8.1613   * Level triggered interrupts can just be masked,
  8.1614   * and shutting down and starting up the interrupt
  8.1615 @@ -1291,15 +1638,12 @@ static unsigned int startup_level_ioapic
  8.1616  	return 0; /* don't check for pending */
  8.1617  }
  8.1618  
  8.1619 -static void mask_and_ack_level_ioapic_irq(unsigned int irq)
  8.1620 +static void end_level_ioapic_irq (unsigned int irq)
  8.1621  {
  8.1622  	unsigned long v;
  8.1623  	int i;
  8.1624  
  8.1625 -	balance_irq(irq);
  8.1626 -
  8.1627 -	mask_IO_APIC_irq(irq);
  8.1628 -
  8.1629 +	move_irq(irq);
  8.1630  /*
  8.1631   * It appears there is an erratum which affects at least version 0x11
  8.1632   * of I/O APIC (that's the 82093AA and cores integrated into various
  8.1633 @@ -1320,45 +1664,102 @@ static void mask_and_ack_level_ioapic_ir
  8.1634   * The idea is from Manfred Spraul.  --macro
  8.1635   */
  8.1636  	i = IO_APIC_VECTOR(irq);
  8.1637 +
  8.1638  	v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
  8.1639  
  8.1640  	ack_APIC_irq();
  8.1641  
  8.1642  	if (!(v & (1 << (i & 0x1f)))) {
  8.1643 -#ifdef APIC_LOCKUP_DEBUG
  8.1644 -		struct irq_pin_list *entry;
  8.1645 -#endif
  8.1646 -
  8.1647 -#ifdef APIC_MISMATCH_DEBUG
  8.1648  		atomic_inc(&irq_mis_count);
  8.1649 -#endif
  8.1650  		spin_lock(&ioapic_lock);
  8.1651 -		__edge_IO_APIC_irq(irq);
  8.1652 -#ifdef APIC_LOCKUP_DEBUG
  8.1653 -		for (entry = irq_2_pin + irq;;) {
  8.1654 -			unsigned int reg;
  8.1655 -
  8.1656 -			if (entry->pin == -1)
  8.1657 -				break;
  8.1658 -			reg = io_apic_read(entry->apic, 0x10 + entry->pin * 2);
  8.1659 -			if (reg & 0x00004000)
  8.1660 -				printk(KERN_CRIT "Aieee!!!  Remote IRR"
  8.1661 -					" still set after unlock!\n");
  8.1662 -			if (!entry->next)
  8.1663 -				break;
  8.1664 -			entry = irq_2_pin + entry->next;
  8.1665 -		}
  8.1666 -#endif
  8.1667 -		__level_IO_APIC_irq(irq);
  8.1668 +		__mask_and_edge_IO_APIC_irq(irq);
  8.1669 +		__unmask_and_level_IO_APIC_irq(irq);
  8.1670  		spin_unlock(&ioapic_lock);
  8.1671  	}
  8.1672  }
  8.1673  
  8.1674 -static void end_level_ioapic_irq(unsigned int irq)
  8.1675 +#ifdef CONFIG_PCI_MSI
  8.1676 +static unsigned int startup_edge_ioapic_vector(unsigned int vector)
  8.1677 +{
  8.1678 +	int irq = vector_to_irq(vector);
  8.1679 +
  8.1680 +	return startup_edge_ioapic_irq(irq);
  8.1681 +}
  8.1682 +
  8.1683 +static void ack_edge_ioapic_vector(unsigned int vector)
  8.1684 +{
  8.1685 +	int irq = vector_to_irq(vector);
  8.1686 +
  8.1687 +	ack_edge_ioapic_irq(irq);
  8.1688 +}
  8.1689 +
  8.1690 +static unsigned int startup_level_ioapic_vector (unsigned int vector)
  8.1691  {
  8.1692 +	int irq = vector_to_irq(vector);
  8.1693 +
  8.1694 +	return startup_level_ioapic_irq (irq);
  8.1695 +}
  8.1696 +
  8.1697 +static void end_level_ioapic_vector (unsigned int vector)
  8.1698 +{
  8.1699 +	int irq = vector_to_irq(vector);
  8.1700 +
  8.1701 +	end_level_ioapic_irq(irq);
  8.1702 +}
  8.1703 +
  8.1704 +static void mask_IO_APIC_vector (unsigned int vector)
  8.1705 +{
  8.1706 +	int irq = vector_to_irq(vector);
  8.1707 +
  8.1708 +	mask_IO_APIC_irq(irq);
  8.1709 +}
  8.1710 +
  8.1711 +static void unmask_IO_APIC_vector (unsigned int vector)
  8.1712 +{
  8.1713 +	int irq = vector_to_irq(vector);
  8.1714 +
  8.1715  	unmask_IO_APIC_irq(irq);
  8.1716  }
  8.1717  
  8.1718 +static void set_ioapic_affinity_vector (unsigned int vector,
  8.1719 +					cpumask_t cpu_mask)
  8.1720 +{
  8.1721 +	int irq = vector_to_irq(vector);
  8.1722 +
  8.1723 +	set_ioapic_affinity_irq(irq, cpu_mask);
  8.1724 +}
  8.1725 +#endif
  8.1726 +
  8.1727 +/*
  8.1728 + * Level and edge triggered IO-APIC interrupts need different handling,
  8.1729 + * so we use two separate IRQ descriptors. Edge triggered IRQs can be
  8.1730 + * handled with the level-triggered descriptor, but that one has slightly
  8.1731 + * more overhead. Level-triggered interrupts cannot be handled with the
  8.1732 + * edge-triggered handler, without risking IRQ storms and other ugly
  8.1733 + * races.
  8.1734 + */
  8.1735 +static struct hw_interrupt_type ioapic_edge_type = {
  8.1736 +	.typename 	= "IO-APIC-edge",
  8.1737 +	.startup 	= startup_edge_ioapic,
  8.1738 +	.shutdown 	= shutdown_edge_ioapic,
  8.1739 +	.enable 	= enable_edge_ioapic,
  8.1740 +	.disable 	= disable_edge_ioapic,
  8.1741 +	.ack 		= ack_edge_ioapic,
  8.1742 +	.end 		= end_edge_ioapic,
  8.1743 +	.set_affinity 	= set_ioapic_affinity,
  8.1744 +};
  8.1745 +
  8.1746 +static struct hw_interrupt_type ioapic_level_type = {
  8.1747 +	.typename 	= "IO-APIC-level",
  8.1748 +	.startup 	= startup_level_ioapic,
  8.1749 +	.shutdown 	= shutdown_level_ioapic,
  8.1750 +	.enable 	= enable_level_ioapic,
  8.1751 +	.disable 	= disable_level_ioapic,
  8.1752 +	.ack 		= mask_and_ack_level_ioapic,
  8.1753 +	.end 		= end_level_ioapic,
  8.1754 +	.set_affinity 	= set_ioapic_affinity,
  8.1755 +};
  8.1756 +
  8.1757  static inline void init_IO_APIC_traps(void)
  8.1758  {
  8.1759  	int irq;
  8.1760 @@ -1375,7 +1776,13 @@ static inline void init_IO_APIC_traps(vo
  8.1761  	 * 0x80, because int 0x80 is hm, kind of importantish. ;)
  8.1762  	 */
  8.1763  	for (irq = 0; irq < NR_IRQS ; irq++) {
  8.1764 -		if (IO_APIC_IRQ(irq) && !IO_APIC_VECTOR(irq)) {
  8.1765 +		int tmp = irq;
  8.1766 +		if (use_pci_vector()) {
  8.1767 +			if (!platform_legacy_irq(tmp))
  8.1768 +				if ((tmp = vector_to_irq(tmp)) == -1)
  8.1769 +					continue;
  8.1770 +		}
  8.1771 +		if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
  8.1772  			/*
  8.1773  			 * Hmm.. We don't have an entry for this,
  8.1774  			 * so default to an old-fashioned 8259
  8.1775 @@ -1414,15 +1821,35 @@ static void ack_lapic_irq (unsigned int 
  8.1776  static void end_lapic_irq (unsigned int i) { /* nothing */ }
  8.1777  
  8.1778  static struct hw_interrupt_type lapic_irq_type = {
  8.1779 -	"local-APIC-edge",
  8.1780 -	NULL, /* startup_irq() not used for IRQ0 */
  8.1781 -	NULL, /* shutdown_irq() not used for IRQ0 */
  8.1782 -	enable_lapic_irq,
  8.1783 -	disable_lapic_irq,
  8.1784 -	ack_lapic_irq,
  8.1785 -	end_lapic_irq
  8.1786 +	.typename 	= "local-APIC-edge",
  8.1787 +	.startup 	= NULL, /* startup_irq() not used for IRQ0 */
  8.1788 +	.shutdown 	= NULL, /* shutdown_irq() not used for IRQ0 */
  8.1789 +	.enable 	= enable_lapic_irq,
  8.1790 +	.disable 	= disable_lapic_irq,
  8.1791 +	.ack 		= ack_lapic_irq,
  8.1792 +	.end 		= end_lapic_irq
  8.1793  };
  8.1794  
  8.1795 +#if 0
  8.1796 +static void setup_nmi (void)
  8.1797 +{
  8.1798 +	/*
  8.1799 + 	 * Dirty trick to enable the NMI watchdog ...
  8.1800 +	 * We put the 8259A master into AEOI mode and
  8.1801 +	 * unmask on all local APICs LVT0 as NMI.
  8.1802 +	 *
  8.1803 +	 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
  8.1804 +	 * is from Maciej W. Rozycki - so we do not have to EOI from
  8.1805 +	 * the NMI handler or the timer interrupt.
  8.1806 +	 */ 
  8.1807 +	apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
  8.1808 +
  8.1809 +	on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
  8.1810 +
  8.1811 +	apic_printk(APIC_VERBOSE, " done.\n");
  8.1812 +}
  8.1813 +#endif
  8.1814 +
  8.1815  /*
  8.1816   * This looks a bit hackish but it's about the only one way of sending
  8.1817   * a few INTA cycles to 8259As and any associated glue logic.  ICR does
  8.1818 @@ -1493,7 +1920,6 @@ static inline void unlock_ExtINT_logic(v
  8.1819   */
  8.1820  static inline void check_timer(void)
  8.1821  {
  8.1822 -	extern int timer_ack;
  8.1823  	int pin1, pin2;
  8.1824  	int vector;
  8.1825  
  8.1826 @@ -1526,8 +1952,17 @@ static inline void check_timer(void)
  8.1827  		 * Ok, does IRQ0 through the IOAPIC work?
  8.1828  		 */
  8.1829  		unmask_IO_APIC_irq(0);
  8.1830 -		if (timer_irq_works())
  8.1831 +		if (timer_irq_works()) {
  8.1832 +#if 0
  8.1833 +			if (nmi_watchdog == NMI_IO_APIC) {
  8.1834 +				disable_8259A_irq(0);
  8.1835 +				setup_nmi();
  8.1836 +				enable_8259A_irq(0);
  8.1837 +				check_nmi_watchdog();
  8.1838 +			}
  8.1839 +#endif
  8.1840  			return;
  8.1841 +		}
  8.1842  		clear_IO_APIC_pin(0, pin1);
  8.1843  		printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
  8.1844  	}
  8.1845 @@ -1545,6 +1980,12 @@ static inline void check_timer(void)
  8.1846  				replace_pin_at_irq(0, 0, pin1, 0, pin2);
  8.1847  			else
  8.1848  				add_pin_to_irq(0, 0, pin2);
  8.1849 +#if 0
  8.1850 +			if (nmi_watchdog == NMI_IO_APIC) {
  8.1851 +				setup_nmi();
  8.1852 +				check_nmi_watchdog();
  8.1853 +			}
  8.1854 +#endif
  8.1855  			return;
  8.1856  		}
  8.1857  		/*
  8.1858 @@ -1554,6 +1995,11 @@ static inline void check_timer(void)
  8.1859  	}
  8.1860  	printk(" failed.\n");
  8.1861  
  8.1862 +	if (nmi_watchdog == NMI_IO_APIC) {
  8.1863 +		printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
  8.1864 +		nmi_watchdog = 0;
  8.1865 +	}
  8.1866 +
  8.1867  	printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
  8.1868  
  8.1869  	disable_8259A_irq(0);
  8.1870 @@ -1570,6 +2016,7 @@ static inline void check_timer(void)
  8.1871  
  8.1872  	printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
  8.1873  
  8.1874 +	timer_ack = 0;
  8.1875  	init_8259A(0);
  8.1876  	make_8259A_irq(0);
  8.1877  	apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
  8.1878 @@ -1581,7 +2028,8 @@ static inline void check_timer(void)
  8.1879  		return;
  8.1880  	}
  8.1881  	printk(" failed :(.\n");
  8.1882 -	panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
  8.1883 +	panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
  8.1884 +		"report.  Then try booting with the 'noapic' option");
  8.1885  }
  8.1886  
  8.1887  #define NR_IOAPIC_BIOSIDS 256
  8.1888 @@ -1596,20 +2044,12 @@ static void store_ioapic_biosid_mapping(
  8.1889  
  8.1890  /*
  8.1891   *
  8.1892 - * IRQ's that are handled by the old PIC in all cases:
  8.1893 + * IRQ's that are handled by the PIC in the MPS IOAPIC case.
  8.1894   * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
  8.1895   *   Linux doesn't really care, as it's not actually used
  8.1896   *   for any interrupt handling anyway.
  8.1897 - * - There used to be IRQ13 here as well, but all
  8.1898 - *   MPS-compliant must not use it for FPU coupling and we
  8.1899 - *   want to use exception 16 anyway.  And there are
  8.1900 - *   systems who connect it to an I/O APIC for other uses.
  8.1901 - *   Thus we don't mark it special any longer.
  8.1902 - *
  8.1903 - * Additionally, something is definitely wrong with irq9
  8.1904 - * on PIIX4 boards.
  8.1905   */
  8.1906 -#define PIC_IRQS	(1<<2)
  8.1907 +#define PIC_IRQS	(1 << PIC_CASCADE_IR)
  8.1908  
  8.1909  void __init setup_IO_APIC(void)
  8.1910  {
  8.1911 @@ -1617,7 +2057,11 @@ void __init setup_IO_APIC(void)
  8.1912  
  8.1913  	enable_IO_APIC();
  8.1914  
  8.1915 -	io_apic_irqs = ~PIC_IRQS;
  8.1916 +	if (acpi_ioapic)
  8.1917 +		io_apic_irqs = ~0;	/* all IRQs go through IOAPIC */
  8.1918 +	else
  8.1919 +		io_apic_irqs = ~PIC_IRQS;
  8.1920 +
  8.1921  	printk("ENABLING IO-APIC IRQs\n");
  8.1922  
  8.1923  	/*
  8.1924 @@ -1632,22 +2076,17 @@ void __init setup_IO_APIC(void)
  8.1925  	print_IO_APIC();
  8.1926  }
  8.1927  
  8.1928 -#endif /* CONFIG_X86_IO_APIC */
  8.1929 -
  8.1930 -
  8.1931 -
  8.1932  /* --------------------------------------------------------------------------
  8.1933                            ACPI-based IOAPIC Configuration
  8.1934     -------------------------------------------------------------------------- */
  8.1935  
  8.1936  #ifdef CONFIG_ACPI_BOOT
  8.1937  
  8.1938 -#define IO_APIC_MAX_ID		15
  8.1939 -
  8.1940  int __init io_apic_get_unique_id (int ioapic, int apic_id)
  8.1941  {
  8.1942 -	struct IO_APIC_reg_00 reg_00;
  8.1943 -	static unsigned long apic_id_map = 0;
  8.1944 +	union IO_APIC_reg_00 reg_00;
  8.1945 +	static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
  8.1946 +	physid_mask_t tmp;
  8.1947  	unsigned long flags;
  8.1948  	int i = 0;
  8.1949  
  8.1950 @@ -1660,38 +2099,31 @@ int __init io_apic_get_unique_id (int io
  8.1951  	 *      advantage of new APIC bus architecture.
  8.1952  	 */
  8.1953  
  8.1954 -	if (!apic_id_map)
  8.1955 -		apic_id_map = phys_cpu_present_map;
  8.1956 +	if (physids_empty(apic_id_map))
  8.1957 +		apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
  8.1958  
  8.1959  	spin_lock_irqsave(&ioapic_lock, flags);
  8.1960 -	*(int *)&reg_00 = io_apic_read(ioapic, 0);
  8.1961 +	reg_00.raw = io_apic_read(ioapic, 0);
  8.1962  	spin_unlock_irqrestore(&ioapic_lock, flags);
  8.1963  
  8.1964 -	if (apic_id >= IO_APIC_MAX_ID) {
  8.1965 +	if (apic_id >= get_physical_broadcast()) {
  8.1966  		printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
  8.1967 -			"%d\n", ioapic, apic_id, reg_00.ID);
  8.1968 -		apic_id = reg_00.ID;
  8.1969 -	}
  8.1970 -
  8.1971 -	/* XAPICs do not need unique IDs */
  8.1972 -	if (clustered_apic_mode == CLUSTERED_APIC_XAPIC){
  8.1973 -		printk(KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", 
  8.1974 -			ioapic, apic_id);
  8.1975 -		return apic_id;
  8.1976 +			"%d\n", ioapic, apic_id, reg_00.bits.ID);
  8.1977 +		apic_id = reg_00.bits.ID;
  8.1978  	}
  8.1979  
  8.1980  	/*
  8.1981  	 * Every APIC in a system must have a unique ID or we get lots of nice 
  8.1982  	 * 'stuck on smp_invalidate_needed IPI wait' messages.
  8.1983  	 */
  8.1984 -	if (apic_id_map & (1 << apic_id)) {
  8.1985 +	if (check_apicid_used(apic_id_map, apic_id)) {
  8.1986  
  8.1987 -		for (i = 0; i < IO_APIC_MAX_ID; i++) {
  8.1988 -			if (!(apic_id_map & (1 << i)))
  8.1989 +		for (i = 0; i < get_physical_broadcast(); i++) {
  8.1990 +			if (!check_apicid_used(apic_id_map, i))
  8.1991  				break;
  8.1992  		}
  8.1993  
  8.1994 -		if (i == IO_APIC_MAX_ID)
  8.1995 +		if (i == get_physical_broadcast())
  8.1996  			panic("Max apic_id exceeded!\n");
  8.1997  
  8.1998  		printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
  8.1999 @@ -1700,22 +2132,24 @@ int __init io_apic_get_unique_id (int io
  8.2000  		apic_id = i;
  8.2001  	} 
  8.2002  
  8.2003 -	apic_id_map |= (1 << apic_id);
  8.2004 +	tmp = apicid_to_cpu_present(apic_id);
  8.2005 +	physids_or(apic_id_map, apic_id_map, tmp);
  8.2006  
  8.2007 -	if (reg_00.ID != apic_id) {
  8.2008 -		reg_00.ID = apic_id;
  8.2009 +	if (reg_00.bits.ID != apic_id) {
  8.2010 +		reg_00.bits.ID = apic_id;
  8.2011  
  8.2012  		spin_lock_irqsave(&ioapic_lock, flags);
  8.2013 -		io_apic_write(ioapic, 0, *(int *)&reg_00);
  8.2014 -		*(int *)&reg_00 = io_apic_read(ioapic, 0);
  8.2015 +		io_apic_write(ioapic, 0, reg_00.raw);
  8.2016 +		reg_00.raw = io_apic_read(ioapic, 0);
  8.2017  		spin_unlock_irqrestore(&ioapic_lock, flags);
  8.2018  
  8.2019  		/* Sanity check */
  8.2020 -		if (reg_00.ID != apic_id)
  8.2021 +		if (reg_00.bits.ID != apic_id)
  8.2022  			panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
  8.2023  	}
  8.2024  
  8.2025 -	printk(KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
  8.2026 +	apic_printk(APIC_VERBOSE, KERN_INFO
  8.2027 +			"IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
  8.2028  
  8.2029  	return apic_id;
  8.2030  }
  8.2031 @@ -1723,27 +2157,27 @@ int __init io_apic_get_unique_id (int io
  8.2032  
  8.2033  int __init io_apic_get_version (int ioapic)
  8.2034  {
  8.2035 -	struct IO_APIC_reg_01	reg_01;
  8.2036 +	union IO_APIC_reg_01	reg_01;
  8.2037  	unsigned long flags;
  8.2038  
  8.2039  	spin_lock_irqsave(&ioapic_lock, flags);
  8.2040 -	*(int *)&reg_01 = io_apic_read(ioapic, 1);
  8.2041 +	reg_01.raw = io_apic_read(ioapic, 1);
  8.2042  	spin_unlock_irqrestore(&ioapic_lock, flags);
  8.2043  
  8.2044 -	return reg_01.version;
  8.2045 +	return reg_01.bits.version;
  8.2046  }
  8.2047  
  8.2048  
  8.2049  int __init io_apic_get_redir_entries (int ioapic)
  8.2050  {
  8.2051 -	struct IO_APIC_reg_01	reg_01;
  8.2052 +	union IO_APIC_reg_01	reg_01;
  8.2053  	unsigned long flags;
  8.2054  
  8.2055  	spin_lock_irqsave(&ioapic_lock, flags);
  8.2056 -	*(int *)&reg_01 = io_apic_read(ioapic, 1);
  8.2057 +	reg_01.raw = io_apic_read(ioapic, 1);
  8.2058  	spin_unlock_irqrestore(&ioapic_lock, flags);
  8.2059  
  8.2060 -	return reg_01.entries;
  8.2061 +	return reg_01.bits.entries;
  8.2062  }
  8.2063  
  8.2064  
  8.2065 @@ -1753,7 +2187,7 @@ int io_apic_set_pci_routing (int ioapic,
  8.2066  	unsigned long flags;
  8.2067  
  8.2068  	if (!IO_APIC_IRQ(irq)) {
  8.2069 -		printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0/n", 
  8.2070 +		printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
  8.2071  			ioapic);
  8.2072  		return -EINVAL;
  8.2073  	}
  8.2074 @@ -1766,12 +2200,12 @@ int io_apic_set_pci_routing (int ioapic,
  8.2075  
  8.2076  	memset(&entry,0,sizeof(entry));
  8.2077  
  8.2078 -	entry.delivery_mode = dest_LowestPrio;
  8.2079 -	entry.dest_mode = INT_DELIVERY_MODE;
  8.2080 -	entry.dest.logical.logical_dest = target_cpus();
  8.2081 -	entry.mask = 1;					 /* Disabled (masked) */
  8.2082 +	entry.delivery_mode = INT_DELIVERY_MODE;
  8.2083 +	entry.dest_mode = INT_DEST_MODE;
  8.2084 +	entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
  8.2085  	entry.trigger = edge_level;
  8.2086  	entry.polarity = active_high_low;
  8.2087 +	entry.mask  = 1;
  8.2088  
  8.2089  	/*
  8.2090  	 * IRQs < 16 are already in the irq_2_pin[] map
  8.2091 @@ -1781,17 +2215,12 @@ int io_apic_set_pci_routing (int ioapic,
  8.2092  
  8.2093  	entry.vector = assign_irq_vector(irq);
  8.2094  
  8.2095 -	printk(KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
  8.2096 -		"IRQ %d Mode:%i Active:%i)\n", ioapic,
  8.2097 -		mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq, edge_level, active_high_low);
  8.2098 +	apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
  8.2099 +		"(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
  8.2100 +		mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
  8.2101 +		edge_level, active_high_low);
  8.2102  
  8.2103 -	if (edge_level) {
  8.2104 -		irq_desc[irq].handler = &ioapic_level_irq_type;
  8.2105 -	} else {
  8.2106 -		irq_desc[irq].handler = &ioapic_edge_irq_type;
  8.2107 -	}
  8.2108 -
  8.2109 -	set_intr_gate(entry.vector, interrupt[irq]);
  8.2110 +	ioapic_register_intr(irq, entry.vector, edge_level);
  8.2111  
  8.2112  	if (!ioapic && (irq < 16))
  8.2113  		disable_8259A_irq(irq);
  8.2114 @@ -1806,123 +2235,12 @@ int io_apic_set_pci_routing (int ioapic,
  8.2115  
  8.2116  #endif /*CONFIG_ACPI_BOOT*/
  8.2117  
  8.2118 -/* opt_leveltrigger, opt_edgetrigger: Force an IO-APIC-routed IRQ to be */
  8.2119 -/*                                    level- or edge-triggered.         */
  8.2120 -/* Example: 'leveltrigger=4,5,6,20 edgetrigger=21'. */
  8.2121 -static char opt_leveltrigger[30] = "", opt_edgetrigger[30] = "";
  8.2122 -string_param("leveltrigger", opt_leveltrigger);
  8.2123 -string_param("edgetrigger", opt_edgetrigger);
  8.2124 -
  8.2125 -static int __init ioapic_trigger_setup(void)
  8.2126 -{
  8.2127 -    char       *p;
  8.2128 -    irq_desc_t *desc;
  8.2129 -    long        irq;
  8.2130 -
  8.2131 -    p = opt_leveltrigger;
  8.2132 -    while ( *p != '\0' )
  8.2133 -    {
  8.2134 -        irq = simple_strtol(p, &p, 10);
  8.2135 -        if ( (irq <= 0) || (irq >= NR_IRQS) )
  8.2136 -        {
  8.2137 -            printk("IRQ '%ld' out of range in level-trigger list '%s'\n",
  8.2138 -                   irq, opt_leveltrigger);
  8.2139 -            break;
  8.2140 -        }
  8.2141 -
  8.2142 -        printk("Forcing IRQ %ld to level-trigger: ", irq);
  8.2143 -
  8.2144 -        desc = &irq_desc[irq];
  8.2145 -        spin_lock_irq(&desc->lock);
  8.2146 -
  8.2147 -        if ( desc->handler == &ioapic_level_irq_type )
  8.2148 -        {
  8.2149 -            printk("already level-triggered (no force applied).\n");
  8.2150 -        }
  8.2151 -        else if ( desc->handler != &ioapic_edge_irq_type )
  8.2152 -        {
  8.2153 -            printk("cannot force (can only force IO-APIC-edge IRQs).\n");
  8.2154 -        }
  8.2155 -        else
  8.2156 -        {
  8.2157 -            desc->handler = &ioapic_level_irq_type;
  8.2158 -            __mask_IO_APIC_irq(irq);
  8.2159 -            __level_IO_APIC_irq(irq);        
  8.2160 -            printk("done.\n");
  8.2161 -        }
  8.2162 -
  8.2163 -        spin_unlock_irq(&desc->lock);
  8.2164 -
  8.2165 -        if ( *p == '\0' )
  8.2166 -            break;
  8.2167 -
  8.2168 -        if ( *p != ',' )
  8.2169 -        {
  8.2170 -            printk("Unexpected character '%c' in level-trigger list '%s'\n",
  8.2171 -                   *p, opt_leveltrigger);
  8.2172 -            break;
  8.2173 -        }
  8.2174 -
  8.2175 -        p++;
  8.2176 -    }
  8.2177 -
  8.2178 -    p = opt_edgetrigger;
  8.2179 -    while ( *p != '\0' )
  8.2180 -    {
  8.2181 -        irq = simple_strtol(p, &p, 10);
  8.2182 -        if ( (irq <= 0) || (irq >= NR_IRQS) )
  8.2183 -        {
  8.2184 -            printk("IRQ '%ld' out of range in edge-trigger list '%s'\n",
  8.2185 -                   irq, opt_edgetrigger);
  8.2186 -            break;
  8.2187 -        }
  8.2188 -
  8.2189 -        printk("Forcing IRQ %ld to edge-trigger: ", irq);
  8.2190 -
  8.2191 -        desc = &irq_desc[irq];
  8.2192 -        spin_lock_irq(&desc->lock);
  8.2193 -
  8.2194 -        if ( desc->handler == &ioapic_edge_irq_type )
  8.2195 -        {
  8.2196 -            printk("already edge-triggered (no force applied).\n");
  8.2197 -        }
  8.2198 -        else if ( desc->handler != &ioapic_level_irq_type )
  8.2199 -        {
  8.2200 -            printk("cannot force (can only force IO-APIC-level IRQs).\n");
  8.2201 -        }
  8.2202 -        else
  8.2203 -        {
  8.2204 -            desc->handler = &ioapic_edge_irq_type;
  8.2205 -            __edge_IO_APIC_irq(irq);        
  8.2206 -            desc->status |= IRQ_PENDING; /* may have lost a masked edge */
  8.2207 -            printk("done.\n");
  8.2208 -        }
  8.2209 -
  8.2210 -        spin_unlock_irq(&desc->lock);
  8.2211 -
  8.2212 -        if ( *p == '\0' )
  8.2213 -            break;
  8.2214 -
  8.2215 -        if ( *p != ',' )
  8.2216 -        {
  8.2217 -            printk("Unexpected character '%c' in edge-trigger list '%s'\n",
  8.2218 -                   *p, opt_edgetrigger);
  8.2219 -            break;
  8.2220 -        }
  8.2221 -
  8.2222 -        p++;
  8.2223 -    }
  8.2224 -
  8.2225 -    return 0;
  8.2226 -}
  8.2227 -
  8.2228 -__initcall(ioapic_trigger_setup);
  8.2229  
  8.2230  int ioapic_guest_read(int apicid, int address, u32 *pval)
  8.2231  {
  8.2232      u32 val;
  8.2233      int apicenum;
  8.2234 -    struct IO_APIC_reg_00 reg_00;
  8.2235 +    union IO_APIC_reg_00 reg_00;
  8.2236      unsigned long flags;
  8.2237  
  8.2238      if ( (apicid >= NR_IOAPIC_BIOSIDS) ||
  8.2239 @@ -1936,9 +2254,9 @@ int ioapic_guest_read(int apicid, int ad
  8.2240      /* Rewrite APIC ID to what the BIOS originally specified. */
  8.2241      if ( address == 0 )
  8.2242      {
  8.2243 -        *(int *)&reg_00 = val;
  8.2244 -        reg_00.ID = apicid;
  8.2245 -        val = *(u32 *)&reg_00;
  8.2246 +        reg_00.raw = val;
  8.2247 +        reg_00.bits.ID = apicid;
  8.2248 +        val = reg_00.raw;
  8.2249      }
  8.2250  
  8.2251      *pval = val;
  8.2252 @@ -1974,7 +2292,7 @@ int ioapic_guest_write(int apicid, int a
  8.2253  
  8.2254          /* Set the correct irq-handling type. */
  8.2255          irq_desc[irq].handler = rte.trigger ? 
  8.2256 -            &ioapic_level_irq_type: &ioapic_edge_irq_type;
  8.2257 +            &ioapic_level_type: &ioapic_edge_type;
  8.2258  
  8.2259          /* Record the pin<->irq mapping. */
  8.2260          for ( entry = &irq_2_pin[irq]; ; entry = &irq_2_pin[entry->next] )

     9.1 --- a/xen/arch/x86/irq.c	Mon May 09 14:34:59 2005 +0000
     9.2 +++ b/xen/arch/x86/irq.c	Mon May 09 17:50:11 2005 +0000
     9.3 @@ -42,7 +42,6 @@ struct hw_interrupt_type no_irq_type = {
     9.4  };
     9.5  
     9.6  atomic_t irq_err_count;
     9.7 -atomic_t irq_mis_count;
     9.8  
     9.9  inline void disable_irq_nosync(unsigned int irq)
    9.10  {

    10.1 --- a/xen/arch/x86/microcode.c	Mon May 09 14:34:59 2005 +0000
    10.2 +++ b/xen/arch/x86/microcode.c	Mon May 09 17:50:11 2005 +0000
    10.3 @@ -87,13 +87,6 @@
    10.4  #define vmalloc(_s) xmalloc_bytes(_s)
    10.5  #define vfree(_p) xfree(_p)
    10.6  #define num_online_cpus() smp_num_cpus
    10.7 -static inline int on_each_cpu(
    10.8 -    void (*func) (void *info), void *info, int retry, int wait)
    10.9 -{
   10.10 -    int ret = smp_call_function(func, info, retry, wait);
   10.11 -    func(info);
   10.12 -    return ret;
   10.13 -}
   10.14  
   10.15  #if 0
   10.16  MODULE_DESCRIPTION("Intel CPU (IA-32) Microcode Update Driver");

    11.1 --- a/xen/arch/x86/mpparse.c	Mon May 09 14:34:59 2005 +0000
    11.2 +++ b/xen/arch/x86/mpparse.c	Mon May 09 17:50:11 2005 +0000
    11.3 @@ -1,5 +1,5 @@
    11.4  /*
    11.5 - *	Intel Multiprocessor Specificiation 1.1 and 1.4
    11.6 + *	Intel Multiprocessor Specification 1.1 and 1.4
    11.7   *	compliant MP-table parsing routines.
    11.8   *
    11.9   *	(c) 1995 Alan Cox, Building #3 <alan@redhat.com>
   11.10 @@ -14,44 +14,48 @@
   11.11   */
   11.12  
   11.13  #include <xen/config.h>
   11.14 -#include <xen/init.h>
   11.15 -#include <xen/lib.h>
   11.16 -#include <xen/kernel.h>
   11.17 +#include <xen/types.h>
   11.18  #include <xen/irq.h>
   11.19 -#include <xen/smp.h>
   11.20 -#include <xen/mm.h>
   11.21 +#include <xen/init.h>
   11.22  #include <xen/acpi.h>
   11.23 +#include <xen/delay.h>
   11.24 +#include <xen/sched.h>
   11.25 +
   11.26 +#include <asm/mc146818rtc.h>
   11.27 +#include <asm/bitops.h>
   11.28 +#include <asm/smp.h>
   11.29  #include <asm/acpi.h>
   11.30 -#include <asm/io.h>
   11.31 -#include <asm/apic.h>
   11.32 +#include <asm/mtrr.h>
   11.33  #include <asm/mpspec.h>
   11.34 -#include <asm/flushtlb.h>
   11.35 -#include <asm/smpboot.h>
   11.36 +#include <asm/io_apic.h>
   11.37  
   11.38 -int numnodes = 1; /* XXX Xen */
   11.39 +#include <mach_apic.h>
   11.40 +#include <mach_mpparse.h>
   11.41 +#include <bios_ebda.h>
   11.42 +
   11.43 +#define es7000_plat 0 /* XXX XEN */
   11.44  
   11.45  /* Have we found an MP table */
   11.46  int smp_found_config;
   11.47 +unsigned int __initdata maxcpus = NR_CPUS;
   11.48  
   11.49  /*
   11.50   * Various Linux-internal data structures created from the
   11.51   * MP-table.
   11.52   */
   11.53  int apic_version [MAX_APICS];
   11.54 +int mp_bus_id_to_type [MAX_MP_BUSSES];
   11.55 +int mp_bus_id_to_node [MAX_MP_BUSSES];
   11.56 +int mp_bus_id_to_local [MAX_MP_BUSSES];
   11.57  int quad_local_to_mp_bus_id [NR_CPUS/4][4];
   11.58 +int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
   11.59  int mp_current_pci_id;
   11.60 -int *mp_bus_id_to_type;
   11.61 -int *mp_bus_id_to_node;
   11.62 -int *mp_bus_id_to_local;
   11.63 -int *mp_bus_id_to_pci_bus;
   11.64 -int max_mp_busses;
   11.65 -int max_irq_sources;
   11.66  
   11.67  /* I/O APIC entries */
   11.68  struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
   11.69  
   11.70  /* # of MP IRQ source entries */
   11.71 -struct mpc_config_intsrc *mp_irqs;
   11.72 +struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
   11.73  
   11.74  /* MP IRQ source entries */
   11.75  int mp_irq_entries;
   11.76 @@ -65,24 +69,18 @@ unsigned long mp_lapic_addr;
   11.77  unsigned int boot_cpu_physical_apicid = -1U;
   11.78  unsigned int boot_cpu_logical_apicid = -1U;
   11.79  /* Internal processor count */
   11.80 -static unsigned int num_processors;
   11.81 +static unsigned int __initdata num_processors;
   11.82  
   11.83  /* Bitmask of physically existing CPUs */
   11.84 -unsigned long phys_cpu_present_map;
   11.85 -unsigned long logical_cpu_present_map;
   11.86 +physid_mask_t phys_cpu_present_map;
   11.87  
   11.88 -#ifdef CONFIG_X86_CLUSTERED_APIC
   11.89 -unsigned char esr_disable = 0;
   11.90 -unsigned char clustered_apic_mode = CLUSTERED_APIC_NONE;
   11.91 -unsigned int apic_broadcast_id = APIC_BROADCAST_ID_APIC;
   11.92 -#endif
   11.93 -unsigned char raw_phys_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
   11.94 +u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
   11.95  
   11.96  /*
   11.97   * Intel MP BIOS table parsing routines:
   11.98   */
   11.99  
  11.100 -#ifndef CONFIG_X86_VISWS_APIC
  11.101 +
  11.102  /*
  11.103   * Checksum an MP configuration block.
  11.104   */
  11.105 @@ -98,48 +96,6 @@ static int __init mpf_checksum(unsigned 
  11.106  }
  11.107  
  11.108  /*
  11.109 - * Processor encoding in an MP configuration block
  11.110 - */
  11.111 -
  11.112 -static char __init *mpc_family(int family,int model)
  11.113 -{
  11.114 -	static char n[32];
  11.115 -	static char *model_defs[]=
  11.116 -	{
  11.117 -		"80486DX","80486DX",
  11.118 -		"80486SX","80486DX/2 or 80487",
  11.119 -		"80486SL","80486SX/2",
  11.120 -		"Unknown","80486DX/2-WB",
  11.121 -		"80486DX/4","80486DX/4-WB"
  11.122 -	};
  11.123 -
  11.124 -	switch (family) {
  11.125 -		case 0x04:
  11.126 -			if (model < 10)
  11.127 -				return model_defs[model];
  11.128 -			break;
  11.129 -
  11.130 -		case 0x05:
  11.131 -			return("Pentium(tm)");
  11.132 -
  11.133 -		case 0x06:
  11.134 -			return("Pentium(tm) Pro");
  11.135 -
  11.136 -		case 0x0F:
  11.137 -			if (model == 0x00)
  11.138 -				return("Pentium 4(tm)");
  11.139 -			if (model == 0x01)
  11.140 -				return("Pentium 4(tm)");
  11.141 -			if (model == 0x02)
  11.142 -				return("Pentium 4(tm) XEON(tm)");
  11.143 -			if (model == 0x0F)
  11.144 -				return("Special controller");
  11.145 -	}
  11.146 -	sprintf(n,"Unknown CPU [%d:%d]",family, model);
  11.147 -	return n;
  11.148 -}
  11.149 -
  11.150 -/* 
  11.151   * Have to match translation table entries to main table entries by counter
  11.152   * hence the mpc_record variable .... can't see a less disgusting way of
  11.153   * doing this ....
  11.154 @@ -148,30 +104,30 @@ static char __init *mpc_family(int famil
  11.155  static int mpc_record; 
  11.156  static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata;
  11.157  
  11.158 +#ifdef CONFIG_X86_NUMAQ
  11.159 +static int MP_valid_apicid(int apicid, int version)
  11.160 +{
  11.161 +	return hweight_long(apicid & 0xf) == 1 && (apicid >> 4) != 0xf;
  11.162 +}
  11.163 +#else
  11.164 +static int MP_valid_apicid(int apicid, int version)
  11.165 +{
  11.166 +	if (version >= 0x14)
  11.167 +		return apicid < 0xff;
  11.168 +	else
  11.169 +		return apicid < 0xf;
  11.170 +}
  11.171 +#endif
  11.172 +
  11.173  void __init MP_processor_info (struct mpc_config_processor *m)
  11.174  {
  11.175 - 	int ver, quad, logical_apicid;
  11.176 + 	int ver, apicid;
  11.177 +	physid_mask_t tmp;
  11.178   	
  11.179  	if (!(m->mpc_cpuflag & CPU_ENABLED))
  11.180  		return;
  11.181  
  11.182 -	logical_apicid = m->mpc_apicid;
  11.183 -	if (clustered_apic_mode == CLUSTERED_APIC_NUMAQ) {
  11.184 -		quad = translation_table[mpc_record]->trans_quad;
  11.185 -		logical_apicid = (quad << 4) + 
  11.186 -			(m->mpc_apicid ? m->mpc_apicid << 1 : 1);
  11.187 -		printk("Processor #%d %s APIC version %d (quad %d, apic %d)\n",
  11.188 -			m->mpc_apicid,
  11.189 -			mpc_family((m->mpc_cpufeature & CPU_FAMILY_MASK)>>8 ,
  11.190 -				   (m->mpc_cpufeature & CPU_MODEL_MASK)>>4),
  11.191 -			m->mpc_apicver, quad, logical_apicid);
  11.192 -	} else {
  11.193 -		printk("Processor #%d %s APIC version %d\n",
  11.194 -			m->mpc_apicid,
  11.195 -			mpc_family((m->mpc_cpufeature & CPU_FAMILY_MASK)>>8 ,
  11.196 -				   (m->mpc_cpufeature & CPU_MODEL_MASK)>>4),
  11.197 -			m->mpc_apicver);
  11.198 -	}
  11.199 +	apicid = mpc_apic_id(m, translation_table[mpc_record]);
  11.200  
  11.201  	if (m->mpc_featureflag&(1<<0))
  11.202  		Dprintk("    Floating point unit present.\n");
  11.203 @@ -224,68 +180,68 @@ void __init MP_processor_info (struct mp
  11.204  	if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
  11.205  		Dprintk("    Bootup CPU\n");
  11.206  		boot_cpu_physical_apicid = m->mpc_apicid;
  11.207 -		boot_cpu_logical_apicid = logical_apicid;
  11.208 +		boot_cpu_logical_apicid = apicid;
  11.209  	}
  11.210  
  11.211 -	if (num_processors >= NR_CPUS){
  11.212 -		printk(KERN_WARNING "NR_CPUS limit of %i reached. Cannot "
  11.213 -			"boot CPU(apicid 0x%x).\n", NR_CPUS, m->mpc_apicid);
  11.214 +	if (num_processors >= NR_CPUS) {
  11.215 +		printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
  11.216 +			"  Processor ignored.\n", NR_CPUS); 
  11.217 +		return;
  11.218 +	}
  11.219 +
  11.220 +	if (num_processors >= maxcpus) {
  11.221 +		printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
  11.222 +			" Processor ignored.\n", maxcpus); 
  11.223  		return;
  11.224  	}
  11.225  	num_processors++;
  11.226 +	ver = m->mpc_apicver;
  11.227  
  11.228 -	if (m->mpc_apicid > MAX_APICS) {
  11.229 -		printk("Processor #%d INVALID. (Max ID: %d).\n",
  11.230 +	if (!MP_valid_apicid(apicid, ver)) {
  11.231 +		printk(KERN_WARNING "Processor #%d INVALID. (Max ID: %d).\n",
  11.232  			m->mpc_apicid, MAX_APICS);
  11.233  		--num_processors;
  11.234  		return;
  11.235  	}
  11.236 -	ver = m->mpc_apicver;
  11.237  
  11.238 -	logical_cpu_present_map |= 1 << (num_processors-1);
  11.239 - 	phys_cpu_present_map |= apicid_to_phys_cpu_present(m->mpc_apicid);
  11.240 - 
  11.241 +	tmp = apicid_to_cpu_present(apicid);
  11.242 +	physids_or(phys_cpu_present_map, phys_cpu_present_map, tmp);
  11.243 +	
  11.244  	/*
  11.245  	 * Validate version
  11.246  	 */
  11.247  	if (ver == 0x0) {
  11.248 -		printk("BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
  11.249 +		printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
  11.250  		ver = 0x10;
  11.251  	}
  11.252  	apic_version[m->mpc_apicid] = ver;
  11.253 -	raw_phys_apicid[num_processors - 1] = m->mpc_apicid;
  11.254 +	bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
  11.255  }
  11.256  
  11.257  static void __init MP_bus_info (struct mpc_config_bus *m)
  11.258  {
  11.259  	char str[7];
  11.260 -	int quad;
  11.261  
  11.262  	memcpy(str, m->mpc_bustype, 6);
  11.263  	str[6] = 0;
  11.264 -	
  11.265 -	if (clustered_apic_mode == CLUSTERED_APIC_NUMAQ) {
  11.266 -		quad = translation_table[mpc_record]->trans_quad;
  11.267 -		mp_bus_id_to_node[m->mpc_busid] = quad;
  11.268 -		mp_bus_id_to_local[m->mpc_busid] = translation_table[mpc_record]->trans_local;
  11.269 -		quad_local_to_mp_bus_id[quad][translation_table[mpc_record]->trans_local] = m->mpc_busid;
  11.270 -		printk("Bus #%d is %s (node %d)\n", m->mpc_busid, str, quad);
  11.271 -	} else {
  11.272 -		Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
  11.273 -	}
  11.274 +
  11.275 +	mpc_oem_bus_info(m, str, translation_table[mpc_record]);
  11.276  
  11.277  	if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
  11.278  		mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
  11.279  	} else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
  11.280  		mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
  11.281  	} else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
  11.282 +		mpc_oem_pci_bus(m, translation_table[mpc_record]);
  11.283  		mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
  11.284  		mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
  11.285  		mp_current_pci_id++;
  11.286  	} else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
  11.287  		mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
  11.288 +	} else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) {
  11.289 +		mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98;
  11.290  	} else {
  11.291 -		printk("Unknown bustype %s - ignoring\n", str);
  11.292 +		printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
  11.293  	}
  11.294  }
  11.295  
  11.296 @@ -294,10 +250,10 @@ static void __init MP_ioapic_info (struc
  11.297  	if (!(m->mpc_flags & MPC_APIC_USABLE))
  11.298  		return;
  11.299  
  11.300 -	printk("I/O APIC #%d Version %d at 0x%X.\n",
  11.301 +	printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
  11.302  		m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
  11.303  	if (nr_ioapics >= MAX_IO_APICS) {
  11.304 -		printk("Max # of I/O APICs (%d) exceeded (found %d).\n",
  11.305 +		printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
  11.306  			MAX_IO_APICS, nr_ioapics);
  11.307  		panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
  11.308  	}
  11.309 @@ -318,7 +274,7 @@ static void __init MP_intsrc_info (struc
  11.310  			m->mpc_irqtype, m->mpc_irqflag & 3,
  11.311  			(m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
  11.312  			m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
  11.313 -	if (++mp_irq_entries == max_irq_sources)
  11.314 +	if (++mp_irq_entries == MAX_IRQ_SOURCES)
  11.315  		panic("Max # of irq sources exceeded!!\n");
  11.316  }
  11.317  
  11.318 @@ -344,16 +300,17 @@ static void __init MP_lintsrc_info (stru
  11.319  			BUG();
  11.320  }
  11.321  
  11.322 +#ifdef CONFIG_X86_NUMAQ
  11.323  static void __init MP_translation_info (struct mpc_config_translation *m)
  11.324  {
  11.325 -	printk("Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
  11.326 +	printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
  11.327  
  11.328  	if (mpc_record >= MAX_MPC_ENTRY) 
  11.329 -		printk("MAX_MPC_ENTRY exceeded!\n");
  11.330 +		printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
  11.331  	else
  11.332  		translation_table[mpc_record] = m; /* stash this for later */
  11.333 -	if (m->trans_quad+1 > numnodes)
  11.334 -		numnodes = m->trans_quad+1;
  11.335 +	if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
  11.336 +		node_set_online(m->trans_quad);
  11.337  }
  11.338  
  11.339  /*
  11.340 @@ -366,10 +323,11 @@ static void __init smp_read_mpc_oem(stru
  11.341  	int count = sizeof (*oemtable); /* the header size */
  11.342  	unsigned char *oemptr = ((unsigned char *)oemtable)+count;
  11.343  	
  11.344 -	printk("Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
  11.345 +	mpc_record = 0;
  11.346 +	printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
  11.347  	if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
  11.348  	{
  11.349 -		printk("SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
  11.350 +		printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
  11.351  			oemtable->oem_signature[0],
  11.352  			oemtable->oem_signature[1],
  11.353  			oemtable->oem_signature[2],
  11.354 @@ -378,7 +336,7 @@ static void __init smp_read_mpc_oem(stru
  11.355  	}
  11.356  	if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
  11.357  	{
  11.358 -		printk("SMP oem mptable: checksum error!\n");
  11.359 +		printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
  11.360  		return;
  11.361  	}
  11.362  	while (count < oemtable->oem_length) {
  11.363 @@ -395,36 +353,42 @@ static void __init smp_read_mpc_oem(stru
  11.364  			}
  11.365  			default:
  11.366  			{
  11.367 -				printk("Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
  11.368 +				printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
  11.369  				return;
  11.370  			}
  11.371  		}
  11.372         }
  11.373  }
  11.374  
  11.375 +static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
  11.376 +		char *productid)
  11.377 +{
  11.378 +	if (strncmp(oem, "IBM NUMA", 8))
  11.379 +		printk("Warning!  May not be a NUMA-Q system!\n");
  11.380 +	if (mpc->mpc_oemptr)
  11.381 +		smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
  11.382 +				mpc->mpc_oemsize);
  11.383 +}
  11.384 +#endif	/* CONFIG_X86_NUMAQ */
  11.385 +
  11.386  /*
  11.387   * Read/parse the MPC
  11.388   */
  11.389  
  11.390  static int __init smp_read_mpc(struct mp_config_table *mpc)
  11.391  {
  11.392 -	char oem[16], prod[14];
  11.393 +	char str[16];
  11.394 +	char oem[10];
  11.395  	int count=sizeof(*mpc);
  11.396  	unsigned char *mpt=((unsigned char *)mpc)+count;
  11.397 -	int num_bus = 0;
  11.398 -	int num_irq = 0;
  11.399 -	unsigned char *bus_data;
  11.400  
  11.401  	if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
  11.402 -		panic("SMP mptable: bad signature [%c%c%c%c]!\n",
  11.403 -			mpc->mpc_signature[0],
  11.404 -			mpc->mpc_signature[1],
  11.405 -			mpc->mpc_signature[2],
  11.406 -			mpc->mpc_signature[3]);
  11.407 +		printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
  11.408 +			*(u32 *)mpc->mpc_signature);
  11.409  		return 0;
  11.410  	}
  11.411  	if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
  11.412 -		panic("SMP mptable: checksum error!\n");
  11.413 +		printk(KERN_ERR "SMP mptable: checksum error!\n");
  11.414  		return 0;
  11.415  	}
  11.416  	if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
  11.417 @@ -438,14 +402,14 @@ static int __init smp_read_mpc(struct mp
  11.418  	}
  11.419  	memcpy(oem,mpc->mpc_oem,8);
  11.420  	oem[8]=0;
  11.421 -	printk("OEM ID: %s ",oem);
  11.422 +	printk(KERN_INFO "OEM ID: %s ",oem);
  11.423  
  11.424 -	memcpy(prod,mpc->mpc_productid,12);
  11.425 -	prod[12]=0;
  11.426 -	printk("Product ID: %s ",prod);
  11.427 +	memcpy(str,mpc->mpc_productid,12);
  11.428 +	str[12]=0;
  11.429 +	printk("Product ID: %s ",str);
  11.430  
  11.431 -	detect_clustered_apic(oem, prod);
  11.432 -	
  11.433 +	mps_oem_check(mpc, oem, str);
  11.434 +
  11.435  	printk("APIC at: 0x%X\n",mpc->mpc_lapic);
  11.436  
  11.437  	/* 
  11.438 @@ -455,77 +419,10 @@ static int __init smp_read_mpc(struct mp
  11.439  	if (!acpi_lapic)
  11.440  		mp_lapic_addr = mpc->mpc_lapic;
  11.441  
  11.442 -	if ((clustered_apic_mode == CLUSTERED_APIC_NUMAQ) && mpc->mpc_oemptr) {
  11.443 -		/* We need to process the oem mpc tables to tell us which quad things are in ... */
  11.444 -		mpc_record = 0;
  11.445 -		smp_read_mpc_oem((struct mp_config_oemtable *)(unsigned long)mpc->mpc_oemptr, mpc->mpc_oemsize);
  11.446 -		mpc_record = 0;
  11.447 -	}
  11.448 -
  11.449 -	/* Pre-scan to determine the number of bus and 
  11.450 -	 * interrupts records we have
  11.451 -	 */
  11.452 -	while (count < mpc->mpc_length) {
  11.453 -		switch (*mpt) {
  11.454 -			case MP_PROCESSOR:
  11.455 -				mpt += sizeof(struct mpc_config_processor);
  11.456 -				count += sizeof(struct mpc_config_processor);
  11.457 -				break;
  11.458 -			case MP_BUS:
  11.459 -				++num_bus;
  11.460 -				mpt += sizeof(struct mpc_config_bus);
  11.461 -				count += sizeof(struct mpc_config_bus);
  11.462 -				break;
  11.463 -			case MP_INTSRC:
  11.464 -				++num_irq;
  11.465 -				mpt += sizeof(struct mpc_config_intsrc);
  11.466 -				count += sizeof(struct mpc_config_intsrc);
  11.467 -				break;
  11.468 -			case MP_IOAPIC:
  11.469 -				mpt += sizeof(struct mpc_config_ioapic);
  11.470 -				count += sizeof(struct mpc_config_ioapic);
  11.471 -				break;
  11.472 -			case MP_LINTSRC:
  11.473 -				mpt += sizeof(struct mpc_config_lintsrc);
  11.474 -				count += sizeof(struct mpc_config_lintsrc);
  11.475 -				break;
  11.476 -			default:
  11.477 -				count = mpc->mpc_length;
  11.478 -				break;
  11.479 -		}
  11.480 -	}
  11.481 -	/* 
  11.482 -	 * Paranoia: Allocate one extra of both the number of busses and number
  11.483 -	 * of irqs, and make sure that we have at least 4 interrupts per PCI
  11.484 -	 * slot.  But some machines do not report very many busses, so we need
  11.485 -	 * to fall back on the older defaults.
  11.486 -	 */
  11.487 -	++num_bus;
  11.488 -	max_mp_busses = max(num_bus, MAX_MP_BUSSES);
  11.489 -	if (num_irq < (4 * max_mp_busses))
  11.490 -		num_irq = 4 * num_bus;	/* 4 intr/PCI slot */
  11.491 -	++num_irq;
  11.492 -	max_irq_sources = max(num_irq, MAX_IRQ_SOURCES);
  11.493 -	
  11.494 -	count = (max_mp_busses * sizeof(int)) * 4;
  11.495 -	count += (max_irq_sources * sizeof(struct mpc_config_intsrc));
  11.496 -	bus_data = (void *)alloc_xenheap_pages(get_order(count));
  11.497 -	if (!bus_data) {
  11.498 -		printk(KERN_ERR "SMP mptable: out of memory!\n");
  11.499 -		return 0;
  11.500 -	}
  11.501 -	mp_bus_id_to_type = (int *)&bus_data[0];
  11.502 -	mp_bus_id_to_node = (int *)&bus_data[(max_mp_busses * sizeof(int))];
  11.503 -	mp_bus_id_to_local = (int *)&bus_data[(max_mp_busses * sizeof(int)) * 2];
  11.504 -	mp_bus_id_to_pci_bus = (int *)&bus_data[(max_mp_busses * sizeof(int)) * 3];
  11.505 -	mp_irqs = (struct mpc_config_intsrc *)&bus_data[(max_mp_busses * sizeof(int)) * 4];
  11.506 -	memset(mp_bus_id_to_pci_bus, -1, max_mp_busses * sizeof(int));
  11.507 -
  11.508  	/*
  11.509  	 *	Now process the configuration blocks.
  11.510  	 */
  11.511 -	count = sizeof(*mpc);
  11.512 -	mpt = ((unsigned char *)mpc)+count;
  11.513 +	mpc_record = 0;
  11.514  	while (count < mpc->mpc_length) {
  11.515  		switch(*mpt) {
  11.516  			case MP_PROCESSOR:
  11.517 @@ -584,21 +481,7 @@ static int __init smp_read_mpc(struct mp
  11.518  		}
  11.519  		++mpc_record;
  11.520  	}
  11.521 -
  11.522 -	if (clustered_apic_mode){
  11.523 -		phys_cpu_present_map = logical_cpu_present_map;
  11.524 -	}
  11.525 -
  11.526 -
  11.527 -	printk("Enabling APIC mode: ");
  11.528 -	if(clustered_apic_mode == CLUSTERED_APIC_NUMAQ)
  11.529 -		printk("Clustered Logical.	");
  11.530 -	else if(clustered_apic_mode == CLUSTERED_APIC_XAPIC)
  11.531 -		printk("Physical.	");
  11.532 -	else
  11.533 -		printk("Flat.	");
  11.534 -	printk("Using %d I/O APICs\n",nr_ioapics);
  11.535 -
  11.536 +	clustered_apic_check();
  11.537  	if (!num_processors)
  11.538  		printk(KERN_ERR "SMP mptable: no processors registered!\n");
  11.539  	return num_processors;
  11.540 @@ -634,12 +517,12 @@ static void __init construct_default_ioi
  11.541  	 *  If it does, we assume it's valid.
  11.542  	 */
  11.543  	if (mpc_default_type == 5) {
  11.544 -		printk("ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
  11.545 +		printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
  11.546  
  11.547  		if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
  11.548 -			printk("ELCR contains invalid data... not using ELCR\n");
  11.549 +			printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
  11.550  		else {
  11.551 -			printk("Using ELCR to identify PCI interrupts\n");
  11.552 +			printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
  11.553  			ELCR_fallback = 1;
  11.554  		}
  11.555  	}
  11.556 @@ -686,24 +569,6 @@ static inline void __init construct_defa
  11.557  	struct mpc_config_lintsrc lintsrc;
  11.558  	int linttypes[2] = { mp_ExtINT, mp_NMI };
  11.559  	int i;
  11.560 -	struct {
  11.561 -		int mp_bus_id_to_type[MAX_MP_BUSSES];
  11.562 -		int mp_bus_id_to_node[MAX_MP_BUSSES];
  11.563 -		int mp_bus_id_to_local[MAX_MP_BUSSES];
  11.564 -		int mp_bus_id_to_pci_bus[MAX_MP_BUSSES];
  11.565 -		struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
  11.566 -	} *bus_data;
  11.567 -
  11.568 -	bus_data = (void *)alloc_xenheap_pages(get_order(sizeof(*bus_data)));
  11.569 -	if (!bus_data)
  11.570 -		panic("SMP mptable: out of memory!\n");
  11.571 -	mp_bus_id_to_type = bus_data->mp_bus_id_to_type;
  11.572 -	mp_bus_id_to_node = bus_data->mp_bus_id_to_node;
  11.573 -	mp_bus_id_to_local = bus_data->mp_bus_id_to_local;
  11.574 -	mp_bus_id_to_pci_bus = bus_data->mp_bus_id_to_pci_bus;
  11.575 -	mp_irqs = bus_data->mp_irqs;
  11.576 -	for (i = 0; i < MAX_MP_BUSSES; ++i)
  11.577 -		mp_bus_id_to_pci_bus[i] = -1;
  11.578  
  11.579  	/*
  11.580  	 * local APIC has default address
  11.581 @@ -732,7 +597,8 @@ static inline void __init construct_defa
  11.582  	bus.mpc_busid = 0;
  11.583  	switch (mpc_default_type) {
  11.584  		default:
  11.585 -			printk("???\nUnknown standard configuration %d\n",
  11.586 +			printk("???\n");
  11.587 +			printk(KERN_ERR "Unknown standard configuration %d\n",
  11.588  				mpc_default_type);
  11.589  			/* fall through */
  11.590  		case 1:
  11.591 @@ -790,7 +656,7 @@ void __init get_smp_config (void)
  11.592  
  11.593  	/*
  11.594  	 * ACPI may be used to obtain the entire SMP configuration or just to 
  11.595 -	 * enumerate/configure processors (CONFIG_ACPI_HT_ONLY).  Note that 
  11.596 +	 * enumerate/configure processors (CONFIG_ACPI_BOOT).  Note that 
  11.597  	 * ACPI supports both logical (e.g. Hyper-Threading) and physical 
  11.598  	 * processors, where MPS only supports physical.
  11.599  	 */
  11.600 @@ -801,12 +667,12 @@ void __init get_smp_config (void)
  11.601  	else if (acpi_lapic)
  11.602  		printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
  11.603  
  11.604 -	printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
  11.605 +	printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
  11.606  	if (mpf->mpf_feature2 & (1<<7)) {
  11.607 -		printk("    IMCR and PIC compatibility mode.\n");
  11.608 +		printk(KERN_INFO "    IMCR and PIC compatibility mode.\n");
  11.609  		pic_mode = 1;
  11.610  	} else {
  11.611 -		printk("    Virtual Wire compatibility mode.\n");
  11.612 +		printk(KERN_INFO "    Virtual Wire compatibility mode.\n");
  11.613  		pic_mode = 0;
  11.614  	}
  11.615  
  11.616 @@ -815,7 +681,7 @@ void __init get_smp_config (void)
  11.617  	 */
  11.618  	if (mpf->mpf_feature1 != 0) {
  11.619  
  11.620 -		printk("Default MP configuration #%d\n", mpf->mpf_feature1);
  11.621 +		printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
  11.622  		construct_default_ISA_mptable(mpf->mpf_feature1);
  11.623  
  11.624  	} else if (mpf->mpf_physptr) {
  11.625 @@ -824,7 +690,7 @@ void __init get_smp_config (void)
  11.626  		 * Read the physical hardware table.  Anything here will
  11.627  		 * override the defaults.
  11.628  		 */
  11.629 -		if (!smp_read_mpc((void *)(unsigned long)mpf->mpf_physptr)) {
  11.630 +		if (!smp_read_mpc((void *)mpf->mpf_physptr)) {
  11.631  			smp_found_config = 0;
  11.632  			printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
  11.633  			printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
  11.634 @@ -838,7 +704,7 @@ void __init get_smp_config (void)
  11.635  		if (!mp_irq_entries) {
  11.636  			struct mpc_config_bus bus;
  11.637  
  11.638 -			printk("BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
  11.639 +			printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
  11.640  
  11.641  			bus.mpc_type = MP_BUS;
  11.642  			bus.mpc_busid = 0;
  11.643 @@ -851,7 +717,7 @@ void __init get_smp_config (void)
  11.644  	} else
  11.645  		BUG();
  11.646  
  11.647 -	printk("Processors: %d\n", num_processors);
  11.648 +	printk(KERN_INFO "Processors: %d\n", num_processors);
  11.649  	/*
  11.650  	 * Only use the first configuration found.
  11.651  	 */
  11.652 @@ -859,7 +725,7 @@ void __init get_smp_config (void)
  11.653  
  11.654  static int __init smp_scan_config (unsigned long base, unsigned long length)
  11.655  {
  11.656 -	unsigned int *bp = phys_to_virt(base);
  11.657 +	unsigned long *bp = phys_to_virt(base);
  11.658  	struct intel_mp_floating *mpf;
  11.659  
  11.660  	Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
  11.661 @@ -875,11 +741,27 @@ static int __init smp_scan_config (unsig
  11.662  				|| (mpf->mpf_specification == 4)) ) {
  11.663  
  11.664  			smp_found_config = 1;
  11.665 -			printk("found SMP MP-table at %08lx\n",
  11.666 +			printk(KERN_INFO "found SMP MP-table at %08lx\n",
  11.667  						virt_to_phys(mpf));
  11.668 +#if 0
  11.669  			reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE);
  11.670 -			if (mpf->mpf_physptr)
  11.671 -				reserve_bootmem((unsigned long)mpf->mpf_physptr, PAGE_SIZE);
  11.672 +			if (mpf->mpf_physptr) {
  11.673 +				/*
  11.674 +				 * We cannot access to MPC table to compute
  11.675 +				 * table size yet, as only few megabytes from
  11.676 +				 * the bottom is mapped now.
  11.677 +				 * PC-9800's MPC table places on the very last
  11.678 +				 * of physical memory; so that simply reserving
  11.679 +				 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
  11.680 +				 * in reserve_bootmem.
  11.681 +				 */
  11.682 +				unsigned long size = PAGE_SIZE;
  11.683 +				unsigned long end = max_low_pfn * PAGE_SIZE;
  11.684 +				if (mpf->mpf_physptr + size > end)
  11.685 +					size = end - mpf->mpf_physptr;
  11.686 +				reserve_bootmem(mpf->mpf_physptr, size);
  11.687 +			}
  11.688 +#endif
  11.689  			mpf_found = mpf;
  11.690  			return 1;
  11.691  		}
  11.692 @@ -889,7 +771,7 @@ static int __init smp_scan_config (unsig
  11.693  	return 0;
  11.694  }
  11.695  
  11.696 -void __init find_intel_smp (void)
  11.697 +void __init find_smp_config (void)
  11.698  {
  11.699  	unsigned int address;
  11.700  
  11.701 @@ -913,53 +795,20 @@ void __init find_intel_smp (void)
  11.702  	 * there is a real-mode segmented pointer pointing to the
  11.703  	 * 4K EBDA area at 0x40E, calculate and scan it here.
  11.704  	 *
  11.705 -	 * NOTE! There were Linux loaders that will corrupt the EBDA
  11.706 +	 * NOTE! There are Linux loaders that will corrupt the EBDA
  11.707  	 * area, and as such this kind of SMP config may be less
  11.708  	 * trustworthy, simply because the SMP table may have been
  11.709 -	 * stomped on during early boot.  Thankfully the bootloaders
  11.710 -	 * now honour the EBDA.
  11.711 +	 * stomped on during early boot. These loaders are buggy and
  11.712 +	 * should be fixed.
  11.713 +	 *
  11.714 +	 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
  11.715  	 */
  11.716  
  11.717 -	address = *(unsigned short *)phys_to_virt(0x40E);
  11.718 -	address <<= 4;
  11.719 -	smp_scan_config(address, 0x1000);
  11.720 +	address = get_bios_ebda();
  11.721 +	if (address)
  11.722 +		smp_scan_config(address, 0x400);
  11.723  }
  11.724  
  11.725 -#else
  11.726 -
  11.727 -/*
  11.728 - * The Visual Workstation is Intel MP compliant in the hardware
  11.729 - * sense, but it doesn't have a BIOS(-configuration table).
  11.730 - * No problem for Linux.
  11.731 - */
  11.732 -void __init find_visws_smp(void)
  11.733 -{
  11.734 -	smp_found_config = 1;
  11.735 -
  11.736 -	phys_cpu_present_map |= 2; /* or in id 1 */
  11.737 -	apic_version[1] |= 0x10; /* integrated APIC */
  11.738 -	apic_version[0] |= 0x10;
  11.739 -
  11.740 -	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
  11.741 -}
  11.742 -
  11.743 -#endif
  11.744 -
  11.745 -/*
  11.746 - * - Intel MP Configuration Table
  11.747 - * - or SGI Visual Workstation configuration
  11.748 - */
  11.749 -void __init find_smp_config (void)
  11.750 -{
  11.751 -#ifdef CONFIG_X86_LOCAL_APIC
  11.752 -	find_intel_smp();
  11.753 -#endif
  11.754 -#ifdef CONFIG_VISWS
  11.755 -	find_visws_smp();
  11.756 -#endif
  11.757 -}
  11.758 -
  11.759 -
  11.760  /* --------------------------------------------------------------------------
  11.761                              ACPI-based MP Configuration
  11.762     -------------------------------------------------------------------------- */
  11.763 @@ -987,7 +836,7 @@ void __init mp_register_lapic (
  11.764  	struct mpc_config_processor processor;
  11.765  	int			boot_cpu = 0;
  11.766  	
  11.767 -	if (id >= MAX_APICS) {
  11.768 +	if (MAX_APICS - id <= 0) {
  11.769  		printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
  11.770  			id, MAX_APICS);
  11.771  		return;
  11.772 @@ -998,14 +847,7 @@ void __init mp_register_lapic (
  11.773  
  11.774  	processor.mpc_type = MP_PROCESSOR;
  11.775  	processor.mpc_apicid = id;
  11.776 -
  11.777 -	/*
  11.778 -	 * mp_register_lapic_address() which is called before the
  11.779 -	 * current function does the fixmap of FIX_APIC_BASE.
  11.780 -	 * Read in the correct APIC version from there
  11.781 -	 */
  11.782 -	processor.mpc_apicver = apic_read(APIC_LVR);
  11.783 -
  11.784 +	processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
  11.785  	processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
  11.786  	processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
  11.787  	processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | 
  11.788 @@ -1017,32 +859,32 @@ void __init mp_register_lapic (
  11.789  	MP_processor_info(&processor);
  11.790  }
  11.791  
  11.792 -#if defined(CONFIG_X86_IO_APIC) /*&& defined(CONFIG_ACPI_INTERPRETER)*/
  11.793 +#if defined(CONFIG_X86_IO_APIC) && (defined(CONFIG_ACPI_INTERPRETER) || defined(CONFIG_ACPI_BOOT))
  11.794  
  11.795  #define MP_ISA_BUS		0
  11.796  #define MP_MAX_IOAPIC_PIN	127
  11.797  
  11.798  struct mp_ioapic_routing {
  11.799  	int			apic_id;
  11.800 -	int			irq_start;
  11.801 -	int			irq_end;
  11.802 +	int			gsi_base;
  11.803 +	int			gsi_end;
  11.804  	u32			pin_programmed[4];
  11.805  } mp_ioapic_routing[MAX_IO_APICS];
  11.806  
  11.807  
  11.808 -static int __init mp_find_ioapic (
  11.809 -	int			irq)
  11.810 +static int mp_find_ioapic (
  11.811 +	int			gsi)
  11.812  {
  11.813  	int			i = 0;
  11.814  
  11.815 -	/* Find the IOAPIC that manages this IRQ. */
  11.816 +	/* Find the IOAPIC that manages this GSI. */
  11.817  	for (i = 0; i < nr_ioapics; i++) {
  11.818 -		if ((irq >= mp_ioapic_routing[i].irq_start)
  11.819 -			&& (irq <= mp_ioapic_routing[i].irq_end))
  11.820 +		if ((gsi >= mp_ioapic_routing[i].gsi_base)
  11.821 +			&& (gsi <= mp_ioapic_routing[i].gsi_end))
  11.822  			return i;
  11.823  	}
  11.824  
  11.825 -	printk(KERN_ERR "ERROR: Unable to locate IOAPIC for IRQ %d\n", irq);
  11.826 +	printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
  11.827  
  11.828  	return -1;
  11.829  }
  11.830 @@ -1051,7 +893,7 @@ static int __init mp_find_ioapic (
  11.831  void __init mp_register_ioapic (
  11.832  	u8			id, 
  11.833  	u32			address,
  11.834 -	u32			irq_base)
  11.835 +	u32			gsi_base)
  11.836  {
  11.837  	int			idx = 0;
  11.838  
  11.839 @@ -1077,19 +919,19 @@ void __init mp_register_ioapic (
  11.840  	mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
  11.841  	
  11.842  	/* 
  11.843 -	 * Build basic IRQ lookup table to facilitate irq->io_apic lookups
  11.844 -	 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
  11.845 +	 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
  11.846 +	 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
  11.847  	 */
  11.848  	mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
  11.849 -	mp_ioapic_routing[idx].irq_start = irq_base;
  11.850 -	mp_ioapic_routing[idx].irq_end = irq_base + 
  11.851 +	mp_ioapic_routing[idx].gsi_base = gsi_base;
  11.852 +	mp_ioapic_routing[idx].gsi_end = gsi_base + 
  11.853  		io_apic_get_redir_entries(idx);
  11.854  
  11.855  	printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
  11.856 -		"IRQ %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, 
  11.857 +		"GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid, 
  11.858  		mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
  11.859 -		mp_ioapic_routing[idx].irq_start,
  11.860 -		mp_ioapic_routing[idx].irq_end);
  11.861 +		mp_ioapic_routing[idx].gsi_base,
  11.862 +		mp_ioapic_routing[idx].gsi_end);
  11.863  
  11.864  	return;
  11.865  }
  11.866 @@ -1099,21 +941,19 @@ void __init mp_override_legacy_irq (
  11.867  	u8			bus_irq,
  11.868  	u8			polarity, 
  11.869  	u8			trigger, 
  11.870 -	u32			global_irq)
  11.871 +	u32			gsi)
  11.872  {
  11.873  	struct mpc_config_intsrc intsrc;
  11.874 -	int			i = 0;
  11.875 -	int			found = 0;
  11.876  	int			ioapic = -1;
  11.877  	int			pin = -1;
  11.878  
  11.879  	/* 
  11.880 -	 * Convert 'global_irq' to 'ioapic.pin'.
  11.881 +	 * Convert 'gsi' to 'ioapic.pin'.
  11.882  	 */
  11.883 -	ioapic = mp_find_ioapic(global_irq);
  11.884 +	ioapic = mp_find_ioapic(gsi);
  11.885  	if (ioapic < 0)
  11.886  		return;
  11.887 -	pin = global_irq - mp_ioapic_routing[ioapic].irq_start;
  11.888 +	pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
  11.889  
  11.890  	/*
  11.891  	 * TBD: This check is for faulty timer entries, where the override
  11.892 @@ -1136,23 +976,9 @@ void __init mp_override_legacy_irq (
  11.893  		(intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, 
  11.894  		intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
  11.895  
  11.896 -	/* 
  11.897 -	 * If an existing [IOAPIC.PIN -> IRQ] routing entry exists we override it.
  11.898 -	 * Otherwise create a new entry (e.g. global_irq == 2).
  11.899 -	 */
  11.900 -	for (i = 0; i < mp_irq_entries; i++) {
  11.901 -		if ((mp_irqs[i].mpc_srcbus == intsrc.mpc_srcbus) 
  11.902 -			&& (mp_irqs[i].mpc_srcbusirq == intsrc.mpc_srcbusirq)) {
  11.903 -			mp_irqs[i] = intsrc;
  11.904 -			found = 1;
  11.905 -			break;
  11.906 -		}
  11.907 -	}
  11.908 -	if (!found) {
  11.909 -		mp_irqs[mp_irq_entries] = intsrc;
  11.910 -		if (++mp_irq_entries == MAX_IRQ_SOURCES)
  11.911 -			panic("Max # of irq sources exceeded!\n");
  11.912 -	}
  11.913 +	mp_irqs[mp_irq_entries] = intsrc;
  11.914 +	if (++mp_irq_entries == MAX_IRQ_SOURCES)
  11.915 +		panic("Max # of irq sources exceeded!\n");
  11.916  
  11.917  	return;
  11.918  }
  11.919 @@ -1160,35 +986,22 @@ void __init mp_override_legacy_irq (
  11.920  
  11.921  void __init mp_config_acpi_legacy_irqs (void)
  11.922  {
  11.923 +	struct mpc_config_intsrc intsrc;
  11.924  	int			i = 0;
  11.925  	int			ioapic = -1;
  11.926  
  11.927 -	/*
  11.928 -	 * Initialize mp_irqs for IRQ configuration.
  11.929 -	 */
  11.930 -	unsigned char *bus_data;
  11.931 -	int count;
  11.932 -
  11.933 -	count = (MAX_MP_BUSSES * sizeof(int)) * 4;
  11.934 -	count += (MAX_IRQ_SOURCES * sizeof(int)) * 4;
  11.935 -	bus_data = (void *)alloc_xenheap_pages(get_order(count));
  11.936 -	if (!bus_data) {
  11.937 -		panic("Fatal: can't allocate bus memory for ACPI legacy IRQ!");
  11.938 -	}
  11.939 -	mp_bus_id_to_type = (int *)&bus_data[0];
  11.940 -	mp_bus_id_to_node = (int *)&bus_data[(MAX_MP_BUSSES * sizeof(int))];
  11.941 -	mp_bus_id_to_local = (int *)&bus_data[(MAX_MP_BUSSES * sizeof(int)) * 2];
  11.942 -	mp_bus_id_to_pci_bus = (int *)&bus_data[(MAX_MP_BUSSES * sizeof(int)) * 3];
  11.943 -	mp_irqs = (struct mpc_config_intsrc *)&bus_data[(MAX_MP_BUSSES * sizeof(int)) * 4];
  11.944 -	for (i = 0; i < MAX_MP_BUSSES; ++i)
  11.945 -	  mp_bus_id_to_pci_bus[i] = -1;
  11.946 -
  11.947  	/* 
  11.948  	 * Fabricate the legacy ISA bus (bus #31).
  11.949  	 */
  11.950  	mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
  11.951  	Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
  11.952  
  11.953 +	/*
  11.954 +	 * ES7000 has no legacy identity mappings
  11.955 +	 */
  11.956 +	if (es7000_plat)
  11.957 +		return;
  11.958 +
  11.959  	/* 
  11.960  	 * Locate the IOAPIC that manages the ISA IRQs (0-15). 
  11.961  	 */
  11.962 @@ -1196,118 +1009,101 @@ void __init mp_config_acpi_legacy_irqs (
  11.963  	if (ioapic < 0)
  11.964  		return;
  11.965  
  11.966 +	intsrc.mpc_type = MP_INTSRC;
  11.967 +	intsrc.mpc_irqflag = 0;					/* Conforming */
  11.968 +	intsrc.mpc_srcbus = MP_ISA_BUS;
  11.969 +	intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
  11.970 +
  11.971  	/* 
  11.972 -	 * Use the default configuration for the IRQs 0-15.  These may be
  11.973 +	 * Use the default configuration for the IRQs 0-15.  Unless
  11.974  	 * overriden by (MADT) interrupt source override entries.
  11.975  	 */
  11.976  	for (i = 0; i < 16; i++) {
  11.977 +		int idx;
  11.978  
  11.979 -		if (i == 2)
  11.980 -			continue;			/* Don't connect IRQ2 */
  11.981 +		for (idx = 0; idx < mp_irq_entries; idx++) {
  11.982 +			struct mpc_config_intsrc *irq = mp_irqs + idx;
  11.983 +
  11.984 +			/* Do we already have a mapping for this ISA IRQ? */
  11.985 +			if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
  11.986 +				break;
  11.987  
  11.988 -		mp_irqs[mp_irq_entries].mpc_type = MP_INTSRC;
  11.989 -		mp_irqs[mp_irq_entries].mpc_irqflag = 0;	/* Conforming */
  11.990 -		mp_irqs[mp_irq_entries].mpc_srcbus = MP_ISA_BUS;
  11.991 -		mp_irqs[mp_irq_entries].mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
  11.992 -		mp_irqs[mp_irq_entries].mpc_irqtype = mp_INT;
  11.993 -		mp_irqs[mp_irq_entries].mpc_srcbusirq = i;	   /* Identity mapped */
  11.994 -		mp_irqs[mp_irq_entries].mpc_dstirq = i;
  11.995 +			/* Do we already have a mapping for this IOAPIC pin */
  11.996 +			if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
  11.997 +				(irq->mpc_dstirq == i))
  11.998 +				break;
  11.999 +		}
 11.1000 +
 11.1001 +		if (idx != mp_irq_entries) {
 11.1002 +			printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
 11.1003 +			continue;			/* IRQ already used */
 11.1004 +		}
 11.1005 +
 11.1006 +		intsrc.mpc_irqtype = mp_INT;
 11.1007 +		intsrc.mpc_srcbusirq = i;		   /* Identity mapped */
 11.1008 +		intsrc.mpc_dstirq = i;
 11.1009  
 11.1010  		Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
 11.1011 -			"%d-%d\n", 
 11.1012 -			mp_irqs[mp_irq_entries].mpc_irqtype, 
 11.1013 -			mp_irqs[mp_irq_entries].mpc_irqflag & 3, 
 11.1014 -			(mp_irqs[mp_irq_entries].mpc_irqflag >> 2) & 3, 
 11.1015 -			mp_irqs[mp_irq_entries].mpc_srcbus, 
 11.1016 -			mp_irqs[mp_irq_entries].mpc_srcbusirq, 
 11.1017 -			mp_irqs[mp_irq_entries].mpc_dstapic, 
 11.1018 -			mp_irqs[mp_irq_entries].mpc_dstirq);
 11.1019 +			"%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3, 
 11.1020 +			(intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus, 
 11.1021 +			intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, 
 11.1022 +			intsrc.mpc_dstirq);
 11.1023  
 11.1024 +		mp_irqs[mp_irq_entries] = intsrc;
 11.1025  		if (++mp_irq_entries == MAX_IRQ_SOURCES)
 11.1026  			panic("Max # of irq sources exceeded!\n");
 11.1027  	}
 11.1028  }
 11.1029  
 11.1030 -#ifdef CONFIG_ACPI_PCI
 11.1031 -
 11.1032 -void __init mp_parse_prt (void)
 11.1033 +int mp_register_gsi (u32 gsi, int edge_level, int active_high_low)
 11.1034  {
 11.1035 -	struct acpi_prt_entry	*entry = NULL;
 11.1036  	int			ioapic = -1;
 11.1037  	int			ioapic_pin = 0;
 11.1038 -	int			irq = 0;
 11.1039  	int			idx, bit = 0;
 11.1040 -	int			edge_level = 0;
 11.1041 -	int			active_high_low = 0;
 11.1042 +
 11.1043 +#ifdef CONFIG_ACPI_BUS
 11.1044 +	/* Don't set up the ACPI SCI because it's already set up */
 11.1045 +	if (acpi_fadt.sci_int == gsi)
 11.1046 +		return gsi;
 11.1047 +#endif
 11.1048  
 11.1049 -	/*
 11.1050 -	 * Parsing through the PCI Interrupt Routing Table (PRT) and program
 11.1051 -	 * routing for all entries.
 11.1052 -	 */
 11.1053 -	list_for_each_entry(entry, &acpi_prt.entries, node) {
 11.1054 -		/* Need to get irq for dynamic entry */
 11.1055 -		if (entry->link.handle) {
 11.1056 -			irq = acpi_pci_link_get_irq(entry->link.handle, entry->link.index, &edge_level, &active_high_low);
 11.1057 -			if (!irq)
 11.1058 -				continue;
 11.1059 -		}
 11.1060 -		else {
 11.1061 -			/* Hardwired IRQ. Assume PCI standard settings */
 11.1062 -			irq = entry->link.index;
 11.1063 -			edge_level = 1;
 11.1064 -			active_high_low = 1;
 11.1065 -		}
 11.1066 +	ioapic = mp_find_ioapic(gsi);
 11.1067 +	if (ioapic < 0) {
 11.1068 +		printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
 11.1069 +		return gsi;
 11.1070 +	}
 11.1071  
 11.1072 -		/* Don't set up the ACPI SCI because it's already set up */
 11.1073 -                if (acpi_fadt.sci_int == irq) {
 11.1074 -                        entry->irq = irq; /*we still need to set entry's irq*/
 11.1075 -			continue;
 11.1076 -                }
 11.1077 -	
 11.1078 -		ioapic = mp_find_ioapic(irq);
 11.1079 -		if (ioapic < 0)
 11.1080 -			continue;
 11.1081 -		ioapic_pin = irq - mp_ioapic_routing[ioapic].irq_start;
 11.1082 +	ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
 11.1083 +
 11.1084 +	if (ioapic_renumber_irq)
 11.1085 +		gsi = ioapic_renumber_irq(ioapic, gsi);
 11.1086  
 11.1087 -		/* 
 11.1088 -		 * Avoid pin reprogramming.  PRTs typically include entries  
 11.1089 -		 * with redundant pin->irq mappings (but unique PCI devices);
 11.1090 -		 * we only only program the IOAPIC on the first.
 11.1091 -		 */
 11.1092 -		bit = ioapic_pin % 32;
 11.1093 -		idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
 11.1094 -		if (idx > 3) {
 11.1095 -			printk(KERN_ERR "Invalid reference to IOAPIC pin "
 11.1096 -				"%d-%d\n", mp_ioapic_routing[ioapic].apic_id, 
 11.1097 -				ioapic_pin);
 11.1098 -			continue;
 11.1099 -		}
 11.1100 -		if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
 11.1101 -			Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
 11.1102 -				mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
 11.1103 -			entry->irq = irq;
 11.1104 -			continue;
 11.1105 -		}
 11.1106 +	/* 
 11.1107 +	 * Avoid pin reprogramming.  PRTs typically include entries  
 11.1108 +	 * with redundant pin->gsi mappings (but unique PCI devices);
 11.1109 +	 * we only program the IOAPIC on the first.
 11.1110 +	 */
 11.1111 +	bit = ioapic_pin % 32;
 11.1112 +	idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
 11.1113 +	if (idx > 3) {
 11.1114 +		printk(KERN_ERR "Invalid reference to IOAPIC pin "
 11.1115 +			"%d-%d\n", mp_ioapic_routing[ioapic].apic_id, 
 11.1116 +			ioapic_pin);
 11.1117 +		return gsi;
 11.1118 +	}
 11.1119 +	if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
 11.1120 +		Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
 11.1121 +			mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
 11.1122 +		return gsi;
 11.1123 +	}
 11.1124  
 11.1125 -		mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
 11.1126 -
 11.1127 -		if (!io_apic_set_pci_routing(ioapic, ioapic_pin, irq, edge_level, active_high_low))
 11.1128 -			entry->irq = irq;
 11.1129 +	mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
 11.1130  
 11.1131 -		printk(KERN_DEBUG "%02x:%02x:%02x[%c] -> %d-%d -> IRQ %d\n",
 11.1132 -			entry->id.segment, entry->id.bus, 
 11.1133 -			entry->id.device, ('A' + entry->pin), 
 11.1134 -			mp_ioapic_routing[ioapic].apic_id, ioapic_pin, 
 11.1135 -			entry->irq);
 11.1136 -	}
 11.1137 -	
 11.1138 -	print_IO_APIC();
 11.1139 -
 11.1140 -	return;
 11.1141 +	io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
 11.1142 +		    edge_level == ACPI_EDGE_SENSITIVE ? 0 : 1,
 11.1143 +		    active_high_low == ACPI_ACTIVE_HIGH ? 0 : 1);
 11.1144 +	return gsi;
 11.1145  }
 11.1146  
 11.1147 -#endif /*CONFIG_ACPI_PCI*/
 11.1148 -
 11.1149 -#endif /*CONFIG_X86_IO_APIC && CONFIG_ACPI_INTERPRETER*/
 11.1150 -
 11.1151 -#endif /*CONFIG_ACPI*/
 11.1152 +#endif /*CONFIG_X86_IO_APIC && (CONFIG_ACPI_INTERPRETER || CONFIG_ACPI_BOOT)*/
 11.1153 +#endif /*CONFIG_ACPI_BOOT*/