direct-io.hg

changeset 5533:30f3fdaa5c1f

bitkeeper revision 1.1713.2.19 (42b8a34exK8-Y4Kw6G2q3tZNzQF4oQ)

More hyperprivop stuff
Signed-off-by: Dan Magenheimer <dan.magenheimer@hp.com>
author djm@kirby.fc.hp.com
date Tue Jun 21 23:31:26 2005 +0000 (2005-06-21)
parents e7981e581c6c
children 51d718bd11de
files xen/arch/ia64/hyperprivop.S xen/arch/ia64/privop.c
line diff
     1.1 --- a/xen/arch/ia64/hyperprivop.S	Tue Jun 21 20:10:51 2005 +0000
     1.2 +++ b/xen/arch/ia64/hyperprivop.S	Tue Jun 21 23:31:26 2005 +0000
     1.3 @@ -113,6 +113,14 @@ 1:	// when we get to here r20=~=interrup
     1.4  	cmp.eq p7,p6=XEN_HYPER_PTC_GA,r17
     1.5  (p7)	br.sptk.many hyper_ptc_ga;;
     1.6  
     1.7 +	// HYPERPRIVOP_ITC_D?
     1.8 +	cmp.eq p7,p6=XEN_HYPER_ITC_D,r17
     1.9 +(p7)	br.sptk.many hyper_itc_d;;
    1.10 +
    1.11 +	// HYPERPRIVOP_ITC_I?
    1.12 +	cmp.eq p7,p6=XEN_HYPER_ITC_I,r17
    1.13 +(p7)	br.sptk.many hyper_itc_i;;
    1.14 +
    1.15  	// if not one of the above, give up for now and do it the slow way
    1.16  	br.sptk.many dispatch_break_fault ;;
    1.17  
    1.18 @@ -374,14 +382,15 @@ GLOBAL_ENTRY(fast_break_reflect)
    1.19  // ensure that, if giving up, registers at entry to fast_hyperprivop unchanged
    1.20  ENTRY(hyper_rfi)
    1.21  	// if no interrupts pending, proceed
    1.22 +	mov r30=r0
    1.23  	cmp.eq p7,p0=r20,r0
    1.24  (p7)	br.sptk.many 1f
    1.25 -	// interrupts pending, if rfi'ing to interrupts on, go slow way
    1.26 +	;;
    1.27  	adds r20=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18 ;;
    1.28  	ld8 r21=[r20];;		// r21 = vcr.ipsr
    1.29  	extr.u r22=r21,IA64_PSR_I_BIT,1 ;;
    1.30 -	cmp.ne p7,p0=r22,r0 ;;
    1.31 -(p7)	br.spnt.many dispatch_break_fault ;;
    1.32 +	mov r30=r22	
    1.33 +	// r30 determines whether we might deliver an immediate extint
    1.34  1:
    1.35  	adds r20=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18 ;;
    1.36  	ld8 r21=[r20];;		// r21 = vcr.ipsr
    1.37 @@ -415,13 +424,17 @@ 1:
    1.38  (p7)	cmp.geu p0,p7=r22,r24 ;;	//    !(iip>=high)
    1.39  (p7)	br.sptk.many dispatch_break_fault ;;
    1.40  
    1.41 -	// OK now, let's do an rfi.
    1.42 +1:	// OK now, let's do an rfi.
    1.43  #ifdef FAST_HYPERPRIVOP_CNT
    1.44  	movl r20=fast_hyperpriv_cnt+(8*XEN_HYPER_RFI);;
    1.45  	ld8 r23=[r20];;
    1.46  	adds r23=1,r23;;
    1.47  	st8 [r20]=r23;;
    1.48  #endif
    1.49 +	cmp.ne p6,p0=r30,r0
    1.50 +(p6)	br.cond.sptk.many check_extint;
    1.51 +	;;
    1.52 +just_do_rfi:
    1.53  	// r18=&vpsr.i|vpsr.ic, r21==vpsr, r22=vcr.iip
    1.54  	mov cr.iip=r22;;
    1.55  	adds r20=XSI_INCOMPL_REG_OFS-XSI_PSR_IC_OFS,r18 ;;
    1.56 @@ -434,11 +447,12 @@ 1:
    1.57  	dep r21=-1,r21,IA64_PSR_CPL1_BIT,1 ;;
    1.58  	// vpsr.i = vcr.ipsr.i; vpsr.ic = vcr.ipsr.ic
    1.59  	mov r19=r0 ;;
    1.60 -	extr.u r22=r21,IA64_PSR_I_BIT,1 ;;
    1.61 -	cmp.ne p7,p6=r22,r0 ;;
    1.62 +	extr.u r23=r21,IA64_PSR_I_BIT,1 ;;
    1.63 +	cmp.ne p7,p6=r23,r0 ;;
    1.64 +	// not done yet
    1.65  (p7)	dep r19=-1,r19,32,1
    1.66 -	extr.u r22=r21,IA64_PSR_IC_BIT,1 ;;
    1.67 -	cmp.ne p7,p6=r22,r0 ;;
    1.68 +	extr.u r23=r21,IA64_PSR_IC_BIT,1 ;;
    1.69 +	cmp.ne p7,p6=r23,r0 ;;
    1.70  (p7)	dep r19=-1,r19,0,1 ;;
    1.71  	st8 [r18]=r19 ;;
    1.72  	// force on psr.ic, i, dt, rt, it, bn
    1.73 @@ -452,6 +466,80 @@ 1:
    1.74  	rfi
    1.75  	;;
    1.76  
    1.77 +check_extint:
    1.78 +	br.sptk.many dispatch_break_fault ;;
    1.79 +
    1.80 +	// r18=&vpsr.i|vpsr.ic, r21==vpsr, r22=vcr.iip
    1.81 +	mov r30=IA64_KR(CURRENT);;
    1.82 +	adds r24=IA64_VCPU_INSVC3_OFFSET,r30;;
    1.83 +	mov r25=192
    1.84 +	adds r22=IA64_VCPU_IRR3_OFFSET,r30;;
    1.85 +	ld8 r23=[r22];;
    1.86 +	cmp.eq p6,p0=r23,r0;;
    1.87 +(p6)	adds r22=-8,r22;;
    1.88 +(p6)	adds r24=-8,r24;;
    1.89 +(p6)	adds r25=-64,r25;;
    1.90 +(p6)	ld8 r23=[r22];;
    1.91 +(p6)	cmp.eq p6,p0=r23,r0;;
    1.92 +(p6)	adds r22=-8,r22;;
    1.93 +(p6)	adds r24=-8,r24;;
    1.94 +(p6)	adds r25=-64,r25;;
    1.95 +(p6)	ld8 r23=[r22];;
    1.96 +(p6)	cmp.eq p6,p0=r23,r0;;
    1.97 +(p6)	adds r22=-8,r22;;
    1.98 +(p6)	adds r24=-8,r24;;
    1.99 +(p6)	adds r25=-64,r25;;
   1.100 +(p6)	ld8 r23=[r22];;
   1.101 +(p6)	cmp.eq p6,p0=r23,r0;;
   1.102 +	cmp.eq p6,p0=r23,r0
   1.103 +(p6)	br.cond.sptk.many 1f;	// this is actually an error
   1.104 +	// r22 points to non-zero element of irr, r23 has value
   1.105 +	// r24 points to corr element of insvc, r25 has elt*64
   1.106 +	ld8 r26=[r24];;
   1.107 +	cmp.geu p6,p0=r26,r23
   1.108 +(p6)	br.cond.spnt.many 1f;
   1.109 +	// not masked by insvc, get vector number
   1.110 +	shr.u r26=r23,1;;
   1.111 +	or r26=r23,r26;;
   1.112 +	shr.u r27=r26,2;;
   1.113 +	or r26=r26,r27;;
   1.114 +	shr.u r27=r26,4;;
   1.115 +	or r26=r26,r27;;
   1.116 +	shr.u r27=r26,8;;
   1.117 +	or r26=r26,r27;;
   1.118 +	shr.u r27=r26,16;;
   1.119 +	or r26=r26,r27;;
   1.120 +	shr.u r27=r26,32;;
   1.121 +	or r26=r26,r27;;
   1.122 +	andcm r26=0xffffffffffffffff,r26;;
   1.123 +	popcnt r26=r26;;
   1.124 +	sub r26=63,r26;;
   1.125 +	// r26 now contains the bit index (mod 64)
   1.126 +	mov r27=1;;
   1.127 +	shl r27=r27,r26;;
   1.128 +	// r27 now contains the (within the proper word) bit mask 
   1.129 +	add r26=r25,r26
   1.130 +	// r26 now contains the vector [0..255]
   1.131 +	adds r20=XSI_TPR_OFS-XSI_PSR_IC_OFS,r18 ;;
   1.132 +	ld8 r20=[r20] ;;
   1.133 +	extr.u r28=r20,16,1
   1.134 +	extr.u r29=r20,4,4 ;;
   1.135 +	cmp.ne p6,p0=r28,r0	// if tpr.mmi is set, return SPURIOUS
   1.136 +(p6)	br.cond.sptk.many 1f;
   1.137 +	shl r29=r29,4;;
   1.138 +	adds r29=15,r29;;
   1.139 +	cmp.ge p6,p0=r29,r26
   1.140 +(p6)	br.cond.sptk.many 1f;
   1.141 +	// OK, have an unmasked vector to process/return
   1.142 +	ld8 r25=[r24];;
   1.143 +	or r25=r25,r27;;
   1.144 +	st8 [r24]=r25;;
   1.145 +	ld8 r25=[r22];;
   1.146 +	andcm r25=r25,r27;;
   1.147 +	st8 [r22]=r25;;
   1.148 +	mov r8=r26;;
   1.149 +	// not done yet
   1.150 +
   1.151  ENTRY(hyper_cover)
   1.152  #ifdef FAST_HYPERPRIVOP_CNT
   1.153  	movl r20=fast_hyperpriv_cnt+(8*XEN_HYPER_COVER);;
   1.154 @@ -917,3 +1005,12 @@ END(hyper_set_rr)
   1.155  ENTRY(hyper_ptc_ga)
   1.156  	br.spnt.many dispatch_break_fault ;;
   1.157  END(hyper_ptc_ga)
   1.158 +
   1.159 +ENTRY(hyper_itc_d)
   1.160 +	br.spnt.many dispatch_break_fault ;;
   1.161 +END(hyper_itc_d)
   1.162 +
   1.163 +ENTRY(hyper_itc_i)
   1.164 +	br.spnt.many dispatch_break_fault ;;
   1.165 +END(hyper_itc_i)
   1.166 +
     2.1 --- a/xen/arch/ia64/privop.c	Tue Jun 21 20:10:51 2005 +0000
     2.2 +++ b/xen/arch/ia64/privop.c	Tue Jun 21 23:31:26 2005 +0000
     2.3 @@ -205,8 +205,7 @@ IA64FAULT priv_itc_d(VCPU *vcpu, INST64 
     2.4  		return(IA64_ILLOP_FAULT);
     2.5  	if ((fault = vcpu_get_ifa(vcpu,&ifa)) != IA64_NO_FAULT)
     2.6  		return(IA64_ILLOP_FAULT);
     2.7 -	if (!inst.inst) pte = vcpu_get_tmp(vcpu,0);
     2.8 -	else pte = vcpu_get_gr(vcpu,inst.M41.r2);
     2.9 +	pte = vcpu_get_gr(vcpu,inst.M41.r2);
    2.10  
    2.11  	return (vcpu_itc_d(vcpu,pte,itir,ifa));
    2.12  }
    2.13 @@ -220,8 +219,7 @@ IA64FAULT priv_itc_i(VCPU *vcpu, INST64 
    2.14  		return(IA64_ILLOP_FAULT);
    2.15  	if ((fault = vcpu_get_ifa(vcpu,&ifa)) != IA64_NO_FAULT)
    2.16  		return(IA64_ILLOP_FAULT);
    2.17 -	if (!inst.inst) pte = vcpu_get_tmp(vcpu,0);
    2.18 -	else pte = vcpu_get_gr(vcpu,inst.M41.r2);
    2.19 +	pte = vcpu_get_gr(vcpu,inst.M41.r2);
    2.20  
    2.21  	return (vcpu_itc_i(vcpu,pte,itir,ifa));
    2.22  }
    2.23 @@ -800,12 +798,14 @@ ia64_hyperprivop(unsigned long iim, REGS
    2.24  		(void)vcpu_cover(v);
    2.25  		return 1;
    2.26  	    case HYPERPRIVOP_ITC_D:
    2.27 -		inst.inst = 0;
    2.28 -		(void)priv_itc_d(v,inst);
    2.29 +		(void)vcpu_get_itir(v,&itir);
    2.30 +		(void)vcpu_get_ifa(v,&ifa);
    2.31 +		(void)vcpu_itc_d(v,regs->r8,itir,ifa);
    2.32  		return 1;
    2.33  	    case HYPERPRIVOP_ITC_I:
    2.34 -		inst.inst = 0;
    2.35 -		(void)priv_itc_i(v,inst);
    2.36 +		(void)vcpu_get_itir(v,&itir);
    2.37 +		(void)vcpu_get_ifa(v,&ifa);
    2.38 +		(void)vcpu_itc_i(v,regs->r8,itir,ifa);
    2.39  		return 1;
    2.40  	    case HYPERPRIVOP_SSM_I:
    2.41  		(void)vcpu_set_psr_i(v);