direct-io.hg

changeset 11590:047669f57e5c

[HVM] A few cleanups to i8259.c -- in particular change
ELCR semantics (should not be modified by PIC reset).

This effectively removes Steve Smith's changeset
11586:08a582a98471da30fb86bca620495f3d91d55800
but the real bug here is not that the ELCR was reset to
zero, but that it was touched at all.

Our BIOS code should set the ELCR correctly (level-triggered)
for PCI IRQs.

Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Sat Sep 23 12:39:18 2006 +0100 (2006-09-23)
parents fb2751668a4d
children dfbadf4696fd
files xen/arch/x86/hvm/i8259.c
line diff
     1.1 --- a/xen/arch/x86/hvm/i8259.c	Fri Sep 22 20:20:57 2006 +0100
     1.2 +++ b/xen/arch/x86/hvm/i8259.c	Sat Sep 23 12:39:18 2006 +0100
     1.3 @@ -35,12 +35,11 @@
     1.4  #include <asm/current.h>
     1.5  
     1.6  /* set irq level. If an edge is detected, then the IRR is set to 1 */
     1.7 -/* Caller must hold vpic lock */
     1.8  static inline void pic_set_irq1(PicState *s, int irq, int level)
     1.9  {
    1.10      int mask;
    1.11  
    1.12 -    BUG_ON(!spin_is_locked(&s->pics_state->lock));
    1.13 +    ASSERT(spin_is_locked(&s->pics_state->lock));
    1.14  
    1.15      mask = 1 << irq;
    1.16      if (s->elcr & mask) {
    1.17 @@ -55,9 +54,8 @@ static inline void pic_set_irq1(PicState
    1.18      } else {
    1.19          /* edge triggered */
    1.20          if (level) {
    1.21 -            if ((s->last_irr & mask) == 0) {
    1.22 +            if ((s->last_irr & mask) == 0)
    1.23                  s->irr |= mask;
    1.24 -            }
    1.25              s->last_irr |= mask;
    1.26          } else {
    1.27              s->last_irr &= ~mask;
    1.28 @@ -67,12 +65,11 @@ static inline void pic_set_irq1(PicState
    1.29  
    1.30  /* return the highest priority found in mask (highest = smallest
    1.31     number). Return 8 if no irq */
    1.32 -/* Caller must hold vpic lock */
    1.33  static inline int get_priority(PicState *s, int mask)
    1.34  {
    1.35      int priority;
    1.36  
    1.37 -    BUG_ON(!spin_is_locked(&s->pics_state->lock));
    1.38 +    ASSERT(spin_is_locked(&s->pics_state->lock));
    1.39  
    1.40      if (mask == 0)
    1.41          return 8;
    1.42 @@ -83,12 +80,11 @@ static inline int get_priority(PicState 
    1.43  }
    1.44  
    1.45  /* return the pic wanted interrupt. return -1 if none */
    1.46 -/* Caller must hold vpic lock */
    1.47  static int pic_get_irq(PicState *s)
    1.48  {
    1.49      int mask, cur_priority, priority;
    1.50  
    1.51 -    BUG_ON(!spin_is_locked(&s->pics_state->lock));
    1.52 +    ASSERT(spin_is_locked(&s->pics_state->lock));
    1.53  
    1.54      mask = s->irr & ~s->imr;
    1.55      priority = get_priority(s, mask);
    1.56 @@ -112,12 +108,11 @@ static int pic_get_irq(PicState *s)
    1.57  /* raise irq to CPU if necessary. must be called every time the active
    1.58     irq may change */
    1.59  /* XXX: should not export it, but it is needed for an APIC kludge */
    1.60 -/* Caller must hold vpic lock */
    1.61  void pic_update_irq(struct hvm_virpic *s)
    1.62  {
    1.63      int irq2, irq;
    1.64  
    1.65 -    BUG_ON(!spin_is_locked(&s->lock));
    1.66 +    ASSERT(spin_is_locked(&s->lock));
    1.67  
    1.68      /* first look at slave pic */
    1.69      irq2 = pic_get_irq(&s->pics[1]);
    1.70 @@ -179,10 +174,9 @@ void pic_set_irq(struct hvm_virpic *isa_
    1.71  }
    1.72  
    1.73  /* acknowledge interrupt 'irq' */
    1.74 -/* Caller must hold vpic lock */
    1.75  static inline void pic_intack(PicState *s, int irq)
    1.76  {
    1.77 -    BUG_ON(!spin_is_locked(&s->pics_state->lock));
    1.78 +    ASSERT(spin_is_locked(&s->pics_state->lock));
    1.79  
    1.80      if (s->auto_eoi) {
    1.81          if (s->rotate_on_auto_eoi)
    1.82 @@ -219,7 +213,6 @@ int pic_read_irq(struct hvm_virpic *s)
    1.83          }
    1.84      } else {
    1.85          /* spurious IRQ on host controller */
    1.86 -        printk("spurious IRQ irq got=%d\n",irq);
    1.87          irq = 7;
    1.88          intno = s->pics[0].irq_base + irq;
    1.89      }
    1.90 @@ -229,12 +222,11 @@ int pic_read_irq(struct hvm_virpic *s)
    1.91      return intno;
    1.92  }
    1.93  
    1.94 -/* Caller must hold vpic lock */
    1.95  static void update_shared_irr(struct hvm_virpic *s, PicState *c)
    1.96  {
    1.97      uint8_t *pl, *pe;
    1.98  
    1.99 -    BUG_ON(!spin_is_locked(&s->lock));
   1.100 +    ASSERT(spin_is_locked(&s->lock));
   1.101  
   1.102      get_sp(current->domain)->sp_global.pic_elcr = 
   1.103          s->pics[0].elcr | ((u16)s->pics[1].elcr << 8);
   1.104 @@ -250,12 +242,11 @@ static void update_shared_irr(struct hvm
   1.105      }
   1.106  }
   1.107  
   1.108 -/* Caller must hold vpic lock */
   1.109  static void pic_reset(void *opaque)
   1.110  {
   1.111      PicState *s = opaque;
   1.112  
   1.113 -    BUG_ON(!spin_is_locked(&s->pics_state->lock));
   1.114 +    ASSERT(spin_is_locked(&s->pics_state->lock));
   1.115  
   1.116      s->last_irr = 0;
   1.117      s->irr = 0;
   1.118 @@ -271,19 +262,15 @@ static void pic_reset(void *opaque)
   1.119      s->rotate_on_auto_eoi = 0;
   1.120      s->special_fully_nested_mode = 0;
   1.121      s->init4 = 0;
   1.122 -
   1.123 -    /* Initialise to level triggered mode, since Linux assumes that in
   1.124 -       a few places and it doesn't appear to break anything. */
   1.125 -    s->elcr = 0xff & s->elcr_mask;
   1.126 +    /* Note: ELCR is not reset */
   1.127  }
   1.128  
   1.129 -/* Caller must hold vpic lock */
   1.130  static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
   1.131  {
   1.132      PicState *s = opaque;
   1.133      int priority, cmd, irq;
   1.134  
   1.135 -    BUG_ON(!spin_is_locked(&s->pics_state->lock));
   1.136 +    ASSERT(spin_is_locked(&s->pics_state->lock));
   1.137  
   1.138      addr &= 1;
   1.139      if (addr == 0) {
   1.140 @@ -371,12 +358,11 @@ static void pic_ioport_write(void *opaqu
   1.141      }
   1.142  }
   1.143  
   1.144 -/* Caller must hold vpic lock */
   1.145  static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
   1.146  {
   1.147      int ret;
   1.148  
   1.149 -    BUG_ON(!spin_is_locked(&s->pics_state->lock));
   1.150 +    ASSERT(spin_is_locked(&s->pics_state->lock));
   1.151  
   1.152      ret = pic_get_irq(s);
   1.153      if (ret >= 0) {
   1.154 @@ -396,14 +382,13 @@ static uint32_t pic_poll_read (PicState 
   1.155      return ret;
   1.156  }
   1.157  
   1.158 -/* Caller must hold vpic lock */
   1.159  static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
   1.160  {
   1.161      PicState *s = opaque;
   1.162      unsigned int addr;
   1.163      int ret;
   1.164  
   1.165 -    BUG_ON(!spin_is_locked(&s->pics_state->lock));
   1.166 +    ASSERT(spin_is_locked(&s->pics_state->lock));
   1.167  
   1.168      addr = addr1;
   1.169      addr &= 1;
   1.170 @@ -442,11 +427,10 @@ uint32_t pic_intack_read(struct hvm_virp
   1.171  }
   1.172  
   1.173  static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
   1.174 -/* Caller must hold vpic lock */
   1.175  {
   1.176      PicState *s = opaque;
   1.177  
   1.178 -    BUG_ON(!spin_is_locked(&s->pics_state->lock));
   1.179 +    ASSERT(spin_is_locked(&s->pics_state->lock));
   1.180  
   1.181      s->elcr = val & s->elcr_mask;
   1.182  }
   1.183 @@ -458,10 +442,9 @@ static uint32_t elcr_ioport_read(void *o
   1.184  }
   1.185  
   1.186  /* XXX: add generic master/slave system */
   1.187 -/* Caller must hold vpic lock */
   1.188  static void pic_init1(int io_addr, int elcr_addr, PicState *s)
   1.189  {
   1.190 -    BUG_ON(!spin_is_locked(&s->pics_state->lock));
   1.191 +    ASSERT(spin_is_locked(&s->pics_state->lock));
   1.192  
   1.193      pic_reset(s);
   1.194  }