direct-io.hg

changeset 813:0247e417838a

bitkeeper revision 1.498.1.1 (3f8707eaKlkrjYr25jktT_f0NAFf1A)

New dom0 op to read/write msr's from privileged domains, mainly so you can use perfomance counters.
author iap10@labyrinth.cl.cam.ac.uk
date Fri Oct 10 19:26:34 2003 +0000 (2003-10-10)
parents 79012ba592c9
children b487e696e814
files .rootkeys xen/common/dom0_ops.c xen/common/keyhandler.c xen/include/hypervisor-ifs/dom0_ops.h xenolinux-2.4.22-sparse/include/asm-xeno/msr.h xenolinux-2.4.22-sparse/mkbuildtree
line diff
     1.1 --- a/.rootkeys	Thu Oct 09 09:33:16 2003 +0000
     1.2 +++ b/.rootkeys	Fri Oct 10 19:26:34 2003 +0000
     1.3 @@ -616,6 +616,7 @@ 3e5a4e677VBavzM1UZIEcH1B-RlXMA xenolinux
     1.4  3e5a4e673p7PEOyHFm3nHkYX6HQYBg xenolinux-2.4.22-sparse/include/asm-xeno/irq.h
     1.5  3ead095db_LRUXnxaqs0dA1DWhPoQQ xenolinux-2.4.22-sparse/include/asm-xeno/keyboard.h
     1.6  3e5a4e678ddsQOpbSiRdy1GRcDc9WA xenolinux-2.4.22-sparse/include/asm-xeno/mmu_context.h
     1.7 +3f8707e7ZmZ6TxyX0ZUEfvhA2Pb_xQ xenolinux-2.4.22-sparse/include/asm-xeno/msr.h
     1.8  3e7270deQqtGPSnFxcW4AvJZuTUWfg xenolinux-2.4.22-sparse/include/asm-xeno/multicall.h
     1.9  3e5a4e67mnQfh-R8KcQCaVo2Oho6yg xenolinux-2.4.22-sparse/include/asm-xeno/page.h
    1.10  3e5a4e67uTYU5oEnIDjxuaez8njjqg xenolinux-2.4.22-sparse/include/asm-xeno/pgalloc.h
     2.1 --- a/xen/common/dom0_ops.c	Thu Oct 09 09:33:16 2003 +0000
     2.2 +++ b/xen/common/dom0_ops.c	Fri Oct 10 19:26:34 2003 +0000
     2.3 @@ -14,6 +14,7 @@
     2.4  #include <xeno/sched.h>
     2.5  #include <xeno/event.h>
     2.6  #include <asm/domain_page.h>
     2.7 +#include <asm/msr.h>
     2.8  
     2.9  extern unsigned int alloc_new_dom_mem(struct task_struct *, unsigned int);
    2.10  
    2.11 @@ -61,6 +62,24 @@ static void build_page_list(struct task_
    2.12  
    2.13      unmap_domain_mem(list);
    2.14  }
    2.15 +
    2.16 +static int msr_cpu_mask;
    2.17 +static unsigned long msr_addr;
    2.18 +static unsigned long msr_lo;
    2.19 +static unsigned long msr_hi;
    2.20 +
    2.21 +static void write_msr_for(void *unused)
    2.22 +{
    2.23 +    if (((1 << current->processor) & msr_cpu_mask))
    2.24 +        wrmsr(msr_addr, msr_lo, msr_hi);
    2.25 +}
    2.26 +
    2.27 +static void read_msr_for(void *unused)
    2.28 +{
    2.29 +    if (((1 << current->processor) & msr_cpu_mask))
    2.30 +	rdmsr(msr_addr, msr_lo, msr_hi);
    2.31 +}
    2.32 +
    2.33      
    2.34  long do_dom0_op(dom0_op_t *u_dom0_op)
    2.35  {
    2.36 @@ -262,6 +281,33 @@ long do_dom0_op(dom0_op_t *u_dom0_op)
    2.37      }
    2.38      break;
    2.39  
    2.40 +    case DOM0_MSR:
    2.41 +    {
    2.42 +      if (op.u.msr.write)
    2.43 +	{
    2.44 +	  msr_cpu_mask = op.u.msr.cpu_mask;
    2.45 +	  msr_addr = op.u.msr.msr;
    2.46 +	  msr_lo = op.u.msr.in1;
    2.47 +	  msr_hi = op.u.msr.in2;
    2.48 +	  smp_call_function(write_msr_for, NULL, 1, 1);
    2.49 +	  write_msr_for(NULL);
    2.50 +	}
    2.51 +      else
    2.52 +	{
    2.53 +          msr_cpu_mask = op.u.msr.cpu_mask;
    2.54 +          msr_addr = op.u.msr.msr;
    2.55 +	  smp_call_function(read_msr_for, NULL, 1, 1);
    2.56 +	  read_msr_for(NULL);
    2.57 +
    2.58 +          op.u.msr.out1 = msr_lo;
    2.59 +          op.u.msr.out2 = msr_hi;
    2.60 +	  copy_to_user(u_dom0_op, &op, sizeof(op));
    2.61 +	}
    2.62 +      ret = 0;
    2.63 +    }
    2.64 +    break;
    2.65 +
    2.66 +
    2.67      default:
    2.68          ret = -ENOSYS;
    2.69  
     3.1 --- a/xen/common/keyhandler.c	Thu Oct 09 09:33:16 2003 +0000
     3.2 +++ b/xen/common/keyhandler.c	Fri Oct 10 19:26:34 2003 +0000
     3.3 @@ -128,6 +128,26 @@ void do_task_queues(u_char key, void *de
     3.4      read_unlock_irqrestore(&tasklist_lock, flags); 
     3.5  }
     3.6  
     3.7 +void cpu_counters(u_char key, void *dev_id, struct pt_regs *regs)
     3.8 +{
     3.9 +    printk("CPU performance counters for CPU %d (current):\n",
    3.10 +        smp_processor_id());
    3.11 +    {
    3.12 +        unsigned int one1,one2,zero1,zero2;
    3.13 +        rdmsr(MSR_P6_PERFCTR0, zero1, zero2);
    3.14 +        rdmsr(MSR_P6_PERFCTR1, one1, one2);
    3.15 +        printk("CPU%02d counter0=0x%02x:%08x  counter1=0x%02x:%08x\n",
    3.16 +           smp_processor_id(), zero2,zero1,one2,one1 );
    3.17 +    }
    3.18 +}
    3.19 +
    3.20 +void cpu_counters_reset(u_char key, void *dev_id, struct pt_regs *regs)
    3.21 +{
    3.22 +    printk("Reset CPU performance counters for CPU %d (current):\n",
    3.23 +	smp_processor_id());
    3.24 +    wrmsr(MSR_P6_PERFCTR0,0,0);
    3.25 +    wrmsr(MSR_P6_PERFCTR1,0,0);
    3.26 +}
    3.27  
    3.28  extern void perfc_printall (u_char key, void *dev_id, struct pt_regs *regs);
    3.29  extern void perfc_reset (u_char key, void *dev_id, struct pt_regs *regs);
    3.30 @@ -155,6 +175,7 @@ void initialize_keytable()
    3.31      add_key_handler('r', dump_runq,      "dump run queues");
    3.32      add_key_handler('B', kill_dom0,      "reboot machine gracefully"); 
    3.33      add_key_handler('R', halt_machine,   "reboot machine ungracefully"); 
    3.34 -    
    3.35 +    add_key_handler('c', cpu_counters,   "CPU performance counters");
    3.36 +    add_key_handler('C', cpu_counters_reset,"reset CPU perfomance counters");    
    3.37      return; 
    3.38  }
     4.1 --- a/xen/include/hypervisor-ifs/dom0_ops.h	Thu Oct 09 09:33:16 2003 +0000
     4.2 +++ b/xen/include/hypervisor-ifs/dom0_ops.h	Fri Oct 10 19:26:34 2003 +0000
     4.3 @@ -20,6 +20,7 @@
     4.4  #define DOM0_GETDOMAININFO 12
     4.5  #define DOM0_BUILDDOMAIN   13
     4.6  #define DOM0_IOPL          14
     4.7 +#define DOM0_MSR           15
     4.8  
     4.9  #define MAX_CMD_LEN       256
    4.10  #define MAX_DOMAIN_NAME    16
    4.11 @@ -97,6 +98,16 @@ typedef struct dom0_iopl_st
    4.12      unsigned int iopl;
    4.13  } dom0_iopl_t;
    4.14  
    4.15 +typedef struct dom0_msr_st
    4.16 +{
    4.17 +    /* IN variables. */
    4.18 +    int write, cpu_mask, msr;
    4.19 +    unsigned int in1, in2;
    4.20 +    /* OUT variables. */
    4.21 +    unsigned int out1, out2;
    4.22 +
    4.23 +} dom0_msr_t;
    4.24 +
    4.25  typedef struct dom0_op_st
    4.26  {
    4.27      unsigned long cmd;
    4.28 @@ -110,6 +121,7 @@ typedef struct dom0_op_st
    4.29          dom_meminfo_t meminfo;
    4.30          dom0_getdominfo_t getdominfo;
    4.31          dom0_iopl_t iopl;
    4.32 +	dom0_msr_t msr;
    4.33      }
    4.34      u;
    4.35  } dom0_op_t;
     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/xenolinux-2.4.22-sparse/include/asm-xeno/msr.h	Fri Oct 10 19:26:34 2003 +0000
     5.3 @@ -0,0 +1,138 @@
     5.4 +#ifndef __ASM_MSR_H
     5.5 +#define __ASM_MSR_H
     5.6 +
     5.7 +/*
     5.8 + * Access to machine-specific registers (available on 586 and better only)
     5.9 + * Note: the rd* operations modify the parameters directly (without using
    5.10 + * pointer indirection), this allows gcc to optimize better
    5.11 + */
    5.12 +
    5.13 +#define rdmsr(msr,val1,val2) \
    5.14 +{ \
    5.15 +  dom0_op_t op; \
    5.16 +  op.cmd = DOM0_MSR; \
    5.17 +  op.u.msr.write = 0; \
    5.18 +  op.u.msr.msr = msr; \
    5.19 +  op.u.msr.cpu_mask = (1 << current->processor); \
    5.20 +  HYPERVISOR_dom0_op(&op); \
    5.21 +  val1 = op.u.msr.out1; \
    5.22 +  val2 = op.u.msr.out2; \
    5.23 +}     
    5.24 +
    5.25 +#define wrmsr(msr,val1,val2) \
    5.26 +{ \
    5.27 +  dom0_op_t op; \
    5.28 +  op.cmd = DOM0_MSR; \
    5.29 +  op.u.msr.write = 1; \
    5.30 +  op.u.msr.cpu_mask = (1 << current->processor); \
    5.31 +  op.u.msr.msr = msr; \
    5.32 +  op.u.msr.in1 = val1; \
    5.33 +  op.u.msr.in2 = val2; \
    5.34 +  HYPERVISOR_dom0_op(&op); \
    5.35 +}     
    5.36 +
    5.37 +#define rdtsc(low,high) \
    5.38 +     __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
    5.39 +
    5.40 +#define rdtscl(low) \
    5.41 +     __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
    5.42 +
    5.43 +#define rdtscll(val) \
    5.44 +     __asm__ __volatile__("rdtsc" : "=A" (val))
    5.45 +
    5.46 +#define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
    5.47 +
    5.48 +#define rdpmc(counter,low,high) \
    5.49 +     __asm__ __volatile__("rdpmc" \
    5.50 +			  : "=a" (low), "=d" (high) \
    5.51 +			  : "c" (counter))
    5.52 +
    5.53 +/* symbolic names for some interesting MSRs */
    5.54 +/* Intel defined MSRs. */
    5.55 +#define MSR_IA32_P5_MC_ADDR		0
    5.56 +#define MSR_IA32_P5_MC_TYPE		1
    5.57 +#define MSR_IA32_PLATFORM_ID		0x17
    5.58 +#define MSR_IA32_EBL_CR_POWERON		0x2a
    5.59 +
    5.60 +#define MSR_IA32_APICBASE		0x1b
    5.61 +#define MSR_IA32_APICBASE_BSP		(1<<8)
    5.62 +#define MSR_IA32_APICBASE_ENABLE	(1<<11)
    5.63 +#define MSR_IA32_APICBASE_BASE		(0xfffff<<12)
    5.64 +
    5.65 +#define MSR_IA32_UCODE_WRITE		0x79
    5.66 +#define MSR_IA32_UCODE_REV		0x8b
    5.67 +
    5.68 +#define MSR_IA32_BBL_CR_CTL		0x119
    5.69 +
    5.70 +#define MSR_IA32_MCG_CAP		0x179
    5.71 +#define MSR_IA32_MCG_STATUS		0x17a
    5.72 +#define MSR_IA32_MCG_CTL		0x17b
    5.73 +
    5.74 +#define MSR_IA32_THERM_CONTROL		0x19a
    5.75 +#define MSR_IA32_THERM_INTERRUPT	0x19b
    5.76 +#define MSR_IA32_THERM_STATUS		0x19c
    5.77 +#define MSR_IA32_MISC_ENABLE		0x1a0
    5.78 +
    5.79 +#define MSR_IA32_DEBUGCTLMSR		0x1d9
    5.80 +#define MSR_IA32_LASTBRANCHFROMIP	0x1db
    5.81 +#define MSR_IA32_LASTBRANCHTOIP		0x1dc
    5.82 +#define MSR_IA32_LASTINTFROMIP		0x1dd
    5.83 +#define MSR_IA32_LASTINTTOIP		0x1de
    5.84 +
    5.85 +#define MSR_IA32_MC0_CTL		0x400
    5.86 +#define MSR_IA32_MC0_STATUS		0x401
    5.87 +#define MSR_IA32_MC0_ADDR		0x402
    5.88 +#define MSR_IA32_MC0_MISC		0x403
    5.89 +
    5.90 +#define MSR_P6_PERFCTR0			0xc1
    5.91 +#define MSR_P6_PERFCTR1			0xc2
    5.92 +#define MSR_P6_EVNTSEL0			0x186
    5.93 +#define MSR_P6_EVNTSEL1			0x187
    5.94 +
    5.95 +#define MSR_IA32_PERF_STATUS		0x198
    5.96 +#define MSR_IA32_PERF_CTL		0x199
    5.97 +
    5.98 +/* AMD Defined MSRs */
    5.99 +#define MSR_K6_EFER			0xC0000080
   5.100 +#define MSR_K6_STAR			0xC0000081
   5.101 +#define MSR_K6_WHCR			0xC0000082
   5.102 +#define MSR_K6_UWCCR			0xC0000085
   5.103 +#define MSR_K6_EPMR			0xC0000086
   5.104 +#define MSR_K6_PSOR			0xC0000087
   5.105 +#define MSR_K6_PFIR			0xC0000088
   5.106 +
   5.107 +#define MSR_K7_EVNTSEL0			0xC0010000
   5.108 +#define MSR_K7_PERFCTR0			0xC0010004
   5.109 +#define MSR_K7_HWCR			0xC0010015
   5.110 +#define MSR_K7_CLK_CTL			0xC001001b
   5.111 +#define MSR_K7_FID_VID_CTL		0xC0010041
   5.112 +#define MSR_K7_VID_STATUS		0xC0010042
   5.113 +
   5.114 +/* Centaur-Hauls/IDT defined MSRs. */
   5.115 +#define MSR_IDT_FCR1			0x107
   5.116 +#define MSR_IDT_FCR2			0x108
   5.117 +#define MSR_IDT_FCR3			0x109
   5.118 +#define MSR_IDT_FCR4			0x10a
   5.119 +
   5.120 +#define MSR_IDT_MCR0			0x110
   5.121 +#define MSR_IDT_MCR1			0x111
   5.122 +#define MSR_IDT_MCR2			0x112
   5.123 +#define MSR_IDT_MCR3			0x113
   5.124 +#define MSR_IDT_MCR4			0x114
   5.125 +#define MSR_IDT_MCR5			0x115
   5.126 +#define MSR_IDT_MCR6			0x116
   5.127 +#define MSR_IDT_MCR7			0x117
   5.128 +#define MSR_IDT_MCR_CTRL		0x120
   5.129 +
   5.130 +/* VIA Cyrix defined MSRs*/
   5.131 +#define MSR_VIA_FCR			0x1107
   5.132 +#define MSR_VIA_LONGHAUL		0x110a
   5.133 +#define MSR_VIA_BCR2			0x1147
   5.134 +
   5.135 +/* Transmeta defined MSRs */
   5.136 +#define MSR_TMTA_LONGRUN_CTRL		0x80868010
   5.137 +#define MSR_TMTA_LONGRUN_FLAGS		0x80868011
   5.138 +#define MSR_TMTA_LRTI_READOUT		0x80868018
   5.139 +#define MSR_TMTA_LRTI_VOLT_MHZ		0x8086801a
   5.140 +
   5.141 +#endif /* __ASM_MSR_H */
     6.1 --- a/xenolinux-2.4.22-sparse/mkbuildtree	Thu Oct 09 09:33:16 2003 +0000
     6.2 +++ b/xenolinux-2.4.22-sparse/mkbuildtree	Fri Oct 10 19:26:34 2003 +0000
     6.3 @@ -130,7 +130,6 @@ ln -sf ../asm-i386/mmx.h
     6.4  ln -sf ../asm-i386/module.h 
     6.5  ln -sf ../asm-i386/mpspec.h 
     6.6  ln -sf ../asm-i386/msgbuf.h 
     6.7 -ln -sf ../asm-i386/msr.h 
     6.8  ln -sf ../asm-i386/mtrr.h 
     6.9  ln -sf ../asm-i386/namei.h 
    6.10  ln -sf ../asm-i386/param.h