direct-io.hg

changeset 5446:01a9f1e50dd8

bitkeeper revision 1.1709.1.2 (42adf1880UbcLgsnM7VU7-bfN_g6JA)

Finish reserved VA bit assignment, handle uncached address
range with lower half (0xe8...0-0xefff...f) of reserved
range in region 7
Signed-off by: Dan Magenheimer <dan.magenheimer@hp.com>
author djm@kirby.fc.hp.com
date Mon Jun 13 20:50:16 2005 +0000 (2005-06-13)
parents 9dc7db2ffb41
children dce7deb4c508 e9bf6cebd37d
files xen/arch/ia64/ivt.S xen/arch/ia64/patch/linux-2.6.11/io.h
line diff
     1.1 --- a/xen/arch/ia64/ivt.S	Mon Jun 13 16:19:16 2005 +0000
     1.2 +++ b/xen/arch/ia64/ivt.S	Mon Jun 13 20:50:16 2005 +0000
     1.3 @@ -367,9 +367,15 @@ ENTRY(alt_itlb_miss)
     1.4  #endif
     1.5  	extr.u r23=r21,IA64_PSR_CPL0_BIT,2	// extract psr.cpl
     1.6  	and r19=r19,r16		// clear ed, reserved bits, and PTE control bits
     1.7 +#ifdef XEN
     1.8 +	shr.u r18=r16,55	// move address bit 59 to bit 4
     1.9 +	;;
    1.10 +	and r18=0x10,r18	// bit 4=address-bit(59)
    1.11 +#else
    1.12  	shr.u r18=r16,57	// move address bit 61 to bit 4
    1.13  	;;
    1.14  	andcm r18=0x10,r18	// bit 4=~address-bit(61)
    1.15 +#endif
    1.16  	cmp.ne p8,p0=r0,r23	// psr.cpl != 0?
    1.17  	or r19=r17,r19		// insert PTE control bits into r19
    1.18  	;;
    1.19 @@ -414,24 +420,33 @@ ENTRY(alt_dtlb_miss)
    1.20  	extr.u r23=r21,IA64_PSR_CPL0_BIT,2	// extract psr.cpl
    1.21  	and r22=IA64_ISR_CODE_MASK,r20		// get the isr.code field
    1.22  	tbit.nz p6,p7=r20,IA64_ISR_SP_BIT	// is speculation bit on?
    1.23 +#ifdef XEN
    1.24 +	shr.u r18=r16,55			// move address bit 59 to bit 4
    1.25 +	and r19=r19,r16				// clear ed, reserved bits, and PTE control bits
    1.26 +	tbit.nz p9,p0=r20,IA64_ISR_NA_BIT	// is non-access bit on?
    1.27 +	;;
    1.28 +	and r18=0x10,r18	// bit 4=address-bit(59)
    1.29 +#else
    1.30  	shr.u r18=r16,57			// move address bit 61 to bit 4
    1.31  	and r19=r19,r16				// clear ed, reserved bits, and PTE control bits
    1.32  	tbit.nz p9,p0=r20,IA64_ISR_NA_BIT	// is non-access bit on?
    1.33  	;;
    1.34  	andcm r18=0x10,r18	// bit 4=~address-bit(61)
    1.35 +#endif
    1.36  	cmp.ne p8,p0=r0,r23
    1.37  (p9)	cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22	// check isr.code field
    1.38  (p8)	br.cond.spnt page_fault
    1.39  #ifdef XEN
    1.40  	;;
    1.41 -	// FIXME: inadequate test, this is where we test for Xen address
    1.42 -	// note that 0xf000 (cached) and 0xd000 (uncached) addresses
    1.43 -	// should be OK.  (Though no I/O is done in Xen, EFI needs uncached
    1.44 -	// addresses and some domain EFI calls are passed through)
    1.45 -	tbit.nz p0,p8=r16,60
    1.46 -(p8)	br.cond.spnt page_fault
    1.47 -//(p8)	br.cond.spnt 0
    1.48 -	;;
    1.49 +	// Test for Xen address, if not handle via page_fault
    1.50 +	// note that 0xf000 (cached) and 0xe800 (uncached) addresses
    1.51 +	// should be OK.
    1.52 +	extr.u r22=r16,59,5;;
    1.53 +	cmp.eq p8,p0=0x1e,r22
    1.54 +(p8)	br.cond.spnt 1f;;
    1.55 +	cmp.ne p8,p0=0x1d,r22
    1.56 +(p8)	br.cond.sptk page_fault ;;
    1.57 +1:
    1.58  #endif
    1.59  
    1.60  	dep r21=-1,r21,IA64_PSR_ED_BIT,1
     2.1 --- a/xen/arch/ia64/patch/linux-2.6.11/io.h	Mon Jun 13 16:19:16 2005 +0000
     2.2 +++ b/xen/arch/ia64/patch/linux-2.6.11/io.h	Mon Jun 13 20:50:16 2005 +0000
     2.3 @@ -5,7 +5,7 @@
     2.4   #define SLOW_DOWN_IO	do { } while (0)
     2.5   
     2.6  +#ifdef XEN
     2.7 -+#define __IA64_UNCACHED_OFFSET	0xd000000000000000UL	/* region 6 */
     2.8 ++#define __IA64_UNCACHED_OFFSET	0xe800000000000000UL
     2.9  +#else
    2.10   #define __IA64_UNCACHED_OFFSET	0xc000000000000000UL	/* region 6 */
    2.11  +#endif