direct-io.hg

view xen/include/asm-x86/vmx_vmcs.h @ 5669:ff5d7ccd8d69

No changes from me.
author cl349@firebug.cl.cam.ac.uk
date Tue Jul 05 08:47:55 2005 +0000 (2005-07-05)
parents 8bd2e8933277
children 6e11af443eb1 b53a65034532
line source
1 /*
2 * vmx_vmcs.h: VMCS related definitions
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19 #ifndef __ASM_X86_VMX_VMCS_H__
20 #define __ASM_X86_VMX_VMCS_H__
22 #include <asm/config.h>
23 #include <asm/vmx_cpu.h>
24 #include <asm/vmx_platform.h>
25 #include <public/vmx_assist.h>
27 extern int start_vmx(void);
28 extern void stop_vmx(void);
30 #if defined (__x86_64__)
31 extern void vmx_load_msrs(struct vcpu *p, struct vcpu *n);
32 void vmx_restore_msrs(struct vcpu *d);
33 #else
34 #define vmx_load_msrs(_p, _n) ((void)0)
35 #define vmx_restore_msrs(_v) ((void)0)
36 #endif
38 void vmx_enter_scheduler(void);
40 enum {
41 VMX_CPU_STATE_PG_ENABLED=0,
42 VMX_CPU_STATE_PAE_ENABLED,
43 VMX_CPU_STATE_LME_ENABLED,
44 VMX_CPU_STATE_LMA_ENABLED,
45 VMX_CPU_STATE_ASSIST_ENABLED,
46 };
48 #define VMX_LONG_GUEST(ed) \
49 (test_bit(VMX_CPU_STATE_LMA_ENABLED, &ed->arch.arch_vmx.cpu_state))
51 struct vmcs_struct {
52 u32 vmcs_revision_id;
53 unsigned char data [0]; /* vmcs size is read from MSR */
54 };
56 enum {
57 VMX_INDEX_MSR_LSTAR = 0,
58 VMX_INDEX_MSR_STAR,
59 VMX_INDEX_MSR_CSTAR,
60 VMX_INDEX_MSR_SYSCALL_MASK,
61 VMX_INDEX_MSR_EFER,
63 VMX_MSR_COUNT,
64 };
66 struct msr_state{
67 unsigned long flags;
68 unsigned long msr_items[VMX_MSR_COUNT];
69 unsigned long shadow_gs;
70 };
72 struct arch_vmx_struct {
73 struct vmcs_struct *vmcs; /* VMCS pointer in virtual */
74 unsigned long flags; /* VMCS flags */
75 unsigned long cpu_cr2; /* save CR2 */
76 unsigned long cpu_cr3;
77 unsigned long cpu_state;
78 struct msr_state msr_content;
79 };
81 #define vmx_schedule_tail(next) \
82 (next)->thread.arch_vmx.arch_vmx_schedule_tail((next))
84 #define VMX_DOMAIN(ed) ((ed)->arch.arch_vmx.flags)
86 #define ARCH_VMX_VMCS_LOADED 0 /* VMCS has been loaded and active */
87 #define ARCH_VMX_VMCS_LAUNCH 1 /* Needs VMCS launch */
88 #define ARCH_VMX_VMCS_RESUME 2 /* Needs VMCS resume */
89 #define ARCH_VMX_IO_WAIT 3 /* Waiting for I/O completion */
91 void vmx_do_launch(struct vcpu *);
92 void vmx_do_resume(struct vcpu *);
94 struct vmcs_struct *alloc_vmcs(void);
95 void free_vmcs(struct vmcs_struct *);
96 int load_vmcs(struct arch_vmx_struct *, u64);
97 int store_vmcs(struct arch_vmx_struct *, u64);
98 int construct_vmcs(struct arch_vmx_struct *, struct cpu_user_regs *,
99 struct vcpu_guest_context *, int);
101 #define VMCS_USE_HOST_ENV 1
102 #define VMCS_USE_SEPARATE_ENV 0
104 /* this works for both 32bit & 64bit eflags filteration done in construct_init_vmcs_guest() */
105 #define VMCS_EFLAGS_RESERVED_0 0xffc08028 /* bitmap for 0 */
106 #define VMCS_EFLAGS_RESERVED_1 0x00000002 /* bitmap for 1 */
108 extern int vmcs_version;
110 #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
111 #define CPU_BASED_USE_TSC_OFFSETING 0x00000008
112 #define CPU_BASED_HLT_EXITING 0x00000080
113 #define CPU_BASED_INVDPG_EXITING 0x00000200
114 #define CPU_BASED_MWAIT_EXITING 0x00000400
115 #define CPU_BASED_RDPMC_EXITING 0x00000800
116 #define CPU_BASED_RDTSC_EXITING 0x00001000
117 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000
118 #define CPU_BASED_CR8_STORE_EXITING 0x00100000
119 #define CPU_BASED_TPR_SHADOW 0x00200000
120 #define CPU_BASED_MOV_DR_EXITING 0x00800000
121 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000
122 #define CPU_BASED_ACTIVATE_IO_BITMAP 0x02000000
123 #define CPU_BASED_MONITOR_EXITING 0x20000000
124 #define CPU_BASED_PAUSE_EXITING 0x40000000
125 #define PIN_BASED_EXT_INTR_MASK 0x1
126 #define PIN_BASED_NMI_EXITING 0x8
128 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
129 #define VM_EXIT_HOST_ADD_SPACE_SIZE 0x00000200
132 /* VMCS Encordings */
133 enum vmcs_field {
134 GUEST_ES_SELECTOR = 0x00000800,
135 GUEST_CS_SELECTOR = 0x00000802,
136 GUEST_SS_SELECTOR = 0x00000804,
137 GUEST_DS_SELECTOR = 0x00000806,
138 GUEST_FS_SELECTOR = 0x00000808,
139 GUEST_GS_SELECTOR = 0x0000080a,
140 GUEST_LDTR_SELECTOR = 0x0000080c,
141 GUEST_TR_SELECTOR = 0x0000080e,
142 HOST_ES_SELECTOR = 0x00000c00,
143 HOST_CS_SELECTOR = 0x00000c02,
144 HOST_SS_SELECTOR = 0x00000c04,
145 HOST_DS_SELECTOR = 0x00000c06,
146 HOST_FS_SELECTOR = 0x00000c08,
147 HOST_GS_SELECTOR = 0x00000c0a,
148 HOST_TR_SELECTOR = 0x00000c0c,
149 IO_BITMAP_A = 0x00002000,
150 IO_BITMAP_A_HIGH = 0x00002001,
151 IO_BITMAP_B = 0x00002002,
152 IO_BITMAP_B_HIGH = 0x00002003,
153 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
154 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
155 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
156 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
157 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
158 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
159 TSC_OFFSET = 0x00002010,
160 TSC_OFFSET_HIGH = 0x00002011,
161 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
162 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
163 VMCS_LINK_POINTER = 0x00002800,
164 VMCS_LINK_POINTER_HIGH = 0x00002801,
165 GUEST_IA32_DEBUGCTL = 0x00002802,
166 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
167 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
168 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
169 EXCEPTION_BITMAP = 0x00004004,
170 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
171 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
172 CR3_TARGET_COUNT = 0x0000400a,
173 VM_EXIT_CONTROLS = 0x0000400c,
174 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
175 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
176 VM_ENTRY_CONTROLS = 0x00004012,
177 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
178 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
179 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
180 VM_ENTRY_INSTRUCTION_LENGTH = 0x0000401a,
181 TPR_THRESHOLD = 0x0000401c,
182 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
183 VM_INSTRUCTION_ERROR = 0x00004400,
184 VM_EXIT_REASON = 0x00004402,
185 VM_EXIT_INTR_INFO = 0x00004404,
186 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
187 IDT_VECTORING_INFO_FIELD = 0x00004408,
188 IDT_VECTORING_ERROR_CODE = 0x0000440a,
189 INSTRUCTION_LEN = 0x0000440c,
190 VMX_INSTRUCTION_INFO = 0x0000440e,
191 GUEST_ES_LIMIT = 0x00004800,
192 GUEST_CS_LIMIT = 0x00004802,
193 GUEST_SS_LIMIT = 0x00004804,
194 GUEST_DS_LIMIT = 0x00004806,
195 GUEST_FS_LIMIT = 0x00004808,
196 GUEST_GS_LIMIT = 0x0000480a,
197 GUEST_LDTR_LIMIT = 0x0000480c,
198 GUEST_TR_LIMIT = 0x0000480e,
199 GUEST_GDTR_LIMIT = 0x00004810,
200 GUEST_IDTR_LIMIT = 0x00004812,
201 GUEST_ES_AR_BYTES = 0x00004814,
202 GUEST_CS_AR_BYTES = 0x00004816,
203 GUEST_SS_AR_BYTES = 0x00004818,
204 GUEST_DS_AR_BYTES = 0x0000481a,
205 GUEST_FS_AR_BYTES = 0x0000481c,
206 GUEST_GS_AR_BYTES = 0x0000481e,
207 GUEST_LDTR_AR_BYTES = 0x00004820,
208 GUEST_TR_AR_BYTES = 0x00004822,
209 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
210 GUEST_SYSENTER_CS = 0x0000482A,
211 HOST_IA32_SYSENTER_CS = 0x00004c00,
212 CR0_GUEST_HOST_MASK = 0x00006000,
213 CR4_GUEST_HOST_MASK = 0x00006002,
214 CR0_READ_SHADOW = 0x00006004,
215 CR4_READ_SHADOW = 0x00006006,
216 CR3_TARGET_VALUE0 = 0x00006008,
217 CR3_TARGET_VALUE1 = 0x0000600a,
218 CR3_TARGET_VALUE2 = 0x0000600c,
219 CR3_TARGET_VALUE3 = 0x0000600e,
220 EXIT_QUALIFICATION = 0x00006400,
221 GUEST_LINEAR_ADDRESS = 0x0000640a,
222 GUEST_CR0 = 0x00006800,
223 GUEST_CR3 = 0x00006802,
224 GUEST_CR4 = 0x00006804,
225 GUEST_ES_BASE = 0x00006806,
226 GUEST_CS_BASE = 0x00006808,
227 GUEST_SS_BASE = 0x0000680a,
228 GUEST_DS_BASE = 0x0000680c,
229 GUEST_FS_BASE = 0x0000680e,
230 GUEST_GS_BASE = 0x00006810,
231 GUEST_LDTR_BASE = 0x00006812,
232 GUEST_TR_BASE = 0x00006814,
233 GUEST_GDTR_BASE = 0x00006816,
234 GUEST_IDTR_BASE = 0x00006818,
235 GUEST_DR7 = 0x0000681a,
236 GUEST_RSP = 0x0000681c,
237 GUEST_RIP = 0x0000681e,
238 GUEST_RFLAGS = 0x00006820,
239 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
240 GUEST_SYSENTER_ESP = 0x00006824,
241 GUEST_SYSENTER_EIP = 0x00006826,
242 HOST_CR0 = 0x00006c00,
243 HOST_CR3 = 0x00006c02,
244 HOST_CR4 = 0x00006c04,
245 HOST_FS_BASE = 0x00006c06,
246 HOST_GS_BASE = 0x00006c08,
247 HOST_TR_BASE = 0x00006c0a,
248 HOST_GDTR_BASE = 0x00006c0c,
249 HOST_IDTR_BASE = 0x00006c0e,
250 HOST_IA32_SYSENTER_ESP = 0x00006c10,
251 HOST_IA32_SYSENTER_EIP = 0x00006c12,
252 HOST_RSP = 0x00006c14,
253 HOST_RIP = 0x00006c16,
254 };
256 #define VMX_DEBUG 1
257 #if VMX_DEBUG
258 #define DBG_LEVEL_0 (1 << 0)
259 #define DBG_LEVEL_1 (1 << 1)
260 #define DBG_LEVEL_2 (1 << 2)
261 #define DBG_LEVEL_3 (1 << 3)
262 #define DBG_LEVEL_IO (1 << 4)
263 #define DBG_LEVEL_VMMU (1 << 5)
265 extern unsigned int opt_vmx_debug_level;
266 #define VMX_DBG_LOG(level, _f, _a...) \
267 if ((level) & opt_vmx_debug_level) \
268 printk("[VMX]" _f "\n", ## _a )
269 #else
270 #define VMX_DBG_LOG(level, _f, _a...)
271 #endif
273 #define __vmx_bug(regs) \
274 do { \
275 printk("__vmx_bug at %s:%d\n", __FILE__, __LINE__); \
276 show_registers(regs); \
277 domain_crash_synchronous(); \
278 } while (0)
280 #endif /* ASM_X86_VMX_VMCS_H__ */
282 /*
283 * Local variables:
284 * mode: C
285 * c-set-style: "BSD"
286 * c-basic-offset: 4
287 * tab-width: 4
288 * indent-tabs-mode: nil
289 * End:
290 */