direct-io.hg

view xen/include/asm-x86/msr.h @ 5669:ff5d7ccd8d69

No changes from me.
author cl349@firebug.cl.cam.ac.uk
date Tue Jul 05 08:47:55 2005 +0000 (2005-07-05)
parents 8bd2e8933277
children 9b77ba29108d a83ac0806d6b
line source
1 #ifndef __ASM_MSR_H
2 #define __ASM_MSR_H
4 #define rdmsr(msr,val1,val2) \
5 __asm__ __volatile__("rdmsr" \
6 : "=a" (val1), "=d" (val2) \
7 : "c" (msr))
9 #define rdmsrl(msr,val) do { unsigned long a__,b__; \
10 __asm__ __volatile__("rdmsr" \
11 : "=a" (a__), "=d" (b__) \
12 : "c" (msr)); \
13 val = a__ | (b__<<32); \
14 } while(0);
16 #define wrmsr(msr,val1,val2) \
17 __asm__ __volatile__("wrmsr" \
18 : /* no outputs */ \
19 : "c" (msr), "a" (val1), "d" (val2))
21 #define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
23 #define rdmsr_user(msr,val1,val2) ({\
24 int _rc; \
25 __asm__ __volatile__( \
26 "1: rdmsr\n2:\n" \
27 ".section .fixup,\"ax\"\n" \
28 "3: movl $1,%2\n; jmp 2b\n" \
29 ".previous\n" \
30 ".section __ex_table,\"a\"\n" \
31 " "__FIXUP_ALIGN"\n" \
32 " "__FIXUP_WORD" 1b,3b\n" \
33 ".previous\n" \
34 : "=a" (val1), "=d" (val2), "=&r" (_rc) \
35 : "c" (msr), "2" (0)); \
36 _rc; })
38 #define wrmsr_user(msr,val1,val2) ({\
39 int _rc; \
40 __asm__ __volatile__( \
41 "1: wrmsr\n2:\n" \
42 ".section .fixup,\"ax\"\n" \
43 "3: movl $1,%0\n; jmp 2b\n" \
44 ".previous\n" \
45 ".section __ex_table,\"a\"\n" \
46 " "__FIXUP_ALIGN"\n" \
47 " "__FIXUP_WORD" 1b,3b\n" \
48 ".previous\n" \
49 : "=&r" (_rc) \
50 : "c" (msr), "a" (val1), "d" (val2), "0" (0)); \
51 _rc; })
53 #define rdtsc(low,high) \
54 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
56 #define rdtscl(low) \
57 __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
59 #if defined(__i386__)
60 #define rdtscll(val) \
61 __asm__ __volatile__("rdtsc" : "=A" (val))
62 #elif defined(__x86_64__)
63 #define rdtscll(val) do { \
64 unsigned int a,d; \
65 asm volatile("rdtsc" : "=a" (a), "=d" (d)); \
66 (val) = ((unsigned long)a) | (((unsigned long)d)<<32); \
67 } while(0)
68 #endif
70 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
72 #define rdpmc(counter,low,high) \
73 __asm__ __volatile__("rdpmc" \
74 : "=a" (low), "=d" (high) \
75 : "c" (counter))
77 /* symbolic names for some interesting MSRs */
78 /* Intel defined MSRs. */
79 #define MSR_IA32_P5_MC_ADDR 0
80 #define MSR_IA32_P5_MC_TYPE 1
81 #define MSR_IA32_PLATFORM_ID 0x17
82 #define MSR_IA32_EBL_CR_POWERON 0x2a
84 #define MSR_IA32_APICBASE 0x1b
85 #define MSR_IA32_APICBASE_BSP (1<<8)
86 #define MSR_IA32_APICBASE_ENABLE (1<<11)
87 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
89 #define MSR_IA32_UCODE_WRITE 0x79
90 #define MSR_IA32_UCODE_REV 0x8b
92 #define MSR_P6_PERFCTR0 0xc1
93 #define MSR_P6_PERFCTR1 0xc2
95 /* MSRs & bits used for VMX enabling */
96 #define MSR_IA32_VMX_BASIC_MSR 0x480
97 #define IA32_FEATURE_CONTROL_MSR 0x3a
98 #define IA32_FEATURE_CONTROL_MSR_LOCK 0x1
99 #define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON 0x4
101 /* AMD/K8 specific MSRs */
102 #define MSR_EFER 0xc0000080 /* extended feature register */
103 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
104 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
105 #define MSR_CSTAR 0xc0000083 /* compatibility mode SYSCALL target */
106 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
107 #define MSR_FS_BASE 0xc0000100 /* 64bit GS base */
108 #define MSR_GS_BASE 0xc0000101 /* 64bit FS base */
109 #define MSR_SHADOW_GS_BASE 0xc0000102 /* SwapGS GS shadow */
110 /* EFER bits: */
111 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
112 #define _EFER_LME 8 /* Long mode enable */
113 #define _EFER_LMA 10 /* Long mode active (read-only) */
114 #define _EFER_NX 11 /* No execute enable */
116 #define EFER_SCE (1<<_EFER_SCE)
117 #define EFER_LME (1<<_EFER_LME)
118 #define EFER_LMA (1<<_EFER_LMA)
119 #define EFER_NX (1<<_EFER_NX)
121 /* Intel MSRs. Some also available on other CPUs */
122 #define MSR_IA32_PLATFORM_ID 0x17
124 #define MSR_MTRRcap 0x0fe
125 #define MSR_IA32_BBL_CR_CTL 0x119
127 #define MSR_IA32_SYSENTER_CS 0x174
128 #define MSR_IA32_SYSENTER_ESP 0x175
129 #define MSR_IA32_SYSENTER_EIP 0x176
131 #define MSR_IA32_MCG_CAP 0x179
132 #define MSR_IA32_MCG_STATUS 0x17a
133 #define MSR_IA32_MCG_CTL 0x17b
135 #define MSR_MTRRfix64K_00000 0x250
136 #define MSR_MTRRfix16K_80000 0x258
137 #define MSR_MTRRfix16K_A0000 0x259
138 #define MSR_MTRRfix4K_C0000 0x268
139 #define MSR_MTRRfix4K_C8000 0x269
140 #define MSR_MTRRfix4K_D0000 0x26a
141 #define MSR_MTRRfix4K_D8000 0x26b
142 #define MSR_MTRRfix4K_E0000 0x26c
143 #define MSR_MTRRfix4K_E8000 0x26d
144 #define MSR_MTRRfix4K_F0000 0x26e
145 #define MSR_MTRRfix4K_F8000 0x26f
146 #define MSR_MTRRdefType 0x2ff
148 #define MSR_IA32_MC0_CTL 0x400
149 #define MSR_IA32_MC0_STATUS 0x401
150 #define MSR_IA32_MC0_ADDR 0x402
151 #define MSR_IA32_MC0_MISC 0x403
153 #define MSR_IA32_DS_AREA 0x600
155 #define MSR_IA32_BBL_CR_CTL 0x119
157 #define MSR_IA32_MCG_CAP 0x179
158 #define MSR_IA32_MCG_STATUS 0x17a
159 #define MSR_IA32_MCG_CTL 0x17b
161 #define MSR_IA32_THERM_CONTROL 0x19a
162 #define MSR_IA32_THERM_INTERRUPT 0x19b
163 #define MSR_IA32_THERM_STATUS 0x19c
164 #define MSR_IA32_MISC_ENABLE 0x1a0
166 #define MSR_IA32_MISC_ENABLE_PERF_AVAIL (1<<7)
167 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11)
168 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
170 #define MSR_IA32_DEBUGCTLMSR 0x1d9
171 #define MSR_IA32_DEBUGCTLMSR_LBR (1<<0)
172 #define MSR_IA32_DEBUGCTLMSR_BTF (1<<1)
173 #define MSR_IA32_DEBUGCTLMSR_TR (1<<2)
174 #define MSR_IA32_DEBUGCTLMSR_BTS (1<<3)
175 #define MSR_IA32_DEBUGCTLMSR_BTINT (1<<4)
177 #define MSR_IA32_LASTBRANCH_TOS 0x1da
178 #define MSR_IA32_LASTBRANCH_0 0x1db
179 #define MSR_IA32_LASTBRANCH_1 0x1dc
180 #define MSR_IA32_LASTBRANCH_2 0x1dd
181 #define MSR_IA32_LASTBRANCH_3 0x1de
183 #define MSR_IA32_MC0_CTL 0x400
184 #define MSR_IA32_MC0_STATUS 0x401
185 #define MSR_IA32_MC0_ADDR 0x402
186 #define MSR_IA32_MC0_MISC 0x403
188 #define MSR_P6_PERFCTR0 0xc1
189 #define MSR_P6_PERFCTR1 0xc2
190 #define MSR_P6_EVNTSEL0 0x186
191 #define MSR_P6_EVNTSEL1 0x187
194 /* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */
195 #define MSR_K7_EVNTSEL0 0xC0010000
196 #define MSR_K7_PERFCTR0 0xC0010004
197 #define MSR_K7_EVNTSEL1 0xC0010001
198 #define MSR_K7_PERFCTR1 0xC0010005
199 #define MSR_K7_EVNTSEL2 0xC0010002
200 #define MSR_K7_PERFCTR2 0xC0010006
201 #define MSR_K7_EVNTSEL3 0xC0010003
202 #define MSR_K7_PERFCTR3 0xC0010007
203 #define MSR_K8_TOP_MEM1 0xC001001A
204 #define MSR_K8_TOP_MEM2 0xC001001D
205 #define MSR_K8_SYSCFG 0xC0000010
206 #define MSR_K7_HWCR 0xC0010015
207 #define MSR_K7_CLK_CTL 0xC001001b
208 #define MSR_K7_FID_VID_CTL 0xC0010041
209 #define MSR_K7_VID_STATUS 0xC0010042
211 /* K6 MSRs */
212 #define MSR_K6_EFER 0xC0000080
213 #define MSR_K6_STAR 0xC0000081
214 #define MSR_K6_WHCR 0xC0000082
215 #define MSR_K6_UWCCR 0xC0000085
216 #define MSR_K6_EPMR 0xC0000086
217 #define MSR_K6_PSOR 0xC0000087
218 #define MSR_K6_PFIR 0xC0000088
220 /* Centaur-Hauls/IDT defined MSRs. */
221 #define MSR_IDT_FCR1 0x107
222 #define MSR_IDT_FCR2 0x108
223 #define MSR_IDT_FCR3 0x109
224 #define MSR_IDT_FCR4 0x10a
226 #define MSR_IDT_MCR0 0x110
227 #define MSR_IDT_MCR1 0x111
228 #define MSR_IDT_MCR2 0x112
229 #define MSR_IDT_MCR3 0x113
230 #define MSR_IDT_MCR4 0x114
231 #define MSR_IDT_MCR5 0x115
232 #define MSR_IDT_MCR6 0x116
233 #define MSR_IDT_MCR7 0x117
234 #define MSR_IDT_MCR_CTRL 0x120
236 /* VIA Cyrix defined MSRs*/
237 #define MSR_VIA_FCR 0x1107
238 #define MSR_VIA_LONGHAUL 0x110a
239 #define MSR_VIA_RNG 0x110b
240 #define MSR_VIA_BCR2 0x1147
242 /* Transmeta defined MSRs */
243 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
244 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
245 #define MSR_TMTA_LRTI_READOUT 0x80868018
246 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
248 #endif /* __ASM_MSR_H */