direct-io.hg

view xen/arch/x86/hvm/vlapic.c @ 15456:eb2b7ce05f97

hvm vlapic: Fix one_shot argument passed to create_periodic_time().
Signed-off-by: Yosuke Iwamatsu <y-iwamatsu@ab.jp.nec.com>
author kfraser@localhost.localdomain
date Tue Jul 03 11:47:08 2007 +0100 (2007-07-03)
parents 005dd6b1cf8e
children
line source
1 /*
2 * vlapic.c: virtualize LAPIC for HVM vcpus.
3 *
4 * Copyright (c) 2004, Intel Corporation.
5 * Copyright (c) 2006 Keir Fraser, XenSource Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
18 * Place - Suite 330, Boston, MA 02111-1307 USA.
19 */
21 #include <xen/config.h>
22 #include <xen/types.h>
23 #include <xen/mm.h>
24 #include <xen/xmalloc.h>
25 #include <xen/domain_page.h>
26 #include <asm/page.h>
27 #include <xen/event.h>
28 #include <xen/trace.h>
29 #include <asm/hvm/hvm.h>
30 #include <asm/hvm/io.h>
31 #include <asm/hvm/support.h>
32 #include <xen/lib.h>
33 #include <xen/sched.h>
34 #include <asm/current.h>
35 #include <asm/hvm/vmx/vmx.h>
36 #include <public/hvm/ioreq.h>
37 #include <public/hvm/params.h>
39 #define VLAPIC_VERSION 0x00050014
40 #define VLAPIC_LVT_NUM 6
42 /* vlapic's frequence is 100 MHz */
43 #define APIC_BUS_CYCLE_NS 10
45 #define LVT_MASK \
46 APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK
48 #define LINT_MASK \
49 LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY |\
50 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER
52 static unsigned int vlapic_lvt_mask[VLAPIC_LVT_NUM] =
53 {
54 /* LVTT */
55 LVT_MASK | APIC_LVT_TIMER_PERIODIC,
56 /* LVTTHMR */
57 LVT_MASK | APIC_MODE_MASK,
58 /* LVTPC */
59 LVT_MASK | APIC_MODE_MASK,
60 /* LVT0-1 */
61 LINT_MASK, LINT_MASK,
62 /* LVTERR */
63 LVT_MASK
64 };
66 /* Following could belong in apicdef.h */
67 #define APIC_SHORT_MASK 0xc0000
68 #define APIC_DEST_NOSHORT 0x0
69 #define APIC_DEST_MASK 0x800
71 #define vlapic_lvt_enabled(vlapic, lvt_type) \
72 (!(vlapic_get_reg(vlapic, lvt_type) & APIC_LVT_MASKED))
74 #define vlapic_lvt_vector(vlapic, lvt_type) \
75 (vlapic_get_reg(vlapic, lvt_type) & APIC_VECTOR_MASK)
77 #define vlapic_lvt_dm(vlapic, lvt_type) \
78 (vlapic_get_reg(vlapic, lvt_type) & APIC_MODE_MASK)
80 #define vlapic_lvtt_period(vlapic) \
81 (vlapic_get_reg(vlapic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC)
84 /*
85 * Generic APIC bitmap vector update & search routines.
86 */
88 #define VEC_POS(v) ((v)%32)
89 #define REG_POS(v) (((v)/32)* 0x10)
90 #define vlapic_test_and_set_vector(vec, bitmap) \
91 test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec))
92 #define vlapic_test_and_clear_vector(vec, bitmap) \
93 test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec))
94 #define vlapic_set_vector(vec, bitmap) \
95 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec))
96 #define vlapic_clear_vector(vec, bitmap) \
97 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec))
99 static int vlapic_find_highest_vector(void *bitmap)
100 {
101 uint32_t *word = bitmap;
102 int word_offset = MAX_VECTOR / 32;
104 /* Work backwards through the bitmap (first 32-bit word in every four). */
105 while ( (word_offset != 0) && (word[(--word_offset)*4] == 0) )
106 continue;
108 return (fls(word[word_offset*4]) - 1) + (word_offset * 32);
109 }
112 /*
113 * IRR-specific bitmap update & search routines.
114 */
116 static int vlapic_test_and_set_irr(int vector, struct vlapic *vlapic)
117 {
118 return vlapic_test_and_set_vector(vector, &vlapic->regs->data[APIC_IRR]);
119 }
121 static void vlapic_clear_irr(int vector, struct vlapic *vlapic)
122 {
123 vlapic_clear_vector(vector, &vlapic->regs->data[APIC_IRR]);
124 }
126 int vlapic_find_highest_irr(struct vlapic *vlapic)
127 {
128 int result;
130 result = vlapic_find_highest_vector(&vlapic->regs->data[APIC_IRR]);
131 ASSERT((result == -1) || (result >= 16));
133 return result;
134 }
136 int vlapic_set_irq(struct vlapic *vlapic, uint8_t vec, uint8_t trig)
137 {
138 int ret;
140 ret = !vlapic_test_and_set_irr(vec, vlapic);
141 if ( trig )
142 vlapic_set_vector(vec, &vlapic->regs->data[APIC_TMR]);
144 /* We may need to wake up target vcpu, besides set pending bit here */
145 return ret;
146 }
148 int vlapic_find_highest_isr(struct vlapic *vlapic)
149 {
150 int result;
152 result = vlapic_find_highest_vector(&vlapic->regs->data[APIC_ISR]);
153 ASSERT((result == -1) || (result >= 16));
155 return result;
156 }
158 uint32_t vlapic_get_ppr(struct vlapic *vlapic)
159 {
160 uint32_t tpr, isrv, ppr;
161 int isr;
163 tpr = vlapic_get_reg(vlapic, APIC_TASKPRI);
164 isr = vlapic_find_highest_isr(vlapic);
165 isrv = (isr != -1) ? isr : 0;
167 if ( (tpr & 0xf0) >= (isrv & 0xf0) )
168 ppr = tpr & 0xff;
169 else
170 ppr = isrv & 0xf0;
172 HVM_DBG_LOG(DBG_LEVEL_VLAPIC_INTERRUPT,
173 "vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
174 vlapic, ppr, isr, isrv);
176 return ppr;
177 }
179 int vlapic_match_logical_addr(struct vlapic *vlapic, uint8_t mda)
180 {
181 int result = 0;
182 uint8_t logical_id;
184 logical_id = GET_APIC_LOGICAL_ID(vlapic_get_reg(vlapic, APIC_LDR));
186 switch ( vlapic_get_reg(vlapic, APIC_DFR) )
187 {
188 case APIC_DFR_FLAT:
189 if ( logical_id & mda )
190 result = 1;
191 break;
192 case APIC_DFR_CLUSTER:
193 if ( ((logical_id >> 4) == (mda >> 0x4)) && (logical_id & mda & 0xf) )
194 result = 1;
195 break;
196 default:
197 gdprintk(XENLOG_WARNING, "Bad DFR value for lapic of vcpu %d: %08x\n",
198 vlapic_vcpu(vlapic)->vcpu_id,
199 vlapic_get_reg(vlapic, APIC_DFR));
200 break;
201 }
203 return result;
204 }
206 static int vlapic_match_dest(struct vcpu *v, struct vlapic *source,
207 int short_hand, int dest, int dest_mode)
208 {
209 int result = 0;
210 struct vlapic *target = vcpu_vlapic(v);
212 HVM_DBG_LOG(DBG_LEVEL_VLAPIC, "target %p, source %p, dest 0x%x, "
213 "dest_mode 0x%x, short_hand 0x%x",
214 target, source, dest, dest_mode, short_hand);
216 switch ( short_hand )
217 {
218 case APIC_DEST_NOSHORT:
219 if ( dest_mode == 0 )
220 {
221 /* Physical mode. */
222 if ( (dest == 0xFF) || (dest == VLAPIC_ID(target)) )
223 result = 1;
224 }
225 else
226 {
227 /* Logical mode. */
228 result = vlapic_match_logical_addr(target, dest);
229 }
230 break;
232 case APIC_DEST_SELF:
233 if ( target == source )
234 result = 1;
235 break;
237 case APIC_DEST_ALLINC:
238 result = 1;
239 break;
241 case APIC_DEST_ALLBUT:
242 if ( target != source )
243 result = 1;
244 break;
246 default:
247 gdprintk(XENLOG_WARNING, "Bad dest shorthand value %x\n", short_hand);
248 break;
249 }
251 return result;
252 }
254 /* Add a pending IRQ into lapic. */
255 static int vlapic_accept_irq(struct vcpu *v, int delivery_mode,
256 int vector, int level, int trig_mode)
257 {
258 int result = 0;
259 struct vlapic *vlapic = vcpu_vlapic(v);
261 switch ( delivery_mode )
262 {
263 case APIC_DM_FIXED:
264 case APIC_DM_LOWEST:
265 /* FIXME add logic for vcpu on reset */
266 if ( unlikely(!vlapic_enabled(vlapic)) )
267 break;
269 if ( vlapic_test_and_set_irr(vector, vlapic) && trig_mode )
270 {
271 HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
272 "level trig mode repeatedly for vector %d", vector);
273 break;
274 }
276 if ( trig_mode )
277 {
278 HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
279 "level trig mode for vector %d", vector);
280 vlapic_set_vector(vector, &vlapic->regs->data[APIC_TMR]);
281 }
283 vcpu_kick(v);
285 result = 1;
286 break;
288 case APIC_DM_REMRD:
289 gdprintk(XENLOG_WARNING, "Ignoring delivery mode 3\n");
290 break;
292 case APIC_DM_SMI:
293 gdprintk(XENLOG_WARNING, "Ignoring guest SMI\n");
294 break;
296 case APIC_DM_NMI:
297 if ( !test_and_set_bool(v->arch.hvm_vcpu.nmi_pending) )
298 vcpu_kick(v);
299 break;
301 case APIC_DM_INIT:
302 /* No work on INIT de-assert for P4-type APIC. */
303 if ( trig_mode && !(level & APIC_INT_ASSERT) )
304 break;
305 /* FIXME How to check the situation after vcpu reset? */
306 if ( v->is_initialised )
307 hvm_vcpu_reset(v);
308 v->arch.hvm_vcpu.init_sipi_sipi_state =
309 HVM_VCPU_INIT_SIPI_SIPI_STATE_WAIT_SIPI;
310 result = 1;
311 break;
313 case APIC_DM_STARTUP:
314 if ( v->arch.hvm_vcpu.init_sipi_sipi_state ==
315 HVM_VCPU_INIT_SIPI_SIPI_STATE_NORM )
316 break;
318 v->arch.hvm_vcpu.init_sipi_sipi_state =
319 HVM_VCPU_INIT_SIPI_SIPI_STATE_NORM;
321 if ( v->is_initialised )
322 {
323 gdprintk(XENLOG_ERR, "SIPI for initialized vcpu %x\n", v->vcpu_id);
324 goto exit_and_crash;
325 }
327 if ( hvm_bringup_ap(v->vcpu_id, vector) != 0 )
328 result = 0;
329 break;
331 default:
332 gdprintk(XENLOG_ERR, "TODO: unsupported delivery mode %x\n",
333 delivery_mode);
334 goto exit_and_crash;
335 }
337 return result;
339 exit_and_crash:
340 domain_crash(v->domain);
341 return 0;
342 }
344 /* This function is used by both ioapic and lapic.The bitmap is for vcpu_id. */
345 struct vlapic *apic_round_robin(
346 struct domain *d, uint8_t vector, uint32_t bitmap)
347 {
348 int next, old;
349 struct vlapic *target = NULL;
351 old = next = d->arch.hvm_domain.irq.round_robin_prev_vcpu;
353 do {
354 if ( ++next == MAX_VIRT_CPUS )
355 next = 0;
356 if ( (d->vcpu[next] == NULL) || !test_bit(next, &bitmap) )
357 continue;
358 target = vcpu_vlapic(d->vcpu[next]);
359 if ( vlapic_enabled(target) )
360 break;
361 target = NULL;
362 } while ( next != old );
364 d->arch.hvm_domain.irq.round_robin_prev_vcpu = next;
366 return target;
367 }
369 void vlapic_EOI_set(struct vlapic *vlapic)
370 {
371 int vector = vlapic_find_highest_isr(vlapic);
373 /* Some EOI writes may not have a matching to an in-service interrupt. */
374 if ( vector == -1 )
375 return;
377 vlapic_clear_vector(vector, &vlapic->regs->data[APIC_ISR]);
379 if ( vlapic_test_and_clear_vector(vector, &vlapic->regs->data[APIC_TMR]) )
380 vioapic_update_EOI(vlapic_domain(vlapic), vector);
381 }
383 static void vlapic_ipi(struct vlapic *vlapic)
384 {
385 uint32_t icr_low = vlapic_get_reg(vlapic, APIC_ICR);
386 uint32_t icr_high = vlapic_get_reg(vlapic, APIC_ICR2);
388 unsigned int dest = GET_APIC_DEST_FIELD(icr_high);
389 unsigned int short_hand = icr_low & APIC_SHORT_MASK;
390 unsigned int trig_mode = icr_low & APIC_INT_LEVELTRIG;
391 unsigned int level = icr_low & APIC_INT_ASSERT;
392 unsigned int dest_mode = icr_low & APIC_DEST_MASK;
393 unsigned int delivery_mode =icr_low & APIC_MODE_MASK;
394 unsigned int vector = icr_low & APIC_VECTOR_MASK;
396 struct vlapic *target;
397 struct vcpu *v;
398 uint32_t lpr_map = 0;
400 HVM_DBG_LOG(DBG_LEVEL_VLAPIC, "icr_high 0x%x, icr_low 0x%x, "
401 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
402 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x",
403 icr_high, icr_low, short_hand, dest,
404 trig_mode, level, dest_mode, delivery_mode, vector);
406 for_each_vcpu ( vlapic_domain(vlapic), v )
407 {
408 if ( vlapic_match_dest(v, vlapic, short_hand, dest, dest_mode) )
409 {
410 if ( delivery_mode == APIC_DM_LOWEST )
411 set_bit(v->vcpu_id, &lpr_map);
412 else
413 vlapic_accept_irq(v, delivery_mode,
414 vector, level, trig_mode);
415 }
416 }
418 if ( delivery_mode == APIC_DM_LOWEST )
419 {
420 target = apic_round_robin(vlapic_domain(v), vector, lpr_map);
421 if ( target != NULL )
422 vlapic_accept_irq(vlapic_vcpu(target), delivery_mode,
423 vector, level, trig_mode);
424 }
425 }
427 static uint32_t vlapic_get_tmcct(struct vlapic *vlapic)
428 {
429 struct vcpu *v = current;
430 uint32_t tmcct, tmict = vlapic_get_reg(vlapic, APIC_TMICT);
431 uint64_t counter_passed;
433 counter_passed = (hvm_get_guest_time(v) - vlapic->pt.last_plt_gtime) // TSC
434 * 1000000000ULL / ticks_per_sec(v) // NS
435 / APIC_BUS_CYCLE_NS / vlapic->hw.timer_divisor;
436 tmcct = tmict - counter_passed;
438 HVM_DBG_LOG(DBG_LEVEL_VLAPIC_TIMER,
439 "timer initial count %d, timer current count %d, "
440 "offset %"PRId64,
441 tmict, tmcct, counter_passed);
443 return tmcct;
444 }
446 static void vlapic_set_tdcr(struct vlapic *vlapic, unsigned int val)
447 {
448 /* Only bits 0, 1 and 3 are settable; others are MBZ. */
449 val &= 0xb;
450 vlapic_set_reg(vlapic, APIC_TDCR, val);
452 /* Update the demangled hw.timer_divisor. */
453 val = ((val & 3) | ((val & 8) >> 1)) + 1;
454 vlapic->hw.timer_divisor = 1 << (val & 7);
456 HVM_DBG_LOG(DBG_LEVEL_VLAPIC_TIMER,
457 "timer_divisor: %d", vlapic->hw.timer_divisor);
458 }
460 static void vlapic_read_aligned(struct vlapic *vlapic, unsigned int offset,
461 unsigned int len, unsigned int *result)
462 {
463 ASSERT((len == 4) && (offset >= 0) && (offset <= APIC_TDCR));
465 switch ( offset )
466 {
467 case APIC_PROCPRI:
468 *result = vlapic_get_ppr(vlapic);
469 break;
471 case APIC_TMCCT: /* Timer CCR */
472 *result = vlapic_get_tmcct(vlapic);
473 break;
475 default:
476 *result = vlapic_get_reg(vlapic, offset);
477 break;
478 }
479 }
481 static unsigned long vlapic_read(struct vcpu *v, unsigned long address,
482 unsigned long len)
483 {
484 unsigned int alignment;
485 unsigned int tmp;
486 unsigned long result;
487 struct vlapic *vlapic = vcpu_vlapic(v);
488 unsigned int offset = address - vlapic_base_address(vlapic);
490 if ( offset > APIC_TDCR )
491 return 0;
493 /* some bugs on kernel cause read this with byte*/
494 if ( len != 4 )
495 HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
496 "read with len=0x%lx, should be 4 instead",
497 len);
499 alignment = offset & 0x3;
501 vlapic_read_aligned(vlapic, offset & ~0x3, 4, &tmp);
502 switch ( len )
503 {
504 case 1:
505 result = *((unsigned char *)&tmp + alignment);
506 break;
508 case 2:
509 ASSERT( alignment != 3 );
510 result = *(unsigned short *)((unsigned char *)&tmp + alignment);
511 break;
513 case 4:
514 ASSERT( alignment == 0 );
515 result = *(unsigned int *)((unsigned char *)&tmp + alignment);
516 break;
518 default:
519 gdprintk(XENLOG_ERR, "Local APIC read with len=0x%lx, "
520 "should be 4 instead.\n", len);
521 goto exit_and_crash;
522 }
524 HVM_DBG_LOG(DBG_LEVEL_VLAPIC, "offset 0x%x with length 0x%lx, "
525 "and the result is 0x%lx", offset, len, result);
527 return result;
529 exit_and_crash:
530 domain_crash(v->domain);
531 return 0;
532 }
534 static void vlapic_write(struct vcpu *v, unsigned long address,
535 unsigned long len, unsigned long val)
536 {
537 struct vlapic *vlapic = vcpu_vlapic(v);
538 unsigned int offset = address - vlapic_base_address(vlapic);
540 if ( offset != 0xb0 )
541 HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
542 "offset 0x%x with length 0x%lx, and value is 0x%lx",
543 offset, len, val);
545 /*
546 * According to the IA32 Manual, all accesses should be 32 bits.
547 * Some OSes do 8- or 16-byte accesses, however.
548 */
549 val &= 0xffffffff;
550 if ( len != 4 )
551 {
552 unsigned int tmp;
553 unsigned char alignment;
555 gdprintk(XENLOG_INFO, "Notice: Local APIC write with len = %lx\n",len);
557 alignment = offset & 0x3;
558 tmp = vlapic_read(v, offset & ~0x3, 4);
560 switch ( len )
561 {
562 case 1:
563 val = (tmp & ~(0xff << (8*alignment))) |
564 ((val & 0xff) << (8*alignment));
565 break;
567 case 2:
568 if ( alignment & 1 )
569 {
570 gdprintk(XENLOG_ERR, "Uneven alignment error for "
571 "2-byte vlapic access\n");
572 goto exit_and_crash;
573 }
575 val = (tmp & ~(0xffff << (8*alignment))) |
576 ((val & 0xffff) << (8*alignment));
577 break;
579 default:
580 gdprintk(XENLOG_ERR, "Local APIC write with len = %lx, "
581 "should be 4 instead\n", len);
582 exit_and_crash:
583 domain_crash(v->domain);
584 return;
585 }
586 }
588 offset &= 0xff0;
590 switch ( offset )
591 {
592 case APIC_TASKPRI:
593 vlapic_set_reg(vlapic, APIC_TASKPRI, val & 0xff);
594 hvm_update_vtpr(v, (val >> 4) & 0x0f);
595 break;
597 case APIC_EOI:
598 vlapic_EOI_set(vlapic);
599 break;
601 case APIC_LDR:
602 vlapic_set_reg(vlapic, APIC_LDR, val & APIC_LDR_MASK);
603 break;
605 case APIC_DFR:
606 vlapic_set_reg(vlapic, APIC_DFR, val | 0x0FFFFFFF);
607 break;
609 case APIC_SPIV:
610 vlapic_set_reg(vlapic, APIC_SPIV, val & 0x3ff);
612 if ( !(val & APIC_SPIV_APIC_ENABLED) )
613 {
614 int i;
615 uint32_t lvt_val;
617 vlapic->hw.disabled |= VLAPIC_SW_DISABLED;
619 for ( i = 0; i < VLAPIC_LVT_NUM; i++ )
620 {
621 lvt_val = vlapic_get_reg(vlapic, APIC_LVTT + 0x10 * i);
622 vlapic_set_reg(vlapic, APIC_LVTT + 0x10 * i,
623 lvt_val | APIC_LVT_MASKED);
624 }
625 }
626 else
627 vlapic->hw.disabled &= ~VLAPIC_SW_DISABLED;
628 break;
630 case APIC_ESR:
631 /* Nothing to do. */
632 break;
634 case APIC_ICR:
635 /* No delay here, so we always clear the pending bit*/
636 vlapic_set_reg(vlapic, APIC_ICR, val & ~(1 << 12));
637 vlapic_ipi(vlapic);
638 break;
640 case APIC_ICR2:
641 vlapic_set_reg(vlapic, APIC_ICR2, val & 0xff000000);
642 break;
644 case APIC_LVTT: /* LVT Timer Reg */
645 vlapic->pt.irq = val & APIC_VECTOR_MASK;
646 case APIC_LVTTHMR: /* LVT Thermal Monitor */
647 case APIC_LVTPC: /* LVT Performance Counter */
648 case APIC_LVT0: /* LVT LINT0 Reg */
649 case APIC_LVT1: /* LVT Lint1 Reg */
650 case APIC_LVTERR: /* LVT Error Reg */
651 if ( vlapic_sw_disabled(vlapic) )
652 val |= APIC_LVT_MASKED;
653 val &= vlapic_lvt_mask[(offset - APIC_LVTT) >> 4];
654 vlapic_set_reg(vlapic, offset, val);
655 break;
657 case APIC_TMICT:
658 {
659 uint64_t period = APIC_BUS_CYCLE_NS * (uint32_t)val * vlapic->hw.timer_divisor;
661 vlapic_set_reg(vlapic, APIC_TMICT, val);
662 create_periodic_time(current, &vlapic->pt, period, vlapic->pt.irq,
663 !vlapic_lvtt_period(vlapic), NULL, vlapic);
665 HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
666 "bus cycle is %uns, "
667 "initial count %lu, period %"PRIu64"ns",
668 APIC_BUS_CYCLE_NS, val, period);
669 }
670 break;
672 case APIC_TDCR:
673 vlapic_set_tdcr(vlapic, val & 0xb);
674 HVM_DBG_LOG(DBG_LEVEL_VLAPIC_TIMER, "timer divisor is 0x%x",
675 vlapic->hw.timer_divisor);
676 break;
678 default:
679 gdprintk(XENLOG_DEBUG,
680 "Local APIC Write to read-only register 0x%x\n", offset);
681 break;
682 }
683 }
685 static int vlapic_range(struct vcpu *v, unsigned long addr)
686 {
687 struct vlapic *vlapic = vcpu_vlapic(v);
688 unsigned long offset = addr - vlapic_base_address(vlapic);
689 return (!vlapic_hw_disabled(vlapic) && (offset < PAGE_SIZE));
690 }
692 struct hvm_mmio_handler vlapic_mmio_handler = {
693 .check_handler = vlapic_range,
694 .read_handler = vlapic_read,
695 .write_handler = vlapic_write
696 };
698 void vlapic_msr_set(struct vlapic *vlapic, uint64_t value)
699 {
700 if ( (vlapic->hw.apic_base_msr ^ value) & MSR_IA32_APICBASE_ENABLE )
701 {
702 if ( value & MSR_IA32_APICBASE_ENABLE )
703 {
704 vlapic_reset(vlapic);
705 vlapic->hw.disabled &= ~VLAPIC_HW_DISABLED;
706 }
707 else
708 {
709 vlapic->hw.disabled |= VLAPIC_HW_DISABLED;
710 }
711 }
713 vlapic->hw.apic_base_msr = value;
715 vmx_vlapic_msr_changed(vlapic_vcpu(vlapic));
717 HVM_DBG_LOG(DBG_LEVEL_VLAPIC,
718 "apic base msr is 0x%016"PRIx64, vlapic->hw.apic_base_msr);
719 }
721 int vlapic_accept_pic_intr(struct vcpu *v)
722 {
723 struct vlapic *vlapic = vcpu_vlapic(v);
724 uint32_t lvt0 = vlapic_get_reg(vlapic, APIC_LVT0);
726 /*
727 * Only CPU0 is wired to the 8259A. INTA cycles occur if LINT0 is set up
728 * accept ExtInts, or if the LAPIC is disabled (so LINT0 behaves as INTR).
729 */
730 return ((v->vcpu_id == 0) &&
731 (((lvt0 & (APIC_MODE_MASK|APIC_LVT_MASKED)) == APIC_DM_EXTINT) ||
732 vlapic_hw_disabled(vlapic)));
733 }
735 int vlapic_has_interrupt(struct vcpu *v)
736 {
737 struct vlapic *vlapic = vcpu_vlapic(v);
738 int highest_irr;
740 if ( !vlapic_enabled(vlapic) )
741 return -1;
743 highest_irr = vlapic_find_highest_irr(vlapic);
744 if ( (highest_irr == -1) ||
745 ((highest_irr & 0xF0) <= vlapic_get_ppr(vlapic)) )
746 return -1;
748 return highest_irr;
749 }
751 int cpu_get_apic_interrupt(struct vcpu *v)
752 {
753 int vector = vlapic_has_interrupt(v);
754 struct vlapic *vlapic = vcpu_vlapic(v);
756 if ( vector == -1 )
757 return -1;
759 vlapic_set_vector(vector, &vlapic->regs->data[APIC_ISR]);
760 vlapic_clear_irr(vector, vlapic);
761 return vector;
762 }
764 /* Reset the VLPAIC back to its power-on/reset state. */
765 void vlapic_reset(struct vlapic *vlapic)
766 {
767 struct vcpu *v = vlapic_vcpu(vlapic);
768 int i;
770 vlapic_set_reg(vlapic, APIC_ID, (v->vcpu_id * 2) << 24);
771 vlapic_set_reg(vlapic, APIC_LVR, VLAPIC_VERSION);
773 for ( i = 0; i < 8; i++ )
774 {
775 vlapic_set_reg(vlapic, APIC_IRR + 0x10 * i, 0);
776 vlapic_set_reg(vlapic, APIC_ISR + 0x10 * i, 0);
777 vlapic_set_reg(vlapic, APIC_TMR + 0x10 * i, 0);
778 }
779 vlapic_set_reg(vlapic, APIC_ICR, 0);
780 vlapic_set_reg(vlapic, APIC_ICR2, 0);
781 vlapic_set_reg(vlapic, APIC_LDR, 0);
782 vlapic_set_reg(vlapic, APIC_TASKPRI, 0);
783 vlapic_set_reg(vlapic, APIC_TMICT, 0);
784 vlapic_set_reg(vlapic, APIC_TMCCT, 0);
785 vlapic_set_tdcr(vlapic, 0);
787 vlapic_set_reg(vlapic, APIC_DFR, 0xffffffffU);
789 for ( i = 0; i < VLAPIC_LVT_NUM; i++ )
790 vlapic_set_reg(vlapic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
792 vlapic_set_reg(vlapic, APIC_SPIV, 0xff);
793 vlapic->hw.disabled |= VLAPIC_SW_DISABLED;
794 }
796 #ifdef HVM_DEBUG_SUSPEND
797 static void lapic_info(struct vlapic *s)
798 {
799 printk("*****lapic state:*****\n");
800 printk("lapic 0x%"PRIx64".\n", s->hw.apic_base_msr);
801 printk("lapic 0x%x.\n", s->hw.disabled);
802 printk("lapic 0x%x.\n", s->hw.timer_divisor);
803 }
804 #else
805 static void lapic_info(struct vlapic *s)
806 {
807 }
808 #endif
810 /* rearm the actimer if needed, after a HVM restore */
811 static void lapic_rearm(struct vlapic *s)
812 {
813 unsigned long tmict;
815 tmict = vlapic_get_reg(s, APIC_TMICT);
816 if (tmict > 0) {
817 uint64_t period = APIC_BUS_CYCLE_NS * (uint32_t)tmict * s->hw.timer_divisor;
818 uint32_t lvtt = vlapic_get_reg(s, APIC_LVTT);
820 s->pt.irq = lvtt & APIC_VECTOR_MASK;
821 create_periodic_time(vlapic_vcpu(s), &s->pt, period, s->pt.irq,
822 !vlapic_lvtt_period(s), NULL, s);
824 printk("lapic_load to rearm the actimer:"
825 "bus cycle is %uns, "
826 "saved tmict count %lu, period %"PRIu64"ns, irq=%"PRIu8"\n",
827 APIC_BUS_CYCLE_NS, tmict, period, s->pt.irq);
828 }
830 lapic_info(s);
831 }
833 static int lapic_save_hidden(struct domain *d, hvm_domain_context_t *h)
834 {
835 struct vcpu *v;
836 struct vlapic *s;
838 for_each_vcpu(d, v)
839 {
840 s = vcpu_vlapic(v);
841 lapic_info(s);
843 if ( hvm_save_entry(LAPIC, v->vcpu_id, h, &s->hw) != 0 )
844 return 1;
845 }
846 return 0;
847 }
849 static int lapic_save_regs(struct domain *d, hvm_domain_context_t *h)
850 {
851 struct vcpu *v;
852 struct vlapic *s;
854 for_each_vcpu(d, v)
855 {
856 s = vcpu_vlapic(v);
857 if ( hvm_save_entry(LAPIC_REGS, v->vcpu_id, h, s->regs) != 0 )
858 return 1;
859 }
860 return 0;
861 }
863 static int lapic_load_hidden(struct domain *d, hvm_domain_context_t *h)
864 {
865 uint16_t vcpuid;
866 struct vcpu *v;
867 struct vlapic *s;
869 /* Which vlapic to load? */
870 vcpuid = hvm_load_instance(h);
871 if ( vcpuid > MAX_VIRT_CPUS || (v = d->vcpu[vcpuid]) == NULL )
872 {
873 gdprintk(XENLOG_ERR, "HVM restore: domain has no vlapic %u\n", vcpuid);
874 return -EINVAL;
875 }
876 s = vcpu_vlapic(v);
878 if ( hvm_load_entry(LAPIC, h, &s->hw) != 0 )
879 return -EINVAL;
881 lapic_info(s);
883 vmx_vlapic_msr_changed(v);
885 return 0;
886 }
888 static int lapic_load_regs(struct domain *d, hvm_domain_context_t *h)
889 {
890 uint16_t vcpuid;
891 struct vcpu *v;
892 struct vlapic *s;
894 /* Which vlapic to load? */
895 vcpuid = hvm_load_instance(h);
896 if ( vcpuid > MAX_VIRT_CPUS || (v = d->vcpu[vcpuid]) == NULL )
897 {
898 gdprintk(XENLOG_ERR, "HVM restore: domain has no vlapic %u\n", vcpuid);
899 return -EINVAL;
900 }
901 s = vcpu_vlapic(v);
903 if ( hvm_load_entry(LAPIC_REGS, h, s->regs) != 0 )
904 return -EINVAL;
906 lapic_rearm(s);
907 return 0;
908 }
910 HVM_REGISTER_SAVE_RESTORE(LAPIC, lapic_save_hidden, lapic_load_hidden,
911 1, HVMSR_PER_VCPU);
912 HVM_REGISTER_SAVE_RESTORE(LAPIC_REGS, lapic_save_regs, lapic_load_regs,
913 1, HVMSR_PER_VCPU);
915 int vlapic_init(struct vcpu *v)
916 {
917 struct vlapic *vlapic = vcpu_vlapic(v);
919 HVM_DBG_LOG(DBG_LEVEL_VLAPIC, "%d", v->vcpu_id);
921 vlapic->regs_page = alloc_domheap_page(NULL);
922 if ( vlapic->regs_page == NULL )
923 {
924 dprintk(XENLOG_ERR, "alloc vlapic regs error: %d/%d\n",
925 v->domain->domain_id, v->vcpu_id);
926 return -ENOMEM;
927 }
929 vlapic->regs = map_domain_page_global(page_to_mfn(vlapic->regs_page));
930 if ( vlapic->regs == NULL )
931 {
932 dprintk(XENLOG_ERR, "map vlapic regs error: %d/%d\n",
933 v->domain->domain_id, v->vcpu_id);
934 return -ENOMEM;
935 }
937 clear_page(vlapic->regs);
939 vlapic_reset(vlapic);
941 vlapic->hw.apic_base_msr = (MSR_IA32_APICBASE_ENABLE |
942 APIC_DEFAULT_PHYS_BASE);
943 if ( v->vcpu_id == 0 )
944 vlapic->hw.apic_base_msr |= MSR_IA32_APICBASE_BSP;
946 return 0;
947 }
949 void vlapic_destroy(struct vcpu *v)
950 {
951 struct vlapic *vlapic = vcpu_vlapic(v);
953 destroy_periodic_time(&vlapic->pt);
954 unmap_domain_page_global(vlapic->regs);
955 free_domheap_page(vlapic->regs_page);
956 }
958 int is_lvtt(struct vcpu *v, int vector)
959 {
960 return vcpu_vlapic(v)->pt.enabled &&
961 vector == vlapic_lvt_vector(vcpu_vlapic(v), APIC_LVTT);
962 }
964 int is_lvtt_enabled(struct vcpu *v)
965 {
966 if ( unlikely(!vlapic_enabled(vcpu_vlapic(v))) ||
967 !vlapic_lvt_enabled(vcpu_vlapic(v), APIC_LVTT))
968 return 0;
970 return 1;
971 }