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view xen/include/asm-x86/processor.h @ 3280:dda5ab69e74a

bitkeeper revision 1.1159.1.477 (41bf20d2wgoxIqhcE0nzBC8W-yFPhg)

sync w/ head.
author cl349@arcadians.cl.cam.ac.uk
date Tue Dec 14 17:20:18 2004 +0000 (2004-12-14)
parents c23dd7ec1f54 da409d40699a
children eb8866af6c4b
line source
1 /*
2 * include/asm-x86/processor.h
3 *
4 * Copyright (C) 1994 Linus Torvalds
5 */
7 #ifndef __ASM_X86_PROCESSOR_H
8 #define __ASM_X86_PROCESSOR_H
10 #ifndef __ASSEMBLY__
11 #include <asm/page.h>
12 #include <asm/types.h>
13 #include <asm/cpufeature.h>
14 #include <asm/desc.h>
15 #include <asm/flushtlb.h>
16 #include <asm/pdb.h>
17 #include <xen/config.h>
18 #include <xen/spinlock.h>
19 #include <public/xen.h>
20 #endif
22 /*
23 * CPU vendor IDs
24 */
25 #define X86_VENDOR_INTEL 0
26 #define X86_VENDOR_CYRIX 1
27 #define X86_VENDOR_AMD 2
28 #define X86_VENDOR_UMC 3
29 #define X86_VENDOR_NEXGEN 4
30 #define X86_VENDOR_CENTAUR 5
31 #define X86_VENDOR_RISE 6
32 #define X86_VENDOR_TRANSMETA 7
33 #define X86_VENDOR_NSC 8
34 #define X86_VENDOR_SIS 9
35 #define X86_VENDOR_NUM 10
36 #define X86_VENDOR_UNKNOWN 0xff
38 /*
39 * EFLAGS bits
40 */
41 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
42 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
43 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
44 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
45 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
46 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
47 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
48 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
49 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
50 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
51 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
52 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
53 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
54 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
55 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
56 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
57 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
59 /*
60 * Intel CPU flags in CR0
61 */
62 #define X86_CR0_PE 0x00000001 /* Enable Protected Mode (RW) */
63 #define X86_CR0_MP 0x00000002 /* Monitor Coprocessor (RW) */
64 #define X86_CR0_EM 0x00000004 /* Require FPU Emulation (RO) */
65 #define X86_CR0_TS 0x00000008 /* Task Switched (RW) */
66 #define X86_CR0_NE 0x00000020 /* Numeric Error Reporting (RW) */
67 #define X86_CR0_WP 0x00010000 /* Supervisor Write Protect (RW) */
68 #define X86_CR0_AM 0x00040000 /* Alignment Checking (RW) */
69 #define X86_CR0_NW 0x20000000 /* Not Write-Through (RW) */
70 #define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */
71 #define X86_CR0_PG 0x80000000 /* Paging (RW) */
73 /*
74 * Intel CPU features in CR4
75 */
76 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
77 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
78 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
79 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
80 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
81 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
82 #define X86_CR4_MCE 0x0040 /* Machine check enable */
83 #define X86_CR4_PGE 0x0080 /* enable global pages */
84 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
85 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
86 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
88 /*
89 * Trap/fault mnemonics.
90 */
91 #define TRAP_divide_error 0
92 #define TRAP_debug 1
93 #define TRAP_nmi 2
94 #define TRAP_int3 3
95 #define TRAP_overflow 4
96 #define TRAP_bounds 5
97 #define TRAP_invalid_op 6
98 #define TRAP_no_device 7
99 #define TRAP_double_fault 8
100 #define TRAP_copro_seg 9
101 #define TRAP_invalid_tss 10
102 #define TRAP_no_segment 11
103 #define TRAP_stack_error 12
104 #define TRAP_gp_fault 13
105 #define TRAP_page_fault 14
106 #define TRAP_spurious_int 15
107 #define TRAP_copro_error 16
108 #define TRAP_alignment_check 17
109 #define TRAP_machine_check 18
110 #define TRAP_simd_error 19
112 /*
113 * Non-fatal fault/trap handlers return an error code to the caller. If the
114 * code is non-zero, it means that either the exception was not due to a fault
115 * (i.e., it was a trap) or that the fault has been fixed up so the instruction
116 * replay ought to succeed.
117 */
118 #define EXCRET_not_a_fault 1 /* It was a trap. No instruction replay needed. */
119 #define EXCRET_fault_fixed 1 /* It was fault that we fixed: try a replay. */
121 /*
122 * 'trap_bounce' flags values.
123 */
124 #define TBF_EXCEPTION 1
125 #define TBF_EXCEPTION_ERRCODE 2
126 #define TBF_EXCEPTION_CR2 4
127 #define TBF_INTERRUPT 8
128 #define TBF_FAILSAFE 16
130 /*
131 * thread.flags values.
132 */
133 #define TF_failsafe_return 1
135 #ifndef __ASSEMBLY__
137 struct domain;
138 struct exec_domain;
140 /*
141 * Default implementation of macro that returns current
142 * instruction pointer ("program counter").
143 */
144 #ifdef __x86_64__
145 #define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })
146 #else
147 #define current_text_addr() \
148 ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
149 #endif
151 /*
152 * CPU type and hardware bug flags. Kept separately for each CPU.
153 * Members of this structure are referenced in head.S, so think twice
154 * before touching them. [mj]
155 */
157 struct cpuinfo_x86 {
158 __u8 x86; /* CPU family */
159 __u8 x86_vendor; /* CPU vendor */
160 __u8 x86_model;
161 __u8 x86_mask;
162 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
163 __u32 x86_capability[NCAPINTS];
164 char x86_vendor_id[16];
165 int x86_cache_size; /* in KB - for CPUS that support this call */
166 int x86_clflush_size;
167 int x86_tlbsize; /* number of 4K pages in DTLB/ITLB combined */
168 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
170 /*
171 * capabilities of CPUs
172 */
174 extern struct cpuinfo_x86 boot_cpu_data;
175 extern struct tss_struct init_tss[NR_CPUS];
177 #ifdef CONFIG_SMP
178 extern struct cpuinfo_x86 cpu_data[];
179 #define current_cpu_data cpu_data[smp_processor_id()]
180 #else
181 #define cpu_data (&boot_cpu_data)
182 #define current_cpu_data boot_cpu_data
183 #endif
185 extern char ignore_irq13;
187 extern void identify_cpu(struct cpuinfo_x86 *);
188 extern void print_cpu_info(struct cpuinfo_x86 *);
189 extern void dodgy_tsc(void);
191 /*
192 * Generic CPUID function
193 */
194 static inline void cpuid(int op, int *eax, int *ebx, int *ecx, int *edx)
195 {
196 __asm__("cpuid"
197 : "=a" (*eax),
198 "=b" (*ebx),
199 "=c" (*ecx),
200 "=d" (*edx)
201 : "0" (op));
202 }
204 /*
205 * CPUID functions returning a single datum
206 */
207 static inline unsigned int cpuid_eax(unsigned int op)
208 {
209 unsigned int eax;
211 __asm__("cpuid"
212 : "=a" (eax)
213 : "0" (op)
214 : "bx", "cx", "dx");
215 return eax;
216 }
217 static inline unsigned int cpuid_ebx(unsigned int op)
218 {
219 unsigned int eax, ebx;
221 __asm__("cpuid"
222 : "=a" (eax), "=b" (ebx)
223 : "0" (op)
224 : "cx", "dx" );
225 return ebx;
226 }
227 static inline unsigned int cpuid_ecx(unsigned int op)
228 {
229 unsigned int eax, ecx;
231 __asm__("cpuid"
232 : "=a" (eax), "=c" (ecx)
233 : "0" (op)
234 : "bx", "dx" );
235 return ecx;
236 }
237 static inline unsigned int cpuid_edx(unsigned int op)
238 {
239 unsigned int eax, edx;
241 __asm__("cpuid"
242 : "=a" (eax), "=d" (edx)
243 : "0" (op)
244 : "bx", "cx");
245 return edx;
246 }
249 #define read_cr0() ({ \
250 unsigned long __dummy; \
251 __asm__( \
252 "mov"__OS" %%cr0,%0\n\t" \
253 :"=r" (__dummy)); \
254 __dummy; \
255 })
257 #define write_cr0(x) \
258 __asm__("mov"__OS" %0,%%cr0": :"r" ((unsigned long)x));
260 #define read_cr4() ({ \
261 unsigned long __dummy; \
262 __asm__( \
263 "mov"__OS" %%cr4,%0\n\t" \
264 :"=r" (__dummy)); \
265 __dummy; \
266 })
268 #define write_cr4(x) \
269 __asm__("mov"__OS" %0,%%cr4": :"r" ((unsigned long)x));
271 /*
272 * Save the cr4 feature set we're using (ie
273 * Pentium 4MB enable and PPro Global page
274 * enable), so that any CPU's that boot up
275 * after us can get the correct flags.
276 */
277 extern unsigned long mmu_cr4_features;
279 static inline void set_in_cr4 (unsigned long mask)
280 {
281 mmu_cr4_features |= mask;
282 __asm__("mov"__OS" %%cr4,%%"__OP"ax\n\t"
283 "or"__OS" %0,%%"__OP"ax\n\t"
284 "mov"__OS" %%"__OP"ax,%%cr4\n"
285 : : "irg" (mask)
286 :"ax");
287 }
289 static inline void clear_in_cr4 (unsigned long mask)
290 {
291 mmu_cr4_features &= ~mask;
292 __asm__("mov"__OS" %%cr4,%%"__OP"ax\n\t"
293 "and"__OS" %0,%%"__OP"ax\n\t"
294 "mov"__OS" %%"__OP"ax,%%cr4\n"
295 : : "irg" (~mask)
296 :"ax");
297 }
299 /*
300 * NSC/Cyrix CPU configuration register indexes
301 */
303 #define CX86_PCR0 0x20
304 #define CX86_GCR 0xb8
305 #define CX86_CCR0 0xc0
306 #define CX86_CCR1 0xc1
307 #define CX86_CCR2 0xc2
308 #define CX86_CCR3 0xc3
309 #define CX86_CCR4 0xe8
310 #define CX86_CCR5 0xe9
311 #define CX86_CCR6 0xea
312 #define CX86_CCR7 0xeb
313 #define CX86_PCR1 0xf0
314 #define CX86_DIR0 0xfe
315 #define CX86_DIR1 0xff
316 #define CX86_ARR_BASE 0xc4
317 #define CX86_RCR_BASE 0xdc
319 /*
320 * NSC/Cyrix CPU indexed register access macros
321 */
323 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
325 #define setCx86(reg, data) do { \
326 outb((reg), 0x22); \
327 outb((data), 0x23); \
328 } while (0)
330 #define IOBMP_BYTES 8192
331 #define IOBMP_BYTES_PER_SELBIT (IOBMP_BYTES / 64)
332 #define IOBMP_BITS_PER_SELBIT (IOBMP_BYTES_PER_SELBIT * 8)
333 #define IOBMP_OFFSET offsetof(struct tss_struct, io_bitmap)
334 #define IOBMP_INVALID_OFFSET 0x8000
336 struct i387_state {
337 u8 state[512]; /* big enough for FXSAVE */
338 } __attribute__ ((aligned (16)));
340 struct tss_struct {
341 unsigned short back_link,__blh;
342 #ifdef __x86_64__
343 u64 rsp0;
344 u64 rsp1;
345 u64 rsp2;
346 u64 reserved1;
347 u64 ist[7];
348 u64 reserved2;
349 u16 reserved3;
350 #else
351 u32 esp0;
352 u16 ss0,__ss0h;
353 u32 esp1;
354 u16 ss1,__ss1h;
355 u32 esp2;
356 u16 ss2,__ss2h;
357 u32 __cr3;
358 u32 eip;
359 u32 eflags;
360 u32 eax,ecx,edx,ebx;
361 u32 esp;
362 u32 ebp;
363 u32 esi;
364 u32 edi;
365 u16 es, __esh;
366 u16 cs, __csh;
367 u16 ss, __ssh;
368 u16 ds, __dsh;
369 u16 fs, __fsh;
370 u16 gs, __gsh;
371 u16 ldt, __ldth;
372 u16 trace;
373 #endif
374 u16 bitmap;
375 u8 io_bitmap[IOBMP_BYTES+1];
376 /* Pads the TSS to be cacheline-aligned (total size is 0x2080). */
377 u8 __cacheline_filler[23];
378 };
380 struct trap_bounce {
381 unsigned long error_code;
382 unsigned long cr2;
383 unsigned short flags; /* TBF_ */
384 unsigned short cs;
385 unsigned long eip;
386 };
388 struct thread_struct {
389 unsigned long guestos_sp;
390 unsigned long guestos_ss;
392 unsigned long flags; /* TF_ */
394 /* Hardware debugging registers */
395 unsigned long debugreg[8]; /* %%db0-7 debug registers */
397 /* floating point info */
398 struct i387_state i387;
400 /* general user-visible register state */
401 execution_context_t user_ctxt;
403 void (*schedule_tail) (struct domain *);
405 /*
406 * Return vectors pushed to us by guest OS.
407 * The stack frame for events is exactly that of an x86 hardware interrupt.
408 * The stack frame for a failsafe callback is augmented with saved values
409 * for segment registers %ds, %es, %fs and %gs:
410 * %ds, %es, %fs, %gs, %eip, %cs, %eflags [, %oldesp, %oldss]
411 */
412 unsigned long event_selector; /* 08: entry CS */
413 unsigned long event_address; /* 12: entry EIP */
415 unsigned long failsafe_selector; /* 16: entry CS */
416 unsigned long failsafe_address; /* 20: entry EIP */
418 /* Bounce information for propagating an exception to guest OS. */
419 struct trap_bounce trap_bounce;
421 /* I/O-port access bitmap. */
422 u64 io_bitmap_sel; /* Selector to tell us which part of the IO bitmap are
423 * "interesting" (i.e. have clear bits) */
424 u8 *io_bitmap; /* Pointer to task's IO bitmap or NULL */
426 /* Trap info. */
427 #ifdef __i386__
428 int fast_trap_idx;
429 struct desc_struct fast_trap_desc;
430 #endif
431 trap_info_t traps[256];
432 };
434 #define IDT_ENTRIES 256
435 extern struct desc_struct idt_table[];
436 extern struct desc_struct *idt_tables[];
438 #if defined(__i386__)
440 #define SET_DEFAULT_FAST_TRAP(_p) \
441 (_p)->fast_trap_idx = 0x20; \
442 (_p)->fast_trap_desc.a = 0; \
443 (_p)->fast_trap_desc.b = 0;
445 #define CLEAR_FAST_TRAP(_p) \
446 (memset(idt_tables[smp_processor_id()] + (_p)->fast_trap_idx, \
447 0, 8))
449 #ifdef XEN_DEBUGGER
450 #define SET_FAST_TRAP(_p) \
451 (pdb_initialized ? (void *) 0 : \
452 (memcpy(idt_tables[smp_processor_id()] + (_p)->fast_trap_idx, \
453 &((_p)->fast_trap_desc), 8)))
454 #else
455 #define SET_FAST_TRAP(_p) \
456 (memcpy(idt_tables[smp_processor_id()] + (_p)->fast_trap_idx, \
457 &((_p)->fast_trap_desc), 8))
458 #endif
460 long set_fast_trap(struct exec_domain *p, int idx);
462 #endif
464 #define INIT_THREAD { 0 }
466 extern int gpf_emulate_4gb(struct xen_regs *regs);
468 struct mm_struct {
469 /*
470 * Every domain has a L1 pagetable of its own. Per-domain mappings
471 * are put in this table (eg. the current GDT is mapped here).
472 */
473 l1_pgentry_t *perdomain_ptes;
474 pagetable_t pagetable;
476 /* shadow mode status and controls */
477 unsigned int shadow_mode; /* flags to control shadow table operation */
478 pagetable_t shadow_table;
479 spinlock_t shadow_lock;
480 unsigned int shadow_max_page_count; // currently unused
482 /* shadow hashtable */
483 struct shadow_status *shadow_ht;
484 struct shadow_status *shadow_ht_free;
485 struct shadow_status *shadow_ht_extras; /* extra allocation units */
486 unsigned int shadow_extras_count;
488 /* shadow dirty bitmap */
489 unsigned long *shadow_dirty_bitmap;
490 unsigned int shadow_dirty_bitmap_size; /* in pages, bit per page */
492 /* shadow mode stats */
493 unsigned int shadow_page_count;
494 unsigned int shadow_fault_count;
495 unsigned int shadow_dirty_count;
496 unsigned int shadow_dirty_net_count;
497 unsigned int shadow_dirty_block_count;
499 /* Current LDT details. */
500 unsigned long ldt_base, ldt_ents, shadow_ldt_mapcnt;
501 /* Next entry is passed to LGDT on domain switch. */
502 char gdt[10]; /* NB. 10 bytes needed for x86_64. Use 6 bytes for x86_32. */
503 };
505 static inline void write_ptbase(struct mm_struct *mm)
506 {
507 unsigned long pa;
509 if ( unlikely(mm->shadow_mode) )
510 pa = pagetable_val(mm->shadow_table);
511 else
512 pa = pagetable_val(mm->pagetable);
514 write_cr3(pa);
515 }
517 #define IDLE0_MM \
518 { \
519 perdomain_ptes: 0, \
520 pagetable: mk_pagetable(__pa(idle_pg_table)) \
521 }
523 /* Convenient accessor for mm.gdt. */
524 #define SET_GDT_ENTRIES(_p, _e) ((*(u16 *)((_p)->mm.gdt + 0)) = (((_e)<<3)-1))
525 #define SET_GDT_ADDRESS(_p, _a) ((*(unsigned long *)((_p)->mm.gdt + 2)) = (_a))
526 #define GET_GDT_ENTRIES(_p) (((*(u16 *)((_p)->mm.gdt + 0))+1)>>3)
527 #define GET_GDT_ADDRESS(_p) (*(unsigned long *)((_p)->mm.gdt + 2))
529 void destroy_gdt(struct exec_domain *d);
530 long set_gdt(struct exec_domain *d,
531 unsigned long *frames,
532 unsigned int entries);
534 long set_debugreg(struct exec_domain *p, int reg, unsigned long value);
536 struct microcode {
537 unsigned int hdrver;
538 unsigned int rev;
539 unsigned int date;
540 unsigned int sig;
541 unsigned int cksum;
542 unsigned int ldrver;
543 unsigned int pf;
544 unsigned int reserved[5];
545 unsigned int bits[500];
546 };
548 /* '6' because it used to be for P6 only (but now covers Pentium 4 as well) */
549 #define MICROCODE_IOCFREE _IO('6',0)
551 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
552 static inline void rep_nop(void)
553 {
554 __asm__ __volatile__("rep;nop");
555 }
557 #define cpu_relax() rep_nop()
559 /* Prefetch instructions for Pentium III and AMD Athlon */
560 #ifdef CONFIG_MPENTIUMIII
562 #define ARCH_HAS_PREFETCH
563 extern inline void prefetch(const void *x)
564 {
565 __asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x));
566 }
568 #elif CONFIG_X86_USE_3DNOW
570 #define ARCH_HAS_PREFETCH
571 #define ARCH_HAS_PREFETCHW
572 #define ARCH_HAS_SPINLOCK_PREFETCH
574 extern inline void prefetch(const void *x)
575 {
576 __asm__ __volatile__ ("prefetch (%0)" : : "r"(x));
577 }
579 extern inline void prefetchw(const void *x)
580 {
581 __asm__ __volatile__ ("prefetchw (%0)" : : "r"(x));
582 }
583 #define spin_lock_prefetch(x) prefetchw(x)
585 #endif
587 void show_guest_stack();
588 void show_trace(unsigned long *esp);
589 void show_stack(unsigned long *esp);
590 void show_registers(struct xen_regs *regs);
591 asmlinkage void fatal_trap(int trapnr, struct xen_regs *regs);
593 #endif /* !__ASSEMBLY__ */
595 #endif /* __ASM_X86_PROCESSOR_H */