direct-io.hg

view xen/include/asm-x86/config.h @ 8686:c0a0f4db5ab1

Create a block of reserved PFNs in shadow translate mode guests, and
move the shared info and grant table pfns into that block. This
allows us to remove the get_gnttablist dom0 op, and simplifies the
domain creation code slightly. Having the reserved block managed by
Xen may also make it slightly easier to handle the case where the
grant table needs to be extended at run time.

Suggested-by: kaf24
Signed-off-by: Steven Smith, sos22@cam.ac.uk
author sos22@douglas.cl.cam.ac.uk
date Thu Jan 26 19:40:13 2006 +0100 (2006-01-26)
parents 1572681e4e5a
children 1db05e589fa0
line source
1 /******************************************************************************
2 * config.h
3 *
4 * A Linux-style configuration list.
5 */
7 #ifndef __X86_CONFIG_H__
8 #define __X86_CONFIG_H__
10 #if defined(__x86_64__)
11 # define CONFIG_PAGING_LEVELS 4
12 #elif defined(CONFIG_X86_PAE)
13 # define CONFIG_PAGING_LEVELS 3
14 #else
15 # define CONFIG_PAGING_LEVELS 2
16 #endif
18 #define CONFIG_X86 1
19 #define CONFIG_X86_HT 1
20 #define CONFIG_SHADOW 1
21 #define CONFIG_VMX 1
22 #define CONFIG_SMP 1
23 #define CONFIG_X86_LOCAL_APIC 1
24 #define CONFIG_X86_GOOD_APIC 1
25 #define CONFIG_X86_IO_APIC 1
26 #define CONFIG_HPET_TIMER 1
28 /* Intel P4 currently has largest cache line (L2 line size is 128 bytes). */
29 #define CONFIG_X86_L1_CACHE_SHIFT 7
31 #define CONFIG_ACPI 1
32 #define CONFIG_ACPI_BOOT 1
34 #define HZ 100
36 #define OPT_CONSOLE_STR "com1,vga"
38 #define NR_CPUS 32
40 /* Linkage for x86 */
41 #define __ALIGN .align 16,0x90
42 #define __ALIGN_STR ".align 16,0x90"
43 #ifdef __ASSEMBLY__
44 #define ALIGN __ALIGN
45 #define ALIGN_STR __ALIGN_STR
46 #define ENTRY(name) \
47 .globl name; \
48 ALIGN; \
49 name:
50 #endif
52 #define barrier() __asm__ __volatile__("": : :"memory")
54 #define NR_hypercalls 32
56 #ifndef NDEBUG
57 #define MEMORY_GUARD
58 #ifdef __x86_64__
59 #define STACK_ORDER 2
60 #endif
61 #endif
63 /* How large is the PFN reserved area, when we have one? */
64 #define PFN_HOLE_SIZE 32
66 #ifndef STACK_ORDER
67 #define STACK_ORDER 1
68 #endif
69 #define STACK_SIZE (PAGE_SIZE << STACK_ORDER)
71 #ifndef __ASSEMBLY__
72 extern unsigned long _end; /* standard ELF symbol */
73 #endif /* __ASSEMBLY__ */
75 #define FORCE_CRASH() __asm__ __volatile__ ( "ud2" )
77 #if defined(__x86_64__)
79 #define CONFIG_X86_64 1
81 #define asmlinkage
83 #define XENHEAP_DEFAULT_MB (16)
85 #define PML4_ENTRY_BITS 39
86 #ifndef __ASSEMBLY__
87 #define PML4_ENTRY_BYTES (1UL << PML4_ENTRY_BITS)
88 #define PML4_ADDR(_slot) \
89 ((((_slot ## UL) >> 8) * 0xffff000000000000UL) | \
90 (_slot ## UL << PML4_ENTRY_BITS))
91 #else
92 #define PML4_ENTRY_BYTES (1 << PML4_ENTRY_BITS)
93 #define PML4_ADDR(_slot) \
94 (((_slot >> 8) * 0xffff000000000000) | (_slot << PML4_ENTRY_BITS))
95 #endif
97 /*
98 * Memory layout:
99 * 0x0000000000000000 - 0x00007fffffffffff [128TB, 2^47 bytes, PML4:0-255]
100 * Guest-defined use.
101 * 0x0000800000000000 - 0xffff7fffffffffff [16EB]
102 * Inaccessible: current arch only supports 48-bit sign-extended VAs.
103 * 0xffff800000000000 - 0xffff803fffffffff [256GB, 2^38 bytes, PML4:256]
104 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
105 * 0xffff804000000000 - 0xffff807fffffffff [256GB, 2^38 bytes, PML4:256]
106 * Reserved for future shared info with the guest OS (GUEST ACCESSIBLE).
107 * 0xffff808000000000 - 0xffff80ffffffffff [512GB, 2^39 bytes, PML4:257]
108 * Read-only guest linear page table (GUEST ACCESSIBLE).
109 * 0xffff810000000000 - 0xffff817fffffffff [512GB, 2^39 bytes, PML4:258]
110 * Guest linear page table.
111 * 0xffff818000000000 - 0xffff81ffffffffff [512GB, 2^39 bytes, PML4:259]
112 * Shadow linear page table.
113 * 0xffff820000000000 - 0xffff827fffffffff [512GB, 2^39 bytes, PML4:260]
114 * Per-domain mappings (e.g., GDT, LDT).
115 * 0xffff828000000000 - 0xffff8283ffffffff [16GB, 2^34 bytes, PML4:261]
116 * Machine-to-phys translation table.
117 * 0xffff828400000000 - 0xffff8287ffffffff [16GB, 2^34 bytes, PML4:261]
118 * Page-frame information array.
119 * 0xffff828800000000 - 0xffff828bffffffff [16GB, 2^34 bytes, PML4:261]
120 * ioremap()/fixmap area.
121 * 0xffff828c00000000 - 0xffff82ffffffffff [464GB, PML4:261]
122 * Reserved for future use.
123 * 0xffff830000000000 - 0xffff83ffffffffff [1TB, 2^40 bytes, PML4:262-263]
124 * 1:1 direct mapping of all physical memory. Xen and its heap live here.
125 * 0xffff840000000000 - 0xffff87ffffffffff [4TB, 2^42 bytes, PML4:264-271]
126 * Reserved for future use.
127 * 0xffff880000000000 - 0xffffffffffffffff [120TB, PML4:272-511]
128 * Guest-defined use.
129 */
132 #define ROOT_PAGETABLE_FIRST_XEN_SLOT 256
133 #define ROOT_PAGETABLE_LAST_XEN_SLOT 271
134 #define ROOT_PAGETABLE_XEN_SLOTS \
135 (ROOT_PAGETABLE_LAST_XEN_SLOT - ROOT_PAGETABLE_FIRST_XEN_SLOT + 1)
137 /* Hypervisor reserves PML4 slots 256 to 271 inclusive. */
138 #define HYPERVISOR_VIRT_START (PML4_ADDR(256))
139 #define HYPERVISOR_VIRT_END (HYPERVISOR_VIRT_START + PML4_ENTRY_BYTES*16)
140 /* Slot 256: read-only guest-accessible machine-to-phys translation table. */
141 #define RO_MPT_VIRT_START (PML4_ADDR(256))
142 #define RO_MPT_VIRT_END (RO_MPT_VIRT_START + PML4_ENTRY_BYTES/2)
143 /* Slot 257: read-only guest-accessible linear page table. */
144 #define RO_LINEAR_PT_VIRT_START (PML4_ADDR(257))
145 #define RO_LINEAR_PT_VIRT_END (RO_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
146 /* Slot 258: linear page table (guest table). */
147 #define LINEAR_PT_VIRT_START (PML4_ADDR(258))
148 #define LINEAR_PT_VIRT_END (LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
149 /* Slot 259: linear page table (shadow table). */
150 #define SH_LINEAR_PT_VIRT_START (PML4_ADDR(259))
151 #define SH_LINEAR_PT_VIRT_END (SH_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
152 /* Slot 260: per-domain mappings. */
153 #define PERDOMAIN_VIRT_START (PML4_ADDR(260))
154 #define PERDOMAIN_VIRT_END (PERDOMAIN_VIRT_START + (PERDOMAIN_MBYTES<<20))
155 #define PERDOMAIN_MBYTES ((unsigned long)GDT_LDT_MBYTES)
156 /* Slot 261: machine-to-phys conversion table (16GB). */
157 #define RDWR_MPT_VIRT_START (PML4_ADDR(261))
158 #define RDWR_MPT_VIRT_END (RDWR_MPT_VIRT_START + (16UL<<30))
159 /* Slot 261: page-frame information array (16GB). */
160 #define FRAMETABLE_VIRT_START (RDWR_MPT_VIRT_END)
161 #define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + (16UL<<30))
162 /* Slot 261: ioremap()/fixmap area (16GB). */
163 #define IOREMAP_VIRT_START (FRAMETABLE_VIRT_END)
164 #define IOREMAP_VIRT_END (IOREMAP_VIRT_START + (16UL<<30))
165 /* Slot 262-263: A direct 1:1 mapping of all of physical memory. */
166 #define DIRECTMAP_VIRT_START (PML4_ADDR(262))
167 #define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + PML4_ENTRY_BYTES*2)
169 #define PGT_base_page_table PGT_l4_page_table
171 #define __HYPERVISOR_CS64 0xe010
172 #define __HYPERVISOR_CS32 0xe008
173 #define __HYPERVISOR_CS __HYPERVISOR_CS64
174 #define __HYPERVISOR_DS64 0x0000
175 #define __HYPERVISOR_DS32 0xe018
176 #define __HYPERVISOR_DS __HYPERVISOR_DS64
178 #define __GUEST_CS64 0xe033
179 #define __GUEST_CS32 0xe023
180 #define __GUEST_CS __GUEST_CS64
181 #define __GUEST_DS 0x0000
182 #define __GUEST_SS 0xe02b
184 /* For generic assembly code: use macros to define operation/operand sizes. */
185 #define __OS "q" /* Operation Suffix */
186 #define __OP "r" /* Operand Prefix */
187 #define __FIXUP_ALIGN ".align 8"
188 #define __FIXUP_WORD ".quad"
190 #elif defined(__i386__)
192 #define CONFIG_X86_32 1
193 #define CONFIG_DOMAIN_PAGE 1
195 #define asmlinkage __attribute__((regparm(0)))
197 /*
198 * Memory layout (high to low): SIZE PAE-SIZE
199 * ------ ------
200 * I/O remapping area ( 4MB)
201 * Direct-map (1:1) area [Xen code/data/heap] (12MB)
202 * Per-domain mappings (inc. 4MB map_domain_page cache) ( 4MB)
203 * Shadow linear pagetable ( 4MB) ( 8MB)
204 * Guest linear pagetable ( 4MB) ( 8MB)
205 * Machine-to-physical translation table [writable] ( 4MB) (16MB)
206 * Frame-info table (24MB) (96MB)
207 * * Start of guest inaccessible area
208 * Machine-to-physical translation table [read-only] ( 4MB)
209 * * Start of guest unmodifiable area
210 */
212 #define IOREMAP_MBYTES 4
213 #define DIRECTMAP_MBYTES 12
214 #define MAPCACHE_MBYTES 4
215 #define PERDOMAIN_MBYTES 8
217 #ifdef CONFIG_X86_PAE
218 # define LINEARPT_MBYTES 8
219 # define MACHPHYS_MBYTES 16 /* 1 MB needed per 1 GB memory */
220 # define FRAMETABLE_MBYTES (MACHPHYS_MBYTES * 6)
221 #else
222 # define LINEARPT_MBYTES 4
223 # define MACHPHYS_MBYTES 4
224 # define FRAMETABLE_MBYTES 24
225 #endif
227 #define IOREMAP_VIRT_END 0UL
228 #define IOREMAP_VIRT_START (IOREMAP_VIRT_END - (IOREMAP_MBYTES<<20))
229 #define DIRECTMAP_VIRT_END IOREMAP_VIRT_START
230 #define DIRECTMAP_VIRT_START (DIRECTMAP_VIRT_END - (DIRECTMAP_MBYTES<<20))
231 #define MAPCACHE_VIRT_END DIRECTMAP_VIRT_START
232 #define MAPCACHE_VIRT_START (MAPCACHE_VIRT_END - (MAPCACHE_MBYTES<<20))
233 #define PERDOMAIN_VIRT_END DIRECTMAP_VIRT_START
234 #define PERDOMAIN_VIRT_START (PERDOMAIN_VIRT_END - (PERDOMAIN_MBYTES<<20))
235 #define SH_LINEAR_PT_VIRT_END PERDOMAIN_VIRT_START
236 #define SH_LINEAR_PT_VIRT_START (SH_LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
237 #define LINEAR_PT_VIRT_END SH_LINEAR_PT_VIRT_START
238 #define LINEAR_PT_VIRT_START (LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
239 #define RDWR_MPT_VIRT_END LINEAR_PT_VIRT_START
240 #define RDWR_MPT_VIRT_START (RDWR_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
241 #define FRAMETABLE_VIRT_END RDWR_MPT_VIRT_START
242 #define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - (FRAMETABLE_MBYTES<<20))
243 #define RO_MPT_VIRT_END FRAMETABLE_VIRT_START
244 #define RO_MPT_VIRT_START (RO_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
246 #define XENHEAP_DEFAULT_MB (DIRECTMAP_MBYTES)
247 #define DIRECTMAP_PHYS_END (DIRECTMAP_MBYTES<<20)
249 /* Maximum linear address accessible via guest memory segments. */
250 #define GUEST_SEGMENT_MAX_ADDR RO_MPT_VIRT_END
252 #ifdef CONFIG_X86_PAE
253 /* Hypervisor owns top 168MB of virtual address space. */
254 #define HYPERVISOR_VIRT_START mk_unsigned_long(0xF5800000)
255 #else
256 /* Hypervisor owns top 64MB of virtual address space. */
257 #define HYPERVISOR_VIRT_START mk_unsigned_long(0xFC000000)
258 #endif
260 #define L2_PAGETABLE_FIRST_XEN_SLOT \
261 (HYPERVISOR_VIRT_START >> L2_PAGETABLE_SHIFT)
262 #define L2_PAGETABLE_LAST_XEN_SLOT \
263 (~0UL >> L2_PAGETABLE_SHIFT)
264 #define L2_PAGETABLE_XEN_SLOTS \
265 (L2_PAGETABLE_LAST_XEN_SLOT - L2_PAGETABLE_FIRST_XEN_SLOT + 1)
267 #ifdef CONFIG_X86_PAE
268 # define PGT_base_page_table PGT_l3_page_table
269 #else
270 # define PGT_base_page_table PGT_l2_page_table
271 #endif
273 #define __HYPERVISOR_CS 0xe008
274 #define __HYPERVISOR_DS 0xe010
276 /* For generic assembly code: use macros to define operation/operand sizes. */
277 #define __OS "l" /* Operation Suffix */
278 #define __OP "e" /* Operand Prefix */
279 #define __FIXUP_ALIGN ".align 4"
280 #define __FIXUP_WORD ".long"
282 #endif /* __i386__ */
284 #ifndef __ASSEMBLY__
285 extern unsigned long xenheap_phys_end; /* user-configurable */
286 #endif
288 /* GDT/LDT shadow mapping area. The first per-domain-mapping sub-area. */
289 #define GDT_LDT_VCPU_SHIFT 5
290 #define GDT_LDT_VCPU_VA_SHIFT (GDT_LDT_VCPU_SHIFT + PAGE_SHIFT)
291 #define GDT_LDT_MBYTES (MAX_VIRT_CPUS >> (20-GDT_LDT_VCPU_VA_SHIFT))
292 #define GDT_LDT_VIRT_START PERDOMAIN_VIRT_START
293 #define GDT_LDT_VIRT_END (GDT_LDT_VIRT_START + (GDT_LDT_MBYTES << 20))
295 /* The address of a particular VCPU's GDT or LDT. */
296 #define GDT_VIRT_START(v) \
297 (PERDOMAIN_VIRT_START + ((v)->vcpu_id << GDT_LDT_VCPU_VA_SHIFT))
298 #define LDT_VIRT_START(v) \
299 (GDT_VIRT_START(v) + (64*1024))
301 #define PDPT_L1_ENTRIES \
302 ((PERDOMAIN_VIRT_END - PERDOMAIN_VIRT_START) >> PAGE_SHIFT)
303 #define PDPT_L2_ENTRIES \
304 ((PDPT_L1_ENTRIES + (1 << PAGETABLE_ORDER) - 1) >> PAGETABLE_ORDER)
306 #if defined(__x86_64__)
307 #define ELFSIZE 64
308 #else
309 #define ELFSIZE 32
310 #endif
312 #endif /* __X86_CONFIG_H__ */