direct-io.hg

view xen/arch/x86/hvm/vmx/vmx.c @ 11725:b92104e0cf08

Since shadow_update_paging_modes() will modify v->arch.hvm_vcpu.hw_cr3,
so we should always do shadow_update_paging_modes() before we writes to
GUEST_CR3 with v->arch.hvm_vcpu.hw_cr3.

Signed-off-by: Xiaohui Xin xiaohui.xin@intel.com
Signed-off-by: Xin Li <xin.b.li@intel.com>
author Tim Deegan <tim.deegan@xensource.com>
date Mon Oct 09 10:18:11 2006 +0100 (2006-10-09)
parents 646a120334ef
children bd6d4a499e47
line source
1 /*
2 * vmx.c: handling VMX architecture-related VM exits
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
20 #include <xen/config.h>
21 #include <xen/init.h>
22 #include <xen/lib.h>
23 #include <xen/trace.h>
24 #include <xen/sched.h>
25 #include <xen/irq.h>
26 #include <xen/softirq.h>
27 #include <xen/domain_page.h>
28 #include <xen/hypercall.h>
29 #include <xen/perfc.h>
30 #include <asm/current.h>
31 #include <asm/io.h>
32 #include <asm/regs.h>
33 #include <asm/cpufeature.h>
34 #include <asm/processor.h>
35 #include <asm/types.h>
36 #include <asm/msr.h>
37 #include <asm/spinlock.h>
38 #include <asm/hvm/hvm.h>
39 #include <asm/hvm/support.h>
40 #include <asm/hvm/vmx/vmx.h>
41 #include <asm/hvm/vmx/vmcs.h>
42 #include <asm/hvm/vmx/cpu.h>
43 #include <asm/shadow.h>
44 #include <public/sched.h>
45 #include <public/hvm/ioreq.h>
46 #include <asm/hvm/vpic.h>
47 #include <asm/hvm/vlapic.h>
48 #include <asm/x86_emulate.h>
50 extern uint32_t vlapic_update_ppr(struct vlapic *vlapic);
52 static DEFINE_PER_CPU(unsigned long, trace_values[5]);
53 #define TRACE_VMEXIT(index,value) this_cpu(trace_values)[index]=value
55 static void vmx_ctxt_switch_from(struct vcpu *v);
56 static void vmx_ctxt_switch_to(struct vcpu *v);
58 static int vmx_initialize_guest_resources(struct vcpu *v)
59 {
60 struct domain *d = v->domain;
61 struct vcpu *vc;
62 void *io_bitmap_a, *io_bitmap_b;
63 int rc;
65 v->arch.schedule_tail = arch_vmx_do_launch;
66 v->arch.ctxt_switch_from = vmx_ctxt_switch_from;
67 v->arch.ctxt_switch_to = vmx_ctxt_switch_to;
69 if ( v->vcpu_id != 0 )
70 return 1;
72 if ( !shadow_mode_external(d) )
73 {
74 DPRINTK("Can't init HVM for dom %u vcpu %u: "
75 "not in shadow external mode\n",
76 d->domain_id, v->vcpu_id);
77 domain_crash(d);
78 }
80 for_each_vcpu ( d, vc )
81 {
82 memset(&vc->arch.hvm_vmx, 0, sizeof(struct arch_vmx_struct));
84 if ( (rc = vmx_create_vmcs(vc)) != 0 )
85 {
86 DPRINTK("Failed to create VMCS for vcpu %d: err=%d.\n",
87 vc->vcpu_id, rc);
88 return 0;
89 }
91 spin_lock_init(&vc->arch.hvm_vmx.vmcs_lock);
93 if ( (io_bitmap_a = alloc_xenheap_pages(IO_BITMAP_ORDER)) == NULL )
94 {
95 DPRINTK("Failed to allocate io bitmap b for vcpu %d.\n",
96 vc->vcpu_id);
97 return 0;
98 }
100 if ( (io_bitmap_b = alloc_xenheap_pages(IO_BITMAP_ORDER)) == NULL )
101 {
102 DPRINTK("Failed to allocate io bitmap b for vcpu %d.\n",
103 vc->vcpu_id);
104 return 0;
105 }
107 memset(io_bitmap_a, 0xff, 0x1000);
108 memset(io_bitmap_b, 0xff, 0x1000);
110 /* don't bother debug port access */
111 clear_bit(PC_DEBUG_PORT, io_bitmap_a);
113 vc->arch.hvm_vmx.io_bitmap_a = io_bitmap_a;
114 vc->arch.hvm_vmx.io_bitmap_b = io_bitmap_b;
116 }
118 /*
119 * Required to do this once per domain XXX todo: add a seperate function
120 * to do these.
121 */
122 memset(&d->shared_info->evtchn_mask[0], 0xff,
123 sizeof(d->shared_info->evtchn_mask));
125 return 1;
126 }
128 static void vmx_relinquish_guest_resources(struct domain *d)
129 {
130 struct vcpu *v;
132 for_each_vcpu ( d, v )
133 {
134 vmx_destroy_vmcs(v);
135 if ( !test_bit(_VCPUF_initialised, &v->vcpu_flags) )
136 continue;
137 kill_timer(&v->arch.hvm_vcpu.hlt_timer);
138 if ( VLAPIC(v) != NULL )
139 {
140 kill_timer(&VLAPIC(v)->vlapic_timer);
141 unmap_domain_page_global(VLAPIC(v)->regs);
142 free_domheap_page(VLAPIC(v)->regs_page);
143 xfree(VLAPIC(v));
144 }
145 hvm_release_assist_channel(v);
146 }
148 kill_timer(&d->arch.hvm_domain.pl_time.periodic_tm.timer);
150 if ( d->arch.hvm_domain.shared_page_va )
151 unmap_domain_page_global(
152 (void *)d->arch.hvm_domain.shared_page_va);
154 if ( d->arch.hvm_domain.buffered_io_va )
155 unmap_domain_page_global((void *)d->arch.hvm_domain.buffered_io_va);
156 }
158 #ifdef __x86_64__
160 static DEFINE_PER_CPU(struct vmx_msr_state, percpu_msr);
162 static u32 msr_data_index[VMX_MSR_COUNT] =
163 {
164 MSR_LSTAR, MSR_STAR, MSR_CSTAR,
165 MSR_SYSCALL_MASK, MSR_EFER,
166 };
168 static void vmx_save_segments(struct vcpu *v)
169 {
170 rdmsrl(MSR_SHADOW_GS_BASE, v->arch.hvm_vmx.msr_content.shadow_gs);
171 }
173 /*
174 * To avoid MSR save/restore at every VM exit/entry time, we restore
175 * the x86_64 specific MSRs at domain switch time. Since those MSRs are
176 * are not modified once set for generic domains, we don't save them,
177 * but simply reset them to the values set at percpu_traps_init().
178 */
179 static void vmx_load_msrs(void)
180 {
181 struct vmx_msr_state *host_state = &this_cpu(percpu_msr);
182 int i;
184 while ( host_state->flags )
185 {
186 i = find_first_set_bit(host_state->flags);
187 wrmsrl(msr_data_index[i], host_state->msr_items[i]);
188 clear_bit(i, &host_state->flags);
189 }
190 }
192 static void vmx_save_init_msrs(void)
193 {
194 struct vmx_msr_state *host_state = &this_cpu(percpu_msr);
195 int i;
197 for ( i = 0; i < VMX_MSR_COUNT; i++ )
198 rdmsrl(msr_data_index[i], host_state->msr_items[i]);
199 }
201 #define CASE_READ_MSR(address) \
202 case MSR_ ## address: \
203 msr_content = msr->msr_items[VMX_INDEX_MSR_ ## address]; \
204 break
206 #define CASE_WRITE_MSR(address) \
207 case MSR_ ## address: \
208 { \
209 msr->msr_items[VMX_INDEX_MSR_ ## address] = msr_content; \
210 if (!test_bit(VMX_INDEX_MSR_ ## address, &msr->flags)) { \
211 set_bit(VMX_INDEX_MSR_ ## address, &msr->flags); \
212 } \
213 wrmsrl(MSR_ ## address, msr_content); \
214 set_bit(VMX_INDEX_MSR_ ## address, &host_state->flags); \
215 } \
216 break
218 #define IS_CANO_ADDRESS(add) 1
219 static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
220 {
221 u64 msr_content = 0;
222 struct vcpu *v = current;
223 struct vmx_msr_state *msr = &v->arch.hvm_vmx.msr_content;
225 switch ( regs->ecx ) {
226 case MSR_EFER:
227 HVM_DBG_LOG(DBG_LEVEL_2, "EFER msr_content 0x%"PRIx64, msr_content);
228 msr_content = msr->msr_items[VMX_INDEX_MSR_EFER];
229 break;
231 case MSR_FS_BASE:
232 if ( !(vmx_long_mode_enabled(v)) )
233 /* XXX should it be GP fault */
234 domain_crash_synchronous();
236 __vmread(GUEST_FS_BASE, &msr_content);
237 break;
239 case MSR_GS_BASE:
240 if ( !(vmx_long_mode_enabled(v)) )
241 domain_crash_synchronous();
243 __vmread(GUEST_GS_BASE, &msr_content);
244 break;
246 case MSR_SHADOW_GS_BASE:
247 msr_content = msr->shadow_gs;
248 break;
250 CASE_READ_MSR(STAR);
251 CASE_READ_MSR(LSTAR);
252 CASE_READ_MSR(CSTAR);
253 CASE_READ_MSR(SYSCALL_MASK);
255 default:
256 return 0;
257 }
259 HVM_DBG_LOG(DBG_LEVEL_2, "msr_content: 0x%"PRIx64, msr_content);
261 regs->eax = (u32)(msr_content >> 0);
262 regs->edx = (u32)(msr_content >> 32);
264 return 1;
265 }
267 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
268 {
269 u64 msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
270 struct vcpu *v = current;
271 struct vmx_msr_state *msr = &v->arch.hvm_vmx.msr_content;
272 struct vmx_msr_state *host_state = &this_cpu(percpu_msr);
274 HVM_DBG_LOG(DBG_LEVEL_1, "msr 0x%lx msr_content 0x%"PRIx64"\n",
275 (unsigned long)regs->ecx, msr_content);
277 switch ( regs->ecx ) {
278 case MSR_EFER:
279 /* offending reserved bit will cause #GP */
280 if ( msr_content & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE) )
281 {
282 printk("Trying to set reserved bit in EFER: %"PRIx64"\n",
283 msr_content);
284 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
285 return 0;
286 }
288 if ( (msr_content & EFER_LME)
289 && !(msr->msr_items[VMX_INDEX_MSR_EFER] & EFER_LME) )
290 {
291 if ( unlikely(vmx_paging_enabled(v)) )
292 {
293 printk("Trying to set EFER.LME with paging enabled\n");
294 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
295 return 0;
296 }
297 }
298 else if ( !(msr_content & EFER_LME)
299 && (msr->msr_items[VMX_INDEX_MSR_EFER] & EFER_LME) )
300 {
301 if ( unlikely(vmx_paging_enabled(v)) )
302 {
303 printk("Trying to clear EFER.LME with paging enabled\n");
304 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
305 return 0;
306 }
307 }
309 msr->msr_items[VMX_INDEX_MSR_EFER] = msr_content;
310 break;
312 case MSR_FS_BASE:
313 case MSR_GS_BASE:
314 if ( !(vmx_long_mode_enabled(v)) )
315 domain_crash_synchronous();
317 if ( !IS_CANO_ADDRESS(msr_content) )
318 {
319 HVM_DBG_LOG(DBG_LEVEL_1, "Not cano address of msr write\n");
320 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
321 return 0;
322 }
324 if ( regs->ecx == MSR_FS_BASE )
325 __vmwrite(GUEST_FS_BASE, msr_content);
326 else
327 __vmwrite(GUEST_GS_BASE, msr_content);
329 break;
331 case MSR_SHADOW_GS_BASE:
332 if ( !(vmx_long_mode_enabled(v)) )
333 domain_crash_synchronous();
335 v->arch.hvm_vmx.msr_content.shadow_gs = msr_content;
336 wrmsrl(MSR_SHADOW_GS_BASE, msr_content);
337 break;
339 CASE_WRITE_MSR(STAR);
340 CASE_WRITE_MSR(LSTAR);
341 CASE_WRITE_MSR(CSTAR);
342 CASE_WRITE_MSR(SYSCALL_MASK);
344 default:
345 return 0;
346 }
348 return 1;
349 }
351 static void vmx_restore_msrs(struct vcpu *v)
352 {
353 int i = 0;
354 struct vmx_msr_state *guest_state;
355 struct vmx_msr_state *host_state;
356 unsigned long guest_flags ;
358 guest_state = &v->arch.hvm_vmx.msr_content;;
359 host_state = &this_cpu(percpu_msr);
361 wrmsrl(MSR_SHADOW_GS_BASE, guest_state->shadow_gs);
362 guest_flags = guest_state->flags;
363 if (!guest_flags)
364 return;
366 while (guest_flags){
367 i = find_first_set_bit(guest_flags);
369 HVM_DBG_LOG(DBG_LEVEL_2,
370 "restore guest's index %d msr %lx with %lx\n",
371 i, (unsigned long)msr_data_index[i],
372 (unsigned long)guest_state->msr_items[i]);
373 set_bit(i, &host_state->flags);
374 wrmsrl(msr_data_index[i], guest_state->msr_items[i]);
375 clear_bit(i, &guest_flags);
376 }
377 }
379 #else /* __i386__ */
381 #define vmx_save_segments(v) ((void)0)
382 #define vmx_load_msrs() ((void)0)
383 #define vmx_restore_msrs(v) ((void)0)
384 #define vmx_save_init_msrs() ((void)0)
386 static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
387 {
388 return 0;
389 }
391 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
392 {
393 return 0;
394 }
396 #endif /* __i386__ */
398 #define loaddebug(_v,_reg) \
399 __asm__ __volatile__ ("mov %0,%%db" #_reg : : "r" ((_v)->debugreg[_reg]))
400 #define savedebug(_v,_reg) \
401 __asm__ __volatile__ ("mov %%db" #_reg ",%0" : : "r" ((_v)->debugreg[_reg]))
403 static inline void vmx_save_dr(struct vcpu *v)
404 {
405 if ( v->arch.hvm_vcpu.flag_dr_dirty )
406 {
407 savedebug(&v->arch.guest_context, 0);
408 savedebug(&v->arch.guest_context, 1);
409 savedebug(&v->arch.guest_context, 2);
410 savedebug(&v->arch.guest_context, 3);
411 savedebug(&v->arch.guest_context, 6);
413 v->arch.hvm_vcpu.flag_dr_dirty = 0;
415 v->arch.hvm_vcpu.u.vmx.exec_control |= CPU_BASED_MOV_DR_EXITING;
416 __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
417 v->arch.hvm_vcpu.u.vmx.exec_control);
418 }
419 }
421 static inline void __restore_debug_registers(struct vcpu *v)
422 {
423 loaddebug(&v->arch.guest_context, 0);
424 loaddebug(&v->arch.guest_context, 1);
425 loaddebug(&v->arch.guest_context, 2);
426 loaddebug(&v->arch.guest_context, 3);
427 /* No 4 and 5 */
428 loaddebug(&v->arch.guest_context, 6);
429 /* DR7 is loaded from the vmcs. */
430 }
432 /*
433 * DR7 is saved and restored on every vmexit. Other debug registers only
434 * need to be restored if their value is going to affect execution -- i.e.,
435 * if one of the breakpoints is enabled. So mask out all bits that don't
436 * enable some breakpoint functionality.
437 *
438 * This is in part necessary because bit 10 of DR7 is hardwired to 1, so a
439 * simple if( guest_dr7 ) will always return true. As long as we're masking,
440 * we might as well do it right.
441 */
442 #define DR7_ACTIVE_MASK 0xff
444 static inline void vmx_restore_dr(struct vcpu *v)
445 {
446 unsigned long guest_dr7;
448 __vmread(GUEST_DR7, &guest_dr7);
450 /* Assumes guest does not have DR access at time of context switch. */
451 if ( unlikely(guest_dr7 & DR7_ACTIVE_MASK) )
452 __restore_debug_registers(v);
453 }
455 static void vmx_freeze_time(struct vcpu *v)
456 {
457 struct periodic_time *pt=&v->domain->arch.hvm_domain.pl_time.periodic_tm;
459 if ( pt->enabled && pt->first_injected && !v->arch.hvm_vcpu.guest_time ) {
460 v->arch.hvm_vcpu.guest_time = hvm_get_guest_time(v);
461 stop_timer(&(pt->timer));
462 }
463 }
465 static void vmx_ctxt_switch_from(struct vcpu *v)
466 {
467 vmx_freeze_time(v);
468 vmx_save_segments(v);
469 vmx_load_msrs();
470 vmx_save_dr(v);
471 }
473 static void vmx_ctxt_switch_to(struct vcpu *v)
474 {
475 vmx_restore_msrs(v);
476 vmx_restore_dr(v);
477 }
479 static void stop_vmx(void)
480 {
481 if ( !(read_cr4() & X86_CR4_VMXE) )
482 return;
483 __vmxoff();
484 clear_in_cr4(X86_CR4_VMXE);
485 }
487 void vmx_migrate_timers(struct vcpu *v)
488 {
489 struct periodic_time *pt = &(v->domain->arch.hvm_domain.pl_time.periodic_tm);
491 if ( pt->enabled )
492 {
493 migrate_timer(&pt->timer, v->processor);
494 migrate_timer(&v->arch.hvm_vcpu.hlt_timer, v->processor);
495 }
496 if ( VLAPIC(v) != NULL )
497 migrate_timer(&VLAPIC(v)->vlapic_timer, v->processor);
498 }
500 static void vmx_store_cpu_guest_regs(
501 struct vcpu *v, struct cpu_user_regs *regs, unsigned long *crs)
502 {
503 vmx_vmcs_enter(v);
505 if ( regs != NULL )
506 {
507 __vmread(GUEST_RFLAGS, &regs->eflags);
508 __vmread(GUEST_SS_SELECTOR, &regs->ss);
509 __vmread(GUEST_CS_SELECTOR, &regs->cs);
510 __vmread(GUEST_DS_SELECTOR, &regs->ds);
511 __vmread(GUEST_ES_SELECTOR, &regs->es);
512 __vmread(GUEST_GS_SELECTOR, &regs->gs);
513 __vmread(GUEST_FS_SELECTOR, &regs->fs);
514 __vmread(GUEST_RIP, &regs->eip);
515 __vmread(GUEST_RSP, &regs->esp);
516 }
518 if ( crs != NULL )
519 {
520 __vmread(CR0_READ_SHADOW, &crs[0]);
521 crs[2] = v->arch.hvm_vmx.cpu_cr2;
522 __vmread(GUEST_CR3, &crs[3]);
523 __vmread(CR4_READ_SHADOW, &crs[4]);
524 }
526 vmx_vmcs_exit(v);
527 }
529 /*
530 * The VMX spec (section 4.3.1.2, Checks on Guest Segment
531 * Registers) says that virtual-8086 mode guests' segment
532 * base-address fields in the VMCS must be equal to their
533 * corresponding segment selector field shifted right by
534 * four bits upon vmentry.
535 *
536 * This function (called only for VM86-mode guests) fixes
537 * the bases to be consistent with the selectors in regs
538 * if they're not already. Without this, we can fail the
539 * vmentry check mentioned above.
540 */
541 static void fixup_vm86_seg_bases(struct cpu_user_regs *regs)
542 {
543 int err = 0;
544 unsigned long base;
546 err |= __vmread(GUEST_ES_BASE, &base);
547 if (regs->es << 4 != base)
548 err |= __vmwrite(GUEST_ES_BASE, regs->es << 4);
549 err |= __vmread(GUEST_CS_BASE, &base);
550 if (regs->cs << 4 != base)
551 err |= __vmwrite(GUEST_CS_BASE, regs->cs << 4);
552 err |= __vmread(GUEST_SS_BASE, &base);
553 if (regs->ss << 4 != base)
554 err |= __vmwrite(GUEST_SS_BASE, regs->ss << 4);
555 err |= __vmread(GUEST_DS_BASE, &base);
556 if (regs->ds << 4 != base)
557 err |= __vmwrite(GUEST_DS_BASE, regs->ds << 4);
558 err |= __vmread(GUEST_FS_BASE, &base);
559 if (regs->fs << 4 != base)
560 err |= __vmwrite(GUEST_FS_BASE, regs->fs << 4);
561 err |= __vmread(GUEST_GS_BASE, &base);
562 if (regs->gs << 4 != base)
563 err |= __vmwrite(GUEST_GS_BASE, regs->gs << 4);
565 BUG_ON(err);
566 }
568 static void vmx_load_cpu_guest_regs(struct vcpu *v, struct cpu_user_regs *regs)
569 {
570 vmx_vmcs_enter(v);
572 __vmwrite(GUEST_SS_SELECTOR, regs->ss);
573 __vmwrite(GUEST_DS_SELECTOR, regs->ds);
574 __vmwrite(GUEST_ES_SELECTOR, regs->es);
575 __vmwrite(GUEST_GS_SELECTOR, regs->gs);
576 __vmwrite(GUEST_FS_SELECTOR, regs->fs);
578 __vmwrite(GUEST_RSP, regs->esp);
580 __vmwrite(GUEST_RFLAGS, regs->eflags);
581 if (regs->eflags & EF_TF)
582 __vm_set_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
583 else
584 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_DB);
585 if (regs->eflags & EF_VM)
586 fixup_vm86_seg_bases(regs);
588 __vmwrite(GUEST_CS_SELECTOR, regs->cs);
589 __vmwrite(GUEST_RIP, regs->eip);
591 vmx_vmcs_exit(v);
592 }
594 static unsigned long vmx_get_ctrl_reg(struct vcpu *v, unsigned int num)
595 {
596 switch ( num )
597 {
598 case 0:
599 return v->arch.hvm_vmx.cpu_cr0;
600 case 2:
601 return v->arch.hvm_vmx.cpu_cr2;
602 case 3:
603 return v->arch.hvm_vmx.cpu_cr3;
604 case 4:
605 return v->arch.hvm_vmx.cpu_shadow_cr4;
606 default:
607 BUG();
608 }
609 return 0; /* dummy */
610 }
614 /* Make sure that xen intercepts any FP accesses from current */
615 static void vmx_stts(struct vcpu *v)
616 {
617 unsigned long cr0;
619 /* VMX depends on operating on the current vcpu */
620 ASSERT(v == current);
622 /*
623 * If the guest does not have TS enabled then we must cause and handle an
624 * exception on first use of the FPU. If the guest *does* have TS enabled
625 * then this is not necessary: no FPU activity can occur until the guest
626 * clears CR0.TS, and we will initialise the FPU when that happens.
627 */
628 __vmread_vcpu(v, CR0_READ_SHADOW, &cr0);
629 if ( !(cr0 & X86_CR0_TS) )
630 {
631 __vmread_vcpu(v, GUEST_CR0, &cr0);
632 __vmwrite(GUEST_CR0, cr0 | X86_CR0_TS);
633 __vm_set_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
634 }
635 }
638 static void vmx_set_tsc_offset(struct vcpu *v, u64 offset)
639 {
640 /* VMX depends on operating on the current vcpu */
641 ASSERT(v == current);
643 __vmwrite(TSC_OFFSET, offset);
644 #if defined (__i386__)
645 __vmwrite(TSC_OFFSET_HIGH, offset >> 32);
646 #endif
647 }
651 /* SMP VMX guest support */
652 static void vmx_init_ap_context(struct vcpu_guest_context *ctxt,
653 int vcpuid, int trampoline_vector)
654 {
655 int i;
657 memset(ctxt, 0, sizeof(*ctxt));
659 /*
660 * Initial register values:
661 */
662 ctxt->user_regs.eip = VMXASSIST_BASE;
663 ctxt->user_regs.edx = vcpuid;
664 ctxt->user_regs.ebx = trampoline_vector;
666 ctxt->flags = VGCF_HVM_GUEST;
668 /* Virtual IDT is empty at start-of-day. */
669 for ( i = 0; i < 256; i++ )
670 {
671 ctxt->trap_ctxt[i].vector = i;
672 ctxt->trap_ctxt[i].cs = FLAT_KERNEL_CS;
673 }
675 /* No callback handlers. */
676 #if defined(__i386__)
677 ctxt->event_callback_cs = FLAT_KERNEL_CS;
678 ctxt->failsafe_callback_cs = FLAT_KERNEL_CS;
679 #endif
680 }
682 void do_nmi(struct cpu_user_regs *);
684 static void vmx_init_hypercall_page(struct domain *d, void *hypercall_page)
685 {
686 char *p;
687 int i;
689 memset(hypercall_page, 0, PAGE_SIZE);
691 for ( i = 0; i < (PAGE_SIZE / 32); i++ )
692 {
693 p = (char *)(hypercall_page + (i * 32));
694 *(u8 *)(p + 0) = 0xb8; /* mov imm32, %eax */
695 *(u32 *)(p + 1) = i;
696 *(u8 *)(p + 5) = 0x0f; /* vmcall */
697 *(u8 *)(p + 6) = 0x01;
698 *(u8 *)(p + 7) = 0xc1;
699 *(u8 *)(p + 8) = 0xc3; /* ret */
700 }
702 /* Don't support HYPERVISOR_iret at the moment */
703 *(u16 *)(hypercall_page + (__HYPERVISOR_iret * 32)) = 0x0b0f; /* ud2 */
704 }
706 static int vmx_realmode(struct vcpu *v)
707 {
708 unsigned long rflags;
710 ASSERT(v == current);
712 __vmread(GUEST_RFLAGS, &rflags);
713 return rflags & X86_EFLAGS_VM;
714 }
716 static int vmx_guest_x86_mode(struct vcpu *v)
717 {
718 unsigned long cs_ar_bytes;
720 ASSERT(v == current);
722 __vmread(GUEST_CS_AR_BYTES, &cs_ar_bytes);
724 if ( vmx_long_mode_enabled(v) )
725 return ((cs_ar_bytes & (1u<<13)) ?
726 X86EMUL_MODE_PROT64 : X86EMUL_MODE_PROT32);
728 if ( vmx_realmode(v) )
729 return X86EMUL_MODE_REAL;
731 return ((cs_ar_bytes & (1u<<14)) ?
732 X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16);
733 }
735 /* Setup HVM interfaces */
736 static void vmx_setup_hvm_funcs(void)
737 {
738 if ( hvm_enabled )
739 return;
741 hvm_funcs.disable = stop_vmx;
743 hvm_funcs.initialize_guest_resources = vmx_initialize_guest_resources;
744 hvm_funcs.relinquish_guest_resources = vmx_relinquish_guest_resources;
746 hvm_funcs.store_cpu_guest_regs = vmx_store_cpu_guest_regs;
747 hvm_funcs.load_cpu_guest_regs = vmx_load_cpu_guest_regs;
749 hvm_funcs.realmode = vmx_realmode;
750 hvm_funcs.paging_enabled = vmx_paging_enabled;
751 hvm_funcs.long_mode_enabled = vmx_long_mode_enabled;
752 hvm_funcs.pae_enabled = vmx_pae_enabled;
753 hvm_funcs.guest_x86_mode = vmx_guest_x86_mode;
754 hvm_funcs.get_guest_ctrl_reg = vmx_get_ctrl_reg;
756 hvm_funcs.update_host_cr3 = vmx_update_host_cr3;
758 hvm_funcs.stts = vmx_stts;
759 hvm_funcs.set_tsc_offset = vmx_set_tsc_offset;
761 hvm_funcs.init_ap_context = vmx_init_ap_context;
763 hvm_funcs.init_hypercall_page = vmx_init_hypercall_page;
764 }
766 int start_vmx(void)
767 {
768 u32 eax, edx;
769 struct vmcs_struct *vmcs;
771 /*
772 * Xen does not fill x86_capability words except 0.
773 */
774 boot_cpu_data.x86_capability[4] = cpuid_ecx(1);
776 if ( !test_bit(X86_FEATURE_VMXE, &boot_cpu_data.x86_capability) )
777 return 0;
779 rdmsr(IA32_FEATURE_CONTROL_MSR, eax, edx);
781 if ( eax & IA32_FEATURE_CONTROL_MSR_LOCK )
782 {
783 if ( (eax & IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON) == 0x0 )
784 {
785 printk("VMX disabled by Feature Control MSR.\n");
786 return 0;
787 }
788 }
789 else
790 {
791 wrmsr(IA32_FEATURE_CONTROL_MSR,
792 IA32_FEATURE_CONTROL_MSR_LOCK |
793 IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON, 0);
794 }
796 set_in_cr4(X86_CR4_VMXE);
798 vmx_init_vmcs_config();
800 if ( smp_processor_id() == 0 )
801 setup_vmcs_dump();
803 if ( (vmcs = vmx_alloc_host_vmcs()) == NULL )
804 {
805 clear_in_cr4(X86_CR4_VMXE);
806 printk("Failed to allocate host VMCS\n");
807 return 0;
808 }
810 if ( __vmxon(virt_to_maddr(vmcs)) )
811 {
812 clear_in_cr4(X86_CR4_VMXE);
813 printk("VMXON failed\n");
814 vmx_free_host_vmcs(vmcs);
815 return 0;
816 }
818 printk("VMXON is done\n");
820 vmx_save_init_msrs();
822 vmx_setup_hvm_funcs();
824 hvm_enabled = 1;
826 return 1;
827 }
829 /*
830 * Not all cases receive valid value in the VM-exit instruction length field.
831 * Callers must know what they're doing!
832 */
833 static int __get_instruction_length(void)
834 {
835 int len;
836 __vmread(VM_EXIT_INSTRUCTION_LEN, &len); /* Safe: callers audited */
837 if ( (len < 1) || (len > 15) )
838 __hvm_bug(guest_cpu_user_regs());
839 return len;
840 }
842 static void inline __update_guest_eip(unsigned long inst_len)
843 {
844 unsigned long current_eip;
846 __vmread(GUEST_RIP, &current_eip);
847 __vmwrite(GUEST_RIP, current_eip + inst_len);
848 __vmwrite(GUEST_INTERRUPTIBILITY_INFO, 0);
849 }
851 static int vmx_do_page_fault(unsigned long va, struct cpu_user_regs *regs)
852 {
853 int result;
855 #if 0 /* keep for debugging */
856 {
857 unsigned long eip, cs;
859 __vmread(GUEST_CS_BASE, &cs);
860 __vmread(GUEST_RIP, &eip);
861 HVM_DBG_LOG(DBG_LEVEL_VMMU,
862 "vmx_do_page_fault = 0x%lx, cs_base=%lx, "
863 "eip = %lx, error_code = %lx\n",
864 va, cs, eip, (unsigned long)regs->error_code);
865 }
866 #endif
868 result = shadow_fault(va, regs);
870 TRACE_VMEXIT (2,result);
871 #if 0
872 if ( !result )
873 {
874 __vmread(GUEST_RIP, &eip);
875 printk("vmx pgfault to guest va=%lx eip=%lx\n", va, eip);
876 }
877 #endif
879 return result;
880 }
882 static void vmx_do_no_device_fault(void)
883 {
884 unsigned long cr0;
885 struct vcpu *v = current;
887 setup_fpu(current);
888 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
890 /* Disable TS in guest CR0 unless the guest wants the exception too. */
891 __vmread_vcpu(v, CR0_READ_SHADOW, &cr0);
892 if ( !(cr0 & X86_CR0_TS) )
893 {
894 __vmread_vcpu(v, GUEST_CR0, &cr0);
895 cr0 &= ~X86_CR0_TS;
896 __vmwrite(GUEST_CR0, cr0);
897 }
898 }
900 #define bitmaskof(idx) (1U << ((idx)&31))
901 static void vmx_vmexit_do_cpuid(struct cpu_user_regs *regs)
902 {
903 unsigned int input = (unsigned int)regs->eax;
904 unsigned int count = (unsigned int)regs->ecx;
905 unsigned int eax, ebx, ecx, edx;
906 unsigned long eip;
907 struct vcpu *v = current;
909 __vmread(GUEST_RIP, &eip);
911 HVM_DBG_LOG(DBG_LEVEL_3, "(eax) 0x%08lx, (ebx) 0x%08lx, "
912 "(ecx) 0x%08lx, (edx) 0x%08lx, (esi) 0x%08lx, (edi) 0x%08lx",
913 (unsigned long)regs->eax, (unsigned long)regs->ebx,
914 (unsigned long)regs->ecx, (unsigned long)regs->edx,
915 (unsigned long)regs->esi, (unsigned long)regs->edi);
917 if ( input == CPUID_LEAF_0x4 )
918 {
919 cpuid_count(input, count, &eax, &ebx, &ecx, &edx);
920 eax &= NUM_CORES_RESET_MASK;
921 }
922 else if ( !cpuid_hypervisor_leaves(input, &eax, &ebx, &ecx, &edx) )
923 {
924 cpuid(input, &eax, &ebx, &ecx, &edx);
926 if ( input == CPUID_LEAF_0x1 )
927 {
928 /* mask off reserved bits */
929 ecx &= ~VMX_VCPU_CPUID_L1_ECX_RESERVED;
931 if ( !hvm_apic_support(v->domain) ||
932 !vlapic_global_enabled((VLAPIC(v))) )
933 {
934 /* Since the apic is disabled, avoid any
935 confusion about SMP cpus being available */
937 clear_bit(X86_FEATURE_APIC, &edx);
938 }
940 #if CONFIG_PAGING_LEVELS >= 3
941 if ( !v->domain->arch.hvm_domain.params[HVM_PARAM_PAE_ENABLED] )
942 #endif
943 clear_bit(X86_FEATURE_PAE, &edx);
944 clear_bit(X86_FEATURE_PSE36, &edx);
946 ebx &= NUM_THREADS_RESET_MASK;
948 /* Unsupportable for virtualised CPUs. */
949 ecx &= ~(bitmaskof(X86_FEATURE_VMXE) |
950 bitmaskof(X86_FEATURE_EST) |
951 bitmaskof(X86_FEATURE_TM2) |
952 bitmaskof(X86_FEATURE_CID) |
953 bitmaskof(X86_FEATURE_MWAIT) );
955 edx &= ~( bitmaskof(X86_FEATURE_HT) |
956 bitmaskof(X86_FEATURE_ACPI) |
957 bitmaskof(X86_FEATURE_ACC) );
958 }
959 else if ( ( input == CPUID_LEAF_0x6 )
960 || ( input == CPUID_LEAF_0x9 )
961 || ( input == CPUID_LEAF_0xA ))
962 {
963 eax = ebx = ecx = edx = 0x0;
964 }
965 #ifdef __i386__
966 else if ( input == CPUID_LEAF_0x80000001 )
967 {
968 clear_bit(X86_FEATURE_LAHF_LM & 31, &ecx);
970 clear_bit(X86_FEATURE_LM & 31, &edx);
971 clear_bit(X86_FEATURE_SYSCALL & 31, &edx);
972 }
973 #endif
974 }
976 regs->eax = (unsigned long) eax;
977 regs->ebx = (unsigned long) ebx;
978 regs->ecx = (unsigned long) ecx;
979 regs->edx = (unsigned long) edx;
981 HVM_DBG_LOG(DBG_LEVEL_3, "eip@%lx, input: 0x%lx, "
982 "output: eax = 0x%08lx, ebx = 0x%08lx, "
983 "ecx = 0x%08lx, edx = 0x%08lx",
984 (unsigned long)eip, (unsigned long)input,
985 (unsigned long)eax, (unsigned long)ebx,
986 (unsigned long)ecx, (unsigned long)edx);
987 }
989 #define CASE_GET_REG_P(REG, reg) \
990 case REG_ ## REG: reg_p = (unsigned long *)&(regs->reg); break
992 #ifdef __i386__
993 #define CASE_EXTEND_GET_REG_P
994 #else
995 #define CASE_EXTEND_GET_REG_P \
996 CASE_GET_REG_P(R8, r8); \
997 CASE_GET_REG_P(R9, r9); \
998 CASE_GET_REG_P(R10, r10); \
999 CASE_GET_REG_P(R11, r11); \
1000 CASE_GET_REG_P(R12, r12); \
1001 CASE_GET_REG_P(R13, r13); \
1002 CASE_GET_REG_P(R14, r14); \
1003 CASE_GET_REG_P(R15, r15)
1004 #endif
1006 static void vmx_dr_access(unsigned long exit_qualification,
1007 struct cpu_user_regs *regs)
1009 struct vcpu *v = current;
1011 v->arch.hvm_vcpu.flag_dr_dirty = 1;
1013 /* We could probably be smarter about this */
1014 __restore_debug_registers(v);
1016 /* Allow guest direct access to DR registers */
1017 v->arch.hvm_vcpu.u.vmx.exec_control &= ~CPU_BASED_MOV_DR_EXITING;
1018 __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
1019 v->arch.hvm_vcpu.u.vmx.exec_control);
1022 /*
1023 * Invalidate the TLB for va. Invalidate the shadow page corresponding
1024 * the address va.
1025 */
1026 static void vmx_vmexit_do_invlpg(unsigned long va)
1028 unsigned long eip;
1029 struct vcpu *v = current;
1031 __vmread(GUEST_RIP, &eip);
1033 HVM_DBG_LOG(DBG_LEVEL_VMMU, "vmx_vmexit_do_invlpg: eip=%lx, va=%lx",
1034 eip, va);
1036 /*
1037 * We do the safest things first, then try to update the shadow
1038 * copying from guest
1039 */
1040 shadow_invlpg(v, va);
1044 static int check_for_null_selector(unsigned long eip)
1046 unsigned char inst[MAX_INST_LEN];
1047 unsigned long sel;
1048 int i, inst_len;
1049 int inst_copy_from_guest(unsigned char *, unsigned long, int);
1051 inst_len = __get_instruction_length(); /* Safe: INS/OUTS */
1052 memset(inst, 0, MAX_INST_LEN);
1053 if ( inst_copy_from_guest(inst, eip, inst_len) != inst_len )
1055 printf("check_for_null_selector: get guest instruction failed\n");
1056 domain_crash_synchronous();
1059 for ( i = 0; i < inst_len; i++ )
1061 switch ( inst[i] )
1063 case 0xf3: /* REPZ */
1064 case 0xf2: /* REPNZ */
1065 case 0xf0: /* LOCK */
1066 case 0x66: /* data32 */
1067 case 0x67: /* addr32 */
1068 continue;
1069 case 0x2e: /* CS */
1070 __vmread(GUEST_CS_SELECTOR, &sel);
1071 break;
1072 case 0x36: /* SS */
1073 __vmread(GUEST_SS_SELECTOR, &sel);
1074 break;
1075 case 0x26: /* ES */
1076 __vmread(GUEST_ES_SELECTOR, &sel);
1077 break;
1078 case 0x64: /* FS */
1079 __vmread(GUEST_FS_SELECTOR, &sel);
1080 break;
1081 case 0x65: /* GS */
1082 __vmread(GUEST_GS_SELECTOR, &sel);
1083 break;
1084 case 0x3e: /* DS */
1085 /* FALLTHROUGH */
1086 default:
1087 /* DS is the default */
1088 __vmread(GUEST_DS_SELECTOR, &sel);
1090 return sel == 0 ? 1 : 0;
1093 return 0;
1096 extern void send_pio_req(struct cpu_user_regs *regs, unsigned long port,
1097 unsigned long count, int size, long value,
1098 int dir, int pvalid);
1100 static void vmx_io_instruction(unsigned long exit_qualification,
1101 unsigned long inst_len)
1103 struct cpu_user_regs *regs;
1104 struct hvm_io_op *pio_opp;
1105 unsigned long eip, cs, eflags;
1106 unsigned long port, size, dir;
1107 int vm86;
1109 pio_opp = &current->arch.hvm_vcpu.io_op;
1110 pio_opp->instr = INSTR_PIO;
1111 pio_opp->flags = 0;
1113 regs = &pio_opp->io_context;
1115 /* Copy current guest state into io instruction state structure. */
1116 memcpy(regs, guest_cpu_user_regs(), HVM_CONTEXT_STACK_BYTES);
1117 hvm_store_cpu_guest_regs(current, regs, NULL);
1119 eip = regs->eip;
1120 cs = regs->cs;
1121 eflags = regs->eflags;
1123 vm86 = eflags & X86_EFLAGS_VM ? 1 : 0;
1125 HVM_DBG_LOG(DBG_LEVEL_IO,
1126 "vmx_io_instruction: vm86 %d, eip=%lx:%lx, "
1127 "exit_qualification = %lx",
1128 vm86, cs, eip, exit_qualification);
1130 if (test_bit(6, &exit_qualification))
1131 port = (exit_qualification >> 16) & 0xFFFF;
1132 else
1133 port = regs->edx & 0xffff;
1134 TRACE_VMEXIT(1, port);
1135 size = (exit_qualification & 7) + 1;
1136 dir = test_bit(3, &exit_qualification); /* direction */
1138 if (test_bit(4, &exit_qualification)) { /* string instruction */
1139 unsigned long addr, count = 1;
1140 int sign = regs->eflags & EF_DF ? -1 : 1;
1142 __vmread(GUEST_LINEAR_ADDRESS, &addr);
1144 /*
1145 * In protected mode, guest linear address is invalid if the
1146 * selector is null.
1147 */
1148 if (!vm86 && check_for_null_selector(eip))
1149 addr = dir == IOREQ_WRITE ? regs->esi : regs->edi;
1151 if (test_bit(5, &exit_qualification)) { /* "rep" prefix */
1152 pio_opp->flags |= REPZ;
1153 count = vm86 ? regs->ecx & 0xFFFF : regs->ecx;
1156 /*
1157 * Handle string pio instructions that cross pages or that
1158 * are unaligned. See the comments in hvm_domain.c/handle_mmio()
1159 */
1160 if ((addr & PAGE_MASK) != ((addr + size - 1) & PAGE_MASK)) {
1161 unsigned long value = 0;
1163 pio_opp->flags |= OVERLAP;
1164 if (dir == IOREQ_WRITE)
1165 (void)hvm_copy_from_guest_virt(&value, addr, size);
1166 send_pio_req(regs, port, 1, size, value, dir, 0);
1167 } else {
1168 if ((addr & PAGE_MASK) != ((addr + count * size - 1) & PAGE_MASK)) {
1169 if (sign > 0)
1170 count = (PAGE_SIZE - (addr & ~PAGE_MASK)) / size;
1171 else
1172 count = (addr & ~PAGE_MASK) / size;
1173 } else
1174 regs->eip += inst_len;
1176 send_pio_req(regs, port, count, size, addr, dir, 1);
1178 } else {
1179 if (port == 0xe9 && dir == IOREQ_WRITE && size == 1)
1180 hvm_print_line(current, regs->eax); /* guest debug output */
1182 regs->eip += inst_len;
1183 send_pio_req(regs, port, 1, size, regs->eax, dir, 0);
1187 static int vmx_world_save(struct vcpu *v, struct vmx_assist_context *c)
1189 int error = 0;
1191 /* NB. Skip transition instruction. */
1192 error |= __vmread(GUEST_RIP, &c->eip);
1193 c->eip += __get_instruction_length(); /* Safe: MOV Cn, LMSW, CLTS */
1195 error |= __vmread(GUEST_RSP, &c->esp);
1196 error |= __vmread(GUEST_RFLAGS, &c->eflags);
1198 error |= __vmread(CR0_READ_SHADOW, &c->cr0);
1199 c->cr3 = v->arch.hvm_vmx.cpu_cr3;
1200 error |= __vmread(CR4_READ_SHADOW, &c->cr4);
1202 error |= __vmread(GUEST_IDTR_LIMIT, &c->idtr_limit);
1203 error |= __vmread(GUEST_IDTR_BASE, &c->idtr_base);
1205 error |= __vmread(GUEST_GDTR_LIMIT, &c->gdtr_limit);
1206 error |= __vmread(GUEST_GDTR_BASE, &c->gdtr_base);
1208 error |= __vmread(GUEST_CS_SELECTOR, &c->cs_sel);
1209 error |= __vmread(GUEST_CS_LIMIT, &c->cs_limit);
1210 error |= __vmread(GUEST_CS_BASE, &c->cs_base);
1211 error |= __vmread(GUEST_CS_AR_BYTES, &c->cs_arbytes.bytes);
1213 error |= __vmread(GUEST_DS_SELECTOR, &c->ds_sel);
1214 error |= __vmread(GUEST_DS_LIMIT, &c->ds_limit);
1215 error |= __vmread(GUEST_DS_BASE, &c->ds_base);
1216 error |= __vmread(GUEST_DS_AR_BYTES, &c->ds_arbytes.bytes);
1218 error |= __vmread(GUEST_ES_SELECTOR, &c->es_sel);
1219 error |= __vmread(GUEST_ES_LIMIT, &c->es_limit);
1220 error |= __vmread(GUEST_ES_BASE, &c->es_base);
1221 error |= __vmread(GUEST_ES_AR_BYTES, &c->es_arbytes.bytes);
1223 error |= __vmread(GUEST_SS_SELECTOR, &c->ss_sel);
1224 error |= __vmread(GUEST_SS_LIMIT, &c->ss_limit);
1225 error |= __vmread(GUEST_SS_BASE, &c->ss_base);
1226 error |= __vmread(GUEST_SS_AR_BYTES, &c->ss_arbytes.bytes);
1228 error |= __vmread(GUEST_FS_SELECTOR, &c->fs_sel);
1229 error |= __vmread(GUEST_FS_LIMIT, &c->fs_limit);
1230 error |= __vmread(GUEST_FS_BASE, &c->fs_base);
1231 error |= __vmread(GUEST_FS_AR_BYTES, &c->fs_arbytes.bytes);
1233 error |= __vmread(GUEST_GS_SELECTOR, &c->gs_sel);
1234 error |= __vmread(GUEST_GS_LIMIT, &c->gs_limit);
1235 error |= __vmread(GUEST_GS_BASE, &c->gs_base);
1236 error |= __vmread(GUEST_GS_AR_BYTES, &c->gs_arbytes.bytes);
1238 error |= __vmread(GUEST_TR_SELECTOR, &c->tr_sel);
1239 error |= __vmread(GUEST_TR_LIMIT, &c->tr_limit);
1240 error |= __vmread(GUEST_TR_BASE, &c->tr_base);
1241 error |= __vmread(GUEST_TR_AR_BYTES, &c->tr_arbytes.bytes);
1243 error |= __vmread(GUEST_LDTR_SELECTOR, &c->ldtr_sel);
1244 error |= __vmread(GUEST_LDTR_LIMIT, &c->ldtr_limit);
1245 error |= __vmread(GUEST_LDTR_BASE, &c->ldtr_base);
1246 error |= __vmread(GUEST_LDTR_AR_BYTES, &c->ldtr_arbytes.bytes);
1248 return !error;
1251 static int vmx_world_restore(struct vcpu *v, struct vmx_assist_context *c)
1253 unsigned long mfn, old_base_mfn;
1254 int error = 0;
1256 error |= __vmwrite(GUEST_RIP, c->eip);
1257 error |= __vmwrite(GUEST_RSP, c->esp);
1258 error |= __vmwrite(GUEST_RFLAGS, c->eflags);
1260 error |= __vmwrite(CR0_READ_SHADOW, c->cr0);
1262 if (!vmx_paging_enabled(v))
1263 goto skip_cr3;
1265 if (c->cr3 == v->arch.hvm_vmx.cpu_cr3) {
1266 /*
1267 * This is simple TLB flush, implying the guest has
1268 * removed some translation or changed page attributes.
1269 * We simply invalidate the shadow.
1270 */
1271 mfn = get_mfn_from_gpfn(c->cr3 >> PAGE_SHIFT);
1272 if (mfn != pagetable_get_pfn(v->arch.guest_table)) {
1273 printk("Invalid CR3 value=%x", c->cr3);
1274 domain_crash_synchronous();
1275 return 0;
1277 } else {
1278 /*
1279 * If different, make a shadow. Check if the PDBR is valid
1280 * first.
1281 */
1282 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 c->cr3 = %x", c->cr3);
1283 if ((c->cr3 >> PAGE_SHIFT) > v->domain->max_pages) {
1284 printk("Invalid CR3 value=%x", c->cr3);
1285 domain_crash_synchronous();
1286 return 0;
1288 mfn = get_mfn_from_gpfn(c->cr3 >> PAGE_SHIFT);
1289 if(!get_page(mfn_to_page(mfn), v->domain))
1290 return 0;
1291 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1292 v->arch.guest_table = pagetable_from_pfn(mfn);
1293 if (old_base_mfn)
1294 put_page(mfn_to_page(old_base_mfn));
1295 /*
1296 * arch.shadow_table should now hold the next CR3 for shadow
1297 */
1298 v->arch.hvm_vmx.cpu_cr3 = c->cr3;
1301 skip_cr3:
1303 if (!vmx_paging_enabled(v))
1304 HVM_DBG_LOG(DBG_LEVEL_VMMU, "switching to vmxassist. use phys table");
1305 else
1306 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %x", c->cr3);
1308 error |= __vmwrite(GUEST_CR4, (c->cr4 | VMX_CR4_HOST_MASK));
1309 error |= __vmwrite(CR4_READ_SHADOW, c->cr4);
1311 error |= __vmwrite(GUEST_IDTR_LIMIT, c->idtr_limit);
1312 error |= __vmwrite(GUEST_IDTR_BASE, c->idtr_base);
1314 error |= __vmwrite(GUEST_GDTR_LIMIT, c->gdtr_limit);
1315 error |= __vmwrite(GUEST_GDTR_BASE, c->gdtr_base);
1317 error |= __vmwrite(GUEST_CS_SELECTOR, c->cs_sel);
1318 error |= __vmwrite(GUEST_CS_LIMIT, c->cs_limit);
1319 error |= __vmwrite(GUEST_CS_BASE, c->cs_base);
1320 error |= __vmwrite(GUEST_CS_AR_BYTES, c->cs_arbytes.bytes);
1322 error |= __vmwrite(GUEST_DS_SELECTOR, c->ds_sel);
1323 error |= __vmwrite(GUEST_DS_LIMIT, c->ds_limit);
1324 error |= __vmwrite(GUEST_DS_BASE, c->ds_base);
1325 error |= __vmwrite(GUEST_DS_AR_BYTES, c->ds_arbytes.bytes);
1327 error |= __vmwrite(GUEST_ES_SELECTOR, c->es_sel);
1328 error |= __vmwrite(GUEST_ES_LIMIT, c->es_limit);
1329 error |= __vmwrite(GUEST_ES_BASE, c->es_base);
1330 error |= __vmwrite(GUEST_ES_AR_BYTES, c->es_arbytes.bytes);
1332 error |= __vmwrite(GUEST_SS_SELECTOR, c->ss_sel);
1333 error |= __vmwrite(GUEST_SS_LIMIT, c->ss_limit);
1334 error |= __vmwrite(GUEST_SS_BASE, c->ss_base);
1335 error |= __vmwrite(GUEST_SS_AR_BYTES, c->ss_arbytes.bytes);
1337 error |= __vmwrite(GUEST_FS_SELECTOR, c->fs_sel);
1338 error |= __vmwrite(GUEST_FS_LIMIT, c->fs_limit);
1339 error |= __vmwrite(GUEST_FS_BASE, c->fs_base);
1340 error |= __vmwrite(GUEST_FS_AR_BYTES, c->fs_arbytes.bytes);
1342 error |= __vmwrite(GUEST_GS_SELECTOR, c->gs_sel);
1343 error |= __vmwrite(GUEST_GS_LIMIT, c->gs_limit);
1344 error |= __vmwrite(GUEST_GS_BASE, c->gs_base);
1345 error |= __vmwrite(GUEST_GS_AR_BYTES, c->gs_arbytes.bytes);
1347 error |= __vmwrite(GUEST_TR_SELECTOR, c->tr_sel);
1348 error |= __vmwrite(GUEST_TR_LIMIT, c->tr_limit);
1349 error |= __vmwrite(GUEST_TR_BASE, c->tr_base);
1350 error |= __vmwrite(GUEST_TR_AR_BYTES, c->tr_arbytes.bytes);
1352 error |= __vmwrite(GUEST_LDTR_SELECTOR, c->ldtr_sel);
1353 error |= __vmwrite(GUEST_LDTR_LIMIT, c->ldtr_limit);
1354 error |= __vmwrite(GUEST_LDTR_BASE, c->ldtr_base);
1355 error |= __vmwrite(GUEST_LDTR_AR_BYTES, c->ldtr_arbytes.bytes);
1357 shadow_update_paging_modes(v);
1358 __vmwrite(GUEST_CR3, v->arch.hvm_vcpu.hw_cr3);
1360 return !error;
1363 enum { VMX_ASSIST_INVOKE = 0, VMX_ASSIST_RESTORE };
1365 static int vmx_assist(struct vcpu *v, int mode)
1367 struct vmx_assist_context c;
1368 u32 magic;
1369 u32 cp;
1371 /* make sure vmxassist exists (this is not an error) */
1372 if (hvm_copy_from_guest_phys(&magic, VMXASSIST_MAGIC_OFFSET,
1373 sizeof(magic)))
1374 return 0;
1375 if (magic != VMXASSIST_MAGIC)
1376 return 0;
1378 switch (mode) {
1379 /*
1380 * Transfer control to vmxassist.
1381 * Store the current context in VMXASSIST_OLD_CONTEXT and load
1382 * the new VMXASSIST_NEW_CONTEXT context. This context was created
1383 * by vmxassist and will transfer control to it.
1384 */
1385 case VMX_ASSIST_INVOKE:
1386 /* save the old context */
1387 if (hvm_copy_from_guest_phys(&cp, VMXASSIST_OLD_CONTEXT, sizeof(cp)))
1388 goto error;
1389 if (cp != 0) {
1390 if (!vmx_world_save(v, &c))
1391 goto error;
1392 if (hvm_copy_to_guest_phys(cp, &c, sizeof(c)))
1393 goto error;
1396 /* restore the new context, this should activate vmxassist */
1397 if (hvm_copy_from_guest_phys(&cp, VMXASSIST_NEW_CONTEXT, sizeof(cp)))
1398 goto error;
1399 if (cp != 0) {
1400 if (hvm_copy_from_guest_phys(&c, cp, sizeof(c)))
1401 goto error;
1402 if (!vmx_world_restore(v, &c))
1403 goto error;
1404 v->arch.hvm_vmx.vmxassist_enabled = 1;
1405 return 1;
1407 break;
1409 /*
1410 * Restore the VMXASSIST_OLD_CONTEXT that was saved by
1411 * VMX_ASSIST_INVOKE above.
1412 */
1413 case VMX_ASSIST_RESTORE:
1414 /* save the old context */
1415 if (hvm_copy_from_guest_phys(&cp, VMXASSIST_OLD_CONTEXT, sizeof(cp)))
1416 goto error;
1417 if (cp != 0) {
1418 if (hvm_copy_from_guest_phys(&c, cp, sizeof(c)))
1419 goto error;
1420 if (!vmx_world_restore(v, &c))
1421 goto error;
1422 v->arch.hvm_vmx.vmxassist_enabled = 0;
1423 return 1;
1425 break;
1428 error:
1429 printf("Failed to transfer to vmxassist\n");
1430 domain_crash_synchronous();
1431 return 0;
1434 static int vmx_set_cr0(unsigned long value)
1436 struct vcpu *v = current;
1437 unsigned long mfn;
1438 unsigned long eip;
1439 int paging_enabled;
1440 unsigned long vm_entry_value;
1441 unsigned long old_cr0;
1442 unsigned long old_base_mfn;
1444 /*
1445 * CR0: We don't want to lose PE and PG.
1446 */
1447 __vmread_vcpu(v, CR0_READ_SHADOW, &old_cr0);
1448 paging_enabled = (old_cr0 & X86_CR0_PE) && (old_cr0 & X86_CR0_PG);
1450 /* TS cleared? Then initialise FPU now. */
1451 if ( !(value & X86_CR0_TS) )
1453 setup_fpu(v);
1454 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
1457 __vmwrite(GUEST_CR0, value | X86_CR0_PE | X86_CR0_PG | X86_CR0_NE);
1458 __vmwrite(CR0_READ_SHADOW, value);
1460 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR0 value = %lx\n", value);
1462 if ( (value & X86_CR0_PE) && (value & X86_CR0_PG) && !paging_enabled )
1464 /*
1465 * Trying to enable guest paging.
1466 * The guest CR3 must be pointing to the guest physical.
1467 */
1468 if ( !VALID_MFN(mfn = get_mfn_from_gpfn(
1469 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)) ||
1470 !get_page(mfn_to_page(mfn), v->domain) )
1472 printk("Invalid CR3 value = %lx (mfn=%lx)\n",
1473 v->arch.hvm_vmx.cpu_cr3, mfn);
1474 domain_crash_synchronous(); /* need to take a clean path */
1477 #if defined(__x86_64__)
1478 if ( vmx_lme_is_set(v) )
1480 if ( !(v->arch.hvm_vmx.cpu_shadow_cr4 & X86_CR4_PAE) )
1482 HVM_DBG_LOG(DBG_LEVEL_1, "Guest enabled paging "
1483 "with EFER.LME set but not CR4.PAE\n");
1484 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
1486 else
1488 HVM_DBG_LOG(DBG_LEVEL_1, "Enabling long mode\n");
1489 v->arch.hvm_vmx.msr_content.msr_items[VMX_INDEX_MSR_EFER]
1490 |= EFER_LMA;
1491 __vmread(VM_ENTRY_CONTROLS, &vm_entry_value);
1492 vm_entry_value |= VM_ENTRY_IA32E_MODE;
1493 __vmwrite(VM_ENTRY_CONTROLS, vm_entry_value);
1496 #endif
1498 /*
1499 * Now arch.guest_table points to machine physical.
1500 */
1501 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1502 v->arch.guest_table = pagetable_from_pfn(mfn);
1503 if (old_base_mfn)
1504 put_page(mfn_to_page(old_base_mfn));
1505 shadow_update_paging_modes(v);
1507 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1508 (unsigned long) (mfn << PAGE_SHIFT));
1510 __vmwrite(GUEST_CR3, v->arch.hvm_vcpu.hw_cr3);
1511 /*
1512 * arch->shadow_table should hold the next CR3 for shadow
1513 */
1514 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx, mfn = %lx",
1515 v->arch.hvm_vmx.cpu_cr3, mfn);
1518 if ( !((value & X86_CR0_PE) && (value & X86_CR0_PG)) && paging_enabled )
1519 if ( v->arch.hvm_vmx.cpu_cr3 ) {
1520 put_page(mfn_to_page(get_mfn_from_gpfn(
1521 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)));
1522 v->arch.guest_table = pagetable_null();
1525 /*
1526 * VMX does not implement real-mode virtualization. We emulate
1527 * real-mode by performing a world switch to VMXAssist whenever
1528 * a partition disables the CR0.PE bit.
1529 */
1530 if ( (value & X86_CR0_PE) == 0 )
1532 if ( value & X86_CR0_PG ) {
1533 /* inject GP here */
1534 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
1535 return 0;
1536 } else {
1537 /*
1538 * Disable paging here.
1539 * Same to PE == 1 && PG == 0
1540 */
1541 if ( vmx_long_mode_enabled(v) )
1543 v->arch.hvm_vmx.msr_content.msr_items[VMX_INDEX_MSR_EFER]
1544 &= ~EFER_LMA;
1545 __vmread(VM_ENTRY_CONTROLS, &vm_entry_value);
1546 vm_entry_value &= ~VM_ENTRY_IA32E_MODE;
1547 __vmwrite(VM_ENTRY_CONTROLS, vm_entry_value);
1551 if ( vmx_assist(v, VMX_ASSIST_INVOKE) )
1553 __vmread(GUEST_RIP, &eip);
1554 HVM_DBG_LOG(DBG_LEVEL_1,
1555 "Transfering control to vmxassist %%eip 0x%lx\n", eip);
1556 return 0; /* do not update eip! */
1559 else if ( v->arch.hvm_vmx.vmxassist_enabled )
1561 __vmread(GUEST_RIP, &eip);
1562 HVM_DBG_LOG(DBG_LEVEL_1,
1563 "Enabling CR0.PE at %%eip 0x%lx\n", eip);
1564 if ( vmx_assist(v, VMX_ASSIST_RESTORE) )
1566 __vmread(GUEST_RIP, &eip);
1567 HVM_DBG_LOG(DBG_LEVEL_1,
1568 "Restoring to %%eip 0x%lx\n", eip);
1569 return 0; /* do not update eip! */
1572 else if ( (value & (X86_CR0_PE | X86_CR0_PG)) == X86_CR0_PE )
1574 shadow_update_paging_modes(v);
1575 __vmwrite(GUEST_CR3, v->arch.hvm_vcpu.hw_cr3);
1578 return 1;
1581 #define CASE_SET_REG(REG, reg) \
1582 case REG_ ## REG: regs->reg = value; break
1583 #define CASE_GET_REG(REG, reg) \
1584 case REG_ ## REG: value = regs->reg; break
1586 #define CASE_EXTEND_SET_REG \
1587 CASE_EXTEND_REG(S)
1588 #define CASE_EXTEND_GET_REG \
1589 CASE_EXTEND_REG(G)
1591 #ifdef __i386__
1592 #define CASE_EXTEND_REG(T)
1593 #else
1594 #define CASE_EXTEND_REG(T) \
1595 CASE_ ## T ## ET_REG(R8, r8); \
1596 CASE_ ## T ## ET_REG(R9, r9); \
1597 CASE_ ## T ## ET_REG(R10, r10); \
1598 CASE_ ## T ## ET_REG(R11, r11); \
1599 CASE_ ## T ## ET_REG(R12, r12); \
1600 CASE_ ## T ## ET_REG(R13, r13); \
1601 CASE_ ## T ## ET_REG(R14, r14); \
1602 CASE_ ## T ## ET_REG(R15, r15)
1603 #endif
1605 /*
1606 * Write to control registers
1607 */
1608 static int mov_to_cr(int gp, int cr, struct cpu_user_regs *regs)
1610 unsigned long value;
1611 unsigned long old_cr;
1612 struct vcpu *v = current;
1613 struct vlapic *vlapic = VLAPIC(v);
1615 switch ( gp ) {
1616 CASE_GET_REG(EAX, eax);
1617 CASE_GET_REG(ECX, ecx);
1618 CASE_GET_REG(EDX, edx);
1619 CASE_GET_REG(EBX, ebx);
1620 CASE_GET_REG(EBP, ebp);
1621 CASE_GET_REG(ESI, esi);
1622 CASE_GET_REG(EDI, edi);
1623 CASE_EXTEND_GET_REG;
1624 case REG_ESP:
1625 __vmread(GUEST_RSP, &value);
1626 break;
1627 default:
1628 printk("invalid gp: %d\n", gp);
1629 __hvm_bug(regs);
1632 HVM_DBG_LOG(DBG_LEVEL_1, "CR%d, value = %lx", cr, value);
1634 switch ( cr ) {
1635 case 0:
1636 return vmx_set_cr0(value);
1637 case 3:
1639 unsigned long old_base_mfn, mfn;
1641 /*
1642 * If paging is not enabled yet, simply copy the value to CR3.
1643 */
1644 if (!vmx_paging_enabled(v)) {
1645 v->arch.hvm_vmx.cpu_cr3 = value;
1646 break;
1649 /*
1650 * We make a new one if the shadow does not exist.
1651 */
1652 if (value == v->arch.hvm_vmx.cpu_cr3) {
1653 /*
1654 * This is simple TLB flush, implying the guest has
1655 * removed some translation or changed page attributes.
1656 * We simply invalidate the shadow.
1657 */
1658 mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT);
1659 if (mfn != pagetable_get_pfn(v->arch.guest_table))
1660 __hvm_bug(regs);
1661 shadow_update_cr3(v);
1662 } else {
1663 /*
1664 * If different, make a shadow. Check if the PDBR is valid
1665 * first.
1666 */
1667 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 value = %lx", value);
1668 if ( ((value >> PAGE_SHIFT) > v->domain->max_pages ) ||
1669 !VALID_MFN(mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT)) ||
1670 !get_page(mfn_to_page(mfn), v->domain) )
1672 printk("Invalid CR3 value=%lx", value);
1673 domain_crash_synchronous(); /* need to take a clean path */
1675 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1676 v->arch.guest_table = pagetable_from_pfn(mfn);
1677 if (old_base_mfn)
1678 put_page(mfn_to_page(old_base_mfn));
1679 /*
1680 * arch.shadow_table should now hold the next CR3 for shadow
1681 */
1682 v->arch.hvm_vmx.cpu_cr3 = value;
1683 update_cr3(v);
1684 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx",
1685 value);
1686 __vmwrite(GUEST_CR3, v->arch.hvm_vcpu.hw_cr3);
1688 break;
1690 case 4: /* CR4 */
1692 __vmread(CR4_READ_SHADOW, &old_cr);
1694 if ( value & X86_CR4_PAE && !(old_cr & X86_CR4_PAE) )
1696 if ( vmx_pgbit_test(v) )
1698 /* The guest is a 32-bit PAE guest. */
1699 #if CONFIG_PAGING_LEVELS >= 3
1700 unsigned long mfn, old_base_mfn;
1702 if ( !VALID_MFN(mfn = get_mfn_from_gpfn(
1703 v->arch.hvm_vmx.cpu_cr3 >> PAGE_SHIFT)) ||
1704 !get_page(mfn_to_page(mfn), v->domain) )
1706 printk("Invalid CR3 value = %lx", v->arch.hvm_vmx.cpu_cr3);
1707 domain_crash_synchronous(); /* need to take a clean path */
1711 /*
1712 * Now arch.guest_table points to machine physical.
1713 */
1715 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1716 v->arch.guest_table = pagetable_from_pfn(mfn);
1717 if ( old_base_mfn )
1718 put_page(mfn_to_page(old_base_mfn));
1720 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1721 (unsigned long) (mfn << PAGE_SHIFT));
1723 __vmwrite(GUEST_CR3, v->arch.hvm_vcpu.hw_cr3);
1725 /*
1726 * arch->shadow_table should hold the next CR3 for shadow
1727 */
1729 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx, mfn = %lx",
1730 v->arch.hvm_vmx.cpu_cr3, mfn);
1731 #endif
1734 else if ( !(value & X86_CR4_PAE) )
1736 if ( unlikely(vmx_long_mode_enabled(v)) )
1738 HVM_DBG_LOG(DBG_LEVEL_1, "Guest cleared CR4.PAE while "
1739 "EFER.LMA is set\n");
1740 vmx_inject_hw_exception(v, TRAP_gp_fault, 0);
1744 __vmwrite(GUEST_CR4, value| VMX_CR4_HOST_MASK);
1745 __vmwrite(CR4_READ_SHADOW, value);
1747 /*
1748 * Writing to CR4 to modify the PSE, PGE, or PAE flag invalidates
1749 * all TLB entries except global entries.
1750 */
1751 if ( (old_cr ^ value) & (X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE) )
1752 shadow_update_paging_modes(v);
1753 break;
1755 case 8:
1757 if ( vlapic == NULL )
1758 break;
1759 vlapic_set_reg(vlapic, APIC_TASKPRI, ((value & 0x0F) << 4));
1760 vlapic_update_ppr(vlapic);
1761 break;
1763 default:
1764 printk("invalid cr: %d\n", gp);
1765 __hvm_bug(regs);
1768 return 1;
1771 /*
1772 * Read from control registers. CR0 and CR4 are read from the shadow.
1773 */
1774 static void mov_from_cr(int cr, int gp, struct cpu_user_regs *regs)
1776 unsigned long value = 0;
1777 struct vcpu *v = current;
1778 struct vlapic *vlapic = VLAPIC(v);
1780 switch ( cr )
1782 case 3:
1783 value = (unsigned long)v->arch.hvm_vmx.cpu_cr3;
1784 break;
1785 case 8:
1786 if ( vlapic == NULL )
1787 break;
1788 value = (unsigned long)vlapic_get_reg(vlapic, APIC_TASKPRI);
1789 value = (value & 0xF0) >> 4;
1790 break;
1791 default:
1792 __hvm_bug(regs);
1795 switch ( gp ) {
1796 CASE_SET_REG(EAX, eax);
1797 CASE_SET_REG(ECX, ecx);
1798 CASE_SET_REG(EDX, edx);
1799 CASE_SET_REG(EBX, ebx);
1800 CASE_SET_REG(EBP, ebp);
1801 CASE_SET_REG(ESI, esi);
1802 CASE_SET_REG(EDI, edi);
1803 CASE_EXTEND_SET_REG;
1804 case REG_ESP:
1805 __vmwrite(GUEST_RSP, value);
1806 regs->esp = value;
1807 break;
1808 default:
1809 printk("invalid gp: %d\n", gp);
1810 __hvm_bug(regs);
1813 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR%d, value = %lx", cr, value);
1816 static int vmx_cr_access(unsigned long exit_qualification,
1817 struct cpu_user_regs *regs)
1819 unsigned int gp, cr;
1820 unsigned long value;
1821 struct vcpu *v = current;
1823 switch (exit_qualification & CONTROL_REG_ACCESS_TYPE) {
1824 case TYPE_MOV_TO_CR:
1825 gp = exit_qualification & CONTROL_REG_ACCESS_REG;
1826 cr = exit_qualification & CONTROL_REG_ACCESS_NUM;
1827 TRACE_VMEXIT(1,TYPE_MOV_TO_CR);
1828 TRACE_VMEXIT(2,cr);
1829 TRACE_VMEXIT(3,gp);
1830 return mov_to_cr(gp, cr, regs);
1831 case TYPE_MOV_FROM_CR:
1832 gp = exit_qualification & CONTROL_REG_ACCESS_REG;
1833 cr = exit_qualification & CONTROL_REG_ACCESS_NUM;
1834 TRACE_VMEXIT(1,TYPE_MOV_FROM_CR);
1835 TRACE_VMEXIT(2,cr);
1836 TRACE_VMEXIT(3,gp);
1837 mov_from_cr(cr, gp, regs);
1838 break;
1839 case TYPE_CLTS:
1840 TRACE_VMEXIT(1,TYPE_CLTS);
1842 /* We initialise the FPU now, to avoid needing another vmexit. */
1843 setup_fpu(v);
1844 __vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
1846 __vmread_vcpu(v, GUEST_CR0, &value);
1847 value &= ~X86_CR0_TS; /* clear TS */
1848 __vmwrite(GUEST_CR0, value);
1850 __vmread_vcpu(v, CR0_READ_SHADOW, &value);
1851 value &= ~X86_CR0_TS; /* clear TS */
1852 __vmwrite(CR0_READ_SHADOW, value);
1853 break;
1854 case TYPE_LMSW:
1855 TRACE_VMEXIT(1,TYPE_LMSW);
1856 __vmread_vcpu(v, CR0_READ_SHADOW, &value);
1857 value = (value & ~0xF) |
1858 (((exit_qualification & LMSW_SOURCE_DATA) >> 16) & 0xF);
1859 return vmx_set_cr0(value);
1860 break;
1861 default:
1862 __hvm_bug(regs);
1863 break;
1865 return 1;
1868 static inline void vmx_do_msr_read(struct cpu_user_regs *regs)
1870 u64 msr_content = 0;
1871 u32 eax, edx;
1872 struct vcpu *v = current;
1874 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read: ecx=%lx, eax=%lx, edx=%lx",
1875 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1876 (unsigned long)regs->edx);
1877 switch (regs->ecx) {
1878 case MSR_IA32_TIME_STAMP_COUNTER:
1879 msr_content = hvm_get_guest_time(v);
1880 break;
1881 case MSR_IA32_SYSENTER_CS:
1882 __vmread(GUEST_SYSENTER_CS, (u32 *)&msr_content);
1883 break;
1884 case MSR_IA32_SYSENTER_ESP:
1885 __vmread(GUEST_SYSENTER_ESP, &msr_content);
1886 break;
1887 case MSR_IA32_SYSENTER_EIP:
1888 __vmread(GUEST_SYSENTER_EIP, &msr_content);
1889 break;
1890 case MSR_IA32_APICBASE:
1891 msr_content = VLAPIC(v) ? VLAPIC(v)->apic_base_msr : 0;
1892 break;
1893 default:
1894 if (long_mode_do_msr_read(regs))
1895 return;
1897 if ( rdmsr_hypervisor_regs(regs->ecx, &eax, &edx) )
1899 regs->eax = eax;
1900 regs->edx = edx;
1901 return;
1904 rdmsr_safe(regs->ecx, regs->eax, regs->edx);
1905 return;
1908 regs->eax = msr_content & 0xFFFFFFFF;
1909 regs->edx = msr_content >> 32;
1911 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_read returns: "
1912 "ecx=%lx, eax=%lx, edx=%lx",
1913 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1914 (unsigned long)regs->edx);
1917 static inline void vmx_do_msr_write(struct cpu_user_regs *regs)
1919 u64 msr_content;
1920 struct vcpu *v = current;
1922 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_write: ecx=%lx, eax=%lx, edx=%lx",
1923 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1924 (unsigned long)regs->edx);
1926 msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
1928 switch (regs->ecx) {
1929 case MSR_IA32_TIME_STAMP_COUNTER:
1930 hvm_set_guest_time(v, msr_content);
1931 break;
1932 case MSR_IA32_SYSENTER_CS:
1933 __vmwrite(GUEST_SYSENTER_CS, msr_content);
1934 break;
1935 case MSR_IA32_SYSENTER_ESP:
1936 __vmwrite(GUEST_SYSENTER_ESP, msr_content);
1937 break;
1938 case MSR_IA32_SYSENTER_EIP:
1939 __vmwrite(GUEST_SYSENTER_EIP, msr_content);
1940 break;
1941 case MSR_IA32_APICBASE:
1942 vlapic_msr_set(VLAPIC(v), msr_content);
1943 break;
1944 default:
1945 if ( !long_mode_do_msr_write(regs) )
1946 wrmsr_hypervisor_regs(regs->ecx, regs->eax, regs->edx);
1947 break;
1950 HVM_DBG_LOG(DBG_LEVEL_1, "vmx_do_msr_write returns: "
1951 "ecx=%lx, eax=%lx, edx=%lx",
1952 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1953 (unsigned long)regs->edx);
1956 void vmx_vmexit_do_hlt(void)
1958 unsigned long rflags;
1959 __vmread(GUEST_RFLAGS, &rflags);
1960 hvm_hlt(rflags);
1963 static inline void vmx_vmexit_do_extint(struct cpu_user_regs *regs)
1965 unsigned int vector;
1966 int error;
1968 asmlinkage void do_IRQ(struct cpu_user_regs *);
1969 fastcall void smp_apic_timer_interrupt(struct cpu_user_regs *);
1970 fastcall void smp_event_check_interrupt(void);
1971 fastcall void smp_invalidate_interrupt(void);
1972 fastcall void smp_call_function_interrupt(void);
1973 fastcall void smp_spurious_interrupt(struct cpu_user_regs *regs);
1974 fastcall void smp_error_interrupt(struct cpu_user_regs *regs);
1975 #ifdef CONFIG_X86_MCE_P4THERMAL
1976 fastcall void smp_thermal_interrupt(struct cpu_user_regs *regs);
1977 #endif
1979 if ((error = __vmread(VM_EXIT_INTR_INFO, &vector))
1980 && !(vector & INTR_INFO_VALID_MASK))
1981 __hvm_bug(regs);
1983 vector &= INTR_INFO_VECTOR_MASK;
1984 TRACE_VMEXIT(1,vector);
1986 switch(vector) {
1987 case LOCAL_TIMER_VECTOR:
1988 smp_apic_timer_interrupt(regs);
1989 break;
1990 case EVENT_CHECK_VECTOR:
1991 smp_event_check_interrupt();
1992 break;
1993 case INVALIDATE_TLB_VECTOR:
1994 smp_invalidate_interrupt();
1995 break;
1996 case CALL_FUNCTION_VECTOR:
1997 smp_call_function_interrupt();
1998 break;
1999 case SPURIOUS_APIC_VECTOR:
2000 smp_spurious_interrupt(regs);
2001 break;
2002 case ERROR_APIC_VECTOR:
2003 smp_error_interrupt(regs);
2004 break;
2005 #ifdef CONFIG_X86_MCE_P4THERMAL
2006 case THERMAL_APIC_VECTOR:
2007 smp_thermal_interrupt(regs);
2008 break;
2009 #endif
2010 default:
2011 regs->entry_vector = vector;
2012 do_IRQ(regs);
2013 break;
2017 #if defined (__x86_64__)
2018 void store_cpu_user_regs(struct cpu_user_regs *regs)
2020 __vmread(GUEST_SS_SELECTOR, &regs->ss);
2021 __vmread(GUEST_RSP, &regs->rsp);
2022 __vmread(GUEST_RFLAGS, &regs->rflags);
2023 __vmread(GUEST_CS_SELECTOR, &regs->cs);
2024 __vmread(GUEST_DS_SELECTOR, &regs->ds);
2025 __vmread(GUEST_ES_SELECTOR, &regs->es);
2026 __vmread(GUEST_RIP, &regs->rip);
2028 #elif defined (__i386__)
2029 void store_cpu_user_regs(struct cpu_user_regs *regs)
2031 __vmread(GUEST_SS_SELECTOR, &regs->ss);
2032 __vmread(GUEST_RSP, &regs->esp);
2033 __vmread(GUEST_RFLAGS, &regs->eflags);
2034 __vmread(GUEST_CS_SELECTOR, &regs->cs);
2035 __vmread(GUEST_DS_SELECTOR, &regs->ds);
2036 __vmread(GUEST_ES_SELECTOR, &regs->es);
2037 __vmread(GUEST_RIP, &regs->eip);
2039 #endif
2041 #ifdef XEN_DEBUGGER
2042 void save_cpu_user_regs(struct cpu_user_regs *regs)
2044 __vmread(GUEST_SS_SELECTOR, &regs->xss);
2045 __vmread(GUEST_RSP, &regs->esp);
2046 __vmread(GUEST_RFLAGS, &regs->eflags);
2047 __vmread(GUEST_CS_SELECTOR, &regs->xcs);
2048 __vmread(GUEST_RIP, &regs->eip);
2050 __vmread(GUEST_GS_SELECTOR, &regs->xgs);
2051 __vmread(GUEST_FS_SELECTOR, &regs->xfs);
2052 __vmread(GUEST_ES_SELECTOR, &regs->xes);
2053 __vmread(GUEST_DS_SELECTOR, &regs->xds);
2056 void restore_cpu_user_regs(struct cpu_user_regs *regs)
2058 __vmwrite(GUEST_SS_SELECTOR, regs->xss);
2059 __vmwrite(GUEST_RSP, regs->esp);
2060 __vmwrite(GUEST_RFLAGS, regs->eflags);
2061 __vmwrite(GUEST_CS_SELECTOR, regs->xcs);
2062 __vmwrite(GUEST_RIP, regs->eip);
2064 __vmwrite(GUEST_GS_SELECTOR, regs->xgs);
2065 __vmwrite(GUEST_FS_SELECTOR, regs->xfs);
2066 __vmwrite(GUEST_ES_SELECTOR, regs->xes);
2067 __vmwrite(GUEST_DS_SELECTOR, regs->xds);
2069 #endif
2071 static void vmx_reflect_exception(struct vcpu *v)
2073 int error_code, intr_info, vector;
2075 __vmread(VM_EXIT_INTR_INFO, &intr_info);
2076 vector = intr_info & 0xff;
2077 if ( intr_info & INTR_INFO_DELIVER_CODE_MASK )
2078 __vmread(VM_EXIT_INTR_ERROR_CODE, &error_code);
2079 else
2080 error_code = VMX_DELIVER_NO_ERROR_CODE;
2082 #ifndef NDEBUG
2084 unsigned long rip;
2086 __vmread(GUEST_RIP, &rip);
2087 HVM_DBG_LOG(DBG_LEVEL_1, "rip = %lx, error_code = %x",
2088 rip, error_code);
2090 #endif /* NDEBUG */
2092 /*
2093 * According to Intel Virtualization Technology Specification for
2094 * the IA-32 Intel Architecture (C97063-002 April 2005), section
2095 * 2.8.3, SW_EXCEPTION should be used for #BP and #OV, and
2096 * HW_EXCEPTION used for everything else. The main difference
2097 * appears to be that for SW_EXCEPTION, the EIP/RIP is incremented
2098 * by VM_ENTER_INSTRUCTION_LEN bytes, whereas for HW_EXCEPTION,
2099 * it is not.
2100 */
2101 if ( (intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_SW_EXCEPTION )
2103 int ilen = __get_instruction_length(); /* Safe: software exception */
2104 vmx_inject_sw_exception(v, vector, ilen);
2106 else
2108 vmx_inject_hw_exception(v, vector, error_code);
2112 asmlinkage void vmx_vmexit_handler(struct cpu_user_regs *regs)
2114 unsigned int exit_reason;
2115 unsigned long exit_qualification, rip, inst_len = 0;
2116 struct vcpu *v = current;
2118 __vmread(VM_EXIT_REASON, &exit_reason);
2120 perfc_incra(vmexits, exit_reason);
2122 if ( (exit_reason != EXIT_REASON_EXTERNAL_INTERRUPT) &&
2123 (exit_reason != EXIT_REASON_VMCALL) &&
2124 (exit_reason != EXIT_REASON_IO_INSTRUCTION) )
2125 HVM_DBG_LOG(DBG_LEVEL_0, "exit reason = %x", exit_reason);
2127 if ( exit_reason != EXIT_REASON_EXTERNAL_INTERRUPT )
2128 local_irq_enable();
2130 if ( unlikely(exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) )
2132 unsigned int failed_vmentry_reason = exit_reason & 0xFFFF;
2134 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2135 printk("Failed vm entry (exit reason 0x%x) ", exit_reason);
2136 switch ( failed_vmentry_reason ) {
2137 case EXIT_REASON_INVALID_GUEST_STATE:
2138 printk("caused by invalid guest state (%ld).\n", exit_qualification);
2139 break;
2140 case EXIT_REASON_MSR_LOADING:
2141 printk("caused by MSR entry %ld loading.\n", exit_qualification);
2142 break;
2143 case EXIT_REASON_MACHINE_CHECK:
2144 printk("caused by machine check.\n");
2145 break;
2146 default:
2147 printk("reason not known yet!");
2148 break;
2151 printk("************* VMCS Area **************\n");
2152 vmcs_dump_vcpu();
2153 printk("**************************************\n");
2154 domain_crash_synchronous();
2157 TRACE_VMEXIT(0,exit_reason);
2159 switch ( exit_reason )
2161 case EXIT_REASON_EXCEPTION_NMI:
2163 /*
2164 * We don't set the software-interrupt exiting (INT n).
2165 * (1) We can get an exception (e.g. #PG) in the guest, or
2166 * (2) NMI
2167 */
2168 unsigned int vector;
2169 unsigned long va;
2171 if ( __vmread(VM_EXIT_INTR_INFO, &vector) ||
2172 !(vector & INTR_INFO_VALID_MASK) )
2173 domain_crash_synchronous();
2174 vector &= INTR_INFO_VECTOR_MASK;
2176 TRACE_VMEXIT(1,vector);
2177 perfc_incra(cause_vector, vector);
2179 switch ( vector ) {
2180 #ifdef XEN_DEBUGGER
2181 case TRAP_debug:
2183 save_cpu_user_regs(regs);
2184 pdb_handle_exception(1, regs, 1);
2185 restore_cpu_user_regs(regs);
2186 break;
2188 case TRAP_int3:
2190 save_cpu_user_regs(regs);
2191 pdb_handle_exception(3, regs, 1);
2192 restore_cpu_user_regs(regs);
2193 break;
2195 #else
2196 case TRAP_debug:
2198 void store_cpu_user_regs(struct cpu_user_regs *regs);
2200 if ( test_bit(_DOMF_debugging, &v->domain->domain_flags) )
2202 store_cpu_user_regs(regs);
2203 domain_pause_for_debugger();
2204 __vm_clear_bit(GUEST_PENDING_DBG_EXCEPTIONS,
2205 PENDING_DEBUG_EXC_BS);
2207 else
2209 vmx_reflect_exception(v);
2210 __vm_clear_bit(GUEST_PENDING_DBG_EXCEPTIONS,
2211 PENDING_DEBUG_EXC_BS);
2214 break;
2216 case TRAP_int3:
2218 if ( test_bit(_DOMF_debugging, &v->domain->domain_flags) )
2219 domain_pause_for_debugger();
2220 else
2221 vmx_reflect_exception(v);
2222 break;
2224 #endif
2225 case TRAP_no_device:
2227 vmx_do_no_device_fault();
2228 break;
2230 case TRAP_page_fault:
2232 __vmread(EXIT_QUALIFICATION, &va);
2233 __vmread(VM_EXIT_INTR_ERROR_CODE, &regs->error_code);
2235 TRACE_VMEXIT(3, regs->error_code);
2236 TRACE_VMEXIT(4, va);
2238 HVM_DBG_LOG(DBG_LEVEL_VMMU,
2239 "eax=%lx, ebx=%lx, ecx=%lx, edx=%lx, esi=%lx, edi=%lx",
2240 (unsigned long)regs->eax, (unsigned long)regs->ebx,
2241 (unsigned long)regs->ecx, (unsigned long)regs->edx,
2242 (unsigned long)regs->esi, (unsigned long)regs->edi);
2244 if ( !vmx_do_page_fault(va, regs) )
2246 /* Inject #PG using Interruption-Information Fields. */
2247 vmx_inject_hw_exception(v, TRAP_page_fault, regs->error_code);
2248 v->arch.hvm_vmx.cpu_cr2 = va;
2249 TRACE_3D(TRC_VMX_INT, v->domain->domain_id,
2250 TRAP_page_fault, va);
2252 break;
2254 case TRAP_nmi:
2255 do_nmi(regs);
2256 break;
2257 default:
2258 vmx_reflect_exception(v);
2259 break;
2261 break;
2263 case EXIT_REASON_EXTERNAL_INTERRUPT:
2264 vmx_vmexit_do_extint(regs);
2265 break;
2266 case EXIT_REASON_TRIPLE_FAULT:
2267 domain_crash_synchronous();
2268 break;
2269 case EXIT_REASON_PENDING_INTERRUPT:
2270 /* Disable the interrupt window. */
2271 v->arch.hvm_vcpu.u.vmx.exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2272 __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
2273 v->arch.hvm_vcpu.u.vmx.exec_control);
2274 break;
2275 case EXIT_REASON_TASK_SWITCH:
2276 domain_crash_synchronous();
2277 break;
2278 case EXIT_REASON_CPUID:
2279 inst_len = __get_instruction_length(); /* Safe: CPUID */
2280 __update_guest_eip(inst_len);
2281 vmx_vmexit_do_cpuid(regs);
2282 break;
2283 case EXIT_REASON_HLT:
2284 inst_len = __get_instruction_length(); /* Safe: HLT */
2285 __update_guest_eip(inst_len);
2286 vmx_vmexit_do_hlt();
2287 break;
2288 case EXIT_REASON_INVLPG:
2290 unsigned long va;
2291 inst_len = __get_instruction_length(); /* Safe: INVLPG */
2292 __update_guest_eip(inst_len);
2293 __vmread(EXIT_QUALIFICATION, &va);
2294 vmx_vmexit_do_invlpg(va);
2295 break;
2297 case EXIT_REASON_VMCALL:
2299 inst_len = __get_instruction_length(); /* Safe: VMCALL */
2300 __update_guest_eip(inst_len);
2301 __vmread(GUEST_RIP, &rip);
2302 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2303 hvm_do_hypercall(regs);
2304 break;
2306 case EXIT_REASON_CR_ACCESS:
2308 __vmread(GUEST_RIP, &rip);
2309 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2310 inst_len = __get_instruction_length(); /* Safe: MOV Cn, LMSW, CLTS */
2311 if ( vmx_cr_access(exit_qualification, regs) )
2312 __update_guest_eip(inst_len);
2313 TRACE_VMEXIT(3, regs->error_code);
2314 TRACE_VMEXIT(4, exit_qualification);
2315 break;
2317 case EXIT_REASON_DR_ACCESS:
2318 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2319 vmx_dr_access(exit_qualification, regs);
2320 break;
2321 case EXIT_REASON_IO_INSTRUCTION:
2322 __vmread(EXIT_QUALIFICATION, &exit_qualification);
2323 inst_len = __get_instruction_length(); /* Safe: IN, INS, OUT, OUTS */
2324 vmx_io_instruction(exit_qualification, inst_len);
2325 TRACE_VMEXIT(4,exit_qualification);
2326 break;
2327 case EXIT_REASON_MSR_READ:
2328 inst_len = __get_instruction_length(); /* Safe: RDMSR */
2329 __update_guest_eip(inst_len);
2330 vmx_do_msr_read(regs);
2331 break;
2332 case EXIT_REASON_MSR_WRITE:
2333 inst_len = __get_instruction_length(); /* Safe: WRMSR */
2334 __update_guest_eip(inst_len);
2335 vmx_do_msr_write(regs);
2336 break;
2337 case EXIT_REASON_MWAIT_INSTRUCTION:
2338 case EXIT_REASON_MONITOR_INSTRUCTION:
2339 case EXIT_REASON_PAUSE_INSTRUCTION:
2340 domain_crash_synchronous();
2341 break;
2342 case EXIT_REASON_VMCLEAR:
2343 case EXIT_REASON_VMLAUNCH:
2344 case EXIT_REASON_VMPTRLD:
2345 case EXIT_REASON_VMPTRST:
2346 case EXIT_REASON_VMREAD:
2347 case EXIT_REASON_VMRESUME:
2348 case EXIT_REASON_VMWRITE:
2349 case EXIT_REASON_VMXOFF:
2350 case EXIT_REASON_VMXON:
2351 /* Report invalid opcode exception when a VMX guest tries to execute
2352 any of the VMX instructions */
2353 vmx_inject_hw_exception(v, TRAP_invalid_op, VMX_DELIVER_NO_ERROR_CODE);
2354 break;
2356 default:
2357 domain_crash_synchronous(); /* should not happen */
2361 asmlinkage void vmx_load_cr2(void)
2363 struct vcpu *v = current;
2365 local_irq_disable();
2366 asm volatile("mov %0,%%cr2": :"r" (v->arch.hvm_vmx.cpu_cr2));
2369 asmlinkage void vmx_trace_vmentry (void)
2371 TRACE_5D(TRC_VMX_VMENTRY,
2372 this_cpu(trace_values)[0],
2373 this_cpu(trace_values)[1],
2374 this_cpu(trace_values)[2],
2375 this_cpu(trace_values)[3],
2376 this_cpu(trace_values)[4]);
2377 TRACE_VMEXIT(0,9);
2378 TRACE_VMEXIT(1,9);
2379 TRACE_VMEXIT(2,9);
2380 TRACE_VMEXIT(3,9);
2381 TRACE_VMEXIT(4,9);
2382 return;
2385 asmlinkage void vmx_trace_vmexit (void)
2387 TRACE_3D(TRC_VMX_VMEXIT,0,0,0);
2388 return;
2391 /*
2392 * Local variables:
2393 * mode: C
2394 * c-set-style: "BSD"
2395 * c-basic-offset: 4
2396 * tab-width: 4
2397 * indent-tabs-mode: nil
2398 * End:
2399 */