direct-io.hg

view xen/include/asm-x86/processor.h @ 15412:acb7aa72fac7

i386: remove NMI deferral by instead making sure selector registers
are always stored/restored correctly despite the potential for an NMI
(and also MCE, with a subsequent patch) to kick in.

The idea is to always check values read from %ds and %es against
__HYPERVISOR_DS, and only store into the current frame (all normal
handlers) or the outer-most one (NMI and MCE) if the value read is
different. That way, any NMI or MCE occurring during frame setup will
store selectors not saved so far on behalf of the interrupted handler,
with that interrupted handler either having managed to read the guest
selector (in which case it can store it regardless of whether NMI/MCE
kicked in between the read and the store) or finding __HYPERVISOR_DS
already in the register, in which case it'll know not to store (as the
nested handler would have done the store).

For the restore portion this makes use of the fact that there's
exactly one such code sequence, and by moving the selector restore
part past all other restores (including all stack pointer adjustments)
the NMI/MCE handlers can safely detect whether any selector would have
been restored already (by range checking EIP) and move EIP back to the
beginning of the selector restore sequence without having to play with
the stack pointer itself or any other gpr.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Thu Jun 21 12:13:06 2007 +0100 (2007-06-21)
parents bd73cb523111
children 3cf5052ba5e5
line source
2 /* Portions are: Copyright (c) 1994 Linus Torvalds */
4 #ifndef __ASM_X86_PROCESSOR_H
5 #define __ASM_X86_PROCESSOR_H
7 #ifndef __ASSEMBLY__
8 #include <xen/config.h>
9 #include <xen/cache.h>
10 #include <xen/types.h>
11 #include <public/xen.h>
12 #include <asm/types.h>
13 #include <asm/cpufeature.h>
14 #include <asm/desc.h>
15 #endif
17 /*
18 * CPU vendor IDs
19 */
20 #define X86_VENDOR_INTEL 0
21 #define X86_VENDOR_CYRIX 1
22 #define X86_VENDOR_AMD 2
23 #define X86_VENDOR_UMC 3
24 #define X86_VENDOR_NEXGEN 4
25 #define X86_VENDOR_CENTAUR 5
26 #define X86_VENDOR_RISE 6
27 #define X86_VENDOR_TRANSMETA 7
28 #define X86_VENDOR_NSC 8
29 #define X86_VENDOR_NUM 9
30 #define X86_VENDOR_UNKNOWN 0xff
32 /*
33 * EFLAGS bits
34 */
35 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */
36 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */
37 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */
38 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */
39 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */
40 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */
41 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */
42 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */
43 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */
44 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */
45 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */
46 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */
47 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */
48 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */
49 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
50 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
51 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */
53 /*
54 * Intel CPU flags in CR0
55 */
56 #define X86_CR0_PE 0x00000001 /* Enable Protected Mode (RW) */
57 #define X86_CR0_MP 0x00000002 /* Monitor Coprocessor (RW) */
58 #define X86_CR0_EM 0x00000004 /* Require FPU Emulation (RO) */
59 #define X86_CR0_TS 0x00000008 /* Task Switched (RW) */
60 #define X86_CR0_ET 0x00000010 /* Extension type (RO) */
61 #define X86_CR0_NE 0x00000020 /* Numeric Error Reporting (RW) */
62 #define X86_CR0_WP 0x00010000 /* Supervisor Write Protect (RW) */
63 #define X86_CR0_AM 0x00040000 /* Alignment Checking (RW) */
64 #define X86_CR0_NW 0x20000000 /* Not Write-Through (RW) */
65 #define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */
66 #define X86_CR0_PG 0x80000000 /* Paging (RW) */
68 /*
69 * Intel CPU features in CR4
70 */
71 #define X86_CR4_VME 0x0001 /* enable vm86 extensions */
72 #define X86_CR4_PVI 0x0002 /* virtual interrupts flag enable */
73 #define X86_CR4_TSD 0x0004 /* disable time stamp at ipl 3 */
74 #define X86_CR4_DE 0x0008 /* enable debugging extensions */
75 #define X86_CR4_PSE 0x0010 /* enable page size extensions */
76 #define X86_CR4_PAE 0x0020 /* enable physical address extensions */
77 #define X86_CR4_MCE 0x0040 /* Machine check enable */
78 #define X86_CR4_PGE 0x0080 /* enable global pages */
79 #define X86_CR4_PCE 0x0100 /* enable performance counters at ipl 3 */
80 #define X86_CR4_OSFXSR 0x0200 /* enable fast FPU save and restore */
81 #define X86_CR4_OSXMMEXCPT 0x0400 /* enable unmasked SSE exceptions */
82 #define X86_CR4_VMXE 0x2000 /* enable VMX */
84 /*
85 * Trap/fault mnemonics.
86 */
87 #define TRAP_divide_error 0
88 #define TRAP_debug 1
89 #define TRAP_nmi 2
90 #define TRAP_int3 3
91 #define TRAP_overflow 4
92 #define TRAP_bounds 5
93 #define TRAP_invalid_op 6
94 #define TRAP_no_device 7
95 #define TRAP_double_fault 8
96 #define TRAP_copro_seg 9
97 #define TRAP_invalid_tss 10
98 #define TRAP_no_segment 11
99 #define TRAP_stack_error 12
100 #define TRAP_gp_fault 13
101 #define TRAP_page_fault 14
102 #define TRAP_spurious_int 15
103 #define TRAP_copro_error 16
104 #define TRAP_alignment_check 17
105 #define TRAP_machine_check 18
106 #define TRAP_simd_error 19
108 /* Set for entry via SYSCALL. Informs return code to use SYSRETQ not IRETQ. */
109 /* NB. Same as VGCF_in_syscall. No bits in common with any other TRAP_ defn. */
110 #define TRAP_syscall 256
112 /*
113 * Non-fatal fault/trap handlers return an error code to the caller. If the
114 * code is non-zero, it means that either the exception was not due to a fault
115 * (i.e., it was a trap) or that the fault has been fixed up so the instruction
116 * replay ought to succeed.
117 */
118 #define EXCRET_not_a_fault 1 /* It was a trap. No instruction replay needed. */
119 #define EXCRET_fault_fixed 1 /* It was fault that we fixed: try a replay. */
121 /* 'trap_bounce' flags values */
122 #define TBF_EXCEPTION 1
123 #define TBF_EXCEPTION_ERRCODE 2
124 #define TBF_INTERRUPT 8
125 #define TBF_FAILSAFE 16
127 /* 'arch_vcpu' flags values */
128 #define _TF_kernel_mode 0
129 #define TF_kernel_mode (1<<_TF_kernel_mode)
131 /* #PF error code values. */
132 #define PFEC_page_present (1U<<0)
133 #define PFEC_write_access (1U<<1)
134 #define PFEC_user_mode (1U<<2)
135 #define PFEC_reserved_bit (1U<<3)
136 #define PFEC_insn_fetch (1U<<4)
138 #ifndef __ASSEMBLY__
140 struct domain;
141 struct vcpu;
143 /*
144 * Default implementation of macro that returns current
145 * instruction pointer ("program counter").
146 */
147 #ifdef __x86_64__
148 #define current_text_addr() ({ void *pc; asm volatile("leaq 1f(%%rip),%0\n1:":"=r"(pc)); pc; })
149 #else
150 #define current_text_addr() \
151 ({ void *pc; __asm__("movl $1f,%0\n1:":"=g" (pc)); pc; })
152 #endif
154 struct cpuinfo_x86 {
155 __u8 x86; /* CPU family */
156 __u8 x86_vendor; /* CPU vendor */
157 __u8 x86_model;
158 __u8 x86_mask;
159 char wp_works_ok; /* It doesn't on 386's */
160 char hlt_works_ok; /* Problems on some 486Dx4's and old 386's */
161 char hard_math;
162 char rfu;
163 int cpuid_level; /* Maximum supported CPUID level, -1=no CPUID */
164 unsigned int x86_capability[NCAPINTS];
165 char x86_vendor_id[16];
166 char x86_model_id[64];
167 int x86_cache_size; /* in KB - valid for CPUS which support this call */
168 int x86_cache_alignment; /* In bytes */
169 char fdiv_bug;
170 char f00f_bug;
171 char coma_bug;
172 char pad0;
173 int x86_power;
174 unsigned char x86_max_cores; /* cpuid returned max cores value */
175 unsigned char booted_cores; /* number of cores as seen by OS */
176 unsigned char apicid;
177 } __cacheline_aligned;
179 /*
180 * capabilities of CPUs
181 */
183 extern struct cpuinfo_x86 boot_cpu_data;
185 #ifdef CONFIG_SMP
186 extern struct cpuinfo_x86 cpu_data[];
187 #define current_cpu_data cpu_data[smp_processor_id()]
188 #else
189 #define cpu_data (&boot_cpu_data)
190 #define current_cpu_data boot_cpu_data
191 #endif
193 extern int phys_proc_id[NR_CPUS];
194 extern int cpu_core_id[NR_CPUS];
196 extern void identify_cpu(struct cpuinfo_x86 *);
197 extern void print_cpu_info(struct cpuinfo_x86 *);
198 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
199 extern void dodgy_tsc(void);
201 #ifdef CONFIG_X86_HT
202 extern void detect_ht(struct cpuinfo_x86 *c);
203 #else
204 static always_inline void detect_ht(struct cpuinfo_x86 *c) {}
205 #endif
207 /*
208 * Generic CPUID function
209 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
210 * resulting in stale register contents being returned.
211 */
212 #define cpuid(_op,_eax,_ebx,_ecx,_edx) \
213 __asm__("cpuid" \
214 : "=a" (*(int *)(_eax)), \
215 "=b" (*(int *)(_ebx)), \
216 "=c" (*(int *)(_ecx)), \
217 "=d" (*(int *)(_edx)) \
218 : "0" (_op), "2" (0))
220 /* Some CPUID calls want 'count' to be placed in ecx */
221 static inline void cpuid_count(
222 int op,
223 int count,
224 unsigned int *eax,
225 unsigned int *ebx,
226 unsigned int *ecx,
227 unsigned int *edx)
228 {
229 __asm__("cpuid"
230 : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
231 : "0" (op), "c" (count));
232 }
234 /*
235 * CPUID functions returning a single datum
236 */
237 static always_inline unsigned int cpuid_eax(unsigned int op)
238 {
239 unsigned int eax;
241 __asm__("cpuid"
242 : "=a" (eax)
243 : "0" (op)
244 : "bx", "cx", "dx");
245 return eax;
246 }
247 static always_inline unsigned int cpuid_ebx(unsigned int op)
248 {
249 unsigned int eax, ebx;
251 __asm__("cpuid"
252 : "=a" (eax), "=b" (ebx)
253 : "0" (op)
254 : "cx", "dx" );
255 return ebx;
256 }
257 static always_inline unsigned int cpuid_ecx(unsigned int op)
258 {
259 unsigned int eax, ecx;
261 __asm__("cpuid"
262 : "=a" (eax), "=c" (ecx)
263 : "0" (op)
264 : "bx", "dx" );
265 return ecx;
266 }
267 static always_inline unsigned int cpuid_edx(unsigned int op)
268 {
269 unsigned int eax, edx;
271 __asm__("cpuid"
272 : "=a" (eax), "=d" (edx)
273 : "0" (op)
274 : "bx", "cx");
275 return edx;
276 }
280 static inline unsigned long read_cr0(void)
281 {
282 unsigned long __cr0;
283 __asm__("mov %%cr0,%0\n\t" :"=r" (__cr0));
284 return __cr0;
285 }
287 static inline void write_cr0(unsigned long val)
288 {
289 __asm__("mov %0,%%cr0": :"r" ((unsigned long)val));
290 }
292 static inline unsigned long read_cr2(void)
293 {
294 unsigned long __cr2;
295 __asm__("mov %%cr2,%0\n\t" :"=r" (__cr2));
296 return __cr2;
297 }
299 static inline unsigned long read_cr4(void)
300 {
301 unsigned long __cr4;
302 __asm__("mov %%cr4,%0\n\t" :"=r" (__cr4));
303 return __cr4;
304 }
306 static inline void write_cr4(unsigned long val)
307 {
308 __asm__("mov %0,%%cr4": :"r" ((unsigned long)val));
309 }
312 /* Clear and set 'TS' bit respectively */
313 static inline void clts(void)
314 {
315 __asm__ __volatile__ ("clts");
316 }
318 static inline void stts(void)
319 {
320 write_cr0(X86_CR0_TS|read_cr0());
321 }
324 /*
325 * Save the cr4 feature set we're using (ie
326 * Pentium 4MB enable and PPro Global page
327 * enable), so that any CPU's that boot up
328 * after us can get the correct flags.
329 */
330 extern unsigned long mmu_cr4_features;
332 static always_inline void set_in_cr4 (unsigned long mask)
333 {
334 unsigned long dummy;
335 mmu_cr4_features |= mask;
336 __asm__ __volatile__ (
337 "mov %%cr4,%0\n\t"
338 "or %1,%0\n\t"
339 "mov %0,%%cr4\n"
340 : "=&r" (dummy) : "irg" (mask) );
341 }
343 static always_inline void clear_in_cr4 (unsigned long mask)
344 {
345 unsigned long dummy;
346 mmu_cr4_features &= ~mask;
347 __asm__ __volatile__ (
348 "mov %%cr4,%0\n\t"
349 "and %1,%0\n\t"
350 "mov %0,%%cr4\n"
351 : "=&r" (dummy) : "irg" (~mask) );
352 }
354 /*
355 * NSC/Cyrix CPU configuration register indexes
356 */
358 #define CX86_PCR0 0x20
359 #define CX86_GCR 0xb8
360 #define CX86_CCR0 0xc0
361 #define CX86_CCR1 0xc1
362 #define CX86_CCR2 0xc2
363 #define CX86_CCR3 0xc3
364 #define CX86_CCR4 0xe8
365 #define CX86_CCR5 0xe9
366 #define CX86_CCR6 0xea
367 #define CX86_CCR7 0xeb
368 #define CX86_PCR1 0xf0
369 #define CX86_DIR0 0xfe
370 #define CX86_DIR1 0xff
371 #define CX86_ARR_BASE 0xc4
372 #define CX86_RCR_BASE 0xdc
374 /*
375 * NSC/Cyrix CPU indexed register access macros
376 */
378 #define getCx86(reg) ({ outb((reg), 0x22); inb(0x23); })
380 #define setCx86(reg, data) do { \
381 outb((reg), 0x22); \
382 outb((data), 0x23); \
383 } while (0)
385 /* Stop speculative execution */
386 static inline void sync_core(void)
387 {
388 int tmp;
389 asm volatile("cpuid" : "=a" (tmp) : "0" (1) : "ebx","ecx","edx","memory");
390 }
392 static always_inline void __monitor(const void *eax, unsigned long ecx,
393 unsigned long edx)
394 {
395 /* "monitor %eax,%ecx,%edx;" */
396 asm volatile(
397 ".byte 0x0f,0x01,0xc8;"
398 : :"a" (eax), "c" (ecx), "d"(edx));
399 }
401 static always_inline void __mwait(unsigned long eax, unsigned long ecx)
402 {
403 /* "mwait %eax,%ecx;" */
404 asm volatile(
405 ".byte 0x0f,0x01,0xc9;"
406 : :"a" (eax), "c" (ecx));
407 }
409 #define IOBMP_BYTES 8192
410 #define IOBMP_INVALID_OFFSET 0x8000
412 struct tss_struct {
413 unsigned short back_link,__blh;
414 #ifdef __x86_64__
415 union { u64 rsp0, esp0; };
416 union { u64 rsp1, esp1; };
417 union { u64 rsp2, esp2; };
418 u64 reserved1;
419 u64 ist[7];
420 u64 reserved2;
421 u16 reserved3;
422 #else
423 u32 esp0;
424 u16 ss0,__ss0h;
425 u32 esp1;
426 u16 ss1,__ss1h;
427 u32 esp2;
428 u16 ss2,__ss2h;
429 u32 __cr3;
430 u32 eip;
431 u32 eflags;
432 u32 eax,ecx,edx,ebx;
433 u32 esp;
434 u32 ebp;
435 u32 esi;
436 u32 edi;
437 u16 es, __esh;
438 u16 cs, __csh;
439 u16 ss, __ssh;
440 u16 ds, __dsh;
441 u16 fs, __fsh;
442 u16 gs, __gsh;
443 u16 ldt, __ldth;
444 u16 trace;
445 #endif
446 u16 bitmap;
447 /* Pads the TSS to be cacheline-aligned (total size is 0x80). */
448 u8 __cacheline_filler[24];
449 } __cacheline_aligned __attribute__((packed));
451 #define IDT_ENTRIES 256
452 extern idt_entry_t idt_table[];
453 extern idt_entry_t *idt_tables[];
455 extern struct tss_struct init_tss[NR_CPUS];
457 extern void init_int80_direct_trap(struct vcpu *v);
459 #if defined(CONFIG_X86_32)
461 #define set_int80_direct_trap(_ed) \
462 (memcpy(idt_tables[(_ed)->processor] + 0x80, \
463 &((_ed)->arch.int80_desc), 8))
465 #else
467 #define set_int80_direct_trap(_ed) ((void)0)
469 #endif
471 extern int gpf_emulate_4gb(struct cpu_user_regs *regs);
473 extern void write_ptbase(struct vcpu *v);
475 void destroy_gdt(struct vcpu *d);
476 long set_gdt(struct vcpu *d,
477 unsigned long *frames,
478 unsigned int entries);
480 long set_debugreg(struct vcpu *p, int reg, unsigned long value);
482 struct microcode_header {
483 unsigned int hdrver;
484 unsigned int rev;
485 unsigned int date;
486 unsigned int sig;
487 unsigned int cksum;
488 unsigned int ldrver;
489 unsigned int pf;
490 unsigned int datasize;
491 unsigned int totalsize;
492 unsigned int reserved[3];
493 };
495 struct microcode {
496 struct microcode_header hdr;
497 unsigned int bits[0];
498 };
500 typedef struct microcode microcode_t;
501 typedef struct microcode_header microcode_header_t;
503 /* microcode format is extended from prescott processors */
504 struct extended_signature {
505 unsigned int sig;
506 unsigned int pf;
507 unsigned int cksum;
508 };
510 struct extended_sigtable {
511 unsigned int count;
512 unsigned int cksum;
513 unsigned int reserved[3];
514 struct extended_signature sigs[0];
515 };
517 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
518 static always_inline void rep_nop(void)
519 {
520 __asm__ __volatile__ ( "rep;nop" : : : "memory" );
521 }
523 #define cpu_relax() rep_nop()
525 /* Prefetch instructions for Pentium III and AMD Athlon */
526 #ifdef CONFIG_MPENTIUMIII
528 #define ARCH_HAS_PREFETCH
529 extern always_inline void prefetch(const void *x)
530 {
531 __asm__ __volatile__ ("prefetchnta (%0)" : : "r"(x));
532 }
534 #elif CONFIG_X86_USE_3DNOW
536 #define ARCH_HAS_PREFETCH
537 #define ARCH_HAS_PREFETCHW
538 #define ARCH_HAS_SPINLOCK_PREFETCH
540 extern always_inline void prefetch(const void *x)
541 {
542 __asm__ __volatile__ ("prefetch (%0)" : : "r"(x));
543 }
545 extern always_inline void prefetchw(const void *x)
546 {
547 __asm__ __volatile__ ("prefetchw (%0)" : : "r"(x));
548 }
549 #define spin_lock_prefetch(x) prefetchw(x)
551 #endif
553 void show_stack(struct cpu_user_regs *regs);
554 void show_stack_overflow(unsigned int cpu, unsigned long esp);
555 void show_registers(struct cpu_user_regs *regs);
556 void show_execution_state(struct cpu_user_regs *regs);
557 void show_page_walk(unsigned long addr);
558 asmlinkage void fatal_trap(int trapnr, struct cpu_user_regs *regs);
560 #ifdef CONFIG_COMPAT
561 void compat_show_guest_stack(struct cpu_user_regs *, int lines);
562 #else
563 #define compat_show_guest_stack(regs, lines) ((void)0)
564 #endif
566 extern void mtrr_ap_init(void);
567 extern void mtrr_bp_init(void);
569 extern void mcheck_init(struct cpuinfo_x86 *c);
571 int cpuid_hypervisor_leaves(
572 uint32_t idx, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
573 int rdmsr_hypervisor_regs(
574 uint32_t idx, uint32_t *eax, uint32_t *edx);
575 int wrmsr_hypervisor_regs(
576 uint32_t idx, uint32_t eax, uint32_t edx);
578 #endif /* !__ASSEMBLY__ */
580 #endif /* __ASM_X86_PROCESSOR_H */
582 /*
583 * Local variables:
584 * mode: C
585 * c-set-style: "BSD"
586 * c-basic-offset: 4
587 * tab-width: 4
588 * indent-tabs-mode: nil
589 * End:
590 */