direct-io.hg

view xen/arch/x86/mpparse.c @ 11135:88e6bd5e2b54

Whitespace clean-ups.

Signed-off-by: Steven Hand <steven@xensource.com>
author shand@kneesaa.uk.xensource.com
date Wed Aug 16 11:36:13 2006 +0100 (2006-08-16)
parents 887ff2d1e382
children f07cf18343f1
line source
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
16 #include <xen/config.h>
17 #include <xen/types.h>
18 #include <xen/irq.h>
19 #include <xen/init.h>
20 #include <xen/acpi.h>
21 #include <xen/delay.h>
22 #include <xen/sched.h>
24 #include <asm/mc146818rtc.h>
25 #include <asm/bitops.h>
26 #include <asm/smp.h>
27 #include <asm/acpi.h>
28 #include <asm/mtrr.h>
29 #include <asm/mpspec.h>
30 #include <asm/io_apic.h>
32 #include <mach_apic.h>
33 #include <mach_mpparse.h>
34 #include <bios_ebda.h>
36 /* Have we found an MP table */
37 int smp_found_config;
38 unsigned int __devinitdata maxcpus = NR_CPUS;
40 #ifdef CONFIG_HOTPLUG_CPU
41 #define CPU_HOTPLUG_ENABLED (1)
42 #else
43 #define CPU_HOTPLUG_ENABLED (0)
44 #endif
46 /*
47 * Various Linux-internal data structures created from the
48 * MP-table.
49 */
50 int apic_version [MAX_APICS];
51 int mp_bus_id_to_type [MAX_MP_BUSSES];
52 int mp_bus_id_to_node [MAX_MP_BUSSES];
53 int mp_bus_id_to_local [MAX_MP_BUSSES];
54 int quad_local_to_mp_bus_id [NR_CPUS/4][4];
55 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
56 static int mp_current_pci_id;
58 /* I/O APIC entries */
59 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
61 /* # of MP IRQ source entries */
62 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
64 /* MP IRQ source entries */
65 int mp_irq_entries;
67 int nr_ioapics;
69 int pic_mode;
70 unsigned long mp_lapic_addr;
72 unsigned int def_to_bigsmp = 0;
74 /* Processor that is doing the boot up */
75 unsigned int boot_cpu_physical_apicid = -1U;
76 unsigned int boot_cpu_logical_apicid = -1U;
77 /* Internal processor count */
78 static unsigned int __initdata num_processors;
80 /* Bitmask of physically existing CPUs */
81 physid_mask_t phys_cpu_present_map;
83 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
85 /*
86 * Intel MP BIOS table parsing routines:
87 */
90 /*
91 * Checksum an MP configuration block.
92 */
94 static int __init mpf_checksum(unsigned char *mp, int len)
95 {
96 int sum = 0;
98 while (len--)
99 sum += *mp++;
101 return sum & 0xFF;
102 }
104 /*
105 * Have to match translation table entries to main table entries by counter
106 * hence the mpc_record variable .... can't see a less disgusting way of
107 * doing this ....
108 */
110 static int mpc_record;
111 static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata;
113 #ifdef CONFIG_X86_NUMAQ
114 static int MP_valid_apicid(int apicid, int version)
115 {
116 return hweight_long(apicid & 0xf) == 1 && (apicid >> 4) != 0xf;
117 }
118 #else
119 static int MP_valid_apicid(int apicid, int version)
120 {
121 if (version >= 0x14)
122 return apicid < 0xff;
123 else
124 return apicid < 0xf;
125 }
126 #endif
128 static void __devinit MP_processor_info (struct mpc_config_processor *m)
129 {
130 int ver, apicid;
131 physid_mask_t phys_cpu;
133 if (!(m->mpc_cpuflag & CPU_ENABLED))
134 return;
136 apicid = mpc_apic_id(m, translation_table[mpc_record]);
138 if (m->mpc_featureflag&(1<<0))
139 Dprintk(" Floating point unit present.\n");
140 if (m->mpc_featureflag&(1<<7))
141 Dprintk(" Machine Exception supported.\n");
142 if (m->mpc_featureflag&(1<<8))
143 Dprintk(" 64 bit compare & exchange supported.\n");
144 if (m->mpc_featureflag&(1<<9))
145 Dprintk(" Internal APIC present.\n");
146 if (m->mpc_featureflag&(1<<11))
147 Dprintk(" SEP present.\n");
148 if (m->mpc_featureflag&(1<<12))
149 Dprintk(" MTRR present.\n");
150 if (m->mpc_featureflag&(1<<13))
151 Dprintk(" PGE present.\n");
152 if (m->mpc_featureflag&(1<<14))
153 Dprintk(" MCA present.\n");
154 if (m->mpc_featureflag&(1<<15))
155 Dprintk(" CMOV present.\n");
156 if (m->mpc_featureflag&(1<<16))
157 Dprintk(" PAT present.\n");
158 if (m->mpc_featureflag&(1<<17))
159 Dprintk(" PSE present.\n");
160 if (m->mpc_featureflag&(1<<18))
161 Dprintk(" PSN present.\n");
162 if (m->mpc_featureflag&(1<<19))
163 Dprintk(" Cache Line Flush Instruction present.\n");
164 /* 20 Reserved */
165 if (m->mpc_featureflag&(1<<21))
166 Dprintk(" Debug Trace and EMON Store present.\n");
167 if (m->mpc_featureflag&(1<<22))
168 Dprintk(" ACPI Thermal Throttle Registers present.\n");
169 if (m->mpc_featureflag&(1<<23))
170 Dprintk(" MMX present.\n");
171 if (m->mpc_featureflag&(1<<24))
172 Dprintk(" FXSR present.\n");
173 if (m->mpc_featureflag&(1<<25))
174 Dprintk(" XMM present.\n");
175 if (m->mpc_featureflag&(1<<26))
176 Dprintk(" Willamette New Instructions present.\n");
177 if (m->mpc_featureflag&(1<<27))
178 Dprintk(" Self Snoop present.\n");
179 if (m->mpc_featureflag&(1<<28))
180 Dprintk(" HT present.\n");
181 if (m->mpc_featureflag&(1<<29))
182 Dprintk(" Thermal Monitor present.\n");
183 /* 30, 31 Reserved */
186 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
187 Dprintk(" Bootup CPU\n");
188 boot_cpu_physical_apicid = m->mpc_apicid;
189 }
191 ver = m->mpc_apicver;
193 if (!MP_valid_apicid(apicid, ver)) {
194 printk(KERN_WARNING "Processor #%d INVALID. (Max ID: %d).\n",
195 m->mpc_apicid, MAX_APICS);
196 return;
197 }
199 /*
200 * Validate version
201 */
202 if (ver == 0x0) {
203 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
204 "fixing up to 0x10. (tell your hw vendor)\n",
205 m->mpc_apicid);
206 ver = 0x10;
207 }
208 apic_version[m->mpc_apicid] = ver;
210 phys_cpu = apicid_to_cpu_present(apicid);
211 physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
213 if (num_processors >= NR_CPUS) {
214 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
215 " Processor ignored.\n", NR_CPUS);
216 return;
217 }
219 if (num_processors >= maxcpus) {
220 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
221 " Processor ignored.\n", maxcpus);
222 return;
223 }
225 cpu_set(num_processors, cpu_possible_map);
226 num_processors++;
228 if (CPU_HOTPLUG_ENABLED || (num_processors > 8)) {
229 /*
230 * No need for processor or APIC checks: physical delivery
231 * (bigsmp) mode should always work.
232 */
233 def_to_bigsmp = 1;
234 }
235 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
236 }
238 static void __init MP_bus_info (struct mpc_config_bus *m)
239 {
240 char str[7];
242 memcpy(str, m->mpc_bustype, 6);
243 str[6] = 0;
245 mpc_oem_bus_info(m, str, translation_table[mpc_record]);
247 if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) {
248 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
249 } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) {
250 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
251 } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) {
252 mpc_oem_pci_bus(m, translation_table[mpc_record]);
253 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
254 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
255 mp_current_pci_id++;
256 } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) {
257 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
258 } else if (strncmp(str, BUSTYPE_NEC98, sizeof(BUSTYPE_NEC98)-1) == 0) {
259 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_NEC98;
260 } else {
261 printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
262 }
263 }
265 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
266 {
267 if (!(m->mpc_flags & MPC_APIC_USABLE))
268 return;
270 printk(KERN_INFO "I/O APIC #%d Version %d at 0x%X.\n",
271 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
272 if (nr_ioapics >= MAX_IO_APICS) {
273 printk(KERN_CRIT "Max # of I/O APICs (%d) exceeded (found %d).\n",
274 MAX_IO_APICS, nr_ioapics);
275 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
276 }
277 if (!m->mpc_apicaddr) {
278 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
279 " found in MP table, skipping!\n");
280 return;
281 }
282 mp_ioapics[nr_ioapics] = *m;
283 nr_ioapics++;
284 }
286 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
287 {
288 mp_irqs [mp_irq_entries] = *m;
289 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
290 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
291 m->mpc_irqtype, m->mpc_irqflag & 3,
292 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
293 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
294 if (++mp_irq_entries == MAX_IRQ_SOURCES)
295 panic("Max # of irq sources exceeded!!\n");
296 }
298 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
299 {
300 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
301 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
302 m->mpc_irqtype, m->mpc_irqflag & 3,
303 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
304 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
305 /*
306 * Well it seems all SMP boards in existence
307 * use ExtINT/LVT1 == LINT0 and
308 * NMI/LVT2 == LINT1 - the following check
309 * will show us if this assumptions is false.
310 * Until then we do not have to add baggage.
311 */
312 if ((m->mpc_irqtype == mp_ExtINT) &&
313 (m->mpc_destapiclint != 0))
314 BUG();
315 if ((m->mpc_irqtype == mp_NMI) &&
316 (m->mpc_destapiclint != 1))
317 BUG();
318 }
320 #ifdef CONFIG_X86_NUMAQ
321 static void __init MP_translation_info (struct mpc_config_translation *m)
322 {
323 printk(KERN_INFO "Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local);
325 if (mpc_record >= MAX_MPC_ENTRY)
326 printk(KERN_ERR "MAX_MPC_ENTRY exceeded!\n");
327 else
328 translation_table[mpc_record] = m; /* stash this for later */
329 if (m->trans_quad < MAX_NUMNODES && !node_online(m->trans_quad))
330 node_set_online(m->trans_quad);
331 }
333 /*
334 * Read/parse the MPC oem tables
335 */
337 static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \
338 unsigned short oemsize)
339 {
340 int count = sizeof (*oemtable); /* the header size */
341 unsigned char *oemptr = ((unsigned char *)oemtable)+count;
343 mpc_record = 0;
344 printk(KERN_INFO "Found an OEM MPC table at %8p - parsing it ... \n", oemtable);
345 if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4))
346 {
347 printk(KERN_WARNING "SMP mpc oemtable: bad signature [%c%c%c%c]!\n",
348 oemtable->oem_signature[0],
349 oemtable->oem_signature[1],
350 oemtable->oem_signature[2],
351 oemtable->oem_signature[3]);
352 return;
353 }
354 if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length))
355 {
356 printk(KERN_WARNING "SMP oem mptable: checksum error!\n");
357 return;
358 }
359 while (count < oemtable->oem_length) {
360 switch (*oemptr) {
361 case MP_TRANSLATION:
362 {
363 struct mpc_config_translation *m=
364 (struct mpc_config_translation *)oemptr;
365 MP_translation_info(m);
366 oemptr += sizeof(*m);
367 count += sizeof(*m);
368 ++mpc_record;
369 break;
370 }
371 default:
372 {
373 printk(KERN_WARNING "Unrecognised OEM table entry type! - %d\n", (int) *oemptr);
374 return;
375 }
376 }
377 }
378 }
380 static inline void mps_oem_check(struct mp_config_table *mpc, char *oem,
381 char *productid)
382 {
383 if (strncmp(oem, "IBM NUMA", 8))
384 printk("Warning! May not be a NUMA-Q system!\n");
385 if (mpc->mpc_oemptr)
386 smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr,
387 mpc->mpc_oemsize);
388 }
389 #endif /* CONFIG_X86_NUMAQ */
391 /*
392 * Read/parse the MPC
393 */
395 static int __init smp_read_mpc(struct mp_config_table *mpc)
396 {
397 char str[16];
398 char oem[10];
399 int count=sizeof(*mpc);
400 unsigned char *mpt=((unsigned char *)mpc)+count;
402 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
403 printk(KERN_ERR "SMP mptable: bad signature [0x%x]!\n",
404 *(u32 *)mpc->mpc_signature);
405 return 0;
406 }
407 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
408 printk(KERN_ERR "SMP mptable: checksum error!\n");
409 return 0;
410 }
411 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
412 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
413 mpc->mpc_spec);
414 return 0;
415 }
416 if (!mpc->mpc_lapic) {
417 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
418 return 0;
419 }
420 memcpy(oem,mpc->mpc_oem,8);
421 oem[8]=0;
422 printk(KERN_INFO "OEM ID: %s ",oem);
424 memcpy(str,mpc->mpc_productid,12);
425 str[12]=0;
426 printk("Product ID: %s ",str);
428 mps_oem_check(mpc, oem, str);
430 printk("APIC at: 0x%X\n",mpc->mpc_lapic);
432 /*
433 * Save the local APIC address (it might be non-default) -- but only
434 * if we're not using ACPI.
435 */
436 if (!acpi_lapic)
437 mp_lapic_addr = mpc->mpc_lapic;
439 /*
440 * Now process the configuration blocks.
441 */
442 mpc_record = 0;
443 while (count < mpc->mpc_length) {
444 switch(*mpt) {
445 case MP_PROCESSOR:
446 {
447 struct mpc_config_processor *m=
448 (struct mpc_config_processor *)mpt;
449 /* ACPI may have already provided this data */
450 if (!acpi_lapic)
451 MP_processor_info(m);
452 mpt += sizeof(*m);
453 count += sizeof(*m);
454 break;
455 }
456 case MP_BUS:
457 {
458 struct mpc_config_bus *m=
459 (struct mpc_config_bus *)mpt;
460 MP_bus_info(m);
461 mpt += sizeof(*m);
462 count += sizeof(*m);
463 break;
464 }
465 case MP_IOAPIC:
466 {
467 struct mpc_config_ioapic *m=
468 (struct mpc_config_ioapic *)mpt;
469 MP_ioapic_info(m);
470 mpt+=sizeof(*m);
471 count+=sizeof(*m);
472 break;
473 }
474 case MP_INTSRC:
475 {
476 struct mpc_config_intsrc *m=
477 (struct mpc_config_intsrc *)mpt;
479 MP_intsrc_info(m);
480 mpt+=sizeof(*m);
481 count+=sizeof(*m);
482 break;
483 }
484 case MP_LINTSRC:
485 {
486 struct mpc_config_lintsrc *m=
487 (struct mpc_config_lintsrc *)mpt;
488 MP_lintsrc_info(m);
489 mpt+=sizeof(*m);
490 count+=sizeof(*m);
491 break;
492 }
493 default:
494 {
495 count = mpc->mpc_length;
496 break;
497 }
498 }
499 ++mpc_record;
500 }
501 clustered_apic_check();
502 if (!num_processors)
503 printk(KERN_ERR "SMP mptable: no processors registered!\n");
504 return num_processors;
505 }
507 static int __init ELCR_trigger(unsigned int irq)
508 {
509 unsigned int port;
511 port = 0x4d0 + (irq >> 3);
512 return (inb(port) >> (irq & 7)) & 1;
513 }
515 static void __init construct_default_ioirq_mptable(int mpc_default_type)
516 {
517 struct mpc_config_intsrc intsrc;
518 int i;
519 int ELCR_fallback = 0;
521 intsrc.mpc_type = MP_INTSRC;
522 intsrc.mpc_irqflag = 0; /* conforming */
523 intsrc.mpc_srcbus = 0;
524 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
526 intsrc.mpc_irqtype = mp_INT;
528 /*
529 * If true, we have an ISA/PCI system with no IRQ entries
530 * in the MP table. To prevent the PCI interrupts from being set up
531 * incorrectly, we try to use the ELCR. The sanity check to see if
532 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
533 * never be level sensitive, so we simply see if the ELCR agrees.
534 * If it does, we assume it's valid.
535 */
536 if (mpc_default_type == 5) {
537 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
539 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
540 printk(KERN_WARNING "ELCR contains invalid data... not using ELCR\n");
541 else {
542 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
543 ELCR_fallback = 1;
544 }
545 }
547 for (i = 0; i < 16; i++) {
548 switch (mpc_default_type) {
549 case 2:
550 if (i == 0 || i == 13)
551 continue; /* IRQ0 & IRQ13 not connected */
552 /* fall through */
553 default:
554 if (i == 2)
555 continue; /* IRQ2 is never connected */
556 }
558 if (ELCR_fallback) {
559 /*
560 * If the ELCR indicates a level-sensitive interrupt, we
561 * copy that information over to the MP table in the
562 * irqflag field (level sensitive, active high polarity).
563 */
564 if (ELCR_trigger(i))
565 intsrc.mpc_irqflag = 13;
566 else
567 intsrc.mpc_irqflag = 0;
568 }
570 intsrc.mpc_srcbusirq = i;
571 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
572 MP_intsrc_info(&intsrc);
573 }
575 intsrc.mpc_irqtype = mp_ExtINT;
576 intsrc.mpc_srcbusirq = 0;
577 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
578 MP_intsrc_info(&intsrc);
579 }
581 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
582 {
583 struct mpc_config_processor processor;
584 struct mpc_config_bus bus;
585 struct mpc_config_ioapic ioapic;
586 struct mpc_config_lintsrc lintsrc;
587 int linttypes[2] = { mp_ExtINT, mp_NMI };
588 int i;
590 /*
591 * local APIC has default address
592 */
593 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
595 /*
596 * 2 CPUs, numbered 0 & 1.
597 */
598 processor.mpc_type = MP_PROCESSOR;
599 /* Either an integrated APIC or a discrete 82489DX. */
600 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
601 processor.mpc_cpuflag = CPU_ENABLED;
602 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
603 (boot_cpu_data.x86_model << 4) |
604 boot_cpu_data.x86_mask;
605 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
606 processor.mpc_reserved[0] = 0;
607 processor.mpc_reserved[1] = 0;
608 for (i = 0; i < 2; i++) {
609 processor.mpc_apicid = i;
610 MP_processor_info(&processor);
611 }
613 bus.mpc_type = MP_BUS;
614 bus.mpc_busid = 0;
615 switch (mpc_default_type) {
616 default:
617 printk("???\n");
618 printk(KERN_ERR "Unknown standard configuration %d\n",
619 mpc_default_type);
620 /* fall through */
621 case 1:
622 case 5:
623 memcpy(bus.mpc_bustype, "ISA ", 6);
624 break;
625 case 2:
626 case 6:
627 case 3:
628 memcpy(bus.mpc_bustype, "EISA ", 6);
629 break;
630 case 4:
631 case 7:
632 memcpy(bus.mpc_bustype, "MCA ", 6);
633 }
634 MP_bus_info(&bus);
635 if (mpc_default_type > 4) {
636 bus.mpc_busid = 1;
637 memcpy(bus.mpc_bustype, "PCI ", 6);
638 MP_bus_info(&bus);
639 }
641 ioapic.mpc_type = MP_IOAPIC;
642 ioapic.mpc_apicid = 2;
643 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
644 ioapic.mpc_flags = MPC_APIC_USABLE;
645 ioapic.mpc_apicaddr = 0xFEC00000;
646 MP_ioapic_info(&ioapic);
648 /*
649 * We set up most of the low 16 IO-APIC pins according to MPS rules.
650 */
651 construct_default_ioirq_mptable(mpc_default_type);
653 lintsrc.mpc_type = MP_LINTSRC;
654 lintsrc.mpc_irqflag = 0; /* conforming */
655 lintsrc.mpc_srcbusid = 0;
656 lintsrc.mpc_srcbusirq = 0;
657 lintsrc.mpc_destapic = MP_APIC_ALL;
658 for (i = 0; i < 2; i++) {
659 lintsrc.mpc_irqtype = linttypes[i];
660 lintsrc.mpc_destapiclint = i;
661 MP_lintsrc_info(&lintsrc);
662 }
663 }
665 static struct intel_mp_floating *mpf_found;
667 /*
668 * Scan the memory blocks for an SMP configuration block.
669 */
670 void __init get_smp_config (void)
671 {
672 struct intel_mp_floating *mpf = mpf_found;
674 /*
675 * ACPI supports both logical (e.g. Hyper-Threading) and physical
676 * processors, where MPS only supports physical.
677 */
678 if (acpi_lapic && acpi_ioapic) {
679 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
680 return;
681 }
682 else if (acpi_lapic)
683 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
685 printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
686 if (mpf->mpf_feature2 & (1<<7)) {
687 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
688 pic_mode = 1;
689 } else {
690 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
691 pic_mode = 0;
692 }
694 /*
695 * Now see if we need to read further.
696 */
697 if (mpf->mpf_feature1 != 0) {
699 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
700 construct_default_ISA_mptable(mpf->mpf_feature1);
702 } else if (mpf->mpf_physptr) {
704 /*
705 * Read the physical hardware table. Anything here will
706 * override the defaults.
707 */
708 if (!smp_read_mpc((void *)(unsigned long)mpf->mpf_physptr)) {
709 smp_found_config = 0;
710 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
711 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
712 return;
713 }
714 /*
715 * If there are no explicit MP IRQ entries, then we are
716 * broken. We set up most of the low 16 IO-APIC pins to
717 * ISA defaults and hope it will work.
718 */
719 if (!mp_irq_entries) {
720 struct mpc_config_bus bus;
722 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
724 bus.mpc_type = MP_BUS;
725 bus.mpc_busid = 0;
726 memcpy(bus.mpc_bustype, "ISA ", 6);
727 MP_bus_info(&bus);
729 construct_default_ioirq_mptable(0);
730 }
732 } else
733 BUG();
735 printk(KERN_INFO "Processors: %d\n", num_processors);
736 /*
737 * Only use the first configuration found.
738 */
739 }
741 static int __init smp_scan_config (unsigned long base, unsigned long length)
742 {
743 unsigned int *bp = maddr_to_virt(base);
744 struct intel_mp_floating *mpf;
746 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
747 if (sizeof(*mpf) != 16)
748 printk("Error: MPF size\n");
750 while (length > 0) {
751 mpf = (struct intel_mp_floating *)bp;
752 if ((*bp == SMP_MAGIC_IDENT) &&
753 (mpf->mpf_length == 1) &&
754 !mpf_checksum((unsigned char *)bp, 16) &&
755 ((mpf->mpf_specification == 1)
756 || (mpf->mpf_specification == 4)) ) {
758 smp_found_config = 1;
759 printk(KERN_INFO "found SMP MP-table at %08lx\n",
760 virt_to_maddr(mpf));
761 #if 0
762 reserve_bootmem(virt_to_maddr(mpf), PAGE_SIZE);
763 if (mpf->mpf_physptr) {
764 /*
765 * We cannot access to MPC table to compute
766 * table size yet, as only few megabytes from
767 * the bottom is mapped now.
768 * PC-9800's MPC table places on the very last
769 * of physical memory; so that simply reserving
770 * PAGE_SIZE from mpg->mpf_physptr yields BUG()
771 * in reserve_bootmem.
772 */
773 unsigned long size = PAGE_SIZE;
774 unsigned long end = max_low_pfn * PAGE_SIZE;
775 if (mpf->mpf_physptr + size > end)
776 size = end - mpf->mpf_physptr;
777 reserve_bootmem(mpf->mpf_physptr, size);
778 }
779 #endif
780 mpf_found = mpf;
781 return 1;
782 }
783 bp += 4;
784 length -= 16;
785 }
786 return 0;
787 }
789 void __init find_smp_config (void)
790 {
791 unsigned int address;
793 /*
794 * FIXME: Linux assumes you have 640K of base ram..
795 * this continues the error...
796 *
797 * 1) Scan the bottom 1K for a signature
798 * 2) Scan the top 1K of base RAM
799 * 3) Scan the 64K of bios
800 */
801 if (smp_scan_config(0x0,0x400) ||
802 smp_scan_config(639*0x400,0x400) ||
803 smp_scan_config(0xF0000,0x10000))
804 return;
805 /*
806 * If it is an SMP machine we should know now, unless the
807 * configuration is in an EISA/MCA bus machine with an
808 * extended bios data area.
809 *
810 * there is a real-mode segmented pointer pointing to the
811 * 4K EBDA area at 0x40E, calculate and scan it here.
812 *
813 * NOTE! There are Linux loaders that will corrupt the EBDA
814 * area, and as such this kind of SMP config may be less
815 * trustworthy, simply because the SMP table may have been
816 * stomped on during early boot. These loaders are buggy and
817 * should be fixed.
818 *
819 * MP1.4 SPEC states to only scan first 1K of 4K EBDA.
820 */
822 address = get_bios_ebda();
823 if (address)
824 smp_scan_config(address, 0x400);
825 }
827 /* --------------------------------------------------------------------------
828 ACPI-based MP Configuration
829 -------------------------------------------------------------------------- */
831 #ifdef CONFIG_ACPI
833 void __init mp_register_lapic_address (
834 u64 address)
835 {
836 mp_lapic_addr = (unsigned long) address;
838 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
840 if (boot_cpu_physical_apicid == -1U)
841 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
843 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
844 }
847 void __devinit mp_register_lapic (
848 u8 id,
849 u8 enabled)
850 {
851 struct mpc_config_processor processor;
852 int boot_cpu = 0;
854 if (MAX_APICS - id <= 0) {
855 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
856 id, MAX_APICS);
857 return;
858 }
860 if (id == boot_cpu_physical_apicid)
861 boot_cpu = 1;
863 processor.mpc_type = MP_PROCESSOR;
864 processor.mpc_apicid = id;
865 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
866 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
867 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
868 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
869 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
870 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
871 processor.mpc_reserved[0] = 0;
872 processor.mpc_reserved[1] = 0;
874 MP_processor_info(&processor);
875 }
877 #ifdef CONFIG_X86_IO_APIC
879 #define MP_ISA_BUS 0
880 #define MP_MAX_IOAPIC_PIN 127
882 static struct mp_ioapic_routing {
883 int apic_id;
884 int gsi_base;
885 int gsi_end;
886 u32 pin_programmed[4];
887 } mp_ioapic_routing[MAX_IO_APICS];
890 static int mp_find_ioapic (
891 int gsi)
892 {
893 int i = 0;
895 /* Find the IOAPIC that manages this GSI. */
896 for (i = 0; i < nr_ioapics; i++) {
897 if ((gsi >= mp_ioapic_routing[i].gsi_base)
898 && (gsi <= mp_ioapic_routing[i].gsi_end))
899 return i;
900 }
902 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
904 return -1;
905 }
908 void __init mp_register_ioapic (
909 u8 id,
910 u32 address,
911 u32 gsi_base)
912 {
913 int idx = 0;
914 int tmpid;
916 if (nr_ioapics >= MAX_IO_APICS) {
917 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
918 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
919 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
920 }
921 if (!address) {
922 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
923 " found in MADT table, skipping!\n");
924 return;
925 }
927 idx = nr_ioapics++;
929 mp_ioapics[idx].mpc_type = MP_IOAPIC;
930 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
931 mp_ioapics[idx].mpc_apicaddr = address;
933 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
934 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 < 15))
935 tmpid = io_apic_get_unique_id(idx, id);
936 else
937 tmpid = id;
938 if (tmpid == -1) {
939 nr_ioapics--;
940 return;
941 }
942 mp_ioapics[idx].mpc_apicid = tmpid;
943 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
945 /*
946 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
947 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
948 */
949 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
950 mp_ioapic_routing[idx].gsi_base = gsi_base;
951 mp_ioapic_routing[idx].gsi_end = gsi_base +
952 io_apic_get_redir_entries(idx);
954 printk("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
955 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
956 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
957 mp_ioapic_routing[idx].gsi_base,
958 mp_ioapic_routing[idx].gsi_end);
960 return;
961 }
964 void __init mp_override_legacy_irq (
965 u8 bus_irq,
966 u8 polarity,
967 u8 trigger,
968 u32 gsi)
969 {
970 struct mpc_config_intsrc intsrc;
971 int ioapic = -1;
972 int pin = -1;
974 /*
975 * Convert 'gsi' to 'ioapic.pin'.
976 */
977 ioapic = mp_find_ioapic(gsi);
978 if (ioapic < 0)
979 return;
980 pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
982 /*
983 * TBD: This check is for faulty timer entries, where the override
984 * erroneously sets the trigger to level, resulting in a HUGE
985 * increase of timer interrupts!
986 */
987 if ((bus_irq == 0) && (trigger == 3))
988 trigger = 1;
990 intsrc.mpc_type = MP_INTSRC;
991 intsrc.mpc_irqtype = mp_INT;
992 intsrc.mpc_irqflag = (trigger << 2) | polarity;
993 intsrc.mpc_srcbus = MP_ISA_BUS;
994 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
995 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
996 intsrc.mpc_dstirq = pin; /* INTIN# */
998 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
999 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1000 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1001 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
1003 mp_irqs[mp_irq_entries] = intsrc;
1004 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1005 panic("Max # of irq sources exceeded!\n");
1007 return;
1011 void __init mp_config_acpi_legacy_irqs (void)
1013 struct mpc_config_intsrc intsrc;
1014 int i = 0;
1015 int ioapic = -1;
1017 /*
1018 * Fabricate the legacy ISA bus (bus #31).
1019 */
1020 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
1021 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
1023 /*
1024 * Older generations of ES7000 have no legacy identity mappings
1025 */
1026 if (es7000_plat == 1)
1027 return;
1029 /*
1030 * Locate the IOAPIC that manages the ISA IRQs (0-15).
1031 */
1032 ioapic = mp_find_ioapic(0);
1033 if (ioapic < 0)
1034 return;
1036 intsrc.mpc_type = MP_INTSRC;
1037 intsrc.mpc_irqflag = 0; /* Conforming */
1038 intsrc.mpc_srcbus = MP_ISA_BUS;
1039 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
1041 /*
1042 * Use the default configuration for the IRQs 0-15. Unless
1043 * overriden by (MADT) interrupt source override entries.
1044 */
1045 for (i = 0; i < 16; i++) {
1046 int idx;
1048 for (idx = 0; idx < mp_irq_entries; idx++) {
1049 struct mpc_config_intsrc *irq = mp_irqs + idx;
1051 /* Do we already have a mapping for this ISA IRQ? */
1052 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
1053 break;
1055 /* Do we already have a mapping for this IOAPIC pin */
1056 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
1057 (irq->mpc_dstirq == i))
1058 break;
1061 if (idx != mp_irq_entries) {
1062 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
1063 continue; /* IRQ already used */
1066 intsrc.mpc_irqtype = mp_INT;
1067 intsrc.mpc_srcbusirq = i; /* Identity mapped */
1068 intsrc.mpc_dstirq = i;
1070 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
1071 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
1072 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
1073 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
1074 intsrc.mpc_dstirq);
1076 mp_irqs[mp_irq_entries] = intsrc;
1077 if (++mp_irq_entries == MAX_IRQ_SOURCES)
1078 panic("Max # of irq sources exceeded!\n");
1082 #define MAX_GSI_NUM 4096
1084 int mp_register_gsi (u32 gsi, int triggering, int polarity)
1086 int ioapic = -1;
1087 int ioapic_pin = 0;
1088 int idx, bit = 0;
1089 static int pci_irq = 16;
1090 /*
1091 * Mapping between Global System Interrups, which
1092 * represent all possible interrupts, and IRQs
1093 * assigned to actual devices.
1094 */
1095 static int gsi_to_irq[MAX_GSI_NUM];
1097 #ifdef CONFIG_ACPI_BUS
1098 /* Don't set up the ACPI SCI because it's already set up */
1099 if (acpi_fadt.sci_int == gsi)
1100 return gsi;
1101 #endif
1103 ioapic = mp_find_ioapic(gsi);
1104 if (ioapic < 0) {
1105 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
1106 return gsi;
1109 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
1111 if (ioapic_renumber_irq)
1112 gsi = ioapic_renumber_irq(ioapic, gsi);
1114 /*
1115 * Avoid pin reprogramming. PRTs typically include entries
1116 * with redundant pin->gsi mappings (but unique PCI devices);
1117 * we only program the IOAPIC on the first.
1118 */
1119 bit = ioapic_pin % 32;
1120 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
1121 if (idx > 3) {
1122 printk(KERN_ERR "Invalid reference to IOAPIC pin "
1123 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
1124 ioapic_pin);
1125 return gsi;
1127 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
1128 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
1129 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
1130 return gsi_to_irq[gsi];
1133 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
1135 if (triggering == ACPI_LEVEL_SENSITIVE) {
1136 /*
1137 * For PCI devices assign IRQs in order, avoiding gaps
1138 * due to unused I/O APIC pins.
1139 */
1140 int irq = gsi;
1141 if (gsi < MAX_GSI_NUM) {
1142 if (gsi > 15)
1143 gsi = pci_irq++;
1144 #ifdef CONFIG_ACPI_BUS
1145 /*
1146 * Don't assign IRQ used by ACPI SCI
1147 */
1148 if (gsi == acpi_fadt.sci_int)
1149 gsi = pci_irq++;
1150 #endif
1151 gsi_to_irq[irq] = gsi;
1152 } else {
1153 printk(KERN_ERR "GSI %u is too high\n", gsi);
1154 return gsi;
1158 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1159 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1160 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1161 return gsi;
1164 #endif /* CONFIG_X86_IO_APIC */
1165 #endif /* CONFIG_ACPI */