direct-io.hg

view xen/include/asm-x86/config.h @ 15454:83cbda5c1e1b

x86-64: bump STACK_SIZE to 32 so that trampoline and IST stacks fit
without undue squeezing.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
author kfraser@localhost.localdomain
date Tue Jul 03 11:41:25 2007 +0100 (2007-07-03)
parents a5ae31a91b10
children
line source
1 /******************************************************************************
2 * config.h
3 *
4 * A Linux-style configuration list.
5 */
7 #ifndef __X86_CONFIG_H__
8 #define __X86_CONFIG_H__
10 #if defined(__x86_64__)
11 # define CONFIG_PAGING_LEVELS 4
12 #elif defined(CONFIG_X86_PAE)
13 # define CONFIG_PAGING_LEVELS 3
14 #else
15 # define CONFIG_PAGING_LEVELS 2
16 #endif
18 #define CONFIG_X86 1
19 #define CONFIG_X86_HT 1
20 #define CONFIG_SHADOW 1
21 #define CONFIG_SMP 1
22 #define CONFIG_X86_LOCAL_APIC 1
23 #define CONFIG_X86_GOOD_APIC 1
24 #define CONFIG_X86_IO_APIC 1
25 #define CONFIG_X86_PM_TIMER 1
26 #define CONFIG_HPET_TIMER 1
27 #define CONFIG_X86_MCE_P4THERMAL 1
28 #define CONFIG_ACPI_NUMA 1
29 #define CONFIG_NUMA 1
30 #define CONFIG_ACPI_SRAT 1
31 #define CONFIG_DISCONTIGMEM 1
32 #define CONFIG_NUMA_EMU 1
34 /* Intel P4 currently has largest cache line (L2 line size is 128 bytes). */
35 #define CONFIG_X86_L1_CACHE_SHIFT 7
37 #define CONFIG_ACPI 1
38 #define CONFIG_ACPI_BOOT 1
40 #define CONFIG_VGA 1
42 #define HZ 100
44 #define OPT_CONSOLE_STR "com1,vga"
46 #ifdef MAX_PHYS_CPUS
47 #define NR_CPUS MAX_PHYS_CPUS
48 #else
49 #define NR_CPUS 32
50 #endif
52 #if defined(__i386__) && (NR_CPUS > 32)
53 #error "Maximum of 32 physical processors supported by Xen on x86_32"
54 #endif
56 #ifdef CONFIG_X86_SUPERVISOR_MODE_KERNEL
57 # define supervisor_mode_kernel (1)
58 #else
59 # define supervisor_mode_kernel (0)
60 #endif
62 /* Linkage for x86 */
63 #define __ALIGN .align 16,0x90
64 #define __ALIGN_STR ".align 16,0x90"
65 #ifdef __ASSEMBLY__
66 #define ALIGN __ALIGN
67 #define ALIGN_STR __ALIGN_STR
68 #define ENTRY(name) \
69 .globl name; \
70 ALIGN; \
71 name:
72 #endif
74 #define NR_hypercalls 64
76 #ifndef NDEBUG
77 #define MEMORY_GUARD
78 #endif
80 #ifdef __i386__
81 #define STACK_ORDER 2
82 #else
83 #define STACK_ORDER 3
84 #endif
85 #define STACK_SIZE (PAGE_SIZE << STACK_ORDER)
87 /* Primary stack is restricted to 8kB by guard pages. */
88 #define PRIMARY_STACK_SIZE 8192
90 #define CONFIG_DMA_BITSIZE 32
92 #define BOOT_TRAMPOLINE 0x90000
93 #define bootsym_phys(sym) \
94 (((unsigned long)&(sym)-(unsigned long)&trampoline_start)+BOOT_TRAMPOLINE)
95 #define bootsym(sym) \
96 (*RELOC_HIDE((typeof(&(sym)))__va(__pa(&(sym))), \
97 BOOT_TRAMPOLINE-__pa(trampoline_start)))
98 #ifndef __ASSEMBLY__
99 extern char trampoline_start[], trampoline_end[];
100 extern char trampoline_realmode_entry[];
101 extern unsigned int trampoline_xen_phys_start;
102 extern unsigned char trampoline_cpu_started;
103 #endif
105 #if defined(__x86_64__)
107 #define CONFIG_X86_64 1
108 #define CONFIG_COMPAT 1
110 #define asmlinkage
112 #define XENHEAP_DEFAULT_MB (16)
114 #define PML4_ENTRY_BITS 39
115 #ifndef __ASSEMBLY__
116 #define PML4_ENTRY_BYTES (1UL << PML4_ENTRY_BITS)
117 #define PML4_ADDR(_slot) \
118 ((((_slot ## UL) >> 8) * 0xffff000000000000UL) | \
119 (_slot ## UL << PML4_ENTRY_BITS))
120 #else
121 #define PML4_ENTRY_BYTES (1 << PML4_ENTRY_BITS)
122 #define PML4_ADDR(_slot) \
123 (((_slot >> 8) * 0xffff000000000000) | (_slot << PML4_ENTRY_BITS))
124 #endif
126 /*
127 * Memory layout:
128 * 0x0000000000000000 - 0x00007fffffffffff [128TB, 2^47 bytes, PML4:0-255]
129 * Guest-defined use (see below for compatibility mode guests).
130 * 0x0000800000000000 - 0xffff7fffffffffff [16EB]
131 * Inaccessible: current arch only supports 48-bit sign-extended VAs.
132 * 0xffff800000000000 - 0xffff803fffffffff [256GB, 2^38 bytes, PML4:256]
133 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
134 * 0xffff804000000000 - 0xffff807fffffffff [256GB, 2^38 bytes, PML4:256]
135 * Reserved for future shared info with the guest OS (GUEST ACCESSIBLE).
136 * 0xffff808000000000 - 0xffff80ffffffffff [512GB, 2^39 bytes, PML4:257]
137 * Reserved for future use.
138 * 0xffff810000000000 - 0xffff817fffffffff [512GB, 2^39 bytes, PML4:258]
139 * Guest linear page table.
140 * 0xffff818000000000 - 0xffff81ffffffffff [512GB, 2^39 bytes, PML4:259]
141 * Shadow linear page table.
142 * 0xffff820000000000 - 0xffff827fffffffff [512GB, 2^39 bytes, PML4:260]
143 * Per-domain mappings (e.g., GDT, LDT).
144 * 0xffff828000000000 - 0xffff8283ffffffff [16GB, 2^34 bytes, PML4:261]
145 * Machine-to-phys translation table.
146 * 0xffff828400000000 - 0xffff8287ffffffff [16GB, 2^34 bytes, PML4:261]
147 * Page-frame information array.
148 * 0xffff828800000000 - 0xffff828bffffffff [16GB, 2^34 bytes, PML4:261]
149 * ioremap()/fixmap area.
150 * 0xffff828c00000000 - 0xffff828c3fffffff [1GB, 2^30 bytes, PML4:261]
151 * Compatibility machine-to-phys translation table.
152 * 0xffff828c40000000 - 0xffff828c7fffffff [1GB, 2^30 bytes, PML4:261]
153 * High read-only compatibility machine-to-phys translation table.
154 * 0xffff828c80000000 - 0xffff828cbfffffff [1GB, 2^30 bytes, PML4:261]
155 * Xen text, static data, bss.
156 * 0xffff828cc0000000 - 0xffff82ffffffffff [461GB, PML4:261]
157 * Reserved for future use.
158 * 0xffff830000000000 - 0xffff83ffffffffff [1TB, 2^40 bytes, PML4:262-263]
159 * 1:1 direct mapping of all physical memory.
160 * 0xffff840000000000 - 0xffff87ffffffffff [4TB, 2^42 bytes, PML4:264-271]
161 * Reserved for future use.
162 * 0xffff880000000000 - 0xffffffffffffffff [120TB, PML4:272-511]
163 * Guest-defined use.
164 *
165 * Compatibility guest area layout:
166 * 0x0000000000000000 - 0x00000000f57fffff [3928MB, PML4:0]
167 * Guest-defined use.
168 * 0x00000000f5800000 - 0x00000000ffffffff [168MB, PML4:0]
169 * Read-only machine-to-phys translation table (GUEST ACCESSIBLE).
170 * 0x0000000100000000 - 0x0000007fffffffff [508GB, PML4:0]
171 * Unused.
172 * 0x0000008000000000 - 0x000000ffffffffff [512GB, 2^39 bytes, PML4:1]
173 * Hypercall argument translation area.
174 * 0x0000010000000000 - 0x00007fffffffffff [127TB, 2^46 bytes, PML4:2-255]
175 * Reserved for future use.
176 */
179 #define ROOT_PAGETABLE_FIRST_XEN_SLOT 256
180 #define ROOT_PAGETABLE_LAST_XEN_SLOT 271
181 #define ROOT_PAGETABLE_XEN_SLOTS \
182 (ROOT_PAGETABLE_LAST_XEN_SLOT - ROOT_PAGETABLE_FIRST_XEN_SLOT + 1)
184 /* Hypervisor reserves PML4 slots 256 to 271 inclusive. */
185 #define HYPERVISOR_VIRT_START (PML4_ADDR(256))
186 #define HYPERVISOR_VIRT_END (HYPERVISOR_VIRT_START + PML4_ENTRY_BYTES*16)
187 /* Slot 256: read-only guest-accessible machine-to-phys translation table. */
188 #define RO_MPT_VIRT_START (PML4_ADDR(256))
189 #define RO_MPT_VIRT_END (RO_MPT_VIRT_START + PML4_ENTRY_BYTES/2)
190 /* Slot 258: linear page table (guest table). */
191 #define LINEAR_PT_VIRT_START (PML4_ADDR(258))
192 #define LINEAR_PT_VIRT_END (LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
193 /* Slot 259: linear page table (shadow table). */
194 #define SH_LINEAR_PT_VIRT_START (PML4_ADDR(259))
195 #define SH_LINEAR_PT_VIRT_END (SH_LINEAR_PT_VIRT_START + PML4_ENTRY_BYTES)
196 /* Slot 260: per-domain mappings. */
197 #define PERDOMAIN_VIRT_START (PML4_ADDR(260))
198 #define PERDOMAIN_VIRT_END (PERDOMAIN_VIRT_START + (PERDOMAIN_MBYTES<<20))
199 #define PERDOMAIN_MBYTES ((unsigned long)GDT_LDT_MBYTES)
200 /* Slot 261: machine-to-phys conversion table (16GB). */
201 #define RDWR_MPT_VIRT_START (PML4_ADDR(261))
202 #define RDWR_MPT_VIRT_END (RDWR_MPT_VIRT_START + (16UL<<30))
203 /* Slot 261: page-frame information array (16GB). */
204 #define FRAMETABLE_VIRT_START (RDWR_MPT_VIRT_END)
205 #define FRAMETABLE_VIRT_END (FRAMETABLE_VIRT_START + (16UL<<30))
206 /* Slot 261: ioremap()/fixmap area (16GB). */
207 #define IOREMAP_VIRT_START (FRAMETABLE_VIRT_END)
208 #define IOREMAP_VIRT_END (IOREMAP_VIRT_START + (16UL<<30))
209 /* Slot 261: compatibility machine-to-phys conversion table (1GB). */
210 #define RDWR_COMPAT_MPT_VIRT_START IOREMAP_VIRT_END
211 #define RDWR_COMPAT_MPT_VIRT_END (RDWR_COMPAT_MPT_VIRT_START + (1UL << 30))
212 /* Slot 261: high read-only compat machine-to-phys conversion table (1GB). */
213 #define HIRO_COMPAT_MPT_VIRT_START RDWR_COMPAT_MPT_VIRT_END
214 #define HIRO_COMPAT_MPT_VIRT_END (HIRO_COMPAT_MPT_VIRT_START + (1UL << 30))
215 /* Slot 261: xen text, static data and bss (1GB). */
216 #define XEN_VIRT_START (HIRO_COMPAT_MPT_VIRT_END)
217 #define XEN_VIRT_END (XEN_VIRT_START + (1UL << 30))
218 /* Slot 262-263: A direct 1:1 mapping of all of physical memory. */
219 #define DIRECTMAP_VIRT_START (PML4_ADDR(262))
220 #define DIRECTMAP_VIRT_END (DIRECTMAP_VIRT_START + PML4_ENTRY_BYTES*2)
222 #ifndef __ASSEMBLY__
224 /* This is not a fixed value, just a lower limit. */
225 #define __HYPERVISOR_COMPAT_VIRT_START 0xF5800000
226 #define HYPERVISOR_COMPAT_VIRT_START(d) ((d)->arch.hv_compat_vstart)
227 #define MACH2PHYS_COMPAT_VIRT_START HYPERVISOR_COMPAT_VIRT_START
228 #define MACH2PHYS_COMPAT_VIRT_END 0xFFE00000
229 #define MACH2PHYS_COMPAT_NR_ENTRIES(d) \
230 ((MACH2PHYS_COMPAT_VIRT_END-MACH2PHYS_COMPAT_VIRT_START(d))>>2)
232 #define COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) \
233 l2_table_offset(HYPERVISOR_COMPAT_VIRT_START(d))
234 #define COMPAT_L2_PAGETABLE_LAST_XEN_SLOT l2_table_offset(~0U)
235 #define COMPAT_L2_PAGETABLE_XEN_SLOTS(d) \
236 (COMPAT_L2_PAGETABLE_LAST_XEN_SLOT - COMPAT_L2_PAGETABLE_FIRST_XEN_SLOT(d) + 1)
238 #endif
240 #define COMPAT_ARG_XLAT_VIRT_BASE (1UL << ROOT_PAGETABLE_SHIFT)
241 #define COMPAT_ARG_XLAT_SHIFT 0
242 #define COMPAT_ARG_XLAT_PAGES (1U << COMPAT_ARG_XLAT_SHIFT)
243 #define COMPAT_ARG_XLAT_SIZE (COMPAT_ARG_XLAT_PAGES << PAGE_SHIFT)
244 #define COMPAT_ARG_XLAT_VIRT_START(vcpu_id) \
245 (COMPAT_ARG_XLAT_VIRT_BASE + ((unsigned long)(vcpu_id) << \
246 (PAGE_SHIFT + COMPAT_ARG_XLAT_SHIFT + 1)))
248 #define PGT_base_page_table PGT_l4_page_table
250 #define __HYPERVISOR_CS64 0xe008
251 #define __HYPERVISOR_CS32 0xe038
252 #define __HYPERVISOR_CS __HYPERVISOR_CS64
253 #define __HYPERVISOR_DS64 0x0000
254 #define __HYPERVISOR_DS32 0xe010
255 #define __HYPERVISOR_DS __HYPERVISOR_DS64
257 /* For generic assembly code: use macros to define operation/operand sizes. */
258 #define __OS "q" /* Operation Suffix */
259 #define __OP "r" /* Operand Prefix */
260 #define __FIXUP_ALIGN ".align 8"
261 #define __FIXUP_WORD ".quad"
263 #elif defined(__i386__)
265 #define CONFIG_X86_32 1
266 #define CONFIG_DOMAIN_PAGE 1
268 #define asmlinkage __attribute__((regparm(0)))
270 /*
271 * Memory layout (high to low): SIZE PAE-SIZE
272 * ------ ------
273 * I/O remapping area ( 4MB)
274 * Direct-map (1:1) area [Xen code/data/heap] (12MB)
275 * Per-domain mappings (inc. 4MB map_domain_page cache) ( 8MB)
276 * Shadow linear pagetable ( 4MB) ( 8MB)
277 * Guest linear pagetable ( 4MB) ( 8MB)
278 * Machine-to-physical translation table [writable] ( 4MB) (16MB)
279 * Frame-info table (24MB) (96MB)
280 * * Start of guest inaccessible area
281 * Machine-to-physical translation table [read-only] ( 4MB) (16MB)
282 * * Start of guest unmodifiable area
283 */
285 #define IOREMAP_MBYTES 4
286 #define DIRECTMAP_MBYTES 12
287 #define MAPCACHE_MBYTES 4
288 #define PERDOMAIN_MBYTES 8
290 #ifdef CONFIG_X86_PAE
291 # define LINEARPT_MBYTES 8
292 # define MACHPHYS_MBYTES 16 /* 1 MB needed per 1 GB memory */
293 # define FRAMETABLE_MBYTES (MACHPHYS_MBYTES * 6)
294 #else
295 # define LINEARPT_MBYTES 4
296 # define MACHPHYS_MBYTES 4
297 # define FRAMETABLE_MBYTES 24
298 #endif
300 #define IOREMAP_VIRT_END 0UL
301 #define IOREMAP_VIRT_START (IOREMAP_VIRT_END - (IOREMAP_MBYTES<<20))
302 #define DIRECTMAP_VIRT_END IOREMAP_VIRT_START
303 #define DIRECTMAP_VIRT_START (DIRECTMAP_VIRT_END - (DIRECTMAP_MBYTES<<20))
304 #define MAPCACHE_VIRT_END DIRECTMAP_VIRT_START
305 #define MAPCACHE_VIRT_START (MAPCACHE_VIRT_END - (MAPCACHE_MBYTES<<20))
306 #define PERDOMAIN_VIRT_END DIRECTMAP_VIRT_START
307 #define PERDOMAIN_VIRT_START (PERDOMAIN_VIRT_END - (PERDOMAIN_MBYTES<<20))
308 #define SH_LINEAR_PT_VIRT_END PERDOMAIN_VIRT_START
309 #define SH_LINEAR_PT_VIRT_START (SH_LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
310 #define LINEAR_PT_VIRT_END SH_LINEAR_PT_VIRT_START
311 #define LINEAR_PT_VIRT_START (LINEAR_PT_VIRT_END - (LINEARPT_MBYTES<<20))
312 #define RDWR_MPT_VIRT_END LINEAR_PT_VIRT_START
313 #define RDWR_MPT_VIRT_START (RDWR_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
314 #define FRAMETABLE_VIRT_END RDWR_MPT_VIRT_START
315 #define FRAMETABLE_VIRT_START (FRAMETABLE_VIRT_END - (FRAMETABLE_MBYTES<<20))
316 #define RO_MPT_VIRT_END FRAMETABLE_VIRT_START
317 #define RO_MPT_VIRT_START (RO_MPT_VIRT_END - (MACHPHYS_MBYTES<<20))
319 #define XENHEAP_DEFAULT_MB (DIRECTMAP_MBYTES)
320 #define DIRECTMAP_PHYS_END (DIRECTMAP_MBYTES<<20)
322 /* Maximum linear address accessible via guest memory segments. */
323 #define GUEST_SEGMENT_MAX_ADDR RO_MPT_VIRT_END
325 #ifdef CONFIG_X86_PAE
326 /* Hypervisor owns top 168MB of virtual address space. */
327 #define HYPERVISOR_VIRT_START mk_unsigned_long(0xF5800000)
328 #else
329 /* Hypervisor owns top 64MB of virtual address space. */
330 #define HYPERVISOR_VIRT_START mk_unsigned_long(0xFC000000)
331 #endif
333 #define L2_PAGETABLE_FIRST_XEN_SLOT \
334 (HYPERVISOR_VIRT_START >> L2_PAGETABLE_SHIFT)
335 #define L2_PAGETABLE_LAST_XEN_SLOT \
336 (~0UL >> L2_PAGETABLE_SHIFT)
337 #define L2_PAGETABLE_XEN_SLOTS \
338 (L2_PAGETABLE_LAST_XEN_SLOT - L2_PAGETABLE_FIRST_XEN_SLOT + 1)
340 #ifdef CONFIG_X86_PAE
341 # define PGT_base_page_table PGT_l3_page_table
342 #else
343 # define PGT_base_page_table PGT_l2_page_table
344 #endif
346 #define __HYPERVISOR_CS 0xe008
347 #define __HYPERVISOR_DS 0xe010
349 /* For generic assembly code: use macros to define operation/operand sizes. */
350 #define __OS "l" /* Operation Suffix */
351 #define __OP "e" /* Operand Prefix */
352 #define __FIXUP_ALIGN ".align 4"
353 #define __FIXUP_WORD ".long"
355 #endif /* __i386__ */
357 #ifndef __ASSEMBLY__
358 extern unsigned long xen_phys_start, xenheap_phys_start, xenheap_phys_end;
359 #endif
361 /* GDT/LDT shadow mapping area. The first per-domain-mapping sub-area. */
362 #define GDT_LDT_VCPU_SHIFT 5
363 #define GDT_LDT_VCPU_VA_SHIFT (GDT_LDT_VCPU_SHIFT + PAGE_SHIFT)
364 #define GDT_LDT_MBYTES (MAX_VIRT_CPUS >> (20-GDT_LDT_VCPU_VA_SHIFT))
365 #define GDT_LDT_VIRT_START PERDOMAIN_VIRT_START
366 #define GDT_LDT_VIRT_END (GDT_LDT_VIRT_START + (GDT_LDT_MBYTES << 20))
368 /* The address of a particular VCPU's GDT or LDT. */
369 #define GDT_VIRT_START(v) \
370 (PERDOMAIN_VIRT_START + ((v)->vcpu_id << GDT_LDT_VCPU_VA_SHIFT))
371 #define LDT_VIRT_START(v) \
372 (GDT_VIRT_START(v) + (64*1024))
374 #define PDPT_L1_ENTRIES \
375 ((PERDOMAIN_VIRT_END - PERDOMAIN_VIRT_START) >> PAGE_SHIFT)
376 #define PDPT_L2_ENTRIES \
377 ((PDPT_L1_ENTRIES + (1 << PAGETABLE_ORDER) - 1) >> PAGETABLE_ORDER)
379 #if defined(__x86_64__)
380 #define ELFSIZE 64
381 #else
382 #define ELFSIZE 32
383 #endif
385 #endif /* __X86_CONFIG_H__ */