direct-io.hg

view xen/arch/x86/hvm/svm/svm.c @ 12350:5a4517468f4f

[HVM] Remove HVM halt timer. It's no longer needed since interrupts
can wake it up now.

Signed-off-by: Xin Li <xin.b.li@intel.com>
author kfraser@localhost.localdomain
date Fri Nov 10 11:01:15 2006 +0000 (2006-11-10)
parents 9f9f569b0a1d
children f78bfe7bff73
line source
1 /*
2 * svm.c: handling SVM architecture-related VM exits
3 * Copyright (c) 2004, Intel Corporation.
4 * Copyright (c) 2005, AMD Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
17 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 *
19 */
21 #include <xen/config.h>
22 #include <xen/init.h>
23 #include <xen/lib.h>
24 #include <xen/trace.h>
25 #include <xen/sched.h>
26 #include <xen/irq.h>
27 #include <xen/softirq.h>
28 #include <xen/hypercall.h>
29 #include <xen/domain_page.h>
30 #include <asm/current.h>
31 #include <asm/io.h>
32 #include <asm/shadow.h>
33 #include <asm/regs.h>
34 #include <asm/cpufeature.h>
35 #include <asm/processor.h>
36 #include <asm/types.h>
37 #include <asm/msr.h>
38 #include <asm/spinlock.h>
39 #include <asm/hvm/hvm.h>
40 #include <asm/hvm/support.h>
41 #include <asm/hvm/io.h>
42 #include <asm/hvm/svm/svm.h>
43 #include <asm/hvm/svm/vmcb.h>
44 #include <asm/hvm/svm/emulate.h>
45 #include <asm/hvm/svm/vmmcall.h>
46 #include <asm/hvm/svm/intr.h>
47 #include <asm/x86_emulate.h>
48 #include <public/sched.h>
50 #define SVM_EXTRA_DEBUG
52 #define set_segment_register(name, value) \
53 __asm__ __volatile__ ( "movw %%ax ,%%" STR(name) "" : : "a" (value) )
55 /* External functions. We should move these to some suitable header file(s) */
57 extern int inst_copy_from_guest(unsigned char *buf, unsigned long guest_eip,
58 int inst_len);
59 extern asmlinkage void do_IRQ(struct cpu_user_regs *);
60 extern void svm_dump_inst(unsigned long eip);
61 extern int svm_dbg_on;
62 void svm_dump_regs(const char *from, struct cpu_user_regs *regs);
64 static int svm_do_vmmcall_reset_to_realmode(struct vcpu *v,
65 struct cpu_user_regs *regs);
67 /* va of hardware host save area */
68 static void *hsa[NR_CPUS] __read_mostly;
70 /* vmcb used for extended host state */
71 static void *root_vmcb[NR_CPUS] __read_mostly;
73 /* physical address of above for host VMSAVE/VMLOAD */
74 u64 root_vmcb_pa[NR_CPUS] __read_mostly;
77 /* ASID API */
78 enum {
79 ASID_AVAILABLE = 0,
80 ASID_INUSE,
81 ASID_RETIRED
82 };
83 #define INITIAL_ASID 0
84 #define ASID_MAX 64
86 struct asid_pool {
87 spinlock_t asid_lock;
88 u32 asid[ASID_MAX];
89 };
91 static DEFINE_PER_CPU(struct asid_pool, asid_pool);
94 /*
95 * Initializes the POOL of ASID used by the guests per core.
96 */
97 void asidpool_init(int core)
98 {
99 int i;
101 spin_lock_init(&per_cpu(asid_pool,core).asid_lock);
103 /* Host ASID is always in use */
104 per_cpu(asid_pool,core).asid[INITIAL_ASID] = ASID_INUSE;
105 for ( i = 1; i < ASID_MAX; i++ )
106 per_cpu(asid_pool,core).asid[i] = ASID_AVAILABLE;
107 }
110 /* internal function to get the next available ASID */
111 static int asidpool_fetch_next(struct vmcb_struct *vmcb, int core)
112 {
113 int i;
114 for ( i = 1; i < ASID_MAX; i++ )
115 {
116 if ( per_cpu(asid_pool,core).asid[i] == ASID_AVAILABLE )
117 {
118 vmcb->guest_asid = i;
119 per_cpu(asid_pool,core).asid[i] = ASID_INUSE;
120 return i;
121 }
122 }
123 return -1;
124 }
127 /*
128 * This functions assigns on the passed VMCB, the next
129 * available ASID number. If none are available, the
130 * TLB flush flag is set, and all retireds ASID
131 * are made available.
132 *
133 * Returns: 1 -- sucess;
134 * 0 -- failure -- no more ASID numbers
135 * available.
136 */
137 int asidpool_assign_next( struct vmcb_struct *vmcb, int retire_current,
138 int oldcore, int newcore )
139 {
140 int i;
141 int res = 1;
142 static unsigned long cnt=0;
144 spin_lock(&per_cpu(asid_pool,oldcore).asid_lock);
145 if( retire_current && vmcb->guest_asid ) {
146 per_cpu(asid_pool,oldcore).asid[vmcb->guest_asid & (ASID_MAX-1)] =
147 ASID_RETIRED;
148 }
149 spin_unlock(&per_cpu(asid_pool,oldcore).asid_lock);
150 spin_lock(&per_cpu(asid_pool,newcore).asid_lock);
151 if( asidpool_fetch_next( vmcb, newcore ) < 0 ) {
152 if (svm_dbg_on)
153 printk( "SVM: tlb(%ld)\n", cnt++ );
154 /* FLUSH the TLB and all retired slots are made available */
155 vmcb->tlb_control = 1;
156 for( i = 1; i < ASID_MAX; i++ ) {
157 if( per_cpu(asid_pool,newcore).asid[i] == ASID_RETIRED ) {
158 per_cpu(asid_pool,newcore).asid[i] = ASID_AVAILABLE;
159 }
160 }
161 /* Get the First slot available */
162 res = asidpool_fetch_next( vmcb, newcore ) > 0;
163 }
164 spin_unlock(&per_cpu(asid_pool,newcore).asid_lock);
165 return res;
166 }
168 void asidpool_retire( struct vmcb_struct *vmcb, int core )
169 {
170 spin_lock(&per_cpu(asid_pool,core).asid_lock);
171 if( vmcb->guest_asid ) {
172 per_cpu(asid_pool,core).asid[vmcb->guest_asid & (ASID_MAX-1)] =
173 ASID_RETIRED;
174 }
175 spin_unlock(&per_cpu(asid_pool,core).asid_lock);
176 }
178 static inline void svm_inject_exception(struct vcpu *v, int trap,
179 int ev, int error_code)
180 {
181 eventinj_t event;
182 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
184 event.bytes = 0;
185 event.fields.v = 1;
186 event.fields.type = EVENTTYPE_EXCEPTION;
187 event.fields.vector = trap;
188 event.fields.ev = ev;
189 event.fields.errorcode = error_code;
191 ASSERT(vmcb->eventinj.fields.v == 0);
193 vmcb->eventinj = event;
194 v->arch.hvm_svm.inject_event=1;
195 }
197 static void stop_svm(void)
198 {
199 u32 eax, edx;
200 int cpu = smp_processor_id();
202 /* We turn off the EFER_SVME bit. */
203 rdmsr(MSR_EFER, eax, edx);
204 eax &= ~EFER_SVME;
205 wrmsr(MSR_EFER, eax, edx);
207 /* release the HSA */
208 free_host_save_area(hsa[cpu]);
209 hsa[cpu] = NULL;
210 wrmsr(MSR_K8_VM_HSAVE_PA, 0, 0 );
212 /* free up the root vmcb */
213 free_vmcb(root_vmcb[cpu]);
214 root_vmcb[cpu] = NULL;
215 root_vmcb_pa[cpu] = 0;
216 }
218 static void svm_store_cpu_guest_regs(
219 struct vcpu *v, struct cpu_user_regs *regs, unsigned long *crs)
220 {
221 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
223 if ( regs != NULL )
224 {
225 regs->eip = vmcb->rip;
226 regs->esp = vmcb->rsp;
227 regs->eflags = vmcb->rflags;
228 regs->cs = vmcb->cs.sel;
229 regs->ds = vmcb->ds.sel;
230 regs->es = vmcb->es.sel;
231 regs->ss = vmcb->ss.sel;
232 regs->gs = vmcb->gs.sel;
233 regs->fs = vmcb->fs.sel;
234 }
236 if ( crs != NULL )
237 {
238 /* Returning the guest's regs */
239 crs[0] = v->arch.hvm_svm.cpu_shadow_cr0;
240 crs[2] = v->arch.hvm_svm.cpu_cr2;
241 crs[3] = v->arch.hvm_svm.cpu_cr3;
242 crs[4] = v->arch.hvm_svm.cpu_shadow_cr4;
243 }
244 }
246 static int svm_paging_enabled(struct vcpu *v)
247 {
248 unsigned long cr0;
250 cr0 = v->arch.hvm_svm.cpu_shadow_cr0;
252 return (cr0 & X86_CR0_PE) && (cr0 & X86_CR0_PG);
253 }
255 static int svm_pae_enabled(struct vcpu *v)
256 {
257 unsigned long cr4;
259 if(!svm_paging_enabled(v))
260 return 0;
262 cr4 = v->arch.hvm_svm.cpu_shadow_cr4;
264 return (cr4 & X86_CR4_PAE);
265 }
267 static int svm_long_mode_enabled(struct vcpu *v)
268 {
269 return test_bit(SVM_CPU_STATE_LMA_ENABLED, &v->arch.hvm_svm.cpu_state);
270 }
272 #define IS_CANO_ADDRESS(add) 1
274 static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
275 {
276 u64 msr_content = 0;
277 struct vcpu *vc = current;
278 struct vmcb_struct *vmcb = vc->arch.hvm_svm.vmcb;
280 switch (regs->ecx)
281 {
282 case MSR_EFER:
283 msr_content = vmcb->efer;
284 msr_content &= ~EFER_SVME;
285 break;
287 case MSR_FS_BASE:
288 msr_content = vmcb->fs.base;
289 break;
291 case MSR_GS_BASE:
292 msr_content = vmcb->gs.base;
293 break;
295 case MSR_SHADOW_GS_BASE:
296 msr_content = vmcb->kerngsbase;
297 break;
299 case MSR_STAR:
300 msr_content = vmcb->star;
301 break;
303 case MSR_LSTAR:
304 msr_content = vmcb->lstar;
305 break;
307 case MSR_CSTAR:
308 msr_content = vmcb->cstar;
309 break;
311 case MSR_SYSCALL_MASK:
312 msr_content = vmcb->sfmask;
313 break;
314 default:
315 return 0;
316 }
318 HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %"PRIx64"\n",
319 msr_content);
321 regs->eax = (u32)(msr_content >> 0);
322 regs->edx = (u32)(msr_content >> 32);
323 return 1;
324 }
326 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
327 {
328 u64 msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
329 struct vcpu *vc = current;
330 struct vmcb_struct *vmcb = vc->arch.hvm_svm.vmcb;
332 HVM_DBG_LOG(DBG_LEVEL_1, "mode_do_msr_write msr %lx "
333 "msr_content %"PRIx64"\n",
334 (unsigned long)regs->ecx, msr_content);
336 switch (regs->ecx)
337 {
338 case MSR_EFER:
339 #ifdef __x86_64__
340 /* offending reserved bit will cause #GP */
341 if ( msr_content & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE) )
342 {
343 printk("Trying to set reserved bit in EFER: %"PRIx64"\n",
344 msr_content);
345 svm_inject_exception(vc, TRAP_gp_fault, 1, 0);
346 return 0;
347 }
349 /* LME: 0 -> 1 */
350 if ( msr_content & EFER_LME &&
351 !test_bit(SVM_CPU_STATE_LME_ENABLED, &vc->arch.hvm_svm.cpu_state))
352 {
353 if ( svm_paging_enabled(vc) ||
354 !test_bit(SVM_CPU_STATE_PAE_ENABLED,
355 &vc->arch.hvm_svm.cpu_state) )
356 {
357 printk("Trying to set LME bit when "
358 "in paging mode or PAE bit is not set\n");
359 svm_inject_exception(vc, TRAP_gp_fault, 1, 0);
360 return 0;
361 }
362 set_bit(SVM_CPU_STATE_LME_ENABLED, &vc->arch.hvm_svm.cpu_state);
363 }
365 /* We have already recorded that we want LME, so it will be set
366 * next time CR0 gets updated. So we clear that bit and continue.
367 */
368 if ((msr_content ^ vmcb->efer) & EFER_LME)
369 msr_content &= ~EFER_LME;
370 /* No update for LME/LMA since it have no effect */
371 #endif
372 vmcb->efer = msr_content | EFER_SVME;
373 break;
375 case MSR_FS_BASE:
376 case MSR_GS_BASE:
377 if ( !svm_long_mode_enabled(vc) )
378 domain_crash_synchronous();
380 if (!IS_CANO_ADDRESS(msr_content))
381 {
382 HVM_DBG_LOG(DBG_LEVEL_1, "Not cano address of msr write\n");
383 svm_inject_exception(vc, TRAP_gp_fault, 1, 0);
384 }
386 if (regs->ecx == MSR_FS_BASE)
387 vmcb->fs.base = msr_content;
388 else
389 vmcb->gs.base = msr_content;
390 break;
392 case MSR_SHADOW_GS_BASE:
393 vmcb->kerngsbase = msr_content;
394 break;
396 case MSR_STAR:
397 vmcb->star = msr_content;
398 break;
400 case MSR_LSTAR:
401 vmcb->lstar = msr_content;
402 break;
404 case MSR_CSTAR:
405 vmcb->cstar = msr_content;
406 break;
408 case MSR_SYSCALL_MASK:
409 vmcb->sfmask = msr_content;
410 break;
412 default:
413 return 0;
414 }
415 return 1;
416 }
419 #define loaddebug(_v,_reg) \
420 __asm__ __volatile__ ("mov %0,%%db" #_reg : : "r" ((_v)->debugreg[_reg]))
421 #define savedebug(_v,_reg) \
422 __asm__ __volatile__ ("mov %%db" #_reg ",%0" : : "r" ((_v)->debugreg[_reg]))
425 static inline void svm_save_dr(struct vcpu *v)
426 {
427 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
429 if ( !v->arch.hvm_vcpu.flag_dr_dirty )
430 return;
432 /* Clear the DR dirty flag and re-enable intercepts for DR accesses. */
433 v->arch.hvm_vcpu.flag_dr_dirty = 0;
434 v->arch.hvm_svm.vmcb->dr_intercepts = DR_INTERCEPT_ALL_WRITES;
436 savedebug(&v->arch.guest_context, 0);
437 savedebug(&v->arch.guest_context, 1);
438 savedebug(&v->arch.guest_context, 2);
439 savedebug(&v->arch.guest_context, 3);
440 v->arch.guest_context.debugreg[6] = vmcb->dr6;
441 v->arch.guest_context.debugreg[7] = vmcb->dr7;
442 }
445 static inline void __restore_debug_registers(struct vcpu *v)
446 {
447 loaddebug(&v->arch.guest_context, 0);
448 loaddebug(&v->arch.guest_context, 1);
449 loaddebug(&v->arch.guest_context, 2);
450 loaddebug(&v->arch.guest_context, 3);
451 /* DR6 and DR7 are loaded from the VMCB. */
452 }
455 static inline void svm_restore_dr(struct vcpu *v)
456 {
457 if ( unlikely(v->arch.guest_context.debugreg[7] & 0xFF) )
458 __restore_debug_registers(v);
459 }
462 static int svm_realmode(struct vcpu *v)
463 {
464 unsigned long cr0 = v->arch.hvm_svm.cpu_shadow_cr0;
465 unsigned long eflags = v->arch.hvm_svm.vmcb->rflags;
467 return (eflags & X86_EFLAGS_VM) || !(cr0 & X86_CR0_PE);
468 }
470 static int svm_guest_x86_mode(struct vcpu *v)
471 {
472 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
474 if ( vmcb->efer & EFER_LMA )
475 return (vmcb->cs.attributes.fields.l ?
476 X86EMUL_MODE_PROT64 : X86EMUL_MODE_PROT32);
478 if ( svm_realmode(v) )
479 return X86EMUL_MODE_REAL;
481 return (vmcb->cs.attributes.fields.db ?
482 X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16);
483 }
485 void svm_update_host_cr3(struct vcpu *v)
486 {
487 /* SVM doesn't have a HOST_CR3 equivalent to update. */
488 }
490 unsigned long svm_get_ctrl_reg(struct vcpu *v, unsigned int num)
491 {
492 switch ( num )
493 {
494 case 0:
495 return v->arch.hvm_svm.cpu_shadow_cr0;
496 case 2:
497 return v->arch.hvm_svm.cpu_cr2;
498 case 3:
499 return v->arch.hvm_svm.cpu_cr3;
500 case 4:
501 return v->arch.hvm_svm.cpu_shadow_cr4;
502 default:
503 BUG();
504 }
505 return 0; /* dummy */
506 }
509 /* Make sure that xen intercepts any FP accesses from current */
510 static void svm_stts(struct vcpu *v)
511 {
512 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
514 /*
515 * If the guest does not have TS enabled then we must cause and handle an
516 * exception on first use of the FPU. If the guest *does* have TS enabled
517 * then this is not necessary: no FPU activity can occur until the guest
518 * clears CR0.TS, and we will initialise the FPU when that happens.
519 */
520 if ( !(v->arch.hvm_svm.cpu_shadow_cr0 & X86_CR0_TS) )
521 {
522 v->arch.hvm_svm.vmcb->exception_intercepts |= EXCEPTION_BITMAP_NM;
523 vmcb->cr0 |= X86_CR0_TS;
524 }
525 }
528 static void svm_set_tsc_offset(struct vcpu *v, u64 offset)
529 {
530 v->arch.hvm_svm.vmcb->tsc_offset = offset;
531 }
534 static void svm_init_ap_context(
535 struct vcpu_guest_context *ctxt, int vcpuid, int trampoline_vector)
536 {
537 memset(ctxt, 0, sizeof(*ctxt));
539 /*
540 * We execute the trampoline code in real mode. The trampoline vector
541 * passed to us is page alligned and is the physicall frame number for
542 * the code. We will execute this code in real mode.
543 */
544 ctxt->user_regs.eip = 0x0;
545 ctxt->user_regs.cs = (trampoline_vector << 8);
546 }
548 static void svm_init_hypercall_page(struct domain *d, void *hypercall_page)
549 {
550 char *p;
551 int i;
553 memset(hypercall_page, 0, PAGE_SIZE);
555 for ( i = 0; i < (PAGE_SIZE / 32); i++ )
556 {
557 p = (char *)(hypercall_page + (i * 32));
558 *(u8 *)(p + 0) = 0xb8; /* mov imm32, %eax */
559 *(u32 *)(p + 1) = i;
560 *(u8 *)(p + 5) = 0x0f; /* vmmcall */
561 *(u8 *)(p + 6) = 0x01;
562 *(u8 *)(p + 7) = 0xd9;
563 *(u8 *)(p + 8) = 0xc3; /* ret */
564 }
566 /* Don't support HYPERVISOR_iret at the moment */
567 *(u16 *)(hypercall_page + (__HYPERVISOR_iret * 32)) = 0x0b0f; /* ud2 */
568 }
571 int svm_dbg_on = 0;
573 static inline int svm_do_debugout(unsigned long exit_code)
574 {
575 int i;
577 static unsigned long counter = 0;
578 static unsigned long works[] =
579 {
580 VMEXIT_IOIO,
581 VMEXIT_HLT,
582 VMEXIT_CPUID,
583 VMEXIT_DR0_READ,
584 VMEXIT_DR1_READ,
585 VMEXIT_DR2_READ,
586 VMEXIT_DR3_READ,
587 VMEXIT_DR6_READ,
588 VMEXIT_DR7_READ,
589 VMEXIT_DR0_WRITE,
590 VMEXIT_DR1_WRITE,
591 VMEXIT_DR2_WRITE,
592 VMEXIT_DR3_WRITE,
593 VMEXIT_CR0_READ,
594 VMEXIT_CR0_WRITE,
595 VMEXIT_CR3_READ,
596 VMEXIT_CR4_READ,
597 VMEXIT_MSR,
598 VMEXIT_CR0_WRITE,
599 VMEXIT_CR3_WRITE,
600 VMEXIT_CR4_WRITE,
601 VMEXIT_EXCEPTION_PF,
602 VMEXIT_INTR,
603 VMEXIT_INVLPG,
604 VMEXIT_EXCEPTION_NM
605 };
608 #if 0
609 if (svm_dbg_on && exit_code != 0x7B)
610 return 1;
611 #endif
613 counter++;
615 #if 0
616 if ((exit_code == 0x4E
617 || exit_code == VMEXIT_CR0_READ
618 || exit_code == VMEXIT_CR0_WRITE)
619 && counter < 200000)
620 return 0;
622 if ((exit_code == 0x4E) && counter < 500000)
623 return 0;
624 #endif
626 for (i = 0; i < sizeof(works) / sizeof(works[0]); i++)
627 if (exit_code == works[i])
628 return 0;
630 return 1;
631 }
633 static void save_svm_cpu_user_regs(struct vcpu *v, struct cpu_user_regs *ctxt)
634 {
635 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
637 ASSERT(vmcb);
639 ctxt->eax = vmcb->rax;
640 ctxt->ss = vmcb->ss.sel;
641 ctxt->esp = vmcb->rsp;
642 ctxt->eflags = vmcb->rflags;
643 ctxt->cs = vmcb->cs.sel;
644 ctxt->eip = vmcb->rip;
646 ctxt->gs = vmcb->gs.sel;
647 ctxt->fs = vmcb->fs.sel;
648 ctxt->es = vmcb->es.sel;
649 ctxt->ds = vmcb->ds.sel;
650 }
652 static void svm_store_cpu_user_regs(struct cpu_user_regs *regs, struct vcpu *v)
653 {
654 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
656 regs->eip = vmcb->rip;
657 regs->esp = vmcb->rsp;
658 regs->eflags = vmcb->rflags;
659 regs->cs = vmcb->cs.sel;
660 regs->ds = vmcb->ds.sel;
661 regs->es = vmcb->es.sel;
662 regs->ss = vmcb->ss.sel;
663 }
665 /* XXX Use svm_load_cpu_guest_regs instead */
666 static void svm_load_cpu_user_regs(struct vcpu *v, struct cpu_user_regs *regs)
667 {
668 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
669 u32 *intercepts = &v->arch.hvm_svm.vmcb->exception_intercepts;
671 /* Write the guest register value into VMCB */
672 vmcb->rax = regs->eax;
673 vmcb->ss.sel = regs->ss;
674 vmcb->rsp = regs->esp;
675 vmcb->rflags = regs->eflags | 2UL;
676 vmcb->cs.sel = regs->cs;
677 vmcb->rip = regs->eip;
678 if (regs->eflags & EF_TF)
679 *intercepts |= EXCEPTION_BITMAP_DB;
680 else
681 *intercepts &= ~EXCEPTION_BITMAP_DB;
682 }
684 static void svm_load_cpu_guest_regs(
685 struct vcpu *v, struct cpu_user_regs *regs)
686 {
687 svm_load_cpu_user_regs(v, regs);
688 }
690 static void arch_svm_do_launch(struct vcpu *v)
691 {
692 svm_do_launch(v);
694 if ( v->vcpu_id != 0 )
695 {
696 cpu_user_regs_t *regs = &current->arch.guest_context.user_regs;
697 u16 cs_sel = regs->cs;
698 /*
699 * This is the launch of an AP; set state so that we begin executing
700 * the trampoline code in real-mode.
701 */
702 svm_do_vmmcall_reset_to_realmode(v, regs);
703 /* Adjust the state to execute the trampoline code.*/
704 v->arch.hvm_svm.vmcb->rip = 0;
705 v->arch.hvm_svm.vmcb->cs.sel= cs_sel;
706 v->arch.hvm_svm.vmcb->cs.base = (cs_sel << 4);
707 }
709 reset_stack_and_jump(svm_asm_do_launch);
710 }
712 static void svm_freeze_time(struct vcpu *v)
713 {
714 struct periodic_time *pt=&v->domain->arch.hvm_domain.pl_time.periodic_tm;
716 if ( pt->enabled && pt->first_injected
717 && (v->vcpu_id == pt->bind_vcpu)
718 && !v->arch.hvm_vcpu.guest_time ) {
719 v->arch.hvm_vcpu.guest_time = hvm_get_guest_time(v);
720 if ( test_bit(_VCPUF_blocked, &v->vcpu_flags) )
721 stop_timer(&pt->timer);
722 }
723 }
726 static void svm_ctxt_switch_from(struct vcpu *v)
727 {
728 svm_freeze_time(v);
729 svm_save_dr(v);
730 }
732 static void svm_ctxt_switch_to(struct vcpu *v)
733 {
734 #ifdef __x86_64__
735 /*
736 * This is required, because VMRUN does consistency check
737 * and some of the DOM0 selectors are pointing to
738 * invalid GDT locations, and cause AMD processors
739 * to shutdown.
740 */
741 set_segment_register(ds, 0);
742 set_segment_register(es, 0);
743 set_segment_register(ss, 0);
744 #endif
745 svm_restore_dr(v);
746 }
748 static int svm_vcpu_initialise(struct vcpu *v)
749 {
750 int rc;
752 v->arch.schedule_tail = arch_svm_do_launch;
753 v->arch.ctxt_switch_from = svm_ctxt_switch_from;
754 v->arch.ctxt_switch_to = svm_ctxt_switch_to;
756 v->arch.hvm_svm.saved_irq_vector = -1;
758 if ( (rc = svm_create_vmcb(v)) != 0 )
759 {
760 dprintk(XENLOG_WARNING,
761 "Failed to create VMCB for vcpu %d: err=%d.\n",
762 v->vcpu_id, rc);
763 return rc;
764 }
766 return 0;
767 }
769 static void svm_vcpu_destroy(struct vcpu *v)
770 {
771 svm_destroy_vmcb(v);
772 }
774 int start_svm(void)
775 {
776 u32 eax, ecx, edx;
777 u32 phys_hsa_lo, phys_hsa_hi;
778 u64 phys_hsa;
779 int cpu = smp_processor_id();
781 /* Xen does not fill x86_capability words except 0. */
782 ecx = cpuid_ecx(0x80000001);
783 boot_cpu_data.x86_capability[5] = ecx;
785 if (!(test_bit(X86_FEATURE_SVME, &boot_cpu_data.x86_capability)))
786 return 0;
788 /* check whether SVM feature is disabled in BIOS */
789 rdmsr(MSR_K8_VM_CR, eax, edx);
790 if ( eax & K8_VMCR_SVME_DISABLE )
791 {
792 printk("AMD SVM Extension is disabled in BIOS.\n");
793 return 0;
794 }
796 if (!(hsa[cpu] = alloc_host_save_area()))
797 return 0;
799 rdmsr(MSR_EFER, eax, edx);
800 eax |= EFER_SVME;
801 wrmsr(MSR_EFER, eax, edx);
802 asidpool_init( cpu );
803 printk("AMD SVM Extension is enabled for cpu %d.\n", cpu );
805 /* Initialize the HSA for this core */
806 phys_hsa = (u64) virt_to_maddr(hsa[cpu]);
807 phys_hsa_lo = (u32) phys_hsa;
808 phys_hsa_hi = (u32) (phys_hsa >> 32);
809 wrmsr(MSR_K8_VM_HSAVE_PA, phys_hsa_lo, phys_hsa_hi);
811 if (!(root_vmcb[cpu] = alloc_vmcb()))
812 return 0;
813 root_vmcb_pa[cpu] = virt_to_maddr(root_vmcb[cpu]);
815 if (cpu == 0)
816 setup_vmcb_dump();
818 /* Setup HVM interfaces */
819 hvm_funcs.disable = stop_svm;
821 hvm_funcs.vcpu_initialise = svm_vcpu_initialise;
822 hvm_funcs.vcpu_destroy = svm_vcpu_destroy;
824 hvm_funcs.store_cpu_guest_regs = svm_store_cpu_guest_regs;
825 hvm_funcs.load_cpu_guest_regs = svm_load_cpu_guest_regs;
827 hvm_funcs.realmode = svm_realmode;
828 hvm_funcs.paging_enabled = svm_paging_enabled;
829 hvm_funcs.long_mode_enabled = svm_long_mode_enabled;
830 hvm_funcs.pae_enabled = svm_pae_enabled;
831 hvm_funcs.guest_x86_mode = svm_guest_x86_mode;
832 hvm_funcs.get_guest_ctrl_reg = svm_get_ctrl_reg;
834 hvm_funcs.update_host_cr3 = svm_update_host_cr3;
836 hvm_funcs.stts = svm_stts;
837 hvm_funcs.set_tsc_offset = svm_set_tsc_offset;
839 hvm_funcs.init_ap_context = svm_init_ap_context;
840 hvm_funcs.init_hypercall_page = svm_init_hypercall_page;
842 hvm_enabled = 1;
844 return 1;
845 }
848 static void svm_migrate_timers(struct vcpu *v)
849 {
850 struct periodic_time *pt =
851 &(v->domain->arch.hvm_domain.pl_time.periodic_tm);
852 struct RTCState *vrtc = &v->domain->arch.hvm_domain.pl_time.vrtc;
853 struct PMTState *vpmt = &v->domain->arch.hvm_domain.pl_time.vpmt;
855 if ( pt->enabled )
856 {
857 migrate_timer(&pt->timer, v->processor);
858 }
859 migrate_timer(&vcpu_vlapic(v)->vlapic_timer, v->processor);
860 migrate_timer(&vrtc->second_timer, v->processor);
861 migrate_timer(&vrtc->second_timer2, v->processor);
862 migrate_timer(&vpmt->timer, v->processor);
863 }
866 void arch_svm_do_resume(struct vcpu *v)
867 {
868 /* pinning VCPU to a different core? */
869 if ( v->arch.hvm_svm.launch_core == smp_processor_id()) {
870 hvm_do_resume( v );
871 reset_stack_and_jump( svm_asm_do_resume );
872 }
873 else {
874 if (svm_dbg_on)
875 printk("VCPU core pinned: %d to %d\n",
876 v->arch.hvm_svm.launch_core, smp_processor_id() );
877 v->arch.hvm_svm.launch_core = smp_processor_id();
878 svm_migrate_timers( v );
879 hvm_do_resume( v );
880 reset_stack_and_jump( svm_asm_do_resume );
881 }
882 }
886 static int svm_do_page_fault(unsigned long va, struct cpu_user_regs *regs)
887 {
888 struct vcpu *v = current;
889 unsigned long eip;
890 int result;
891 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
893 ASSERT(vmcb);
895 //#if HVM_DEBUG
896 eip = vmcb->rip;
897 HVM_DBG_LOG(DBG_LEVEL_VMMU,
898 "svm_do_page_fault = 0x%lx, eip = %lx, error_code = %lx",
899 va, eip, (unsigned long)regs->error_code);
900 //#endif
902 result = shadow_fault(va, regs);
904 if( result ) {
905 /* Let's make sure that the Guest TLB is flushed */
906 set_bit(ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags);
907 }
909 return result;
910 }
913 static void svm_do_no_device_fault(struct vmcb_struct *vmcb)
914 {
915 struct vcpu *v = current;
917 setup_fpu(v);
918 vmcb->exception_intercepts &= ~EXCEPTION_BITMAP_NM;
920 if ( !(v->arch.hvm_svm.cpu_shadow_cr0 & X86_CR0_TS) )
921 vmcb->cr0 &= ~X86_CR0_TS;
922 }
925 static void svm_do_general_protection_fault(struct vcpu *v,
926 struct cpu_user_regs *regs)
927 {
928 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
929 unsigned long eip, error_code;
931 ASSERT(vmcb);
933 eip = vmcb->rip;
934 error_code = vmcb->exitinfo1;
936 if (vmcb->idtr.limit == 0) {
937 printk("Huh? We got a GP Fault with an invalid IDTR!\n");
938 svm_dump_vmcb(__func__, vmcb);
939 svm_dump_regs(__func__, regs);
940 svm_dump_inst(vmcb->rip);
941 __hvm_bug(regs);
942 }
944 HVM_DBG_LOG(DBG_LEVEL_1,
945 "svm_general_protection_fault: eip = %lx, erro_code = %lx",
946 eip, error_code);
948 HVM_DBG_LOG(DBG_LEVEL_1,
949 "eax=%lx, ebx=%lx, ecx=%lx, edx=%lx, esi=%lx, edi=%lx",
950 (unsigned long)regs->eax, (unsigned long)regs->ebx,
951 (unsigned long)regs->ecx, (unsigned long)regs->edx,
952 (unsigned long)regs->esi, (unsigned long)regs->edi);
954 /* Reflect it back into the guest */
955 svm_inject_exception(v, TRAP_gp_fault, 1, error_code);
956 }
958 /* Reserved bits ECX: [31:14], [12:4], [2:1]*/
959 #define SVM_VCPU_CPUID_L1_ECX_RESERVED 0xffffdff6
960 /* Reserved bits EDX: [31:29], [27], [22:20], [18], [10] */
961 #define SVM_VCPU_CPUID_L1_EDX_RESERVED 0xe8740400
963 static void svm_vmexit_do_cpuid(struct vmcb_struct *vmcb, unsigned long input,
964 struct cpu_user_regs *regs)
965 {
966 unsigned int eax, ebx, ecx, edx;
967 unsigned long eip;
968 struct vcpu *v = current;
969 int inst_len;
971 ASSERT(vmcb);
973 eip = vmcb->rip;
975 HVM_DBG_LOG(DBG_LEVEL_1,
976 "do_cpuid: (eax) %lx, (ebx) %lx, (ecx) %lx, (edx) %lx,"
977 " (esi) %lx, (edi) %lx",
978 (unsigned long)regs->eax, (unsigned long)regs->ebx,
979 (unsigned long)regs->ecx, (unsigned long)regs->edx,
980 (unsigned long)regs->esi, (unsigned long)regs->edi);
982 if ( !cpuid_hypervisor_leaves(input, &eax, &ebx, &ecx, &edx) )
983 {
984 cpuid(input, &eax, &ebx, &ecx, &edx);
985 if (input == 0x00000001 || input == 0x80000001 )
986 {
987 if ( !vlapic_global_enabled(vcpu_vlapic(v)) )
988 {
989 /* Since the apic is disabled, avoid any confusion
990 about SMP cpus being available */
991 clear_bit(X86_FEATURE_APIC, &edx);
992 }
993 #if CONFIG_PAGING_LEVELS >= 3
994 if ( !v->domain->arch.hvm_domain.params[HVM_PARAM_PAE_ENABLED] )
995 #endif
996 {
997 clear_bit(X86_FEATURE_PAE, &edx);
998 if (input == 0x80000001 )
999 clear_bit(X86_FEATURE_NX & 31, &edx);
1001 clear_bit(X86_FEATURE_PSE36, &edx);
1002 if (input == 0x00000001 )
1004 /* Clear out reserved bits. */
1005 ecx &= ~SVM_VCPU_CPUID_L1_ECX_RESERVED;
1006 edx &= ~SVM_VCPU_CPUID_L1_EDX_RESERVED;
1008 clear_bit(X86_FEATURE_MWAIT & 31, &ecx);
1010 /* Guest should only see one logical processor.
1011 * See details on page 23 of AMD CPUID Specification.
1012 */
1013 clear_bit(X86_FEATURE_HT, &edx); /* clear the hyperthread bit */
1014 ebx &= 0xFF00FFFF; /* clear the logical processor count when HTT=0 */
1015 ebx |= 0x00010000; /* set to 1 just for precaution */
1017 else
1019 /* Clear the Cmp_Legacy bit
1020 * This bit is supposed to be zero when HTT = 0.
1021 * See details on page 23 of AMD CPUID Specification.
1022 */
1023 clear_bit(X86_FEATURE_CMP_LEGACY & 31, &ecx);
1024 /* Make SVM feature invisible to the guest. */
1025 clear_bit(X86_FEATURE_SVME & 31, &ecx);
1026 #ifdef __i386__
1027 /* Mask feature for Intel ia32e or AMD long mode. */
1028 clear_bit(X86_FEATURE_LAHF_LM & 31, &ecx);
1030 clear_bit(X86_FEATURE_LM & 31, &edx);
1031 clear_bit(X86_FEATURE_SYSCALL & 31, &edx);
1032 #endif
1033 /* So far, we do not support 3DNow for the guest. */
1034 clear_bit(X86_FEATURE_3DNOW & 31, &edx);
1035 clear_bit(X86_FEATURE_3DNOWEXT & 31, &edx);
1038 else if ( ( input == 0x80000007 ) || ( input == 0x8000000A ) )
1040 /* Mask out features of power management and SVM extension. */
1041 eax = ebx = ecx = edx = 0;
1043 else if ( input == 0x80000008 )
1045 /* Make sure Number of CPU core is 1 when HTT=0 */
1046 ecx &= 0xFFFFFF00;
1050 regs->eax = (unsigned long)eax;
1051 regs->ebx = (unsigned long)ebx;
1052 regs->ecx = (unsigned long)ecx;
1053 regs->edx = (unsigned long)edx;
1055 HVM_DBG_LOG(DBG_LEVEL_1,
1056 "svm_vmexit_do_cpuid: eip: %lx, input: %lx, out:eax=%x, "
1057 "ebx=%x, ecx=%x, edx=%x",
1058 eip, input, eax, ebx, ecx, edx);
1060 inst_len = __get_instruction_length(vmcb, INSTR_CPUID, NULL);
1061 ASSERT(inst_len > 0);
1062 __update_guest_eip(vmcb, inst_len);
1066 static inline unsigned long *get_reg_p(unsigned int gpreg,
1067 struct cpu_user_regs *regs, struct vmcb_struct *vmcb)
1069 unsigned long *reg_p = NULL;
1070 switch (gpreg)
1072 case SVM_REG_EAX:
1073 reg_p = (unsigned long *)&regs->eax;
1074 break;
1075 case SVM_REG_EBX:
1076 reg_p = (unsigned long *)&regs->ebx;
1077 break;
1078 case SVM_REG_ECX:
1079 reg_p = (unsigned long *)&regs->ecx;
1080 break;
1081 case SVM_REG_EDX:
1082 reg_p = (unsigned long *)&regs->edx;
1083 break;
1084 case SVM_REG_EDI:
1085 reg_p = (unsigned long *)&regs->edi;
1086 break;
1087 case SVM_REG_ESI:
1088 reg_p = (unsigned long *)&regs->esi;
1089 break;
1090 case SVM_REG_EBP:
1091 reg_p = (unsigned long *)&regs->ebp;
1092 break;
1093 case SVM_REG_ESP:
1094 reg_p = (unsigned long *)&vmcb->rsp;
1095 break;
1096 #ifdef __x86_64__
1097 case SVM_REG_R8:
1098 reg_p = (unsigned long *)&regs->r8;
1099 break;
1100 case SVM_REG_R9:
1101 reg_p = (unsigned long *)&regs->r9;
1102 break;
1103 case SVM_REG_R10:
1104 reg_p = (unsigned long *)&regs->r10;
1105 break;
1106 case SVM_REG_R11:
1107 reg_p = (unsigned long *)&regs->r11;
1108 break;
1109 case SVM_REG_R12:
1110 reg_p = (unsigned long *)&regs->r12;
1111 break;
1112 case SVM_REG_R13:
1113 reg_p = (unsigned long *)&regs->r13;
1114 break;
1115 case SVM_REG_R14:
1116 reg_p = (unsigned long *)&regs->r14;
1117 break;
1118 case SVM_REG_R15:
1119 reg_p = (unsigned long *)&regs->r15;
1120 break;
1121 #endif
1122 default:
1123 BUG();
1126 return reg_p;
1130 static inline unsigned long get_reg(unsigned int gpreg,
1131 struct cpu_user_regs *regs, struct vmcb_struct *vmcb)
1133 unsigned long *gp;
1134 gp = get_reg_p(gpreg, regs, vmcb);
1135 return *gp;
1139 static inline void set_reg(unsigned int gpreg, unsigned long value,
1140 struct cpu_user_regs *regs, struct vmcb_struct *vmcb)
1142 unsigned long *gp;
1143 gp = get_reg_p(gpreg, regs, vmcb);
1144 *gp = value;
1148 static void svm_dr_access(struct vcpu *v, struct cpu_user_regs *regs)
1150 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1152 v->arch.hvm_vcpu.flag_dr_dirty = 1;
1154 __restore_debug_registers(v);
1156 /* allow the guest full access to the debug registers */
1157 vmcb->dr_intercepts = 0;
1161 static void svm_get_prefix_info(
1162 struct vmcb_struct *vmcb,
1163 unsigned int dir, segment_selector_t **seg, unsigned int *asize)
1165 unsigned char inst[MAX_INST_LEN];
1166 int i;
1168 memset(inst, 0, MAX_INST_LEN);
1169 if (inst_copy_from_guest(inst, svm_rip2pointer(vmcb), sizeof(inst))
1170 != MAX_INST_LEN)
1172 printk("%s: get guest instruction failed\n", __func__);
1173 domain_crash_synchronous();
1176 for (i = 0; i < MAX_INST_LEN; i++)
1178 switch (inst[i])
1180 case 0xf3: /* REPZ */
1181 case 0xf2: /* REPNZ */
1182 case 0xf0: /* LOCK */
1183 case 0x66: /* data32 */
1184 #ifdef __x86_64__
1185 /* REX prefixes */
1186 case 0x40:
1187 case 0x41:
1188 case 0x42:
1189 case 0x43:
1190 case 0x44:
1191 case 0x45:
1192 case 0x46:
1193 case 0x47:
1195 case 0x48:
1196 case 0x49:
1197 case 0x4a:
1198 case 0x4b:
1199 case 0x4c:
1200 case 0x4d:
1201 case 0x4e:
1202 case 0x4f:
1203 #endif
1204 continue;
1205 case 0x67: /* addr32 */
1206 *asize ^= 48; /* Switch 16/32 bits */
1207 continue;
1208 case 0x2e: /* CS */
1209 *seg = &vmcb->cs;
1210 continue;
1211 case 0x36: /* SS */
1212 *seg = &vmcb->ss;
1213 continue;
1214 case 0x26: /* ES */
1215 *seg = &vmcb->es;
1216 continue;
1217 case 0x64: /* FS */
1218 *seg = &vmcb->fs;
1219 continue;
1220 case 0x65: /* GS */
1221 *seg = &vmcb->gs;
1222 continue;
1223 case 0x3e: /* DS */
1224 *seg = &vmcb->ds;
1225 continue;
1226 default:
1227 break;
1229 return;
1234 /* Get the address of INS/OUTS instruction */
1235 static inline int svm_get_io_address(
1236 struct vcpu *v,
1237 struct cpu_user_regs *regs, unsigned int dir,
1238 unsigned long *count, unsigned long *addr)
1240 unsigned long reg;
1241 unsigned int asize = 0;
1242 unsigned int isize;
1243 int long_mode;
1244 ioio_info_t info;
1245 segment_selector_t *seg = NULL;
1246 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1248 info.bytes = vmcb->exitinfo1;
1250 /* If we're in long mode, we shouldn't check the segment presence & limit */
1251 long_mode = vmcb->cs.attributes.fields.l && vmcb->efer & EFER_LMA;
1253 /* d field of cs.attributes is 1 for 32-bit, 0 for 16 or 64 bit.
1254 * l field combined with EFER_LMA -> longmode says whether it's 16 or 64 bit.
1255 */
1256 asize = (long_mode)?64:((vmcb->cs.attributes.fields.db)?32:16);
1259 /* The ins/outs instructions are single byte, so if we have got more
1260 * than one byte (+ maybe rep-prefix), we have some prefix so we need
1261 * to figure out what it is...
1262 */
1263 isize = vmcb->exitinfo2 - vmcb->rip;
1265 if (info.fields.rep)
1266 isize --;
1268 if (isize > 1)
1270 svm_get_prefix_info(vmcb, dir, &seg, &asize);
1273 ASSERT(dir == IOREQ_READ || dir == IOREQ_WRITE);
1275 if (dir == IOREQ_WRITE)
1277 reg = regs->esi;
1278 if (!seg) /* If no prefix, used DS. */
1279 seg = &vmcb->ds;
1281 else
1283 reg = regs->edi;
1284 seg = &vmcb->es; /* Note: This is ALWAYS ES. */
1287 /* If the segment isn't present, give GP fault! */
1288 if (!long_mode && !seg->attributes.fields.p)
1290 svm_inject_exception(v, TRAP_gp_fault, 1, seg->sel);
1291 return 0;
1294 if (asize == 16)
1296 *addr = (reg & 0xFFFF);
1297 *count = regs->ecx & 0xffff;
1299 else
1301 *addr = reg;
1302 *count = regs->ecx;
1305 if (!long_mode) {
1306 if (*addr > seg->limit)
1308 svm_inject_exception(v, TRAP_gp_fault, 1, seg->sel);
1309 return 0;
1311 else
1313 *addr += seg->base;
1318 return 1;
1322 static void svm_io_instruction(struct vcpu *v)
1324 struct cpu_user_regs *regs;
1325 struct hvm_io_op *pio_opp;
1326 unsigned int port;
1327 unsigned int size, dir, df;
1328 ioio_info_t info;
1329 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1331 ASSERT(vmcb);
1332 pio_opp = &current->arch.hvm_vcpu.io_op;
1333 pio_opp->instr = INSTR_PIO;
1334 pio_opp->flags = 0;
1336 regs = &pio_opp->io_context;
1338 /* Copy current guest state into io instruction state structure. */
1339 memcpy(regs, guest_cpu_user_regs(), HVM_CONTEXT_STACK_BYTES);
1340 hvm_store_cpu_guest_regs(v, regs, NULL);
1342 info.bytes = vmcb->exitinfo1;
1344 port = info.fields.port; /* port used to be addr */
1345 dir = info.fields.type; /* direction */
1346 df = regs->eflags & X86_EFLAGS_DF ? 1 : 0;
1348 if (info.fields.sz32)
1349 size = 4;
1350 else if (info.fields.sz16)
1351 size = 2;
1352 else
1353 size = 1;
1355 HVM_DBG_LOG(DBG_LEVEL_IO,
1356 "svm_io_instruction: port 0x%x eip=%x:%"PRIx64", "
1357 "exit_qualification = %"PRIx64,
1358 port, vmcb->cs.sel, vmcb->rip, info.bytes);
1360 /* string instruction */
1361 if (info.fields.str)
1363 unsigned long addr, count;
1364 int sign = regs->eflags & X86_EFLAGS_DF ? -1 : 1;
1366 if (!svm_get_io_address(v, regs, dir, &count, &addr))
1368 /* We failed to get a valid address, so don't do the IO operation -
1369 * it would just get worse if we do! Hopefully the guest is handing
1370 * gp-faults...
1371 */
1372 return;
1375 /* "rep" prefix */
1376 if (info.fields.rep)
1378 pio_opp->flags |= REPZ;
1380 else
1382 count = 1;
1385 /*
1386 * Handle string pio instructions that cross pages or that
1387 * are unaligned. See the comments in hvm_platform.c/handle_mmio()
1388 */
1389 if ((addr & PAGE_MASK) != ((addr + size - 1) & PAGE_MASK))
1391 unsigned long value = 0;
1393 pio_opp->flags |= OVERLAP;
1394 pio_opp->addr = addr;
1396 if (dir == IOREQ_WRITE) /* OUTS */
1398 if (hvm_paging_enabled(current))
1399 (void)hvm_copy_from_guest_virt(&value, addr, size);
1400 else
1401 (void)hvm_copy_from_guest_phys(&value, addr, size);
1404 if (count == 1)
1405 regs->eip = vmcb->exitinfo2;
1407 send_pio_req(port, 1, size, value, dir, df, 0);
1409 else
1411 unsigned long last_addr = sign > 0 ? addr + count * size - 1
1412 : addr - (count - 1) * size;
1414 if ((addr & PAGE_MASK) != (last_addr & PAGE_MASK))
1416 if (sign > 0)
1417 count = (PAGE_SIZE - (addr & ~PAGE_MASK)) / size;
1418 else
1419 count = (addr & ~PAGE_MASK) / size + 1;
1421 else
1422 regs->eip = vmcb->exitinfo2;
1424 send_pio_req(port, count, size, addr, dir, df, 1);
1427 else
1429 /*
1430 * On SVM, the RIP of the intruction following the IN/OUT is saved in
1431 * ExitInfo2
1432 */
1433 regs->eip = vmcb->exitinfo2;
1435 if (port == 0xe9 && dir == IOREQ_WRITE && size == 1)
1436 hvm_print_line(v, regs->eax); /* guest debug output */
1438 send_pio_req(port, 1, size, regs->eax, dir, df, 0);
1442 static int svm_set_cr0(unsigned long value)
1444 struct vcpu *v = current;
1445 unsigned long mfn;
1446 int paging_enabled;
1447 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1448 unsigned long old_base_mfn;
1450 ASSERT(vmcb);
1452 /* We don't want to lose PG. ET is reserved and should be always be 1*/
1453 paging_enabled = svm_paging_enabled(v);
1454 value |= X86_CR0_ET;
1455 vmcb->cr0 = value | X86_CR0_PG;
1456 v->arch.hvm_svm.cpu_shadow_cr0 = value;
1458 /* TS cleared? Then initialise FPU now. */
1459 if ( !(value & X86_CR0_TS) )
1461 setup_fpu(v);
1462 vmcb->exception_intercepts &= ~EXCEPTION_BITMAP_NM;
1465 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR0 value = %lx\n", value);
1467 if ((value & X86_CR0_PE) && (value & X86_CR0_PG) && !paging_enabled)
1469 /* The guest CR3 must be pointing to the guest physical. */
1470 mfn = get_mfn_from_gpfn(v->arch.hvm_svm.cpu_cr3 >> PAGE_SHIFT);
1471 if ( !VALID_MFN(mfn) || !get_page(mfn_to_page(mfn), v->domain))
1473 printk("Invalid CR3 value = %lx\n", v->arch.hvm_svm.cpu_cr3);
1474 domain_crash_synchronous(); /* need to take a clean path */
1477 #if defined(__x86_64__)
1478 if (test_bit(SVM_CPU_STATE_LME_ENABLED, &v->arch.hvm_svm.cpu_state)
1479 && !test_bit(SVM_CPU_STATE_PAE_ENABLED,
1480 &v->arch.hvm_svm.cpu_state))
1482 HVM_DBG_LOG(DBG_LEVEL_1, "Enable paging before PAE enable\n");
1483 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1486 if (test_bit(SVM_CPU_STATE_LME_ENABLED, &v->arch.hvm_svm.cpu_state))
1488 /* Here the PAE is should to be opened */
1489 HVM_DBG_LOG(DBG_LEVEL_1, "Enable the Long mode\n");
1490 set_bit(SVM_CPU_STATE_LMA_ENABLED, &v->arch.hvm_svm.cpu_state);
1491 vmcb->efer |= EFER_LMA;
1493 #endif /* __x86_64__ */
1495 /* Now arch.guest_table points to machine physical. */
1496 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1497 v->arch.guest_table = pagetable_from_pfn(mfn);
1498 if ( old_base_mfn )
1499 put_page(mfn_to_page(old_base_mfn));
1500 shadow_update_paging_modes(v);
1502 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1503 (unsigned long) (mfn << PAGE_SHIFT));
1505 vmcb->cr3 = v->arch.hvm_vcpu.hw_cr3;
1506 set_bit(ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags);
1509 if ( !((value & X86_CR0_PE) && (value & X86_CR0_PG)) && paging_enabled )
1510 if ( v->arch.hvm_svm.cpu_cr3 ) {
1511 put_page(mfn_to_page(get_mfn_from_gpfn(
1512 v->arch.hvm_svm.cpu_cr3 >> PAGE_SHIFT)));
1513 v->arch.guest_table = pagetable_null();
1516 /*
1517 * SVM implements paged real-mode and when we return to real-mode
1518 * we revert back to the physical mappings that the domain builder
1519 * created.
1520 */
1521 if ((value & X86_CR0_PE) == 0) {
1522 if (value & X86_CR0_PG) {
1523 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1524 return 0;
1526 shadow_update_paging_modes(v);
1527 vmcb->cr3 = v->arch.hvm_vcpu.hw_cr3;
1528 set_bit(ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags);
1530 else if ( (value & (X86_CR0_PE | X86_CR0_PG)) == X86_CR0_PE )
1532 if ( svm_long_mode_enabled(v) )
1534 vmcb->efer &= ~EFER_LMA;
1535 clear_bit(SVM_CPU_STATE_LMA_ENABLED, &v->arch.hvm_svm.cpu_state);
1537 /* we should take care of this kind of situation */
1538 shadow_update_paging_modes(v);
1539 vmcb->cr3 = v->arch.hvm_vcpu.hw_cr3;
1540 set_bit(ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags);
1543 return 1;
1546 /*
1547 * Read from control registers. CR0 and CR4 are read from the shadow.
1548 */
1549 static void mov_from_cr(int cr, int gp, struct cpu_user_regs *regs)
1551 unsigned long value = 0;
1552 struct vcpu *v = current;
1553 struct vlapic *vlapic = vcpu_vlapic(v);
1554 struct vmcb_struct *vmcb;
1556 vmcb = v->arch.hvm_svm.vmcb;
1557 ASSERT(vmcb);
1559 switch (cr)
1561 case 0:
1562 value = v->arch.hvm_svm.cpu_shadow_cr0;
1563 if (svm_dbg_on)
1564 printk("CR0 read =%lx \n", value );
1565 break;
1566 case 2:
1567 value = vmcb->cr2;
1568 break;
1569 case 3:
1570 value = (unsigned long) v->arch.hvm_svm.cpu_cr3;
1571 if (svm_dbg_on)
1572 printk("CR3 read =%lx \n", value );
1573 break;
1574 case 4:
1575 value = (unsigned long) v->arch.hvm_svm.cpu_shadow_cr4;
1576 if (svm_dbg_on)
1577 printk("CR4 read=%lx\n", value);
1578 break;
1579 case 8:
1580 value = (unsigned long)vlapic_get_reg(vlapic, APIC_TASKPRI);
1581 value = (value & 0xF0) >> 4;
1582 break;
1584 default:
1585 __hvm_bug(regs);
1588 set_reg(gp, value, regs, vmcb);
1590 HVM_DBG_LOG(DBG_LEVEL_VMMU, "mov_from_cr: CR%d, value = %lx,", cr, value);
1594 static inline int svm_pgbit_test(struct vcpu *v)
1596 return v->arch.hvm_svm.cpu_shadow_cr0 & X86_CR0_PG;
1600 /*
1601 * Write to control registers
1602 */
1603 static int mov_to_cr(int gpreg, int cr, struct cpu_user_regs *regs)
1605 unsigned long value;
1606 unsigned long old_cr;
1607 struct vcpu *v = current;
1608 struct vlapic *vlapic = vcpu_vlapic(v);
1609 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1611 ASSERT(vmcb);
1613 value = get_reg(gpreg, regs, vmcb);
1615 HVM_DBG_LOG(DBG_LEVEL_1, "mov_to_cr: CR%d, value = %lx,", cr, value);
1616 HVM_DBG_LOG(DBG_LEVEL_1, "current = %lx,", (unsigned long) current);
1618 switch (cr)
1620 case 0:
1621 if (svm_dbg_on)
1622 printk("CR0 write =%lx \n", value );
1623 return svm_set_cr0(value);
1625 case 3:
1627 unsigned long old_base_mfn, mfn;
1628 if (svm_dbg_on)
1629 printk("CR3 write =%lx \n", value );
1630 /* If paging is not enabled yet, simply copy the value to CR3. */
1631 if (!svm_paging_enabled(v)) {
1632 v->arch.hvm_svm.cpu_cr3 = value;
1633 break;
1635 set_bit(ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags);
1637 /* We make a new one if the shadow does not exist. */
1638 if (value == v->arch.hvm_svm.cpu_cr3)
1640 /*
1641 * This is simple TLB flush, implying the guest has
1642 * removed some translation or changed page attributes.
1643 * We simply invalidate the shadow.
1644 */
1645 mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT);
1646 if (mfn != pagetable_get_pfn(v->arch.guest_table))
1647 __hvm_bug(regs);
1648 shadow_update_cr3(v);
1650 else
1652 /*
1653 * If different, make a shadow. Check if the PDBR is valid
1654 * first.
1655 */
1656 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 value = %lx", value);
1657 mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT);
1658 if ( !VALID_MFN(mfn) || !get_page(mfn_to_page(mfn), v->domain))
1660 printk("Invalid CR3 value=%lx\n", value);
1661 domain_crash_synchronous(); /* need to take a clean path */
1664 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1665 v->arch.guest_table = pagetable_from_pfn(mfn);
1667 if (old_base_mfn)
1668 put_page(mfn_to_page(old_base_mfn));
1670 v->arch.hvm_svm.cpu_cr3 = value;
1671 update_cr3(v);
1672 vmcb->cr3 = v->arch.hvm_vcpu.hw_cr3;
1673 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx", value);
1675 break;
1678 case 4: /* CR4 */
1680 if (svm_dbg_on)
1681 printk( "write cr4=%lx, cr0=%lx\n",
1682 value, v->arch.hvm_svm.cpu_shadow_cr0 );
1683 old_cr = v->arch.hvm_svm.cpu_shadow_cr4;
1684 if ( value & X86_CR4_PAE && !(old_cr & X86_CR4_PAE) )
1686 set_bit(SVM_CPU_STATE_PAE_ENABLED, &v->arch.hvm_svm.cpu_state);
1687 if ( svm_pgbit_test(v) )
1689 /* The guest is a 32-bit PAE guest. */
1690 #if CONFIG_PAGING_LEVELS >= 3
1691 unsigned long mfn, old_base_mfn;
1692 mfn = get_mfn_from_gpfn(v->arch.hvm_svm.cpu_cr3 >> PAGE_SHIFT);
1693 if ( !VALID_MFN(mfn) ||
1694 !get_page(mfn_to_page(mfn), v->domain) )
1696 printk("Invalid CR3 value = %lx", v->arch.hvm_svm.cpu_cr3);
1697 domain_crash_synchronous(); /* need to take a clean path */
1700 /*
1701 * Now arch.guest_table points to machine physical.
1702 */
1704 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1705 v->arch.guest_table = pagetable_from_pfn(mfn);
1706 if ( old_base_mfn )
1707 put_page(mfn_to_page(old_base_mfn));
1708 shadow_update_paging_modes(v);
1710 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1711 (unsigned long) (mfn << PAGE_SHIFT));
1713 vmcb->cr3 = v->arch.hvm_vcpu.hw_cr3;
1715 HVM_DBG_LOG(DBG_LEVEL_VMMU,
1716 "Update CR3 value = %lx, mfn = %lx",
1717 v->arch.hvm_svm.cpu_cr3, mfn);
1718 #endif
1721 else if (value & X86_CR4_PAE) {
1722 set_bit(SVM_CPU_STATE_PAE_ENABLED, &v->arch.hvm_svm.cpu_state);
1723 } else {
1724 if (test_bit(SVM_CPU_STATE_LMA_ENABLED,
1725 &v->arch.hvm_svm.cpu_state)) {
1726 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1728 clear_bit(SVM_CPU_STATE_PAE_ENABLED, &v->arch.hvm_svm.cpu_state);
1731 v->arch.hvm_svm.cpu_shadow_cr4 = value;
1732 vmcb->cr4 = value | SVM_CR4_HOST_MASK;
1734 /*
1735 * Writing to CR4 to modify the PSE, PGE, or PAE flag invalidates
1736 * all TLB entries except global entries.
1737 */
1738 if ((old_cr ^ value) & (X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE))
1740 set_bit(ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags);
1741 shadow_update_paging_modes(v);
1743 break;
1746 case 8:
1748 vlapic_set_reg(vlapic, APIC_TASKPRI, ((value & 0x0F) << 4));
1749 break;
1752 default:
1753 printk("invalid cr: %d\n", cr);
1754 __hvm_bug(regs);
1757 return 1;
1761 #define ARR_SIZE(x) (sizeof(x) / sizeof(x[0]))
1764 static int svm_cr_access(struct vcpu *v, unsigned int cr, unsigned int type,
1765 struct cpu_user_regs *regs)
1767 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1768 int inst_len = 0;
1769 int index;
1770 unsigned int gpreg;
1771 unsigned long value;
1772 u8 buffer[MAX_INST_LEN];
1773 u8 prefix = 0;
1774 int result = 1;
1775 enum instruction_index list_a[] = {INSTR_MOV2CR, INSTR_CLTS, INSTR_LMSW};
1776 enum instruction_index list_b[] = {INSTR_MOVCR2, INSTR_SMSW};
1777 enum instruction_index match;
1779 ASSERT(vmcb);
1781 inst_copy_from_guest(buffer, svm_rip2pointer(vmcb), sizeof(buffer));
1783 /* get index to first actual instruction byte - as we will need to know
1784 where the prefix lives later on */
1785 index = skip_prefix_bytes(buffer, sizeof(buffer));
1787 if ( type == TYPE_MOV_TO_CR )
1789 inst_len = __get_instruction_length_from_list(
1790 vmcb, list_a, ARR_SIZE(list_a), &buffer[index], &match);
1792 else /* type == TYPE_MOV_FROM_CR */
1794 inst_len = __get_instruction_length_from_list(
1795 vmcb, list_b, ARR_SIZE(list_b), &buffer[index], &match);
1798 ASSERT(inst_len > 0);
1800 inst_len += index;
1802 /* Check for REX prefix - it's ALWAYS the last byte of any prefix bytes */
1803 if (index > 0 && (buffer[index-1] & 0xF0) == 0x40)
1804 prefix = buffer[index-1];
1806 HVM_DBG_LOG(DBG_LEVEL_1, "eip = %lx", (unsigned long) vmcb->rip);
1808 switch (match)
1810 case INSTR_MOV2CR:
1811 gpreg = decode_src_reg(prefix, buffer[index+2]);
1812 result = mov_to_cr(gpreg, cr, regs);
1813 break;
1815 case INSTR_MOVCR2:
1816 gpreg = decode_src_reg(prefix, buffer[index+2]);
1817 mov_from_cr(cr, gpreg, regs);
1818 break;
1820 case INSTR_CLTS:
1821 /* TS being cleared means that it's time to restore fpu state. */
1822 setup_fpu(current);
1823 vmcb->exception_intercepts &= ~EXCEPTION_BITMAP_NM;
1824 vmcb->cr0 &= ~X86_CR0_TS; /* clear TS */
1825 v->arch.hvm_svm.cpu_shadow_cr0 &= ~X86_CR0_TS; /* clear TS */
1826 break;
1828 case INSTR_LMSW:
1829 if (svm_dbg_on)
1830 svm_dump_inst(svm_rip2pointer(vmcb));
1832 gpreg = decode_src_reg(prefix, buffer[index+2]);
1833 value = get_reg(gpreg, regs, vmcb) & 0xF;
1835 if (svm_dbg_on)
1836 printk("CR0-LMSW value=%lx, reg=%d, inst_len=%d\n", value, gpreg,
1837 inst_len);
1839 value = (v->arch.hvm_svm.cpu_shadow_cr0 & ~0xF) | value;
1841 if (svm_dbg_on)
1842 printk("CR0-LMSW CR0 - New value=%lx\n", value);
1844 result = svm_set_cr0(value);
1845 break;
1847 case INSTR_SMSW:
1848 if (svm_dbg_on)
1849 svm_dump_inst(svm_rip2pointer(vmcb));
1850 value = v->arch.hvm_svm.cpu_shadow_cr0;
1851 gpreg = decode_src_reg(prefix, buffer[index+2]);
1852 set_reg(gpreg, value, regs, vmcb);
1854 if (svm_dbg_on)
1855 printk("CR0-SMSW value=%lx, reg=%d, inst_len=%d\n", value, gpreg,
1856 inst_len);
1857 break;
1859 default:
1860 __hvm_bug(regs);
1861 break;
1864 ASSERT(inst_len);
1866 __update_guest_eip(vmcb, inst_len);
1868 return result;
1871 static inline void svm_do_msr_access(
1872 struct vcpu *v, struct cpu_user_regs *regs)
1874 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1875 int inst_len;
1876 u64 msr_content=0;
1877 u32 eax, edx;
1879 ASSERT(vmcb);
1881 HVM_DBG_LOG(DBG_LEVEL_1, "svm_do_msr_access: ecx=%lx, eax=%lx, edx=%lx, "
1882 "exitinfo = %lx", (unsigned long)regs->ecx,
1883 (unsigned long)regs->eax, (unsigned long)regs->edx,
1884 (unsigned long)vmcb->exitinfo1);
1886 /* is it a read? */
1887 if (vmcb->exitinfo1 == 0)
1889 inst_len = __get_instruction_length(vmcb, INSTR_RDMSR, NULL);
1891 regs->edx = 0;
1892 switch (regs->ecx) {
1893 case MSR_IA32_TIME_STAMP_COUNTER:
1894 msr_content = hvm_get_guest_time(v);
1895 break;
1896 case MSR_IA32_SYSENTER_CS:
1897 msr_content = vmcb->sysenter_cs;
1898 break;
1899 case MSR_IA32_SYSENTER_ESP:
1900 msr_content = vmcb->sysenter_esp;
1901 break;
1902 case MSR_IA32_SYSENTER_EIP:
1903 msr_content = vmcb->sysenter_eip;
1904 break;
1905 case MSR_IA32_APICBASE:
1906 msr_content = vcpu_vlapic(v)->apic_base_msr;
1907 break;
1908 default:
1909 if (long_mode_do_msr_read(regs))
1910 goto done;
1912 if ( rdmsr_hypervisor_regs(regs->ecx, &eax, &edx) )
1914 regs->eax = eax;
1915 regs->edx = edx;
1916 goto done;
1919 rdmsr_safe(regs->ecx, regs->eax, regs->edx);
1920 break;
1922 regs->eax = msr_content & 0xFFFFFFFF;
1923 regs->edx = msr_content >> 32;
1925 else
1927 inst_len = __get_instruction_length(vmcb, INSTR_WRMSR, NULL);
1928 msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
1930 switch (regs->ecx)
1932 case MSR_IA32_TIME_STAMP_COUNTER:
1933 hvm_set_guest_time(v, msr_content);
1934 break;
1935 case MSR_IA32_SYSENTER_CS:
1936 vmcb->sysenter_cs = msr_content;
1937 break;
1938 case MSR_IA32_SYSENTER_ESP:
1939 vmcb->sysenter_esp = msr_content;
1940 break;
1941 case MSR_IA32_SYSENTER_EIP:
1942 vmcb->sysenter_eip = msr_content;
1943 break;
1944 case MSR_IA32_APICBASE:
1945 vlapic_msr_set(vcpu_vlapic(v), msr_content);
1946 break;
1947 default:
1948 if ( !long_mode_do_msr_write(regs) )
1949 wrmsr_hypervisor_regs(regs->ecx, regs->eax, regs->edx);
1950 break;
1954 done:
1956 HVM_DBG_LOG(DBG_LEVEL_1, "svm_do_msr_access returns: "
1957 "ecx=%lx, eax=%lx, edx=%lx",
1958 (unsigned long)regs->ecx, (unsigned long)regs->eax,
1959 (unsigned long)regs->edx);
1961 __update_guest_eip(vmcb, inst_len);
1965 static inline void svm_vmexit_do_hlt(struct vmcb_struct *vmcb)
1967 __update_guest_eip(vmcb, 1);
1969 /* Check for interrupt not handled or new interrupt. */
1970 if ( (vmcb->rflags & X86_EFLAGS_IF) &&
1971 (vmcb->vintr.fields.irq || cpu_has_pending_irq(current)) )
1972 return;
1974 hvm_hlt(vmcb->rflags);
1978 static void svm_vmexit_do_invd(struct vmcb_struct *vmcb)
1980 int inst_len;
1982 /* Invalidate the cache - we can't really do that safely - maybe we should
1983 * WBINVD, but I think it's just fine to completely ignore it - we should
1984 * have cache-snooping that solves it anyways. -- Mats P.
1985 */
1987 /* Tell the user that we did this - just in case someone runs some really
1988 * weird operating system and wants to know why it's not working...
1989 */
1990 printk("INVD instruction intercepted - ignored\n");
1992 inst_len = __get_instruction_length(vmcb, INSTR_INVD, NULL);
1993 __update_guest_eip(vmcb, inst_len);
1999 #ifdef XEN_DEBUGGER
2000 static void svm_debug_save_cpu_user_regs(struct vmcb_struct *vmcb,
2001 struct cpu_user_regs *regs)
2003 regs->eip = vmcb->rip;
2004 regs->esp = vmcb->rsp;
2005 regs->eflags = vmcb->rflags;
2007 regs->xcs = vmcb->cs.sel;
2008 regs->xds = vmcb->ds.sel;
2009 regs->xes = vmcb->es.sel;
2010 regs->xfs = vmcb->fs.sel;
2011 regs->xgs = vmcb->gs.sel;
2012 regs->xss = vmcb->ss.sel;
2016 static void svm_debug_restore_cpu_user_regs(struct cpu_user_regs *regs)
2018 vmcb->ss.sel = regs->xss;
2019 vmcb->rsp = regs->esp;
2020 vmcb->rflags = regs->eflags;
2021 vmcb->cs.sel = regs->xcs;
2022 vmcb->rip = regs->eip;
2024 vmcb->gs.sel = regs->xgs;
2025 vmcb->fs.sel = regs->xfs;
2026 vmcb->es.sel = regs->xes;
2027 vmcb->ds.sel = regs->xds;
2029 #endif
2032 void svm_handle_invlpg(const short invlpga, struct cpu_user_regs *regs)
2034 struct vcpu *v = current;
2035 u8 opcode[MAX_INST_LEN], prefix, length = MAX_INST_LEN;
2036 unsigned long g_vaddr;
2037 int inst_len;
2038 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2040 ASSERT(vmcb);
2041 /*
2042 * Unknown how many bytes the invlpg instruction will take. Use the
2043 * maximum instruction length here
2044 */
2045 if (inst_copy_from_guest(opcode, svm_rip2pointer(vmcb), length) < length)
2047 printk("svm_handle_invlpg (): Error reading memory %d bytes\n",
2048 length);
2049 __hvm_bug(regs);
2052 if (invlpga)
2054 inst_len = __get_instruction_length(vmcb, INSTR_INVLPGA, opcode);
2055 ASSERT(inst_len > 0);
2056 __update_guest_eip(vmcb, inst_len);
2058 /*
2059 * The address is implicit on this instruction. At the moment, we don't
2060 * use ecx (ASID) to identify individual guests pages
2061 */
2062 g_vaddr = regs->eax;
2064 else
2066 /* What about multiple prefix codes? */
2067 prefix = (is_prefix(opcode[0])?opcode[0]:0);
2068 inst_len = __get_instruction_length(vmcb, INSTR_INVLPG, opcode);
2069 ASSERT(inst_len > 0);
2071 inst_len--;
2072 length -= inst_len;
2074 /*
2075 * Decode memory operand of the instruction including ModRM, SIB, and
2076 * displacement to get effecticve address and length in bytes. Assume
2077 * the system in either 32- or 64-bit mode.
2078 */
2079 g_vaddr = get_effective_addr_modrm64(vmcb, regs, prefix,
2080 &opcode[inst_len], &length);
2082 inst_len += length;
2083 __update_guest_eip (vmcb, inst_len);
2086 /* Overkill, we may not this */
2087 set_bit(ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags);
2088 shadow_invlpg(v, g_vaddr);
2092 /*
2093 * Reset to realmode causes execution to start at 0xF000:0xFFF0 in
2094 * 16-bit realmode. Basically, this mimics a processor reset.
2096 * returns 0 on success, non-zero otherwise
2097 */
2098 static int svm_do_vmmcall_reset_to_realmode(struct vcpu *v,
2099 struct cpu_user_regs *regs)
2101 struct vmcb_struct *vmcb;
2103 ASSERT(v);
2104 ASSERT(regs);
2106 vmcb = v->arch.hvm_svm.vmcb;
2108 ASSERT(vmcb);
2110 /* clear the vmcb and user regs */
2111 memset(regs, 0, sizeof(struct cpu_user_regs));
2113 /* VMCB Control */
2114 vmcb->tsc_offset = 0;
2116 /* VMCB State */
2117 vmcb->cr0 = X86_CR0_ET | X86_CR0_PG;
2118 v->arch.hvm_svm.cpu_shadow_cr0 = X86_CR0_ET;
2120 vmcb->cr2 = 0;
2121 vmcb->efer = EFER_SVME;
2123 vmcb->cr4 = SVM_CR4_HOST_MASK;
2124 v->arch.hvm_svm.cpu_shadow_cr4 = 0;
2125 clear_bit(SVM_CPU_STATE_PAE_ENABLED, &v->arch.hvm_svm.cpu_state);
2127 /* This will jump to ROMBIOS */
2128 vmcb->rip = 0xFFF0;
2130 /* setup the segment registers and all their hidden states */
2131 vmcb->cs.sel = 0xF000;
2132 vmcb->cs.attributes.bytes = 0x089b;
2133 vmcb->cs.limit = 0xffff;
2134 vmcb->cs.base = 0x000F0000;
2136 vmcb->ss.sel = 0x00;
2137 vmcb->ss.attributes.bytes = 0x0893;
2138 vmcb->ss.limit = 0xffff;
2139 vmcb->ss.base = 0x00;
2141 vmcb->ds.sel = 0x00;
2142 vmcb->ds.attributes.bytes = 0x0893;
2143 vmcb->ds.limit = 0xffff;
2144 vmcb->ds.base = 0x00;
2146 vmcb->es.sel = 0x00;
2147 vmcb->es.attributes.bytes = 0x0893;
2148 vmcb->es.limit = 0xffff;
2149 vmcb->es.base = 0x00;
2151 vmcb->fs.sel = 0x00;
2152 vmcb->fs.attributes.bytes = 0x0893;
2153 vmcb->fs.limit = 0xffff;
2154 vmcb->fs.base = 0x00;
2156 vmcb->gs.sel = 0x00;
2157 vmcb->gs.attributes.bytes = 0x0893;
2158 vmcb->gs.limit = 0xffff;
2159 vmcb->gs.base = 0x00;
2161 vmcb->ldtr.sel = 0x00;
2162 vmcb->ldtr.attributes.bytes = 0x0000;
2163 vmcb->ldtr.limit = 0x0;
2164 vmcb->ldtr.base = 0x00;
2166 vmcb->gdtr.sel = 0x00;
2167 vmcb->gdtr.attributes.bytes = 0x0000;
2168 vmcb->gdtr.limit = 0x0;
2169 vmcb->gdtr.base = 0x00;
2171 vmcb->tr.sel = 0;
2172 vmcb->tr.attributes.bytes = 0;
2173 vmcb->tr.limit = 0x0;
2174 vmcb->tr.base = 0;
2176 vmcb->idtr.sel = 0x00;
2177 vmcb->idtr.attributes.bytes = 0x0000;
2178 vmcb->idtr.limit = 0x3ff;
2179 vmcb->idtr.base = 0x00;
2181 vmcb->rax = 0;
2182 vmcb->rsp = 0;
2184 return 0;
2188 /*
2189 * svm_do_vmmcall - SVM VMMCALL handler
2191 * returns 0 on success, non-zero otherwise
2192 */
2193 static int svm_do_vmmcall(struct vcpu *v, struct cpu_user_regs *regs)
2195 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2196 int inst_len;
2198 ASSERT(vmcb);
2199 ASSERT(regs);
2201 inst_len = __get_instruction_length(vmcb, INSTR_VMCALL, NULL);
2202 ASSERT(inst_len > 0);
2204 if ( regs->eax & 0x80000000 )
2206 /* VMMCALL sanity check */
2207 if ( vmcb->cpl > get_vmmcall_cpl(regs->edi) )
2209 printk("VMMCALL CPL check failed\n");
2210 return -1;
2213 /* handle the request */
2214 switch ( regs->eax )
2216 case VMMCALL_RESET_TO_REALMODE:
2217 if ( svm_do_vmmcall_reset_to_realmode(v, regs) )
2219 printk("svm_do_vmmcall_reset_to_realmode() failed\n");
2220 return -1;
2222 /* since we just reset the VMCB, return without adjusting
2223 * the eip */
2224 return 0;
2226 case VMMCALL_DEBUG:
2227 printk("DEBUG features not implemented yet\n");
2228 break;
2229 default:
2230 break;
2233 hvm_print_line(v, regs->eax); /* provides the current domain */
2235 else
2237 hvm_do_hypercall(regs);
2240 __update_guest_eip(vmcb, inst_len);
2241 return 0;
2245 void svm_dump_inst(unsigned long eip)
2247 u8 opcode[256];
2248 unsigned long ptr;
2249 int len;
2250 int i;
2252 ptr = eip & ~0xff;
2253 len = 0;
2255 if (hvm_copy_from_guest_virt(opcode, ptr, sizeof(opcode)) == 0)
2256 len = sizeof(opcode);
2258 printk("Code bytes around(len=%d) %lx:", len, eip);
2259 for (i = 0; i < len; i++)
2261 if ((i & 0x0f) == 0)
2262 printk("\n%08lx:", ptr+i);
2264 printk("%02x ", opcode[i]);
2267 printk("\n");
2271 void svm_dump_regs(const char *from, struct cpu_user_regs *regs)
2273 struct vcpu *v = current;
2274 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2275 unsigned long pt = v->arch.hvm_vcpu.hw_cr3;
2277 printk("%s: guest registers from %s:\n", __func__, from);
2278 #if defined (__x86_64__)
2279 printk("rax: %016lx rbx: %016lx rcx: %016lx\n",
2280 regs->rax, regs->rbx, regs->rcx);
2281 printk("rdx: %016lx rsi: %016lx rdi: %016lx\n",
2282 regs->rdx, regs->rsi, regs->rdi);
2283 printk("rbp: %016lx rsp: %016lx r8: %016lx\n",
2284 regs->rbp, regs->rsp, regs->r8);
2285 printk("r9: %016lx r10: %016lx r11: %016lx\n",
2286 regs->r9, regs->r10, regs->r11);
2287 printk("r12: %016lx r13: %016lx r14: %016lx\n",
2288 regs->r12, regs->r13, regs->r14);
2289 printk("r15: %016lx cr0: %016lx cr3: %016lx\n",
2290 regs->r15, v->arch.hvm_svm.cpu_shadow_cr0, vmcb->cr3);
2291 #else
2292 printk("eax: %08x, ebx: %08x, ecx: %08x, edx: %08x\n",
2293 regs->eax, regs->ebx, regs->ecx, regs->edx);
2294 printk("edi: %08x, esi: %08x, ebp: %08x, esp: %08x\n",
2295 regs->edi, regs->esi, regs->ebp, regs->esp);
2296 printk("%s: guest cr0: %lx\n", __func__,
2297 v->arch.hvm_svm.cpu_shadow_cr0);
2298 printk("guest CR3 = %llx\n", vmcb->cr3);
2299 #endif
2300 printk("%s: pt = %lx\n", __func__, pt);
2304 void svm_dump_host_regs(const char *from)
2306 struct vcpu *v = current;
2307 unsigned long pt = pt = pagetable_get_paddr(v->arch.monitor_table);
2308 unsigned long cr3, cr0;
2309 printk("Host registers at %s\n", from);
2311 __asm__ __volatile__ ("\tmov %%cr0,%0\n"
2312 "\tmov %%cr3,%1\n"
2313 : "=r" (cr0), "=r"(cr3));
2314 printk("%s: pt = %lx, cr3 = %lx, cr0 = %lx\n", __func__, pt, cr3, cr0);
2317 #ifdef SVM_EXTRA_DEBUG
2318 static char *exit_reasons[] = {
2319 [VMEXIT_CR0_READ] = "CR0_READ",
2320 [VMEXIT_CR1_READ] = "CR1_READ",
2321 [VMEXIT_CR2_READ] = "CR2_READ",
2322 [VMEXIT_CR3_READ] = "CR3_READ",
2323 [VMEXIT_CR4_READ] = "CR4_READ",
2324 [VMEXIT_CR5_READ] = "CR5_READ",
2325 [VMEXIT_CR6_READ] = "CR6_READ",
2326 [VMEXIT_CR7_READ] = "CR7_READ",
2327 [VMEXIT_CR8_READ] = "CR8_READ",
2328 [VMEXIT_CR9_READ] = "CR9_READ",
2329 [VMEXIT_CR10_READ] = "CR10_READ",
2330 [VMEXIT_CR11_READ] = "CR11_READ",
2331 [VMEXIT_CR12_READ] = "CR12_READ",
2332 [VMEXIT_CR13_READ] = "CR13_READ",
2333 [VMEXIT_CR14_READ] = "CR14_READ",
2334 [VMEXIT_CR15_READ] = "CR15_READ",
2335 [VMEXIT_CR0_WRITE] = "CR0_WRITE",
2336 [VMEXIT_CR1_WRITE] = "CR1_WRITE",
2337 [VMEXIT_CR2_WRITE] = "CR2_WRITE",
2338 [VMEXIT_CR3_WRITE] = "CR3_WRITE",
2339 [VMEXIT_CR4_WRITE] = "CR4_WRITE",
2340 [VMEXIT_CR5_WRITE] = "CR5_WRITE",
2341 [VMEXIT_CR6_WRITE] = "CR6_WRITE",
2342 [VMEXIT_CR7_WRITE] = "CR7_WRITE",
2343 [VMEXIT_CR8_WRITE] = "CR8_WRITE",
2344 [VMEXIT_CR9_WRITE] = "CR9_WRITE",
2345 [VMEXIT_CR10_WRITE] = "CR10_WRITE",
2346 [VMEXIT_CR11_WRITE] = "CR11_WRITE",
2347 [VMEXIT_CR12_WRITE] = "CR12_WRITE",
2348 [VMEXIT_CR13_WRITE] = "CR13_WRITE",
2349 [VMEXIT_CR14_WRITE] = "CR14_WRITE",
2350 [VMEXIT_CR15_WRITE] = "CR15_WRITE",
2351 [VMEXIT_DR0_READ] = "DR0_READ",
2352 [VMEXIT_DR1_READ] = "DR1_READ",
2353 [VMEXIT_DR2_READ] = "DR2_READ",
2354 [VMEXIT_DR3_READ] = "DR3_READ",
2355 [VMEXIT_DR4_READ] = "DR4_READ",
2356 [VMEXIT_DR5_READ] = "DR5_READ",
2357 [VMEXIT_DR6_READ] = "DR6_READ",
2358 [VMEXIT_DR7_READ] = "DR7_READ",
2359 [VMEXIT_DR8_READ] = "DR8_READ",
2360 [VMEXIT_DR9_READ] = "DR9_READ",
2361 [VMEXIT_DR10_READ] = "DR10_READ",
2362 [VMEXIT_DR11_READ] = "DR11_READ",
2363 [VMEXIT_DR12_READ] = "DR12_READ",
2364 [VMEXIT_DR13_READ] = "DR13_READ",
2365 [VMEXIT_DR14_READ] = "DR14_READ",
2366 [VMEXIT_DR15_READ] = "DR15_READ",
2367 [VMEXIT_DR0_WRITE] = "DR0_WRITE",
2368 [VMEXIT_DR1_WRITE] = "DR1_WRITE",
2369 [VMEXIT_DR2_WRITE] = "DR2_WRITE",
2370 [VMEXIT_DR3_WRITE] = "DR3_WRITE",
2371 [VMEXIT_DR4_WRITE] = "DR4_WRITE",
2372 [VMEXIT_DR5_WRITE] = "DR5_WRITE",
2373 [VMEXIT_DR6_WRITE] = "DR6_WRITE",
2374 [VMEXIT_DR7_WRITE] = "DR7_WRITE",
2375 [VMEXIT_DR8_WRITE] = "DR8_WRITE",
2376 [VMEXIT_DR9_WRITE] = "DR9_WRITE",
2377 [VMEXIT_DR10_WRITE] = "DR10_WRITE",
2378 [VMEXIT_DR11_WRITE] = "DR11_WRITE",
2379 [VMEXIT_DR12_WRITE] = "DR12_WRITE",
2380 [VMEXIT_DR13_WRITE] = "DR13_WRITE",
2381 [VMEXIT_DR14_WRITE] = "DR14_WRITE",
2382 [VMEXIT_DR15_WRITE] = "DR15_WRITE",
2383 [VMEXIT_EXCEPTION_DE] = "EXCEPTION_DE",
2384 [VMEXIT_EXCEPTION_DB] = "EXCEPTION_DB",
2385 [VMEXIT_EXCEPTION_NMI] = "EXCEPTION_NMI",
2386 [VMEXIT_EXCEPTION_BP] = "EXCEPTION_BP",
2387 [VMEXIT_EXCEPTION_OF] = "EXCEPTION_OF",
2388 [VMEXIT_EXCEPTION_BR] = "EXCEPTION_BR",
2389 [VMEXIT_EXCEPTION_UD] = "EXCEPTION_UD",
2390 [VMEXIT_EXCEPTION_NM] = "EXCEPTION_NM",
2391 [VMEXIT_EXCEPTION_DF] = "EXCEPTION_DF",
2392 [VMEXIT_EXCEPTION_09] = "EXCEPTION_09",
2393 [VMEXIT_EXCEPTION_TS] = "EXCEPTION_TS",
2394 [VMEXIT_EXCEPTION_NP] = "EXCEPTION_NP",
2395 [VMEXIT_EXCEPTION_SS] = "EXCEPTION_SS",
2396 [VMEXIT_EXCEPTION_GP] = "EXCEPTION_GP",
2397 [VMEXIT_EXCEPTION_PF] = "EXCEPTION_PF",
2398 [VMEXIT_EXCEPTION_15] = "EXCEPTION_15",
2399 [VMEXIT_EXCEPTION_MF] = "EXCEPTION_MF",
2400 [VMEXIT_EXCEPTION_AC] = "EXCEPTION_AC",
2401 [VMEXIT_EXCEPTION_MC] = "EXCEPTION_MC",
2402 [VMEXIT_EXCEPTION_XF] = "EXCEPTION_XF",
2403 [VMEXIT_INTR] = "INTR",
2404 [VMEXIT_NMI] = "NMI",
2405 [VMEXIT_SMI] = "SMI",
2406 [VMEXIT_INIT] = "INIT",
2407 [VMEXIT_VINTR] = "VINTR",
2408 [VMEXIT_CR0_SEL_WRITE] = "CR0_SEL_WRITE",
2409 [VMEXIT_IDTR_READ] = "IDTR_READ",
2410 [VMEXIT_GDTR_READ] = "GDTR_READ",
2411 [VMEXIT_LDTR_READ] = "LDTR_READ",
2412 [VMEXIT_TR_READ] = "TR_READ",
2413 [VMEXIT_IDTR_WRITE] = "IDTR_WRITE",
2414 [VMEXIT_GDTR_WRITE] = "GDTR_WRITE",
2415 [VMEXIT_LDTR_WRITE] = "LDTR_WRITE",
2416 [VMEXIT_TR_WRITE] = "TR_WRITE",
2417 [VMEXIT_RDTSC] = "RDTSC",
2418 [VMEXIT_RDPMC] = "RDPMC",
2419 [VMEXIT_PUSHF] = "PUSHF",
2420 [VMEXIT_POPF] = "POPF",
2421 [VMEXIT_CPUID] = "CPUID",
2422 [VMEXIT_RSM] = "RSM",
2423 [VMEXIT_IRET] = "IRET",
2424 [VMEXIT_SWINT] = "SWINT",
2425 [VMEXIT_INVD] = "INVD",
2426 [VMEXIT_PAUSE] = "PAUSE",
2427 [VMEXIT_HLT] = "HLT",
2428 [VMEXIT_INVLPG] = "INVLPG",
2429 [VMEXIT_INVLPGA] = "INVLPGA",
2430 [VMEXIT_IOIO] = "IOIO",
2431 [VMEXIT_MSR] = "MSR",
2432 [VMEXIT_TASK_SWITCH] = "TASK_SWITCH",
2433 [VMEXIT_FERR_FREEZE] = "FERR_FREEZE",
2434 [VMEXIT_SHUTDOWN] = "SHUTDOWN",
2435 [VMEXIT_VMRUN] = "VMRUN",
2436 [VMEXIT_VMMCALL] = "VMMCALL",
2437 [VMEXIT_VMLOAD] = "VMLOAD",
2438 [VMEXIT_VMSAVE] = "VMSAVE",
2439 [VMEXIT_STGI] = "STGI",
2440 [VMEXIT_CLGI] = "CLGI",
2441 [VMEXIT_SKINIT] = "SKINIT",
2442 [VMEXIT_RDTSCP] = "RDTSCP",
2443 [VMEXIT_ICEBP] = "ICEBP",
2444 [VMEXIT_NPF] = "NPF"
2445 };
2446 #endif /* SVM_EXTRA_DEBUG */
2448 #ifdef SVM_WALK_GUEST_PAGES
2449 void walk_shadow_and_guest_pt(unsigned long gva)
2451 l2_pgentry_t gpde;
2452 l2_pgentry_t spde;
2453 l1_pgentry_t gpte;
2454 l1_pgentry_t spte;
2455 struct vcpu *v = current;
2456 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2457 paddr_t gpa;
2459 gpa = shadow_gva_to_gpa(current, gva);
2460 printk("gva = %lx, gpa=%"PRIpaddr", gCR3=%x\n", gva, gpa, (u32)vmcb->cr3);
2461 if( !svm_paging_enabled(v) || mmio_space(gpa) )
2462 return;
2464 /* let's dump the guest and shadow page info */
2466 __guest_get_l2e(v, gva, &gpde);
2467 printk( "G-PDE = %x, flags=%x\n", gpde.l2, l2e_get_flags(gpde) );
2468 __shadow_get_l2e( v, gva, &spde );
2469 printk( "S-PDE = %x, flags=%x\n", spde.l2, l2e_get_flags(spde) );
2471 if ( unlikely(!(l2e_get_flags(gpde) & _PAGE_PRESENT)) )
2472 return;
2474 spte = l1e_empty();
2476 /* This is actually overkill - we only need to ensure the hl2 is in-sync.*/
2477 shadow_sync_va(v, gva);
2479 gpte.l1 = 0;
2480 __copy_from_user(&gpte, &linear_pg_table[ l1_linear_offset(gva) ],
2481 sizeof(gpte) );
2482 printk( "G-PTE = %x, flags=%x\n", gpte.l1, l1e_get_flags(gpte) );
2484 BUG(); // need to think about this, and convert usage of
2485 // phys_to_machine_mapping to use pagetable format...
2486 __copy_from_user( &spte, &phys_to_machine_mapping[ l1e_get_pfn( gpte ) ],
2487 sizeof(spte) );
2489 printk( "S-PTE = %x, flags=%x\n", spte.l1, l1e_get_flags(spte));
2491 #endif /* SVM_WALK_GUEST_PAGES */
2494 asmlinkage void svm_vmexit_handler(struct cpu_user_regs *regs)
2496 unsigned int exit_reason;
2497 unsigned long eip;
2498 struct vcpu *v = current;
2499 int error;
2500 int do_debug = 0;
2501 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2503 ASSERT(vmcb);
2505 exit_reason = vmcb->exitcode;
2506 save_svm_cpu_user_regs(v, regs);
2508 v->arch.hvm_svm.inject_event = 0;
2510 if (exit_reason == VMEXIT_INVALID)
2512 svm_dump_vmcb(__func__, vmcb);
2513 domain_crash_synchronous();
2516 #ifdef SVM_EXTRA_DEBUG
2518 #if defined(__i386__)
2519 #define rip eip
2520 #endif
2522 static unsigned long intercepts_counter = 0;
2524 if (svm_dbg_on && exit_reason == VMEXIT_EXCEPTION_PF)
2526 if (svm_paging_enabled(v) &&
2527 !mmio_space(shadow_gva_to_gpa(current, vmcb->exitinfo2)))
2529 printk("I%08ld,ExC=%s(%d),IP=%x:%"PRIx64","
2530 "I1=%"PRIx64",I2=%"PRIx64",INT=%"PRIx64", "
2531 "gpa=%"PRIx64"\n", intercepts_counter,
2532 exit_reasons[exit_reason], exit_reason, regs->cs,
2533 (u64)regs->rip,
2534 (u64)vmcb->exitinfo1,
2535 (u64)vmcb->exitinfo2,
2536 (u64)vmcb->exitintinfo.bytes,
2537 (u64)shadow_gva_to_gpa(current, vmcb->exitinfo2));
2539 else
2541 printk("I%08ld,ExC=%s(%d),IP=%x:%"PRIx64","
2542 "I1=%"PRIx64",I2=%"PRIx64",INT=%"PRIx64"\n",
2543 intercepts_counter,
2544 exit_reasons[exit_reason], exit_reason, regs->cs,
2545 (u64)regs->rip,
2546 (u64)vmcb->exitinfo1,
2547 (u64)vmcb->exitinfo2,
2548 (u64)vmcb->exitintinfo.bytes );
2551 else if ( svm_dbg_on
2552 && exit_reason != VMEXIT_IOIO
2553 && exit_reason != VMEXIT_INTR)
2556 if (exit_reasons[exit_reason])
2558 printk("I%08ld,ExC=%s(%d),IP=%x:%"PRIx64","
2559 "I1=%"PRIx64",I2=%"PRIx64",INT=%"PRIx64"\n",
2560 intercepts_counter,
2561 exit_reasons[exit_reason], exit_reason, regs->cs,
2562 (u64)regs->rip,
2563 (u64)vmcb->exitinfo1,
2564 (u64)vmcb->exitinfo2,
2565 (u64)vmcb->exitintinfo.bytes);
2567 else
2569 printk("I%08ld,ExC=%d(0x%x),IP=%x:%"PRIx64","
2570 "I1=%"PRIx64",I2=%"PRIx64",INT=%"PRIx64"\n",
2571 intercepts_counter, exit_reason, exit_reason, regs->cs,
2572 (u64)regs->rip,
2573 (u64)vmcb->exitinfo1,
2574 (u64)vmcb->exitinfo2,
2575 (u64)vmcb->exitintinfo.bytes);
2579 #ifdef SVM_WALK_GUEST_PAGES
2580 if( exit_reason == VMEXIT_EXCEPTION_PF
2581 && ( ( vmcb->exitinfo2 == vmcb->rip )
2582 || vmcb->exitintinfo.bytes) )
2584 if ( svm_paging_enabled(v) &&
2585 !mmio_space(gva_to_gpa(vmcb->exitinfo2)) )
2586 walk_shadow_and_guest_pt(vmcb->exitinfo2);
2588 #endif
2590 intercepts_counter++;
2592 #if 0
2593 if (svm_dbg_on)
2594 do_debug = svm_do_debugout(exit_reason);
2595 #endif
2597 if (do_debug)
2599 printk("%s:+ guest_table = 0x%08x, monitor_table = 0x%08x, "
2600 "hw_cr3 = 0x%16lx\n",
2601 __func__,
2602 (int) v->arch.guest_table.pfn,
2603 (int) v->arch.monitor_table.pfn,
2604 (long unsigned int) v->arch.hvm_vcpu.hw_cr3);
2606 svm_dump_vmcb(__func__, vmcb);
2607 svm_dump_regs(__func__, regs);
2608 svm_dump_inst(svm_rip2pointer(vmcb));
2611 #if defined(__i386__)
2612 #undef rip
2613 #endif
2616 #endif /* SVM_EXTRA_DEBUG */
2619 perfc_incra(svmexits, exit_reason);
2620 eip = vmcb->rip;
2622 #ifdef SVM_EXTRA_DEBUG
2623 if (do_debug)
2625 printk("eip = %lx, exit_reason = %d (0x%x)\n",
2626 eip, exit_reason, exit_reason);
2628 #endif /* SVM_EXTRA_DEBUG */
2630 TRACE_3D(TRC_VMX_VMEXIT, v->domain->domain_id, eip, exit_reason);
2632 switch (exit_reason)
2634 case VMEXIT_EXCEPTION_DB:
2636 #ifdef XEN_DEBUGGER
2637 svm_debug_save_cpu_user_regs(regs);
2638 pdb_handle_exception(1, regs, 1);
2639 svm_debug_restore_cpu_user_regs(regs);
2640 #else
2641 svm_store_cpu_user_regs(regs, v);
2642 domain_pause_for_debugger();
2643 #endif
2645 break;
2647 case VMEXIT_NMI:
2648 break;
2650 case VMEXIT_SMI:
2651 /*
2652 * For asynchronous SMI's, we just need to allow global interrupts
2653 * so that the SMI is taken properly in the context of the host. The
2654 * standard code does a STGI after the VMEXIT which should accomplish
2655 * this task. Continue as normal and restart the guest.
2656 */
2657 break;
2659 case VMEXIT_INIT:
2660 /*
2661 * Nothing to do, in fact we should never get to this point.
2662 */
2663 break;
2665 case VMEXIT_EXCEPTION_BP:
2666 #ifdef XEN_DEBUGGER
2667 svm_debug_save_cpu_user_regs(regs);
2668 pdb_handle_exception(3, regs, 1);
2669 svm_debug_restore_cpu_user_regs(regs);
2670 #else
2671 if ( test_bit(_DOMF_debugging, &v->domain->domain_flags) )
2672 domain_pause_for_debugger();
2673 else
2674 svm_inject_exception(v, TRAP_int3, 0, 0);
2675 #endif
2676 break;
2678 case VMEXIT_EXCEPTION_NM:
2679 svm_do_no_device_fault(vmcb);
2680 break;
2682 case VMEXIT_EXCEPTION_GP:
2683 /* This should probably not be trapped in the future */
2684 regs->error_code = vmcb->exitinfo1;
2685 svm_do_general_protection_fault(v, regs);
2686 break;
2688 case VMEXIT_EXCEPTION_PF:
2690 unsigned long va;
2691 va = vmcb->exitinfo2;
2692 regs->error_code = vmcb->exitinfo1;
2693 HVM_DBG_LOG(DBG_LEVEL_VMMU,
2694 "eax=%lx, ebx=%lx, ecx=%lx, edx=%lx, esi=%lx, edi=%lx",
2695 (unsigned long)regs->eax, (unsigned long)regs->ebx,
2696 (unsigned long)regs->ecx, (unsigned long)regs->edx,
2697 (unsigned long)regs->esi, (unsigned long)regs->edi);
2699 if (!(error = svm_do_page_fault(va, regs)))
2701 /* Inject #PG using Interruption-Information Fields */
2702 svm_inject_exception(v, TRAP_page_fault, 1, regs->error_code);
2704 v->arch.hvm_svm.cpu_cr2 = va;
2705 vmcb->cr2 = va;
2706 TRACE_3D(TRC_VMX_INTR, v->domain->domain_id,
2707 VMEXIT_EXCEPTION_PF, va);
2709 break;
2712 case VMEXIT_EXCEPTION_DF:
2713 /* Debug info to hopefully help debug WHY the guest double-faulted. */
2714 svm_dump_vmcb(__func__, vmcb);
2715 svm_dump_regs(__func__, regs);
2716 svm_dump_inst(svm_rip2pointer(vmcb));
2717 svm_inject_exception(v, TRAP_double_fault, 1, 0);
2718 break;
2720 case VMEXIT_VINTR:
2721 vmcb->vintr.fields.irq = 0;
2722 vmcb->general1_intercepts &= ~GENERAL1_INTERCEPT_VINTR;
2723 break;
2725 case VMEXIT_INTR:
2726 break;
2728 case VMEXIT_INVD:
2729 svm_vmexit_do_invd(vmcb);
2730 break;
2732 case VMEXIT_GDTR_WRITE:
2733 printk("WRITE to GDTR\n");
2734 break;
2736 case VMEXIT_TASK_SWITCH:
2737 __hvm_bug(regs);
2738 break;
2740 case VMEXIT_CPUID:
2741 svm_vmexit_do_cpuid(vmcb, regs->eax, regs);
2742 break;
2744 case VMEXIT_HLT:
2745 svm_vmexit_do_hlt(vmcb);
2746 break;
2748 case VMEXIT_INVLPG:
2749 svm_handle_invlpg(0, regs);
2750 break;
2752 case VMEXIT_INVLPGA:
2753 svm_handle_invlpg(1, regs);
2754 break;
2756 case VMEXIT_VMMCALL:
2757 svm_do_vmmcall(v, regs);
2758 break;
2760 case VMEXIT_CR0_READ:
2761 svm_cr_access(v, 0, TYPE_MOV_FROM_CR, regs);
2762 break;
2764 case VMEXIT_CR2_READ:
2765 svm_cr_access(v, 2, TYPE_MOV_FROM_CR, regs);
2766 break;
2768 case VMEXIT_CR3_READ:
2769 svm_cr_access(v, 3, TYPE_MOV_FROM_CR, regs);
2770 break;
2772 case VMEXIT_CR4_READ:
2773 svm_cr_access(v, 4, TYPE_MOV_FROM_CR, regs);
2774 break;
2776 case VMEXIT_CR8_READ:
2777 svm_cr_access(v, 8, TYPE_MOV_FROM_CR, regs);
2778 break;
2780 case VMEXIT_CR0_WRITE:
2781 svm_cr_access(v, 0, TYPE_MOV_TO_CR, regs);
2782 break;
2784 case VMEXIT_CR2_WRITE:
2785 svm_cr_access(v, 2, TYPE_MOV_TO_CR, regs);
2786 break;
2788 case VMEXIT_CR3_WRITE:
2789 svm_cr_access(v, 3, TYPE_MOV_TO_CR, regs);
2790 local_flush_tlb();
2791 break;
2793 case VMEXIT_CR4_WRITE:
2794 svm_cr_access(v, 4, TYPE_MOV_TO_CR, regs);
2795 break;
2797 case VMEXIT_CR8_WRITE:
2798 svm_cr_access(v, 8, TYPE_MOV_TO_CR, regs);
2799 break;
2801 case VMEXIT_DR0_WRITE ... VMEXIT_DR7_WRITE:
2802 svm_dr_access(v, regs);
2803 break;
2805 case VMEXIT_IOIO:
2806 svm_io_instruction(v);
2807 break;
2809 case VMEXIT_MSR:
2810 svm_do_msr_access(v, regs);
2811 break;
2813 case VMEXIT_SHUTDOWN:
2814 printk("Guest shutdown exit\n");
2815 domain_crash_synchronous();
2816 break;
2818 default:
2819 printk("unexpected VMEXIT: exit reason = 0x%x, exitinfo1 = %"PRIx64", "
2820 "exitinfo2 = %"PRIx64"\n", exit_reason,
2821 (u64)vmcb->exitinfo1, (u64)vmcb->exitinfo2);
2822 __hvm_bug(regs); /* should not happen */
2823 break;
2826 #ifdef SVM_EXTRA_DEBUG
2827 if (do_debug)
2829 printk("%s: Done switch on vmexit_code\n", __func__);
2830 svm_dump_regs(__func__, regs);
2833 if (do_debug)
2835 printk("vmexit_handler():- guest_table = 0x%08x, "
2836 "monitor_table = 0x%08x, hw_cr3 = 0x%16x\n",
2837 (int)v->arch.guest_table.pfn,
2838 (int)v->arch.monitor_table.pfn,
2839 (int)v->arch.hvm_vcpu.hw_cr3);
2840 printk("svm_vmexit_handler: Returning\n");
2842 #endif
2844 return;
2847 asmlinkage void svm_load_cr2(void)
2849 struct vcpu *v = current;
2851 local_irq_disable();
2852 asm volatile("mov %0,%%cr2": :"r" (v->arch.hvm_svm.cpu_cr2));
2855 asmlinkage void svm_asid(void)
2857 struct vcpu *v = current;
2858 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2860 /*
2861 * if need to assign new asid, or if switching cores,
2862 * retire asid for the old core, and assign a new asid to the current core.
2863 */
2864 if ( test_bit( ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags ) ||
2865 ( v->arch.hvm_svm.asid_core != v->arch.hvm_svm.launch_core )) {
2866 /* recycle asid */
2867 if ( !asidpool_assign_next(vmcb, 1,
2868 v->arch.hvm_svm.asid_core,
2869 v->arch.hvm_svm.launch_core) )
2871 /* If we get here, we have a major problem */
2872 domain_crash_synchronous();
2875 v->arch.hvm_svm.asid_core = v->arch.hvm_svm.launch_core;
2876 clear_bit( ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags );
2880 /*
2881 * Local variables:
2882 * mode: C
2883 * c-set-style: "BSD"
2884 * c-basic-offset: 4
2885 * tab-width: 4
2886 * indent-tabs-mode: nil
2887 * End:
2888 */