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view xen/include/asm-x86/hvm/vmx/vmx.h @ 15388:50358c4b37f4

hvm: Support injection of virtual NMIs and clean up ExtInt handling in general.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Wed Jun 20 11:50:16 2007 +0100 (2007-06-20)
parents 4d8381679606
children 3cf5052ba5e5
line source
1 /*
2 * vmx.h: VMX Architecture related definitions
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19 #ifndef __ASM_X86_HVM_VMX_VMX_H__
20 #define __ASM_X86_HVM_VMX_VMX_H__
22 #include <xen/sched.h>
23 #include <asm/types.h>
24 #include <asm/regs.h>
25 #include <asm/processor.h>
26 #include <asm/hvm/vmx/vmcs.h>
27 #include <asm/i387.h>
28 #include <asm/hvm/trace.h>
30 void vmx_asm_vmexit_handler(struct cpu_user_regs);
31 void vmx_asm_do_vmentry(void);
32 void vmx_intr_assist(void);
33 void vmx_do_resume(struct vcpu *);
34 void set_guest_time(struct vcpu *v, u64 gtime);
35 void vmx_vlapic_msr_changed(struct vcpu *v);
37 /*
38 * Exit Reasons
39 */
40 #define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000
42 #define EXIT_REASON_EXCEPTION_NMI 0
43 #define EXIT_REASON_EXTERNAL_INTERRUPT 1
44 #define EXIT_REASON_TRIPLE_FAULT 2
45 #define EXIT_REASON_INIT 3
46 #define EXIT_REASON_SIPI 4
47 #define EXIT_REASON_IO_SMI 5
48 #define EXIT_REASON_OTHER_SMI 6
49 #define EXIT_REASON_PENDING_VIRT_INTR 7
50 #define EXIT_REASON_PENDING_VIRT_NMI 8
51 #define EXIT_REASON_TASK_SWITCH 9
52 #define EXIT_REASON_CPUID 10
53 #define EXIT_REASON_HLT 12
54 #define EXIT_REASON_INVD 13
55 #define EXIT_REASON_INVLPG 14
56 #define EXIT_REASON_RDPMC 15
57 #define EXIT_REASON_RDTSC 16
58 #define EXIT_REASON_RSM 17
59 #define EXIT_REASON_VMCALL 18
60 #define EXIT_REASON_VMCLEAR 19
61 #define EXIT_REASON_VMLAUNCH 20
62 #define EXIT_REASON_VMPTRLD 21
63 #define EXIT_REASON_VMPTRST 22
64 #define EXIT_REASON_VMREAD 23
65 #define EXIT_REASON_VMRESUME 24
66 #define EXIT_REASON_VMWRITE 25
67 #define EXIT_REASON_VMXOFF 26
68 #define EXIT_REASON_VMXON 27
69 #define EXIT_REASON_CR_ACCESS 28
70 #define EXIT_REASON_DR_ACCESS 29
71 #define EXIT_REASON_IO_INSTRUCTION 30
72 #define EXIT_REASON_MSR_READ 31
73 #define EXIT_REASON_MSR_WRITE 32
75 #define EXIT_REASON_INVALID_GUEST_STATE 33
76 #define EXIT_REASON_MSR_LOADING 34
78 #define EXIT_REASON_MWAIT_INSTRUCTION 36
79 #define EXIT_REASON_MONITOR_INSTRUCTION 39
80 #define EXIT_REASON_PAUSE_INSTRUCTION 40
82 #define EXIT_REASON_MACHINE_CHECK 41
84 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
85 #define EXIT_REASON_APIC_ACCESS 44
87 /*
88 * Interruption-information format
89 */
90 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
91 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
92 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
93 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
95 #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
96 #define INTR_TYPE_NMI (2 << 8) /* NMI */
97 #define INTR_TYPE_HW_EXCEPTION (3 << 8) /* hardware exception */
98 #define INTR_TYPE_SW_EXCEPTION (6 << 8) /* software exception */
100 /*
101 * Exit Qualifications for MOV for Control Register Access
102 */
103 #define CONTROL_REG_ACCESS_NUM 0xf /* 3:0, number of control register */
104 #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
105 #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose register */
106 #define LMSW_SOURCE_DATA (0xFFFF << 16) /* 16:31 lmsw source */
107 #define REG_EAX (0 << 8)
108 #define REG_ECX (1 << 8)
109 #define REG_EDX (2 << 8)
110 #define REG_EBX (3 << 8)
111 #define REG_ESP (4 << 8)
112 #define REG_EBP (5 << 8)
113 #define REG_ESI (6 << 8)
114 #define REG_EDI (7 << 8)
115 #define REG_R8 (8 << 8)
116 #define REG_R9 (9 << 8)
117 #define REG_R10 (10 << 8)
118 #define REG_R11 (11 << 8)
119 #define REG_R12 (12 << 8)
120 #define REG_R13 (13 << 8)
121 #define REG_R14 (14 << 8)
122 #define REG_R15 (15 << 8)
124 /*
125 * Exit Qualifications for MOV for Debug Register Access
126 */
127 #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug register */
128 #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
129 #define TYPE_MOV_TO_DR (0 << 4)
130 #define TYPE_MOV_FROM_DR (1 << 4)
131 #define DEBUG_REG_ACCESS_REG 0xf00 /* 11:8, general purpose register */
133 /*
134 * Access Rights
135 */
136 #define X86_SEG_AR_SEG_TYPE 0xf /* 3:0, segment type */
137 #define X86_SEG_AR_DESC_TYPE (1u << 4) /* 4, descriptor type */
138 #define X86_SEG_AR_DPL 0x60 /* 6:5, descriptor privilege level */
139 #define X86_SEG_AR_SEG_PRESENT (1u << 7) /* 7, segment present */
140 #define X86_SEG_AR_AVL (1u << 12) /* 12, available for system software */
141 #define X86_SEG_AR_CS_LM_ACTIVE (1u << 13) /* 13, long mode active (CS only) */
142 #define X86_SEG_AR_DEF_OP_SIZE (1u << 14) /* 14, default operation size */
143 #define X86_SEG_AR_GRANULARITY (1u << 15) /* 15, granularity */
144 #define X86_SEG_AR_SEG_UNUSABLE (1u << 16) /* 16, segment unusable */
146 /* These bits in the CR4 are owned by the host */
147 #if CONFIG_PAGING_LEVELS >= 3
148 #define VMX_CR4_HOST_MASK (X86_CR4_VMXE | X86_CR4_PAE)
149 #else
150 #define VMX_CR4_HOST_MASK (X86_CR4_VMXE)
151 #endif
153 #define VMCALL_OPCODE ".byte 0x0f,0x01,0xc1\n"
154 #define VMCLEAR_OPCODE ".byte 0x66,0x0f,0xc7\n" /* reg/opcode: /6 */
155 #define VMLAUNCH_OPCODE ".byte 0x0f,0x01,0xc2\n"
156 #define VMPTRLD_OPCODE ".byte 0x0f,0xc7\n" /* reg/opcode: /6 */
157 #define VMPTRST_OPCODE ".byte 0x0f,0xc7\n" /* reg/opcode: /7 */
158 #define VMREAD_OPCODE ".byte 0x0f,0x78\n"
159 #define VMRESUME_OPCODE ".byte 0x0f,0x01,0xc3\n"
160 #define VMWRITE_OPCODE ".byte 0x0f,0x79\n"
161 #define VMXOFF_OPCODE ".byte 0x0f,0x01,0xc4\n"
162 #define VMXON_OPCODE ".byte 0xf3,0x0f,0xc7\n"
164 #define MODRM_EAX_06 ".byte 0x30\n" /* [EAX], with reg/opcode: /6 */
165 #define MODRM_EAX_07 ".byte 0x38\n" /* [EAX], with reg/opcode: /7 */
166 #define MODRM_EAX_ECX ".byte 0xc1\n" /* [EAX], [ECX] */
168 static inline void __vmptrld(u64 addr)
169 {
170 __asm__ __volatile__ ( VMPTRLD_OPCODE
171 MODRM_EAX_06
172 /* CF==1 or ZF==1 --> crash (ud2) */
173 "ja 1f ; ud2 ; 1:\n"
174 :
175 : "a" (&addr)
176 : "memory");
177 }
179 static inline void __vmptrst(u64 addr)
180 {
181 __asm__ __volatile__ ( VMPTRST_OPCODE
182 MODRM_EAX_07
183 :
184 : "a" (&addr)
185 : "memory");
186 }
188 static inline void __vmpclear(u64 addr)
189 {
190 __asm__ __volatile__ ( VMCLEAR_OPCODE
191 MODRM_EAX_06
192 /* CF==1 or ZF==1 --> crash (ud2) */
193 "ja 1f ; ud2 ; 1:\n"
194 :
195 : "a" (&addr)
196 : "memory");
197 }
199 static inline unsigned long __vmread(unsigned long field)
200 {
201 unsigned long ecx;
203 __asm__ __volatile__ ( VMREAD_OPCODE
204 MODRM_EAX_ECX
205 /* CF==1 or ZF==1 --> crash (ud2) */
206 "ja 1f ; ud2 ; 1:\n"
207 : "=c" (ecx)
208 : "a" (field)
209 : "memory");
211 return ecx;
212 }
214 static inline void __vmwrite(unsigned long field, unsigned long value)
215 {
216 __asm__ __volatile__ ( VMWRITE_OPCODE
217 MODRM_EAX_ECX
218 /* CF==1 or ZF==1 --> crash (ud2) */
219 "ja 1f ; ud2 ; 1:\n"
220 :
221 : "a" (field) , "c" (value)
222 : "memory");
223 }
225 static inline unsigned long __vmread_safe(unsigned long field, int *error)
226 {
227 unsigned long ecx;
229 __asm__ __volatile__ ( VMREAD_OPCODE
230 MODRM_EAX_ECX
231 /* CF==1 or ZF==1 --> rc = -1 */
232 "setna %b0 ; neg %0"
233 : "=q" (*error), "=c" (ecx)
234 : "0" (0), "a" (field)
235 : "memory");
237 return ecx;
238 }
240 static inline void __vm_set_bit(unsigned long field, unsigned int bit)
241 {
242 __vmwrite(field, __vmread(field) | (1UL << bit));
243 }
245 static inline void __vm_clear_bit(unsigned long field, unsigned int bit)
246 {
247 __vmwrite(field, __vmread(field) & ~(1UL << bit));
248 }
250 static inline void __vmxoff (void)
251 {
252 __asm__ __volatile__ ( VMXOFF_OPCODE
253 ::: "memory");
254 }
256 static inline int __vmxon (u64 addr)
257 {
258 int rc;
260 __asm__ __volatile__ ( VMXON_OPCODE
261 MODRM_EAX_06
262 /* CF==1 or ZF==1 --> rc = -1 */
263 "setna %b0 ; neg %0"
264 : "=q" (rc)
265 : "0" (0), "a" (&addr)
266 : "memory");
268 return rc;
269 }
271 static inline int vmx_paging_enabled(struct vcpu *v)
272 {
273 unsigned long cr0 = v->arch.hvm_vmx.cpu_shadow_cr0;
274 return ((cr0 & (X86_CR0_PE|X86_CR0_PG)) == (X86_CR0_PE|X86_CR0_PG));
275 }
277 static inline int vmx_long_mode_enabled(struct vcpu *v)
278 {
279 return v->arch.hvm_vmx.efer & EFER_LMA;
280 }
282 static inline int vmx_lme_is_set(struct vcpu *v)
283 {
284 return v->arch.hvm_vmx.efer & EFER_LME;
285 }
287 static inline int vmx_pgbit_test(struct vcpu *v)
288 {
289 unsigned long cr0 = v->arch.hvm_vmx.cpu_shadow_cr0;
290 return (cr0 & X86_CR0_PG);
291 }
293 static inline void __vmx_inject_exception(struct vcpu *v, int trap, int type,
294 int error_code, int ilen)
295 {
296 unsigned long intr_fields;
298 /*
299 * NB. Callers do not need to worry about clearing STI/MOV-SS blocking:
300 * "If the VM entry is injecting, there is no blocking by STI or by
301 * MOV SS following the VM entry, regardless of the contents of the
302 * interruptibility-state field [in the guest-state area before the
303 * VM entry]", PRM Vol. 3, 22.6.1 (Interruptibility State).
304 */
306 intr_fields = (INTR_INFO_VALID_MASK | type | trap);
307 if ( error_code != VMX_DELIVER_NO_ERROR_CODE ) {
308 __vmwrite(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
309 intr_fields |= INTR_INFO_DELIVER_CODE_MASK;
310 }
312 if ( ilen )
313 __vmwrite(VM_ENTRY_INSTRUCTION_LEN, ilen);
315 __vmwrite(VM_ENTRY_INTR_INFO_FIELD, intr_fields);
317 if (trap == TRAP_page_fault)
318 HVMTRACE_2D(PF_INJECT, v, v->arch.hvm_vmx.cpu_cr2, error_code);
319 else
320 HVMTRACE_2D(INJ_EXC, v, trap, error_code);
321 }
323 static inline void vmx_inject_hw_exception(
324 struct vcpu *v, int trap, int error_code)
325 {
326 v->arch.hvm_vmx.vector_injected = 1;
327 __vmx_inject_exception(v, trap, INTR_TYPE_HW_EXCEPTION, error_code, 0);
328 }
330 static inline void vmx_inject_sw_exception(
331 struct vcpu *v, int trap, int instruction_len)
332 {
333 v->arch.hvm_vmx.vector_injected = 1;
334 __vmx_inject_exception(v, trap, INTR_TYPE_SW_EXCEPTION,
335 VMX_DELIVER_NO_ERROR_CODE,
336 instruction_len);
337 }
339 static inline void vmx_inject_extint(struct vcpu *v, int trap)
340 {
341 __vmx_inject_exception(v, trap, INTR_TYPE_EXT_INTR,
342 VMX_DELIVER_NO_ERROR_CODE, 0);
343 }
345 static inline void vmx_inject_nmi(struct vcpu *v)
346 {
347 __vmx_inject_exception(v, 2, INTR_TYPE_NMI,
348 VMX_DELIVER_NO_ERROR_CODE, 0);
349 }
351 #endif /* __ASM_X86_HVM_VMX_VMX_H__ */