direct-io.hg

view xen/arch/x86/hvm/svm/svm.c @ 15388:50358c4b37f4

hvm: Support injection of virtual NMIs and clean up ExtInt handling in general.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Wed Jun 20 11:50:16 2007 +0100 (2007-06-20)
parents 739d698986e9
children 3624ba0caccc
line source
1 /*
2 * svm.c: handling SVM architecture-related VM exits
3 * Copyright (c) 2004, Intel Corporation.
4 * Copyright (c) 2005-2007, Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
17 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 */
20 #include <xen/config.h>
21 #include <xen/init.h>
22 #include <xen/lib.h>
23 #include <xen/trace.h>
24 #include <xen/sched.h>
25 #include <xen/irq.h>
26 #include <xen/softirq.h>
27 #include <xen/hypercall.h>
28 #include <xen/domain_page.h>
29 #include <asm/current.h>
30 #include <asm/io.h>
31 #include <asm/paging.h>
32 #include <asm/p2m.h>
33 #include <asm/regs.h>
34 #include <asm/cpufeature.h>
35 #include <asm/processor.h>
36 #include <asm/types.h>
37 #include <asm/msr.h>
38 #include <asm/spinlock.h>
39 #include <asm/hvm/hvm.h>
40 #include <asm/hvm/support.h>
41 #include <asm/hvm/io.h>
42 #include <asm/hvm/svm/asid.h>
43 #include <asm/hvm/svm/svm.h>
44 #include <asm/hvm/svm/vmcb.h>
45 #include <asm/hvm/svm/emulate.h>
46 #include <asm/hvm/svm/intr.h>
47 #include <asm/x86_emulate.h>
48 #include <public/sched.h>
49 #include <asm/hvm/vpt.h>
50 #include <asm/hvm/trace.h>
51 #include <asm/hap.h>
53 #define set_segment_register(name, value) \
54 asm volatile ( "movw %%ax ,%%" STR(name) "" : : "a" (value) )
56 int inst_copy_from_guest(unsigned char *buf, unsigned long guest_eip,
57 int inst_len);
58 asmlinkage void do_IRQ(struct cpu_user_regs *);
60 static int svm_reset_to_realmode(struct vcpu *v,
61 struct cpu_user_regs *regs);
63 /* va of hardware host save area */
64 static void *hsa[NR_CPUS] __read_mostly;
66 /* vmcb used for extended host state */
67 static void *root_vmcb[NR_CPUS] __read_mostly;
69 /* hardware assisted paging bits */
70 extern int opt_hap_enabled;
72 static inline void svm_inject_exception(struct vcpu *v, int trap,
73 int ev, int error_code)
74 {
75 eventinj_t event;
76 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
78 if ( trap == TRAP_page_fault )
79 HVMTRACE_2D(PF_INJECT, v, v->arch.hvm_svm.cpu_cr2, error_code);
80 else
81 HVMTRACE_2D(INJ_EXC, v, trap, error_code);
83 event.bytes = 0;
84 event.fields.v = 1;
85 event.fields.type = EVENTTYPE_EXCEPTION;
86 event.fields.vector = trap;
87 event.fields.ev = ev;
88 event.fields.errorcode = error_code;
90 ASSERT(vmcb->eventinj.fields.v == 0);
92 vmcb->eventinj = event;
93 }
95 static void stop_svm(void)
96 {
97 /* We turn off the EFER_SVME bit. */
98 write_efer(read_efer() & ~EFER_SVME);
99 }
101 static void svm_store_cpu_guest_regs(
102 struct vcpu *v, struct cpu_user_regs *regs, unsigned long *crs)
103 {
104 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
106 if ( regs != NULL )
107 {
108 regs->ss = vmcb->ss.sel;
109 regs->esp = vmcb->rsp;
110 regs->eflags = vmcb->rflags;
111 regs->cs = vmcb->cs.sel;
112 regs->eip = vmcb->rip;
113 }
115 if ( crs != NULL )
116 {
117 /* Returning the guest's regs */
118 crs[0] = v->arch.hvm_svm.cpu_shadow_cr0;
119 crs[2] = v->arch.hvm_svm.cpu_cr2;
120 crs[3] = v->arch.hvm_svm.cpu_cr3;
121 crs[4] = v->arch.hvm_svm.cpu_shadow_cr4;
122 }
123 }
125 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
126 {
127 u64 msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
128 u32 ecx = regs->ecx;
129 struct vcpu *v = current;
130 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
132 HVM_DBG_LOG(DBG_LEVEL_0, "msr %x msr_content %"PRIx64,
133 ecx, msr_content);
135 switch ( ecx )
136 {
137 case MSR_EFER:
138 /* Offending reserved bit will cause #GP. */
139 #ifdef __x86_64__
140 if ( (msr_content & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE)) ||
141 #else
142 if ( (msr_content & ~(EFER_NX | EFER_SCE)) ||
143 #endif
144 (!cpu_has_nx && (msr_content & EFER_NX)) ||
145 (!cpu_has_syscall && (msr_content & EFER_SCE)) )
146 {
147 gdprintk(XENLOG_WARNING, "Trying to set reserved bit in "
148 "EFER: %"PRIx64"\n", msr_content);
149 goto gp_fault;
150 }
152 #ifdef __x86_64__
153 if ( (msr_content & EFER_LME) && !svm_lme_is_set(v) )
154 {
155 /* EFER.LME transition from 0 to 1. */
156 if ( svm_paging_enabled(v) || !svm_cr4_pae_is_set(v) )
157 {
158 gdprintk(XENLOG_WARNING, "Trying to set LME bit when "
159 "in paging mode or PAE bit is not set\n");
160 goto gp_fault;
161 }
162 }
163 else if ( !(msr_content & EFER_LME) && svm_lme_is_set(v) )
164 {
165 /* EFER.LME transistion from 1 to 0. */
166 if ( svm_paging_enabled(v) )
167 {
168 gdprintk(XENLOG_WARNING,
169 "Trying to clear EFER.LME while paging enabled\n");
170 goto gp_fault;
171 }
172 }
173 #endif /* __x86_64__ */
175 v->arch.hvm_svm.cpu_shadow_efer = msr_content;
176 vmcb->efer = msr_content | EFER_SVME;
177 if ( !svm_paging_enabled(v) )
178 vmcb->efer &= ~(EFER_LME | EFER_LMA);
180 break;
182 case MSR_K8_MC4_MISC: /* Threshold register */
183 /*
184 * MCA/MCE: Threshold register is reported to be locked, so we ignore
185 * all write accesses. This behaviour matches real HW, so guests should
186 * have no problem with this.
187 */
188 break;
190 default:
191 return 0;
192 }
194 return 1;
196 gp_fault:
197 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
198 return 0;
199 }
202 #define loaddebug(_v,_reg) \
203 asm volatile ("mov %0,%%db" #_reg : : "r" ((_v)->debugreg[_reg]))
204 #define savedebug(_v,_reg) \
205 asm volatile ("mov %%db" #_reg ",%0" : : "r" ((_v)->debugreg[_reg]))
207 static inline void svm_save_dr(struct vcpu *v)
208 {
209 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
211 if ( !v->arch.hvm_vcpu.flag_dr_dirty )
212 return;
214 /* Clear the DR dirty flag and re-enable intercepts for DR accesses. */
215 v->arch.hvm_vcpu.flag_dr_dirty = 0;
216 v->arch.hvm_svm.vmcb->dr_intercepts = DR_INTERCEPT_ALL_WRITES;
218 savedebug(&v->arch.guest_context, 0);
219 savedebug(&v->arch.guest_context, 1);
220 savedebug(&v->arch.guest_context, 2);
221 savedebug(&v->arch.guest_context, 3);
222 v->arch.guest_context.debugreg[6] = vmcb->dr6;
223 v->arch.guest_context.debugreg[7] = vmcb->dr7;
224 }
227 static inline void __restore_debug_registers(struct vcpu *v)
228 {
229 loaddebug(&v->arch.guest_context, 0);
230 loaddebug(&v->arch.guest_context, 1);
231 loaddebug(&v->arch.guest_context, 2);
232 loaddebug(&v->arch.guest_context, 3);
233 /* DR6 and DR7 are loaded from the VMCB. */
234 }
237 int svm_vmcb_save(struct vcpu *v, struct hvm_hw_cpu *c)
238 {
239 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
241 c->rip = vmcb->rip;
243 #ifdef HVM_DEBUG_SUSPEND
244 printk("%s: eip=0x%"PRIx64".\n",
245 __func__,
246 inst_len, c->eip);
247 #endif
249 c->rsp = vmcb->rsp;
250 c->rflags = vmcb->rflags;
252 c->cr0 = v->arch.hvm_svm.cpu_shadow_cr0;
253 c->cr2 = v->arch.hvm_svm.cpu_cr2;
254 c->cr3 = v->arch.hvm_svm.cpu_cr3;
255 c->cr4 = v->arch.hvm_svm.cpu_shadow_cr4;
257 #ifdef HVM_DEBUG_SUSPEND
258 printk("%s: cr3=0x%"PRIx64", cr0=0x%"PRIx64", cr4=0x%"PRIx64".\n",
259 __func__,
260 c->cr3,
261 c->cr0,
262 c->cr4);
263 #endif
265 c->idtr_limit = vmcb->idtr.limit;
266 c->idtr_base = vmcb->idtr.base;
268 c->gdtr_limit = vmcb->gdtr.limit;
269 c->gdtr_base = vmcb->gdtr.base;
271 c->cs_sel = vmcb->cs.sel;
272 c->cs_limit = vmcb->cs.limit;
273 c->cs_base = vmcb->cs.base;
274 c->cs_arbytes = vmcb->cs.attr.bytes;
276 c->ds_sel = vmcb->ds.sel;
277 c->ds_limit = vmcb->ds.limit;
278 c->ds_base = vmcb->ds.base;
279 c->ds_arbytes = vmcb->ds.attr.bytes;
281 c->es_sel = vmcb->es.sel;
282 c->es_limit = vmcb->es.limit;
283 c->es_base = vmcb->es.base;
284 c->es_arbytes = vmcb->es.attr.bytes;
286 c->ss_sel = vmcb->ss.sel;
287 c->ss_limit = vmcb->ss.limit;
288 c->ss_base = vmcb->ss.base;
289 c->ss_arbytes = vmcb->ss.attr.bytes;
291 c->fs_sel = vmcb->fs.sel;
292 c->fs_limit = vmcb->fs.limit;
293 c->fs_base = vmcb->fs.base;
294 c->fs_arbytes = vmcb->fs.attr.bytes;
296 c->gs_sel = vmcb->gs.sel;
297 c->gs_limit = vmcb->gs.limit;
298 c->gs_base = vmcb->gs.base;
299 c->gs_arbytes = vmcb->gs.attr.bytes;
301 c->tr_sel = vmcb->tr.sel;
302 c->tr_limit = vmcb->tr.limit;
303 c->tr_base = vmcb->tr.base;
304 c->tr_arbytes = vmcb->tr.attr.bytes;
306 c->ldtr_sel = vmcb->ldtr.sel;
307 c->ldtr_limit = vmcb->ldtr.limit;
308 c->ldtr_base = vmcb->ldtr.base;
309 c->ldtr_arbytes = vmcb->ldtr.attr.bytes;
311 c->sysenter_cs = vmcb->sysenter_cs;
312 c->sysenter_esp = vmcb->sysenter_esp;
313 c->sysenter_eip = vmcb->sysenter_eip;
315 /* Save any event/interrupt that was being injected when we last exited. */
316 if ( vmcb->exitintinfo.fields.v )
317 {
318 c->pending_event = vmcb->exitintinfo.bytes & 0xffffffff;
319 c->error_code = vmcb->exitintinfo.fields.errorcode;
320 }
321 else if ( vmcb->eventinj.fields.v )
322 {
323 c->pending_event = vmcb->eventinj.bytes & 0xffffffff;
324 c->error_code = vmcb->eventinj.fields.errorcode;
325 }
326 else
327 {
328 c->pending_event = 0;
329 c->error_code = 0;
330 }
332 return 1;
333 }
336 int svm_vmcb_restore(struct vcpu *v, struct hvm_hw_cpu *c)
337 {
338 unsigned long mfn, old_base_mfn;
339 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
341 vmcb->rip = c->rip;
342 vmcb->rsp = c->rsp;
343 vmcb->rflags = c->rflags;
345 v->arch.hvm_svm.cpu_shadow_cr0 = c->cr0;
346 vmcb->cr0 = c->cr0 | X86_CR0_WP | X86_CR0_ET | X86_CR0_PG;
348 v->arch.hvm_svm.cpu_cr2 = c->cr2;
350 #ifdef HVM_DEBUG_SUSPEND
351 printk("%s: cr3=0x%"PRIx64", cr0=0x%"PRIx64", cr4=0x%"PRIx64".\n",
352 __func__,
353 c->cr3,
354 c->cr0,
355 c->cr4);
356 #endif
358 if ( !svm_paging_enabled(v) )
359 {
360 printk("%s: paging not enabled.\n", __func__);
361 goto skip_cr3;
362 }
364 if ( c->cr3 == v->arch.hvm_svm.cpu_cr3 )
365 {
366 /*
367 * This is simple TLB flush, implying the guest has
368 * removed some translation or changed page attributes.
369 * We simply invalidate the shadow.
370 */
371 mfn = gmfn_to_mfn(v->domain, c->cr3 >> PAGE_SHIFT);
372 if ( mfn != pagetable_get_pfn(v->arch.guest_table) )
373 goto bad_cr3;
374 }
375 else
376 {
377 /*
378 * If different, make a shadow. Check if the PDBR is valid
379 * first.
380 */
381 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 c->cr3 = %"PRIx64, c->cr3);
382 mfn = gmfn_to_mfn(v->domain, c->cr3 >> PAGE_SHIFT);
383 if( !mfn_valid(mfn) || !get_page(mfn_to_page(mfn), v->domain) )
384 goto bad_cr3;
386 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
387 v->arch.guest_table = pagetable_from_pfn(mfn);
388 if (old_base_mfn)
389 put_page(mfn_to_page(old_base_mfn));
390 v->arch.hvm_svm.cpu_cr3 = c->cr3;
391 }
393 skip_cr3:
394 vmcb->cr4 = c->cr4 | SVM_CR4_HOST_MASK;
395 v->arch.hvm_svm.cpu_shadow_cr4 = c->cr4;
397 vmcb->idtr.limit = c->idtr_limit;
398 vmcb->idtr.base = c->idtr_base;
400 vmcb->gdtr.limit = c->gdtr_limit;
401 vmcb->gdtr.base = c->gdtr_base;
403 vmcb->cs.sel = c->cs_sel;
404 vmcb->cs.limit = c->cs_limit;
405 vmcb->cs.base = c->cs_base;
406 vmcb->cs.attr.bytes = c->cs_arbytes;
408 vmcb->ds.sel = c->ds_sel;
409 vmcb->ds.limit = c->ds_limit;
410 vmcb->ds.base = c->ds_base;
411 vmcb->ds.attr.bytes = c->ds_arbytes;
413 vmcb->es.sel = c->es_sel;
414 vmcb->es.limit = c->es_limit;
415 vmcb->es.base = c->es_base;
416 vmcb->es.attr.bytes = c->es_arbytes;
418 vmcb->ss.sel = c->ss_sel;
419 vmcb->ss.limit = c->ss_limit;
420 vmcb->ss.base = c->ss_base;
421 vmcb->ss.attr.bytes = c->ss_arbytes;
422 vmcb->cpl = vmcb->ss.attr.fields.dpl;
424 vmcb->fs.sel = c->fs_sel;
425 vmcb->fs.limit = c->fs_limit;
426 vmcb->fs.base = c->fs_base;
427 vmcb->fs.attr.bytes = c->fs_arbytes;
429 vmcb->gs.sel = c->gs_sel;
430 vmcb->gs.limit = c->gs_limit;
431 vmcb->gs.base = c->gs_base;
432 vmcb->gs.attr.bytes = c->gs_arbytes;
434 vmcb->tr.sel = c->tr_sel;
435 vmcb->tr.limit = c->tr_limit;
436 vmcb->tr.base = c->tr_base;
437 vmcb->tr.attr.bytes = c->tr_arbytes;
439 vmcb->ldtr.sel = c->ldtr_sel;
440 vmcb->ldtr.limit = c->ldtr_limit;
441 vmcb->ldtr.base = c->ldtr_base;
442 vmcb->ldtr.attr.bytes = c->ldtr_arbytes;
444 vmcb->sysenter_cs = c->sysenter_cs;
445 vmcb->sysenter_esp = c->sysenter_esp;
446 vmcb->sysenter_eip = c->sysenter_eip;
448 /* update VMCB for nested paging restore */
449 if ( paging_mode_hap(v->domain) ) {
450 vmcb->cr0 = v->arch.hvm_svm.cpu_shadow_cr0;
451 vmcb->cr4 = v->arch.hvm_svm.cpu_shadow_cr4;
452 vmcb->cr3 = c->cr3;
453 vmcb->np_enable = 1;
454 vmcb->g_pat = 0x0007040600070406ULL; /* guest PAT */
455 vmcb->h_cr3 = pagetable_get_paddr(v->domain->arch.phys_table);
456 }
458 vmcb->dr6 = c->dr6;
459 vmcb->dr7 = c->dr7;
461 if ( c->pending_valid )
462 {
463 gdprintk(XENLOG_INFO, "Re-injecting 0x%"PRIx32", 0x%"PRIx32"\n",
464 c->pending_event, c->error_code);
466 /* VMX uses a different type for #OF and #BP; fold into "Exception" */
467 if ( c->pending_type == 6 )
468 c->pending_type = 3;
469 /* Sanity check */
470 if ( c->pending_type == 1 || c->pending_type > 4
471 || c->pending_reserved != 0 )
472 {
473 gdprintk(XENLOG_ERR, "Invalid pending event 0x%"PRIx32"\n",
474 c->pending_event);
475 return -EINVAL;
476 }
477 /* Put this pending event in exitintinfo and svm_intr_assist()
478 * will reinject it when we return to the guest. */
479 vmcb->exitintinfo.bytes = c->pending_event;
480 vmcb->exitintinfo.fields.errorcode = c->error_code;
481 }
483 paging_update_paging_modes(v);
484 /* signal paging update to ASID handler */
485 svm_asid_g_update_paging (v);
487 return 0;
489 bad_cr3:
490 gdprintk(XENLOG_ERR, "Invalid CR3 value=0x%"PRIx64"\n", c->cr3);
491 return -EINVAL;
492 }
495 static void svm_save_cpu_state(struct vcpu *v, struct hvm_hw_cpu *data)
496 {
497 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
499 data->shadow_gs = vmcb->kerngsbase;
500 data->msr_lstar = vmcb->lstar;
501 data->msr_star = vmcb->star;
502 data->msr_cstar = vmcb->cstar;
503 data->msr_syscall_mask = vmcb->sfmask;
504 data->msr_efer = v->arch.hvm_svm.cpu_shadow_efer;
505 data->msr_flags = -1ULL;
507 data->tsc = hvm_get_guest_time(v);
508 }
511 static void svm_load_cpu_state(struct vcpu *v, struct hvm_hw_cpu *data)
512 {
513 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
515 vmcb->kerngsbase = data->shadow_gs;
516 vmcb->lstar = data->msr_lstar;
517 vmcb->star = data->msr_star;
518 vmcb->cstar = data->msr_cstar;
519 vmcb->sfmask = data->msr_syscall_mask;
520 v->arch.hvm_svm.cpu_shadow_efer = data->msr_efer;
521 vmcb->efer = data->msr_efer | EFER_SVME;
522 /* VMCB's EFER.LME isn't set unless we're actually in long mode
523 * (see long_mode_do_msr_write()) */
524 if ( !(vmcb->efer & EFER_LMA) )
525 vmcb->efer &= ~EFER_LME;
527 hvm_set_guest_time(v, data->tsc);
528 }
530 static void svm_save_vmcb_ctxt(struct vcpu *v, struct hvm_hw_cpu *ctxt)
531 {
532 svm_save_cpu_state(v, ctxt);
533 svm_vmcb_save(v, ctxt);
534 }
536 static int svm_load_vmcb_ctxt(struct vcpu *v, struct hvm_hw_cpu *ctxt)
537 {
538 svm_load_cpu_state(v, ctxt);
539 if (svm_vmcb_restore(v, ctxt)) {
540 printk("svm_vmcb restore failed!\n");
541 domain_crash(v->domain);
542 return -EINVAL;
543 }
545 return 0;
546 }
548 static inline void svm_restore_dr(struct vcpu *v)
549 {
550 if ( unlikely(v->arch.guest_context.debugreg[7] & 0xFF) )
551 __restore_debug_registers(v);
552 }
554 static int svm_interrupts_enabled(struct vcpu *v, enum hvm_intack type)
555 {
556 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
558 if ( type == hvm_intack_nmi )
559 return !vmcb->interrupt_shadow;
561 ASSERT((type == hvm_intack_pic) || (type == hvm_intack_lapic));
562 return !irq_masked(vmcb->rflags) && !vmcb->interrupt_shadow;
563 }
565 static int svm_guest_x86_mode(struct vcpu *v)
566 {
567 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
569 if ( unlikely(!(v->arch.hvm_svm.cpu_shadow_cr0 & X86_CR0_PE)) )
570 return 0;
571 if ( unlikely(vmcb->rflags & X86_EFLAGS_VM) )
572 return 1;
573 if ( svm_long_mode_enabled(v) && likely(vmcb->cs.attr.fields.l) )
574 return 8;
575 return (likely(vmcb->cs.attr.fields.db) ? 4 : 2);
576 }
578 static void svm_update_host_cr3(struct vcpu *v)
579 {
580 /* SVM doesn't have a HOST_CR3 equivalent to update. */
581 }
583 static void svm_update_guest_cr3(struct vcpu *v)
584 {
585 v->arch.hvm_svm.vmcb->cr3 = v->arch.hvm_vcpu.hw_cr3;
586 }
588 static void svm_flush_guest_tlbs(void)
589 {
590 /* Roll over the CPU's ASID generation, so it gets a clean TLB when we
591 * next VMRUN. (If ASIDs are disabled, the whole TLB is flushed on
592 * VMRUN anyway). */
593 svm_asid_inc_generation();
594 }
596 static void svm_update_vtpr(struct vcpu *v, unsigned long value)
597 {
598 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
600 vmcb->vintr.fields.tpr = value & 0x0f;
601 }
603 static unsigned long svm_get_ctrl_reg(struct vcpu *v, unsigned int num)
604 {
605 switch ( num )
606 {
607 case 0:
608 return v->arch.hvm_svm.cpu_shadow_cr0;
609 case 2:
610 return v->arch.hvm_svm.cpu_cr2;
611 case 3:
612 return v->arch.hvm_svm.cpu_cr3;
613 case 4:
614 return v->arch.hvm_svm.cpu_shadow_cr4;
615 default:
616 BUG();
617 }
618 return 0; /* dummy */
619 }
621 static void svm_sync_vmcb(struct vcpu *v)
622 {
623 struct arch_svm_struct *arch_svm = &v->arch.hvm_svm;
625 if ( arch_svm->vmcb_in_sync )
626 return;
628 arch_svm->vmcb_in_sync = 1;
630 asm volatile (
631 ".byte 0x0f,0x01,0xdb" /* vmsave */
632 : : "a" (__pa(arch_svm->vmcb)) );
633 }
635 static unsigned long svm_get_segment_base(struct vcpu *v, enum x86_segment seg)
636 {
637 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
638 int long_mode = 0;
640 #ifdef __x86_64__
641 long_mode = vmcb->cs.attr.fields.l && svm_long_mode_enabled(v);
642 #endif
643 switch ( seg )
644 {
645 case x86_seg_cs: return long_mode ? 0 : vmcb->cs.base;
646 case x86_seg_ds: return long_mode ? 0 : vmcb->ds.base;
647 case x86_seg_es: return long_mode ? 0 : vmcb->es.base;
648 case x86_seg_fs: svm_sync_vmcb(v); return vmcb->fs.base;
649 case x86_seg_gs: svm_sync_vmcb(v); return vmcb->gs.base;
650 case x86_seg_ss: return long_mode ? 0 : vmcb->ss.base;
651 case x86_seg_tr: svm_sync_vmcb(v); return vmcb->tr.base;
652 case x86_seg_gdtr: return vmcb->gdtr.base;
653 case x86_seg_idtr: return vmcb->idtr.base;
654 case x86_seg_ldtr: svm_sync_vmcb(v); return vmcb->ldtr.base;
655 }
656 BUG();
657 return 0;
658 }
660 static void svm_get_segment_register(struct vcpu *v, enum x86_segment seg,
661 struct segment_register *reg)
662 {
663 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
664 switch ( seg )
665 {
666 case x86_seg_cs:
667 memcpy(reg, &vmcb->cs, sizeof(*reg));
668 break;
669 case x86_seg_ds:
670 memcpy(reg, &vmcb->ds, sizeof(*reg));
671 break;
672 case x86_seg_es:
673 memcpy(reg, &vmcb->es, sizeof(*reg));
674 break;
675 case x86_seg_fs:
676 svm_sync_vmcb(v);
677 memcpy(reg, &vmcb->fs, sizeof(*reg));
678 break;
679 case x86_seg_gs:
680 svm_sync_vmcb(v);
681 memcpy(reg, &vmcb->gs, sizeof(*reg));
682 break;
683 case x86_seg_ss:
684 memcpy(reg, &vmcb->ss, sizeof(*reg));
685 break;
686 case x86_seg_tr:
687 svm_sync_vmcb(v);
688 memcpy(reg, &vmcb->tr, sizeof(*reg));
689 break;
690 case x86_seg_gdtr:
691 memcpy(reg, &vmcb->gdtr, sizeof(*reg));
692 break;
693 case x86_seg_idtr:
694 memcpy(reg, &vmcb->idtr, sizeof(*reg));
695 break;
696 case x86_seg_ldtr:
697 svm_sync_vmcb(v);
698 memcpy(reg, &vmcb->ldtr, sizeof(*reg));
699 break;
700 default: BUG();
701 }
702 }
704 /* Make sure that xen intercepts any FP accesses from current */
705 static void svm_stts(struct vcpu *v)
706 {
707 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
709 /*
710 * If the guest does not have TS enabled then we must cause and handle an
711 * exception on first use of the FPU. If the guest *does* have TS enabled
712 * then this is not necessary: no FPU activity can occur until the guest
713 * clears CR0.TS, and we will initialise the FPU when that happens.
714 */
715 if ( !(v->arch.hvm_svm.cpu_shadow_cr0 & X86_CR0_TS) )
716 {
717 v->arch.hvm_svm.vmcb->exception_intercepts |= 1U << TRAP_no_device;
718 vmcb->cr0 |= X86_CR0_TS;
719 }
720 }
723 static void svm_set_tsc_offset(struct vcpu *v, u64 offset)
724 {
725 v->arch.hvm_svm.vmcb->tsc_offset = offset;
726 }
729 static void svm_init_ap_context(
730 struct vcpu_guest_context *ctxt, int vcpuid, int trampoline_vector)
731 {
732 struct vcpu *v;
733 struct vmcb_struct *vmcb;
734 cpu_user_regs_t *regs;
735 u16 cs_sel;
737 /* We know this is safe because hvm_bringup_ap() does it */
738 v = current->domain->vcpu[vcpuid];
739 vmcb = v->arch.hvm_svm.vmcb;
740 regs = &v->arch.guest_context.user_regs;
742 memset(ctxt, 0, sizeof(*ctxt));
744 /*
745 * We execute the trampoline code in real mode. The trampoline vector
746 * passed to us is page alligned and is the physical frame number for
747 * the code. We will execute this code in real mode.
748 */
749 cs_sel = trampoline_vector << 8;
750 ctxt->user_regs.eip = 0x0;
751 ctxt->user_regs.cs = cs_sel;
753 /*
754 * This is the launch of an AP; set state so that we begin executing
755 * the trampoline code in real-mode.
756 */
757 svm_reset_to_realmode(v, regs);
758 /* Adjust the vmcb's hidden register state. */
759 vmcb->rip = 0;
760 vmcb->cs.sel = cs_sel;
761 vmcb->cs.base = (cs_sel << 4);
762 }
764 static void svm_init_hypercall_page(struct domain *d, void *hypercall_page)
765 {
766 char *p;
767 int i;
769 memset(hypercall_page, 0, PAGE_SIZE);
771 for ( i = 0; i < (PAGE_SIZE / 32); i++ )
772 {
773 p = (char *)(hypercall_page + (i * 32));
774 *(u8 *)(p + 0) = 0xb8; /* mov imm32, %eax */
775 *(u32 *)(p + 1) = i;
776 *(u8 *)(p + 5) = 0x0f; /* vmmcall */
777 *(u8 *)(p + 6) = 0x01;
778 *(u8 *)(p + 7) = 0xd9;
779 *(u8 *)(p + 8) = 0xc3; /* ret */
780 }
782 /* Don't support HYPERVISOR_iret at the moment */
783 *(u16 *)(hypercall_page + (__HYPERVISOR_iret * 32)) = 0x0b0f; /* ud2 */
784 }
786 static void svm_load_cpu_guest_regs(struct vcpu *v, struct cpu_user_regs *regs)
787 {
788 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
790 vmcb->ss.sel = regs->ss;
791 vmcb->rsp = regs->esp;
792 vmcb->rflags = regs->eflags | 2UL;
793 vmcb->cs.sel = regs->cs;
794 vmcb->rip = regs->eip;
795 }
797 static void svm_ctxt_switch_from(struct vcpu *v)
798 {
799 int cpu = smp_processor_id();
801 svm_save_dr(v);
803 svm_sync_vmcb(v);
805 asm volatile (
806 ".byte 0x0f,0x01,0xda" /* vmload */
807 : : "a" (__pa(root_vmcb[cpu])) );
809 #ifdef __x86_64__
810 /* Resume use of IST2 for NMIs now that the host TR is reinstated. */
811 idt_tables[cpu][TRAP_nmi].a |= 2UL << 32;
812 #endif
813 }
815 static void svm_ctxt_switch_to(struct vcpu *v)
816 {
817 int cpu = smp_processor_id();
819 #ifdef __x86_64__
820 /*
821 * This is required, because VMRUN does consistency check
822 * and some of the DOM0 selectors are pointing to
823 * invalid GDT locations, and cause AMD processors
824 * to shutdown.
825 */
826 set_segment_register(ds, 0);
827 set_segment_register(es, 0);
828 set_segment_register(ss, 0);
830 /*
831 * Cannot use IST2 for NMIs while we are running with the guest TR. But
832 * this doesn't matter: the IST is only needed to handle SYSCALL/SYSRET.
833 */
834 idt_tables[cpu][TRAP_nmi].a &= ~(2UL << 32);
835 #endif
837 svm_restore_dr(v);
839 asm volatile (
840 ".byte 0x0f,0x01,0xdb" /* vmsave */
841 : : "a" (__pa(root_vmcb[cpu])) );
842 asm volatile (
843 ".byte 0x0f,0x01,0xda" /* vmload */
844 : : "a" (__pa(v->arch.hvm_svm.vmcb)) );
845 }
847 static void svm_do_resume(struct vcpu *v)
848 {
849 bool_t debug_state = v->domain->debugger_attached;
851 if ( unlikely(v->arch.hvm_vcpu.debug_state_latch != debug_state) )
852 {
853 uint32_t mask = (1U << TRAP_debug) | (1U << TRAP_int3);
854 v->arch.hvm_vcpu.debug_state_latch = debug_state;
855 if ( debug_state )
856 v->arch.hvm_svm.vmcb->exception_intercepts |= mask;
857 else
858 v->arch.hvm_svm.vmcb->exception_intercepts &= ~mask;
859 }
861 if ( v->arch.hvm_svm.launch_core != smp_processor_id() )
862 {
863 v->arch.hvm_svm.launch_core = smp_processor_id();
864 hvm_migrate_timers(v);
866 /* Migrating to another ASID domain. Request a new ASID. */
867 svm_asid_init_vcpu(v);
868 }
870 hvm_do_resume(v);
871 reset_stack_and_jump(svm_asm_do_resume);
872 }
874 static int svm_domain_initialise(struct domain *d)
875 {
876 return 0;
877 }
879 static void svm_domain_destroy(struct domain *d)
880 {
881 }
883 static int svm_vcpu_initialise(struct vcpu *v)
884 {
885 int rc;
887 v->arch.schedule_tail = svm_do_resume;
888 v->arch.ctxt_switch_from = svm_ctxt_switch_from;
889 v->arch.ctxt_switch_to = svm_ctxt_switch_to;
891 v->arch.hvm_svm.launch_core = -1;
893 if ( (rc = svm_create_vmcb(v)) != 0 )
894 {
895 dprintk(XENLOG_WARNING,
896 "Failed to create VMCB for vcpu %d: err=%d.\n",
897 v->vcpu_id, rc);
898 return rc;
899 }
901 return 0;
902 }
904 static void svm_vcpu_destroy(struct vcpu *v)
905 {
906 svm_destroy_vmcb(v);
907 }
909 static void svm_hvm_inject_exception(
910 unsigned int trapnr, int errcode, unsigned long cr2)
911 {
912 struct vcpu *v = current;
913 if ( trapnr == TRAP_page_fault )
914 v->arch.hvm_svm.vmcb->cr2 = v->arch.hvm_svm.cpu_cr2 = cr2;
915 svm_inject_exception(v, trapnr, (errcode != -1), errcode);
916 }
918 static int svm_event_injection_faulted(struct vcpu *v)
919 {
920 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
921 return vmcb->exitintinfo.fields.v;
922 }
924 static struct hvm_function_table svm_function_table = {
925 .name = "SVM",
926 .disable = stop_svm,
927 .domain_initialise = svm_domain_initialise,
928 .domain_destroy = svm_domain_destroy,
929 .vcpu_initialise = svm_vcpu_initialise,
930 .vcpu_destroy = svm_vcpu_destroy,
931 .store_cpu_guest_regs = svm_store_cpu_guest_regs,
932 .load_cpu_guest_regs = svm_load_cpu_guest_regs,
933 .save_cpu_ctxt = svm_save_vmcb_ctxt,
934 .load_cpu_ctxt = svm_load_vmcb_ctxt,
935 .paging_enabled = svm_paging_enabled,
936 .long_mode_enabled = svm_long_mode_enabled,
937 .pae_enabled = svm_pae_enabled,
938 .nx_enabled = svm_nx_enabled,
939 .interrupts_enabled = svm_interrupts_enabled,
940 .guest_x86_mode = svm_guest_x86_mode,
941 .get_guest_ctrl_reg = svm_get_ctrl_reg,
942 .get_segment_base = svm_get_segment_base,
943 .get_segment_register = svm_get_segment_register,
944 .update_host_cr3 = svm_update_host_cr3,
945 .update_guest_cr3 = svm_update_guest_cr3,
946 .flush_guest_tlbs = svm_flush_guest_tlbs,
947 .update_vtpr = svm_update_vtpr,
948 .stts = svm_stts,
949 .set_tsc_offset = svm_set_tsc_offset,
950 .inject_exception = svm_hvm_inject_exception,
951 .init_ap_context = svm_init_ap_context,
952 .init_hypercall_page = svm_init_hypercall_page,
953 .event_injection_faulted = svm_event_injection_faulted
954 };
956 static void svm_npt_detect(void)
957 {
958 u32 eax, ebx, ecx, edx;
960 /* Check CPUID for nested paging support. */
961 cpuid(0x8000000A, &eax, &ebx, &ecx, &edx);
963 if ( !(edx & 1) && opt_hap_enabled )
964 {
965 printk("SVM: Nested paging is not supported by this CPU.\n");
966 opt_hap_enabled = 0;
967 }
968 }
970 int start_svm(struct cpuinfo_x86 *c)
971 {
972 u32 eax, ecx, edx;
973 u32 phys_hsa_lo, phys_hsa_hi;
974 u64 phys_hsa;
975 int cpu = smp_processor_id();
977 /* Xen does not fill x86_capability words except 0. */
978 ecx = cpuid_ecx(0x80000001);
979 boot_cpu_data.x86_capability[5] = ecx;
981 if ( !(test_bit(X86_FEATURE_SVME, &boot_cpu_data.x86_capability)) )
982 return 0;
984 /* Check whether SVM feature is disabled in BIOS */
985 rdmsr(MSR_K8_VM_CR, eax, edx);
986 if ( eax & K8_VMCR_SVME_DISABLE )
987 {
988 printk("AMD SVM Extension is disabled in BIOS.\n");
989 return 0;
990 }
992 if ( ((hsa[cpu] = alloc_host_save_area()) == NULL) ||
993 ((root_vmcb[cpu] = alloc_vmcb()) == NULL) )
994 return 0;
996 write_efer(read_efer() | EFER_SVME);
998 svm_npt_detect();
1000 /* Initialize the HSA for this core. */
1001 phys_hsa = (u64) virt_to_maddr(hsa[cpu]);
1002 phys_hsa_lo = (u32) phys_hsa;
1003 phys_hsa_hi = (u32) (phys_hsa >> 32);
1004 wrmsr(MSR_K8_VM_HSAVE_PA, phys_hsa_lo, phys_hsa_hi);
1006 /* Initialize core's ASID handling. */
1007 svm_asid_init(c);
1009 if ( cpu != 0 )
1010 return 1;
1012 setup_vmcb_dump();
1014 hvm_enable(&svm_function_table);
1016 if ( opt_hap_enabled )
1017 printk("SVM: Nested paging enabled.\n");
1019 return 1;
1022 static int svm_do_nested_pgfault(paddr_t gpa, struct cpu_user_regs *regs)
1024 if (mmio_space(gpa)) {
1025 handle_mmio(gpa);
1026 return 1;
1029 paging_mark_dirty(current->domain, get_mfn_from_gpfn(gpa >> PAGE_SHIFT));
1030 return p2m_set_flags(current->domain, gpa, __PAGE_HYPERVISOR|_PAGE_USER);
1033 static void svm_do_no_device_fault(struct vmcb_struct *vmcb)
1035 struct vcpu *v = current;
1037 setup_fpu(v);
1038 vmcb->exception_intercepts &= ~(1U << TRAP_no_device);
1040 if ( !(v->arch.hvm_svm.cpu_shadow_cr0 & X86_CR0_TS) )
1041 vmcb->cr0 &= ~X86_CR0_TS;
1044 /* Reserved bits ECX: [31:14], [12:4], [2:1]*/
1045 #define SVM_VCPU_CPUID_L1_ECX_RESERVED 0xffffdff6
1046 /* Reserved bits EDX: [31:29], [27], [22:20], [18], [10] */
1047 #define SVM_VCPU_CPUID_L1_EDX_RESERVED 0xe8740400
1049 static void svm_vmexit_do_cpuid(struct vmcb_struct *vmcb,
1050 struct cpu_user_regs *regs)
1052 unsigned long input = regs->eax;
1053 unsigned int eax, ebx, ecx, edx;
1054 struct vcpu *v = current;
1055 int inst_len;
1057 hvm_cpuid(input, &eax, &ebx, &ecx, &edx);
1059 if ( input == 0x00000001 )
1061 /* Clear out reserved bits. */
1062 ecx &= ~SVM_VCPU_CPUID_L1_ECX_RESERVED;
1063 edx &= ~SVM_VCPU_CPUID_L1_EDX_RESERVED;
1065 /* Guest should only see one logical processor.
1066 * See details on page 23 of AMD CPUID Specification.
1067 */
1068 clear_bit(X86_FEATURE_HT & 31, &edx); /* clear the hyperthread bit */
1069 ebx &= 0xFF00FFFF; /* clear the logical processor count when HTT=0 */
1070 ebx |= 0x00010000; /* set to 1 just for precaution */
1072 else if ( input == 0x80000001 )
1074 if ( vlapic_hw_disabled(vcpu_vlapic(v)) )
1075 clear_bit(X86_FEATURE_APIC & 31, &edx);
1077 #if CONFIG_PAGING_LEVELS >= 3
1078 if ( !v->domain->arch.hvm_domain.params[HVM_PARAM_PAE_ENABLED] )
1079 #endif
1080 clear_bit(X86_FEATURE_PAE & 31, &edx);
1082 clear_bit(X86_FEATURE_PSE36 & 31, &edx);
1084 /* Clear the Cmp_Legacy bit
1085 * This bit is supposed to be zero when HTT = 0.
1086 * See details on page 23 of AMD CPUID Specification.
1087 */
1088 clear_bit(X86_FEATURE_CMP_LEGACY & 31, &ecx);
1090 /* Make SVM feature invisible to the guest. */
1091 clear_bit(X86_FEATURE_SVME & 31, &ecx);
1093 /* So far, we do not support 3DNow for the guest. */
1094 clear_bit(X86_FEATURE_3DNOW & 31, &edx);
1095 clear_bit(X86_FEATURE_3DNOWEXT & 31, &edx);
1096 /* no FFXSR instructions feature. */
1097 clear_bit(X86_FEATURE_FFXSR & 31, &edx);
1099 else if ( input == 0x80000007 || input == 0x8000000A )
1101 /* Mask out features of power management and SVM extension. */
1102 eax = ebx = ecx = edx = 0;
1104 else if ( input == 0x80000008 )
1106 /* Make sure Number of CPU core is 1 when HTT=0 */
1107 ecx &= 0xFFFFFF00;
1110 regs->eax = (unsigned long)eax;
1111 regs->ebx = (unsigned long)ebx;
1112 regs->ecx = (unsigned long)ecx;
1113 regs->edx = (unsigned long)edx;
1115 HVMTRACE_3D(CPUID, v, input,
1116 ((uint64_t)eax << 32) | ebx, ((uint64_t)ecx << 32) | edx);
1118 inst_len = __get_instruction_length(v, INSTR_CPUID, NULL);
1119 ASSERT(inst_len > 0);
1120 __update_guest_eip(vmcb, inst_len);
1123 static inline unsigned long *get_reg_p(
1124 unsigned int gpreg,
1125 struct cpu_user_regs *regs, struct vmcb_struct *vmcb)
1127 unsigned long *reg_p = NULL;
1128 switch (gpreg)
1130 case SVM_REG_EAX:
1131 reg_p = (unsigned long *)&regs->eax;
1132 break;
1133 case SVM_REG_EBX:
1134 reg_p = (unsigned long *)&regs->ebx;
1135 break;
1136 case SVM_REG_ECX:
1137 reg_p = (unsigned long *)&regs->ecx;
1138 break;
1139 case SVM_REG_EDX:
1140 reg_p = (unsigned long *)&regs->edx;
1141 break;
1142 case SVM_REG_EDI:
1143 reg_p = (unsigned long *)&regs->edi;
1144 break;
1145 case SVM_REG_ESI:
1146 reg_p = (unsigned long *)&regs->esi;
1147 break;
1148 case SVM_REG_EBP:
1149 reg_p = (unsigned long *)&regs->ebp;
1150 break;
1151 case SVM_REG_ESP:
1152 reg_p = (unsigned long *)&vmcb->rsp;
1153 break;
1154 #ifdef __x86_64__
1155 case SVM_REG_R8:
1156 reg_p = (unsigned long *)&regs->r8;
1157 break;
1158 case SVM_REG_R9:
1159 reg_p = (unsigned long *)&regs->r9;
1160 break;
1161 case SVM_REG_R10:
1162 reg_p = (unsigned long *)&regs->r10;
1163 break;
1164 case SVM_REG_R11:
1165 reg_p = (unsigned long *)&regs->r11;
1166 break;
1167 case SVM_REG_R12:
1168 reg_p = (unsigned long *)&regs->r12;
1169 break;
1170 case SVM_REG_R13:
1171 reg_p = (unsigned long *)&regs->r13;
1172 break;
1173 case SVM_REG_R14:
1174 reg_p = (unsigned long *)&regs->r14;
1175 break;
1176 case SVM_REG_R15:
1177 reg_p = (unsigned long *)&regs->r15;
1178 break;
1179 #endif
1180 default:
1181 BUG();
1184 return reg_p;
1188 static inline unsigned long get_reg(
1189 unsigned int gpreg, struct cpu_user_regs *regs, struct vmcb_struct *vmcb)
1191 unsigned long *gp;
1192 gp = get_reg_p(gpreg, regs, vmcb);
1193 return *gp;
1197 static inline void set_reg(
1198 unsigned int gpreg, unsigned long value,
1199 struct cpu_user_regs *regs, struct vmcb_struct *vmcb)
1201 unsigned long *gp;
1202 gp = get_reg_p(gpreg, regs, vmcb);
1203 *gp = value;
1207 static void svm_dr_access(struct vcpu *v, struct cpu_user_regs *regs)
1209 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1211 HVMTRACE_0D(DR_WRITE, v);
1213 v->arch.hvm_vcpu.flag_dr_dirty = 1;
1215 __restore_debug_registers(v);
1217 /* allow the guest full access to the debug registers */
1218 vmcb->dr_intercepts = 0;
1222 static void svm_get_prefix_info(struct vcpu *v, unsigned int dir,
1223 svm_segment_register_t **seg,
1224 unsigned int *asize)
1226 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1227 unsigned char inst[MAX_INST_LEN];
1228 int i;
1230 memset(inst, 0, MAX_INST_LEN);
1231 if (inst_copy_from_guest(inst, svm_rip2pointer(v), sizeof(inst))
1232 != MAX_INST_LEN)
1234 gdprintk(XENLOG_ERR, "get guest instruction failed\n");
1235 domain_crash(current->domain);
1236 return;
1239 for (i = 0; i < MAX_INST_LEN; i++)
1241 switch (inst[i])
1243 case 0xf3: /* REPZ */
1244 case 0xf2: /* REPNZ */
1245 case 0xf0: /* LOCK */
1246 case 0x66: /* data32 */
1247 #ifdef __x86_64__
1248 /* REX prefixes */
1249 case 0x40:
1250 case 0x41:
1251 case 0x42:
1252 case 0x43:
1253 case 0x44:
1254 case 0x45:
1255 case 0x46:
1256 case 0x47:
1258 case 0x48:
1259 case 0x49:
1260 case 0x4a:
1261 case 0x4b:
1262 case 0x4c:
1263 case 0x4d:
1264 case 0x4e:
1265 case 0x4f:
1266 #endif
1267 continue;
1268 case 0x67: /* addr32 */
1269 *asize ^= 48; /* Switch 16/32 bits */
1270 continue;
1271 case 0x2e: /* CS */
1272 *seg = &vmcb->cs;
1273 continue;
1274 case 0x36: /* SS */
1275 *seg = &vmcb->ss;
1276 continue;
1277 case 0x26: /* ES */
1278 *seg = &vmcb->es;
1279 continue;
1280 case 0x64: /* FS */
1281 svm_sync_vmcb(v);
1282 *seg = &vmcb->fs;
1283 continue;
1284 case 0x65: /* GS */
1285 svm_sync_vmcb(v);
1286 *seg = &vmcb->gs;
1287 continue;
1288 case 0x3e: /* DS */
1289 *seg = &vmcb->ds;
1290 continue;
1291 default:
1292 break;
1294 return;
1299 /* Get the address of INS/OUTS instruction */
1300 static inline int svm_get_io_address(
1301 struct vcpu *v, struct cpu_user_regs *regs,
1302 unsigned int size, ioio_info_t info,
1303 unsigned long *count, unsigned long *addr)
1305 unsigned long reg;
1306 unsigned int asize, isize;
1307 int long_mode = 0;
1308 svm_segment_register_t *seg = NULL;
1309 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1311 #ifdef __x86_64__
1312 /* If we're in long mode, we shouldn't check the segment presence & limit */
1313 long_mode = vmcb->cs.attr.fields.l && svm_long_mode_enabled(v);
1314 #endif
1316 /* d field of cs.attr is 1 for 32-bit, 0 for 16 or 64 bit.
1317 * l field combined with EFER_LMA says whether it's 16 or 64 bit.
1318 */
1319 asize = (long_mode)?64:((vmcb->cs.attr.fields.db)?32:16);
1322 /* The ins/outs instructions are single byte, so if we have got more
1323 * than one byte (+ maybe rep-prefix), we have some prefix so we need
1324 * to figure out what it is...
1325 */
1326 isize = vmcb->exitinfo2 - vmcb->rip;
1328 if (info.fields.rep)
1329 isize --;
1331 if (isize > 1)
1332 svm_get_prefix_info(v, info.fields.type, &seg, &asize);
1334 if (info.fields.type == IOREQ_WRITE)
1336 reg = regs->esi;
1337 if (!seg) /* If no prefix, used DS. */
1338 seg = &vmcb->ds;
1339 if (!long_mode && (seg->attr.fields.type & 0xa) == 0x8) {
1340 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1341 return 0;
1344 else
1346 reg = regs->edi;
1347 seg = &vmcb->es; /* Note: This is ALWAYS ES. */
1348 if (!long_mode && (seg->attr.fields.type & 0xa) != 0x2) {
1349 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1350 return 0;
1354 /* If the segment isn't present, give GP fault! */
1355 if (!long_mode && !seg->attr.fields.p)
1357 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1358 return 0;
1361 if (asize == 16)
1363 *addr = (reg & 0xFFFF);
1364 *count = regs->ecx & 0xffff;
1366 else
1368 *addr = reg;
1369 *count = regs->ecx;
1371 if (!info.fields.rep)
1372 *count = 1;
1374 if (!long_mode)
1376 ASSERT(*addr == (u32)*addr);
1377 if ((u32)(*addr + size - 1) < (u32)*addr ||
1378 (seg->attr.fields.type & 0xc) != 0x4 ?
1379 *addr + size - 1 > seg->limit :
1380 *addr <= seg->limit)
1382 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1383 return 0;
1386 /* Check the limit for repeated instructions, as above we checked only
1387 the first instance. Truncate the count if a limit violation would
1388 occur. Note that the checking is not necessary for page granular
1389 segments as transfers crossing page boundaries will be broken up
1390 anyway. */
1391 if (!seg->attr.fields.g && *count > 1)
1393 if ((seg->attr.fields.type & 0xc) != 0x4)
1395 /* expand-up */
1396 if (!(regs->eflags & EF_DF))
1398 if (*addr + *count * size - 1 < *addr ||
1399 *addr + *count * size - 1 > seg->limit)
1400 *count = (seg->limit + 1UL - *addr) / size;
1402 else
1404 if (*count - 1 > *addr / size)
1405 *count = *addr / size + 1;
1408 else
1410 /* expand-down */
1411 if (!(regs->eflags & EF_DF))
1413 if (*count - 1 > -(s32)*addr / size)
1414 *count = -(s32)*addr / size + 1UL;
1416 else
1418 if (*addr < (*count - 1) * size ||
1419 *addr - (*count - 1) * size <= seg->limit)
1420 *count = (*addr - seg->limit - 1) / size + 1;
1423 ASSERT(*count);
1426 *addr += seg->base;
1428 #ifdef __x86_64__
1429 else
1431 if (seg == &vmcb->fs || seg == &vmcb->gs)
1432 *addr += seg->base;
1434 if (!is_canonical_address(*addr) ||
1435 !is_canonical_address(*addr + size - 1))
1437 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1438 return 0;
1440 if (*count > (1UL << 48) / size)
1441 *count = (1UL << 48) / size;
1442 if (!(regs->eflags & EF_DF))
1444 if (*addr + *count * size - 1 < *addr ||
1445 !is_canonical_address(*addr + *count * size - 1))
1446 *count = (*addr & ~((1UL << 48) - 1)) / size;
1448 else
1450 if ((*count - 1) * size > *addr ||
1451 !is_canonical_address(*addr + (*count - 1) * size))
1452 *count = (*addr & ~((1UL << 48) - 1)) / size + 1;
1454 ASSERT(*count);
1456 #endif
1458 return 1;
1462 static void svm_io_instruction(struct vcpu *v)
1464 struct cpu_user_regs *regs;
1465 struct hvm_io_op *pio_opp;
1466 unsigned int port;
1467 unsigned int size, dir, df;
1468 ioio_info_t info;
1469 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1471 pio_opp = &current->arch.hvm_vcpu.io_op;
1472 pio_opp->instr = INSTR_PIO;
1473 pio_opp->flags = 0;
1475 regs = &pio_opp->io_context;
1477 /* Copy current guest state into io instruction state structure. */
1478 memcpy(regs, guest_cpu_user_regs(), HVM_CONTEXT_STACK_BYTES);
1479 hvm_store_cpu_guest_regs(v, regs, NULL);
1481 info.bytes = vmcb->exitinfo1;
1483 port = info.fields.port; /* port used to be addr */
1484 dir = info.fields.type; /* direction */
1485 df = regs->eflags & X86_EFLAGS_DF ? 1 : 0;
1487 if (info.fields.sz32)
1488 size = 4;
1489 else if (info.fields.sz16)
1490 size = 2;
1491 else
1492 size = 1;
1494 if (dir==IOREQ_READ)
1495 HVMTRACE_2D(IO_READ, v, port, size);
1496 else
1497 HVMTRACE_2D(IO_WRITE, v, port, size);
1499 HVM_DBG_LOG(DBG_LEVEL_IO,
1500 "svm_io_instruction: port 0x%x eip=%x:%"PRIx64", "
1501 "exit_qualification = %"PRIx64,
1502 port, vmcb->cs.sel, vmcb->rip, info.bytes);
1504 /* string instruction */
1505 if (info.fields.str)
1507 unsigned long addr, count;
1508 paddr_t paddr;
1509 unsigned long gfn;
1510 int sign = regs->eflags & X86_EFLAGS_DF ? -1 : 1;
1512 if (!svm_get_io_address(v, regs, size, info, &count, &addr))
1514 /* We failed to get a valid address, so don't do the IO operation -
1515 * it would just get worse if we do! Hopefully the guest is handing
1516 * gp-faults...
1517 */
1518 return;
1521 /* "rep" prefix */
1522 if (info.fields.rep)
1524 pio_opp->flags |= REPZ;
1527 /* Translate the address to a physical address */
1528 gfn = paging_gva_to_gfn(v, addr);
1529 if ( gfn == INVALID_GFN )
1531 /* The guest does not have the RAM address mapped.
1532 * Need to send in a page fault */
1533 int errcode = 0;
1534 /* IO read --> memory write */
1535 if ( dir == IOREQ_READ ) errcode |= PFEC_write_access;
1536 svm_hvm_inject_exception(TRAP_page_fault, errcode, addr);
1537 return;
1539 paddr = (paddr_t)gfn << PAGE_SHIFT | (addr & ~PAGE_MASK);
1541 /*
1542 * Handle string pio instructions that cross pages or that
1543 * are unaligned. See the comments in hvm_platform.c/handle_mmio()
1544 */
1545 if ((addr & PAGE_MASK) != ((addr + size - 1) & PAGE_MASK))
1547 unsigned long value = 0;
1549 pio_opp->flags |= OVERLAP;
1550 pio_opp->addr = addr;
1552 if (dir == IOREQ_WRITE) /* OUTS */
1554 if ( hvm_paging_enabled(current) )
1556 int rv = hvm_copy_from_guest_virt(&value, addr, size);
1557 if ( rv != 0 )
1559 /* Failed on the page-spanning copy. Inject PF into
1560 * the guest for the address where we failed. */
1561 addr += size - rv;
1562 gdprintk(XENLOG_DEBUG, "Pagefault reading non-io side "
1563 "of a page-spanning PIO: va=%#lx\n", addr);
1564 svm_hvm_inject_exception(TRAP_page_fault, 0, addr);
1565 return;
1568 else
1569 (void) hvm_copy_from_guest_phys(&value, addr, size);
1570 } else /* dir != IOREQ_WRITE */
1571 /* Remember where to write the result, as a *VA*.
1572 * Must be a VA so we can handle the page overlap
1573 * correctly in hvm_pio_assist() */
1574 pio_opp->addr = addr;
1576 if (count == 1)
1577 regs->eip = vmcb->exitinfo2;
1579 send_pio_req(port, 1, size, value, dir, df, 0);
1581 else
1583 unsigned long last_addr = sign > 0 ? addr + count * size - 1
1584 : addr - (count - 1) * size;
1586 if ((addr & PAGE_MASK) != (last_addr & PAGE_MASK))
1588 if (sign > 0)
1589 count = (PAGE_SIZE - (addr & ~PAGE_MASK)) / size;
1590 else
1591 count = (addr & ~PAGE_MASK) / size + 1;
1593 else
1594 regs->eip = vmcb->exitinfo2;
1596 send_pio_req(port, count, size, paddr, dir, df, 1);
1599 else
1601 /*
1602 * On SVM, the RIP of the intruction following the IN/OUT is saved in
1603 * ExitInfo2
1604 */
1605 regs->eip = vmcb->exitinfo2;
1607 if (port == 0xe9 && dir == IOREQ_WRITE && size == 1)
1608 hvm_print_line(v, regs->eax); /* guest debug output */
1610 send_pio_req(port, 1, size, regs->eax, dir, df, 0);
1614 static int svm_set_cr0(unsigned long value)
1616 struct vcpu *v = current;
1617 unsigned long mfn, old_value = v->arch.hvm_svm.cpu_shadow_cr0;
1618 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1619 unsigned long old_base_mfn;
1621 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR0 value = %lx", value);
1623 /* ET is reserved and should be always be 1. */
1624 value |= X86_CR0_ET;
1626 if ( (value & (X86_CR0_PE|X86_CR0_PG)) == X86_CR0_PG )
1628 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1629 return 0;
1632 /* TS cleared? Then initialise FPU now. */
1633 if ( !(value & X86_CR0_TS) )
1635 setup_fpu(v);
1636 vmcb->exception_intercepts &= ~(1U << TRAP_no_device);
1639 if ( (value & X86_CR0_PG) && !(old_value & X86_CR0_PG) )
1641 #if defined(__x86_64__)
1642 if ( svm_lme_is_set(v) )
1644 if ( !svm_cr4_pae_is_set(v) )
1646 HVM_DBG_LOG(DBG_LEVEL_1, "Enable paging before PAE enable");
1647 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1648 return 0;
1650 HVM_DBG_LOG(DBG_LEVEL_1, "Enable the Long mode");
1651 v->arch.hvm_svm.cpu_shadow_efer |= EFER_LMA;
1652 vmcb->efer |= EFER_LMA | EFER_LME;
1654 #endif /* __x86_64__ */
1656 if ( !paging_mode_hap(v->domain) )
1658 /* The guest CR3 must be pointing to the guest physical. */
1659 mfn = get_mfn_from_gpfn(v->arch.hvm_svm.cpu_cr3 >> PAGE_SHIFT);
1660 if ( !mfn_valid(mfn) || !get_page(mfn_to_page(mfn), v->domain))
1662 gdprintk(XENLOG_ERR, "Invalid CR3 value = %lx (mfn=%lx)\n",
1663 v->arch.hvm_svm.cpu_cr3, mfn);
1664 domain_crash(v->domain);
1665 return 0;
1668 /* Now arch.guest_table points to machine physical. */
1669 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1670 v->arch.guest_table = pagetable_from_pfn(mfn);
1671 if ( old_base_mfn )
1672 put_page(mfn_to_page(old_base_mfn));
1674 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1675 (unsigned long) (mfn << PAGE_SHIFT));
1678 else if ( !(value & X86_CR0_PG) && (old_value & X86_CR0_PG) )
1680 /* When CR0.PG is cleared, LMA is cleared immediately. */
1681 if ( svm_long_mode_enabled(v) )
1683 vmcb->efer &= ~(EFER_LME | EFER_LMA);
1684 v->arch.hvm_svm.cpu_shadow_efer &= ~EFER_LMA;
1687 if ( !paging_mode_hap(v->domain) && v->arch.hvm_svm.cpu_cr3 )
1689 put_page(mfn_to_page(get_mfn_from_gpfn(
1690 v->arch.hvm_svm.cpu_cr3 >> PAGE_SHIFT)));
1691 v->arch.guest_table = pagetable_null();
1695 vmcb->cr0 = v->arch.hvm_svm.cpu_shadow_cr0 = value;
1696 if ( !paging_mode_hap(v->domain) )
1697 vmcb->cr0 |= X86_CR0_PG | X86_CR0_WP;
1699 if ( (value ^ old_value) & X86_CR0_PG )
1701 paging_update_paging_modes(v);
1702 /* signal paging update to ASID handler */
1703 svm_asid_g_update_paging (v);
1706 return 1;
1709 /*
1710 * Read from control registers. CR0 and CR4 are read from the shadow.
1711 */
1712 static void mov_from_cr(int cr, int gp, struct cpu_user_regs *regs)
1714 unsigned long value = 0;
1715 struct vcpu *v = current;
1716 struct vlapic *vlapic = vcpu_vlapic(v);
1717 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1719 switch ( cr )
1721 case 0:
1722 value = v->arch.hvm_svm.cpu_shadow_cr0;
1723 break;
1724 case 2:
1725 value = vmcb->cr2;
1726 break;
1727 case 3:
1728 value = (unsigned long)v->arch.hvm_svm.cpu_cr3;
1729 break;
1730 case 4:
1731 value = (unsigned long)v->arch.hvm_svm.cpu_shadow_cr4;
1732 break;
1733 case 8:
1734 value = (unsigned long)vlapic_get_reg(vlapic, APIC_TASKPRI);
1735 value = (value & 0xF0) >> 4;
1736 break;
1738 default:
1739 domain_crash(v->domain);
1740 return;
1743 HVMTRACE_2D(CR_READ, v, cr, value);
1745 set_reg(gp, value, regs, vmcb);
1747 HVM_DBG_LOG(DBG_LEVEL_VMMU, "mov_from_cr: CR%d, value = %lx", cr, value);
1751 /*
1752 * Write to control registers
1753 */
1754 static int mov_to_cr(int gpreg, int cr, struct cpu_user_regs *regs)
1756 unsigned long value, old_cr, old_base_mfn, mfn;
1757 struct vcpu *v = current;
1758 struct vlapic *vlapic = vcpu_vlapic(v);
1759 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1761 value = get_reg(gpreg, regs, vmcb);
1763 HVMTRACE_2D(CR_WRITE, v, cr, value);
1765 HVM_DBG_LOG(DBG_LEVEL_1, "mov_to_cr: CR%d, value = %lx, current = %p",
1766 cr, value, v);
1768 switch ( cr )
1770 case 0:
1771 return svm_set_cr0(value);
1773 case 3:
1774 if ( paging_mode_hap(v->domain) )
1776 vmcb->cr3 = v->arch.hvm_svm.cpu_cr3 = value;
1777 break;
1780 /* If paging is not enabled yet, simply copy the value to CR3. */
1781 if ( !svm_paging_enabled(v) )
1783 v->arch.hvm_svm.cpu_cr3 = value;
1784 break;
1787 /* We make a new one if the shadow does not exist. */
1788 if ( value == v->arch.hvm_svm.cpu_cr3 )
1790 /*
1791 * This is simple TLB flush, implying the guest has
1792 * removed some translation or changed page attributes.
1793 * We simply invalidate the shadow.
1794 */
1795 mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT);
1796 if ( mfn != pagetable_get_pfn(v->arch.guest_table) )
1797 goto bad_cr3;
1798 paging_update_cr3(v);
1799 /* signal paging update to ASID handler */
1800 svm_asid_g_mov_to_cr3 (v);
1802 else
1804 /*
1805 * If different, make a shadow. Check if the PDBR is valid
1806 * first.
1807 */
1808 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 value = %lx", value);
1809 mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT);
1810 if ( !mfn_valid(mfn) || !get_page(mfn_to_page(mfn), v->domain) )
1811 goto bad_cr3;
1813 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1814 v->arch.guest_table = pagetable_from_pfn(mfn);
1816 if ( old_base_mfn )
1817 put_page(mfn_to_page(old_base_mfn));
1819 v->arch.hvm_svm.cpu_cr3 = value;
1820 update_cr3(v);
1821 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx", value);
1822 /* signal paging update to ASID handler */
1823 svm_asid_g_mov_to_cr3 (v);
1825 break;
1827 case 4: /* CR4 */
1828 if ( paging_mode_hap(v->domain) )
1830 vmcb->cr4 = v->arch.hvm_svm.cpu_shadow_cr4 = value;
1831 paging_update_paging_modes(v);
1832 /* signal paging update to ASID handler */
1833 svm_asid_g_update_paging (v);
1834 break;
1837 old_cr = v->arch.hvm_svm.cpu_shadow_cr4;
1838 if ( value & X86_CR4_PAE && !(old_cr & X86_CR4_PAE) )
1840 if ( svm_pgbit_test(v) )
1842 /* The guest is a 32-bit PAE guest. */
1843 #if CONFIG_PAGING_LEVELS >= 3
1844 unsigned long mfn, old_base_mfn;
1845 mfn = get_mfn_from_gpfn(v->arch.hvm_svm.cpu_cr3 >> PAGE_SHIFT);
1846 if ( !mfn_valid(mfn) ||
1847 !get_page(mfn_to_page(mfn), v->domain) )
1848 goto bad_cr3;
1850 /*
1851 * Now arch.guest_table points to machine physical.
1852 */
1854 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1855 v->arch.guest_table = pagetable_from_pfn(mfn);
1856 if ( old_base_mfn )
1857 put_page(mfn_to_page(old_base_mfn));
1858 paging_update_paging_modes(v);
1859 /* signal paging update to ASID handler */
1860 svm_asid_g_update_paging (v);
1862 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1863 (unsigned long) (mfn << PAGE_SHIFT));
1865 HVM_DBG_LOG(DBG_LEVEL_VMMU,
1866 "Update CR3 value = %lx, mfn = %lx",
1867 v->arch.hvm_svm.cpu_cr3, mfn);
1868 #endif
1871 else if ( !(value & X86_CR4_PAE) )
1873 if ( svm_long_mode_enabled(v) )
1875 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1879 v->arch.hvm_svm.cpu_shadow_cr4 = value;
1880 vmcb->cr4 = value | SVM_CR4_HOST_MASK;
1882 /*
1883 * Writing to CR4 to modify the PSE, PGE, or PAE flag invalidates
1884 * all TLB entries except global entries.
1885 */
1886 if ((old_cr ^ value) & (X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE))
1888 paging_update_paging_modes(v);
1889 /* signal paging update to ASID handler */
1890 svm_asid_g_update_paging (v);
1892 break;
1894 case 8:
1895 vlapic_set_reg(vlapic, APIC_TASKPRI, ((value & 0x0F) << 4));
1896 vmcb->vintr.fields.tpr = value & 0x0F;
1897 break;
1899 default:
1900 gdprintk(XENLOG_ERR, "invalid cr: %d\n", cr);
1901 domain_crash(v->domain);
1902 return 0;
1905 return 1;
1907 bad_cr3:
1908 gdprintk(XENLOG_ERR, "Invalid CR3\n");
1909 domain_crash(v->domain);
1910 return 0;
1914 #define ARR_SIZE(x) (sizeof(x) / sizeof(x[0]))
1917 static int svm_cr_access(struct vcpu *v, unsigned int cr, unsigned int type,
1918 struct cpu_user_regs *regs)
1920 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1921 int inst_len = 0;
1922 int index,addr_size,i;
1923 unsigned int gpreg,offset;
1924 unsigned long value,addr;
1925 u8 buffer[MAX_INST_LEN];
1926 u8 prefix = 0;
1927 u8 modrm;
1928 enum x86_segment seg;
1929 int result = 1;
1930 enum instruction_index list_a[] = {INSTR_MOV2CR, INSTR_CLTS, INSTR_LMSW};
1931 enum instruction_index list_b[] = {INSTR_MOVCR2, INSTR_SMSW};
1932 enum instruction_index match;
1934 inst_copy_from_guest(buffer, svm_rip2pointer(v), sizeof(buffer));
1936 /* get index to first actual instruction byte - as we will need to know
1937 where the prefix lives later on */
1938 index = skip_prefix_bytes(buffer, sizeof(buffer));
1940 if ( type == TYPE_MOV_TO_CR )
1942 inst_len = __get_instruction_length_from_list(
1943 v, list_a, ARR_SIZE(list_a), &buffer[index], &match);
1945 else /* type == TYPE_MOV_FROM_CR */
1947 inst_len = __get_instruction_length_from_list(
1948 v, list_b, ARR_SIZE(list_b), &buffer[index], &match);
1951 ASSERT(inst_len > 0);
1953 inst_len += index;
1955 /* Check for REX prefix - it's ALWAYS the last byte of any prefix bytes */
1956 if (index > 0 && (buffer[index-1] & 0xF0) == 0x40)
1957 prefix = buffer[index-1];
1959 HVM_DBG_LOG(DBG_LEVEL_1, "eip = %lx", (unsigned long) vmcb->rip);
1961 switch (match)
1963 case INSTR_MOV2CR:
1964 gpreg = decode_src_reg(prefix, buffer[index+2]);
1965 result = mov_to_cr(gpreg, cr, regs);
1966 break;
1968 case INSTR_MOVCR2:
1969 gpreg = decode_src_reg(prefix, buffer[index+2]);
1970 mov_from_cr(cr, gpreg, regs);
1971 break;
1973 case INSTR_CLTS:
1974 /* TS being cleared means that it's time to restore fpu state. */
1975 setup_fpu(current);
1976 vmcb->exception_intercepts &= ~(1U << TRAP_no_device);
1977 vmcb->cr0 &= ~X86_CR0_TS; /* clear TS */
1978 v->arch.hvm_svm.cpu_shadow_cr0 &= ~X86_CR0_TS; /* clear TS */
1979 break;
1981 case INSTR_LMSW:
1982 gpreg = decode_src_reg(prefix, buffer[index+2]);
1983 value = get_reg(gpreg, regs, vmcb) & 0xF;
1984 value = (v->arch.hvm_svm.cpu_shadow_cr0 & ~0xF) | value;
1985 result = svm_set_cr0(value);
1986 break;
1988 case INSTR_SMSW:
1989 value = v->arch.hvm_svm.cpu_shadow_cr0 & 0xFFFF;
1990 modrm = buffer[index+2];
1991 addr_size = svm_guest_x86_mode(v);
1992 if ( addr_size < 2 )
1993 addr_size = 2;
1994 if ( likely((modrm & 0xC0) >> 6 == 3) )
1996 gpreg = decode_src_reg(prefix, modrm);
1997 set_reg(gpreg, value, regs, vmcb);
1999 /*
2000 * For now, only implement decode of the offset mode, since that's the
2001 * only mode observed in a real-world OS. This code is also making the
2002 * assumption that we'll never hit this code in long mode.
2003 */
2004 else if ( (modrm == 0x26) || (modrm == 0x25) )
2006 seg = x86_seg_ds;
2007 i = index;
2008 /* Segment or address size overrides? */
2009 while ( i-- )
2011 switch ( buffer[i] )
2013 case 0x26: seg = x86_seg_es; break;
2014 case 0x2e: seg = x86_seg_cs; break;
2015 case 0x36: seg = x86_seg_ss; break;
2016 case 0x64: seg = x86_seg_fs; break;
2017 case 0x65: seg = x86_seg_gs; break;
2018 case 0x67: addr_size ^= 6; break;
2021 /* Bail unless this really is a seg_base + offset case */
2022 if ( ((modrm == 0x26) && (addr_size == 4)) ||
2023 ((modrm == 0x25) && (addr_size == 2)) )
2025 gdprintk(XENLOG_ERR, "SMSW emulation at guest address: "
2026 "%lx failed due to unhandled addressing mode."
2027 "ModRM byte was: %x \n", svm_rip2pointer(v), modrm);
2028 domain_crash(v->domain);
2030 inst_len += addr_size;
2031 offset = *(( unsigned int *) ( void *) &buffer[index + 3]);
2032 offset = ( addr_size == 4 ) ? offset : ( offset & 0xFFFF );
2033 addr = hvm_get_segment_base(v, seg);
2034 addr += offset;
2035 hvm_copy_to_guest_virt(addr,&value,2);
2037 else
2039 gdprintk(XENLOG_ERR, "SMSW emulation at guest address: %lx "
2040 "failed due to unhandled addressing mode!"
2041 "ModRM byte was: %x \n", svm_rip2pointer(v), modrm);
2042 domain_crash(v->domain);
2044 break;
2046 default:
2047 BUG();
2050 ASSERT(inst_len);
2052 __update_guest_eip(vmcb, inst_len);
2054 return result;
2057 static inline void svm_do_msr_access(
2058 struct vcpu *v, struct cpu_user_regs *regs)
2060 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2061 int inst_len;
2062 u64 msr_content=0;
2063 u32 ecx = regs->ecx, eax, edx;
2065 HVM_DBG_LOG(DBG_LEVEL_1, "ecx=%x, eax=%x, edx=%x, exitinfo = %lx",
2066 ecx, (u32)regs->eax, (u32)regs->edx,
2067 (unsigned long)vmcb->exitinfo1);
2069 /* is it a read? */
2070 if (vmcb->exitinfo1 == 0)
2072 switch (ecx) {
2073 case MSR_IA32_TIME_STAMP_COUNTER:
2074 msr_content = hvm_get_guest_time(v);
2075 break;
2076 case MSR_IA32_APICBASE:
2077 msr_content = vcpu_vlapic(v)->hw.apic_base_msr;
2078 break;
2079 case MSR_EFER:
2080 msr_content = v->arch.hvm_svm.cpu_shadow_efer;
2081 break;
2083 case MSR_K8_MC4_MISC: /* Threshold register */
2084 /*
2085 * MCA/MCE: We report that the threshold register is unavailable
2086 * for OS use (locked by the BIOS).
2087 */
2088 msr_content = 1ULL << 61; /* MC4_MISC.Locked */
2089 break;
2091 case MSR_IA32_EBC_FREQUENCY_ID:
2092 /*
2093 * This Intel-only register may be accessed if this HVM guest
2094 * has been migrated from an Intel host. The value zero is not
2095 * particularly meaningful, but at least avoids the guest crashing!
2096 */
2097 msr_content = 0;
2098 break;
2100 default:
2101 if ( rdmsr_hypervisor_regs(ecx, &eax, &edx) ||
2102 rdmsr_safe(ecx, eax, edx) == 0 )
2104 regs->eax = eax;
2105 regs->edx = edx;
2106 goto done;
2108 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
2109 return;
2111 regs->eax = msr_content & 0xFFFFFFFF;
2112 regs->edx = msr_content >> 32;
2114 done:
2115 HVMTRACE_2D(MSR_READ, v, ecx, msr_content);
2116 HVM_DBG_LOG(DBG_LEVEL_1, "returns: ecx=%x, eax=%lx, edx=%lx",
2117 ecx, (unsigned long)regs->eax, (unsigned long)regs->edx);
2119 inst_len = __get_instruction_length(v, INSTR_RDMSR, NULL);
2121 else
2123 msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
2125 HVMTRACE_2D(MSR_WRITE, v, ecx, msr_content);
2127 switch (ecx)
2129 case MSR_IA32_TIME_STAMP_COUNTER:
2130 hvm_set_guest_time(v, msr_content);
2131 pt_reset(v);
2132 break;
2133 case MSR_IA32_APICBASE:
2134 vlapic_msr_set(vcpu_vlapic(v), msr_content);
2135 break;
2136 default:
2137 if ( !long_mode_do_msr_write(regs) )
2138 wrmsr_hypervisor_regs(ecx, regs->eax, regs->edx);
2139 break;
2142 inst_len = __get_instruction_length(v, INSTR_WRMSR, NULL);
2145 __update_guest_eip(vmcb, inst_len);
2148 static inline void svm_vmexit_do_hlt(struct vmcb_struct *vmcb)
2150 enum hvm_intack type = hvm_vcpu_has_pending_irq(current);
2152 __update_guest_eip(vmcb, 1);
2154 /* Check for interrupt not handled or new interrupt. */
2155 if ( vmcb->eventinj.fields.v ||
2156 ((type != hvm_intack_none) && hvm_interrupts_enabled(current, type)) )
2158 HVMTRACE_1D(HLT, current, /*int pending=*/ 1);
2159 return;
2162 HVMTRACE_1D(HLT, current, /*int pending=*/ 0);
2163 hvm_hlt(vmcb->rflags);
2166 static void svm_vmexit_do_invd(struct vcpu *v)
2168 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2169 int inst_len;
2171 /* Invalidate the cache - we can't really do that safely - maybe we should
2172 * WBINVD, but I think it's just fine to completely ignore it - we should
2173 * have cache-snooping that solves it anyways. -- Mats P.
2174 */
2176 /* Tell the user that we did this - just in case someone runs some really
2177 * weird operating system and wants to know why it's not working...
2178 */
2179 gdprintk(XENLOG_WARNING, "INVD instruction intercepted - ignored\n");
2181 inst_len = __get_instruction_length(v, INSTR_INVD, NULL);
2182 __update_guest_eip(vmcb, inst_len);
2185 void svm_handle_invlpg(const short invlpga, struct cpu_user_regs *regs)
2187 struct vcpu *v = current;
2188 u8 opcode[MAX_INST_LEN], prefix, length = MAX_INST_LEN;
2189 unsigned long g_vaddr;
2190 int inst_len;
2191 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2193 /*
2194 * Unknown how many bytes the invlpg instruction will take. Use the
2195 * maximum instruction length here
2196 */
2197 if (inst_copy_from_guest(opcode, svm_rip2pointer(v), length) < length)
2199 gdprintk(XENLOG_ERR, "Error reading memory %d bytes\n", length);
2200 domain_crash(v->domain);
2201 return;
2204 if (invlpga)
2206 inst_len = __get_instruction_length(v, INSTR_INVLPGA, opcode);
2207 ASSERT(inst_len > 0);
2208 __update_guest_eip(vmcb, inst_len);
2210 /*
2211 * The address is implicit on this instruction. At the moment, we don't
2212 * use ecx (ASID) to identify individual guests pages
2213 */
2214 g_vaddr = regs->eax;
2216 else
2218 /* What about multiple prefix codes? */
2219 prefix = (is_prefix(opcode[0])?opcode[0]:0);
2220 inst_len = __get_instruction_length(v, INSTR_INVLPG, opcode);
2221 ASSERT(inst_len > 0);
2223 inst_len--;
2224 length -= inst_len;
2226 /*
2227 * Decode memory operand of the instruction including ModRM, SIB, and
2228 * displacement to get effective address and length in bytes. Assume
2229 * the system in either 32- or 64-bit mode.
2230 */
2231 g_vaddr = get_effective_addr_modrm64(regs, prefix, inst_len,
2232 &opcode[inst_len], &length);
2234 inst_len += length;
2235 __update_guest_eip (vmcb, inst_len);
2238 HVMTRACE_3D(INVLPG, v, (invlpga?1:0), g_vaddr, (invlpga?regs->ecx:0));
2240 paging_invlpg(v, g_vaddr);
2241 /* signal invplg to ASID handler */
2242 svm_asid_g_invlpg (v, g_vaddr);
2246 /*
2247 * Reset to realmode causes execution to start at 0xF000:0xFFF0 in
2248 * 16-bit realmode. Basically, this mimics a processor reset.
2250 * returns 0 on success, non-zero otherwise
2251 */
2252 static int svm_reset_to_realmode(struct vcpu *v,
2253 struct cpu_user_regs *regs)
2255 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2257 /* clear the vmcb and user regs */
2258 memset(regs, 0, sizeof(struct cpu_user_regs));
2260 /* VMCB Control */
2261 vmcb->tsc_offset = 0;
2263 /* VMCB State */
2264 vmcb->cr0 = X86_CR0_ET | X86_CR0_PG | X86_CR0_WP;
2265 v->arch.hvm_svm.cpu_shadow_cr0 = X86_CR0_ET;
2267 vmcb->cr2 = 0;
2268 vmcb->efer = EFER_SVME;
2270 vmcb->cr4 = SVM_CR4_HOST_MASK;
2271 v->arch.hvm_svm.cpu_shadow_cr4 = 0;
2273 if ( paging_mode_hap(v->domain) ) {
2274 vmcb->cr0 = v->arch.hvm_svm.cpu_shadow_cr0;
2275 vmcb->cr4 = v->arch.hvm_svm.cpu_shadow_cr4;
2278 /* This will jump to ROMBIOS */
2279 vmcb->rip = 0xFFF0;
2281 /* setup the segment registers and all their hidden states */
2282 vmcb->cs.sel = 0xF000;
2283 vmcb->cs.attr.bytes = 0x089b;
2284 vmcb->cs.limit = 0xffff;
2285 vmcb->cs.base = 0x000F0000;
2287 vmcb->ss.sel = 0x00;
2288 vmcb->ss.attr.bytes = 0x0893;
2289 vmcb->ss.limit = 0xffff;
2290 vmcb->ss.base = 0x00;
2292 vmcb->ds.sel = 0x00;
2293 vmcb->ds.attr.bytes = 0x0893;
2294 vmcb->ds.limit = 0xffff;
2295 vmcb->ds.base = 0x00;
2297 vmcb->es.sel = 0x00;
2298 vmcb->es.attr.bytes = 0x0893;
2299 vmcb->es.limit = 0xffff;
2300 vmcb->es.base = 0x00;
2302 vmcb->fs.sel = 0x00;
2303 vmcb->fs.attr.bytes = 0x0893;
2304 vmcb->fs.limit = 0xffff;
2305 vmcb->fs.base = 0x00;
2307 vmcb->gs.sel = 0x00;
2308 vmcb->gs.attr.bytes = 0x0893;
2309 vmcb->gs.limit = 0xffff;
2310 vmcb->gs.base = 0x00;
2312 vmcb->ldtr.sel = 0x00;
2313 vmcb->ldtr.attr.bytes = 0x0000;
2314 vmcb->ldtr.limit = 0x0;
2315 vmcb->ldtr.base = 0x00;
2317 vmcb->gdtr.sel = 0x00;
2318 vmcb->gdtr.attr.bytes = 0x0000;
2319 vmcb->gdtr.limit = 0x0;
2320 vmcb->gdtr.base = 0x00;
2322 vmcb->tr.sel = 0;
2323 vmcb->tr.attr.bytes = 0;
2324 vmcb->tr.limit = 0x0;
2325 vmcb->tr.base = 0;
2327 vmcb->idtr.sel = 0x00;
2328 vmcb->idtr.attr.bytes = 0x0000;
2329 vmcb->idtr.limit = 0x3ff;
2330 vmcb->idtr.base = 0x00;
2332 vmcb->rax = 0;
2333 vmcb->rsp = 0;
2335 return 0;
2338 asmlinkage void svm_vmexit_handler(struct cpu_user_regs *regs)
2340 unsigned int exit_reason;
2341 unsigned long eip;
2342 struct vcpu *v = current;
2343 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2344 int inst_len, rc;
2346 exit_reason = vmcb->exitcode;
2348 HVMTRACE_2D(VMEXIT, v, vmcb->rip, exit_reason);
2350 if ( unlikely(exit_reason == VMEXIT_INVALID) )
2352 svm_dump_vmcb(__func__, vmcb);
2353 goto exit_and_crash;
2356 perfc_incra(svmexits, exit_reason);
2357 eip = vmcb->rip;
2359 switch ( exit_reason )
2361 case VMEXIT_INTR:
2362 /* Asynchronous event, handled when we STGI'd after the VMEXIT. */
2363 HVMTRACE_0D(INTR, v);
2364 break;
2366 case VMEXIT_NMI:
2367 /* Asynchronous event, handled when we STGI'd after the VMEXIT. */
2368 HVMTRACE_0D(NMI, v);
2369 break;
2371 case VMEXIT_SMI:
2372 /* Asynchronous event, handled when we STGI'd after the VMEXIT. */
2373 HVMTRACE_0D(SMI, v);
2374 break;
2376 case VMEXIT_EXCEPTION_DB:
2377 if ( !v->domain->debugger_attached )
2378 goto exit_and_crash;
2379 domain_pause_for_debugger();
2380 break;
2382 case VMEXIT_EXCEPTION_BP:
2383 if ( !v->domain->debugger_attached )
2384 goto exit_and_crash;
2385 /* AMD Vol2, 15.11: INT3, INTO, BOUND intercepts do not update RIP. */
2386 inst_len = __get_instruction_length(v, INSTR_INT3, NULL);
2387 __update_guest_eip(vmcb, inst_len);
2388 domain_pause_for_debugger();
2389 break;
2391 case VMEXIT_EXCEPTION_NM:
2392 svm_do_no_device_fault(vmcb);
2393 break;
2395 case VMEXIT_EXCEPTION_PF: {
2396 unsigned long va;
2397 va = vmcb->exitinfo2;
2398 regs->error_code = vmcb->exitinfo1;
2399 HVM_DBG_LOG(DBG_LEVEL_VMMU,
2400 "eax=%lx, ebx=%lx, ecx=%lx, edx=%lx, esi=%lx, edi=%lx",
2401 (unsigned long)regs->eax, (unsigned long)regs->ebx,
2402 (unsigned long)regs->ecx, (unsigned long)regs->edx,
2403 (unsigned long)regs->esi, (unsigned long)regs->edi);
2405 if ( paging_fault(va, regs) )
2407 HVMTRACE_2D(PF_XEN, v, va, regs->error_code);
2408 break;
2411 v->arch.hvm_svm.cpu_cr2 = vmcb->cr2 = va;
2412 svm_inject_exception(v, TRAP_page_fault, 1, regs->error_code);
2413 break;
2416 case VMEXIT_VINTR:
2417 vmcb->vintr.fields.irq = 0;
2418 vmcb->general1_intercepts &= ~GENERAL1_INTERCEPT_VINTR;
2419 break;
2421 case VMEXIT_INVD:
2422 svm_vmexit_do_invd(v);
2423 break;
2425 case VMEXIT_GDTR_WRITE:
2426 printk("WRITE to GDTR\n");
2427 break;
2429 case VMEXIT_TASK_SWITCH:
2430 goto exit_and_crash;
2432 case VMEXIT_CPUID:
2433 svm_vmexit_do_cpuid(vmcb, regs);
2434 break;
2436 case VMEXIT_HLT:
2437 svm_vmexit_do_hlt(vmcb);
2438 break;
2440 case VMEXIT_INVLPG:
2441 svm_handle_invlpg(0, regs);
2442 break;
2444 case VMEXIT_INVLPGA:
2445 svm_handle_invlpg(1, regs);
2446 break;
2448 case VMEXIT_VMMCALL:
2449 inst_len = __get_instruction_length(v, INSTR_VMCALL, NULL);
2450 ASSERT(inst_len > 0);
2451 HVMTRACE_1D(VMMCALL, v, regs->eax);
2452 rc = hvm_do_hypercall(regs);
2453 if ( rc != HVM_HCALL_preempted )
2455 __update_guest_eip(vmcb, inst_len);
2456 if ( rc == HVM_HCALL_invalidate )
2457 send_invalidate_req();
2459 break;
2461 case VMEXIT_CR0_READ:
2462 svm_cr_access(v, 0, TYPE_MOV_FROM_CR, regs);
2463 break;
2465 case VMEXIT_CR2_READ:
2466 svm_cr_access(v, 2, TYPE_MOV_FROM_CR, regs);
2467 break;
2469 case VMEXIT_CR3_READ:
2470 svm_cr_access(v, 3, TYPE_MOV_FROM_CR, regs);
2471 break;
2473 case VMEXIT_CR4_READ:
2474 svm_cr_access(v, 4, TYPE_MOV_FROM_CR, regs);
2475 break;
2477 case VMEXIT_CR8_READ:
2478 svm_cr_access(v, 8, TYPE_MOV_FROM_CR, regs);
2479 break;
2481 case VMEXIT_CR0_WRITE:
2482 svm_cr_access(v, 0, TYPE_MOV_TO_CR, regs);
2483 break;
2485 case VMEXIT_CR2_WRITE:
2486 svm_cr_access(v, 2, TYPE_MOV_TO_CR, regs);
2487 break;
2489 case VMEXIT_CR3_WRITE:
2490 svm_cr_access(v, 3, TYPE_MOV_TO_CR, regs);
2491 local_flush_tlb();
2492 break;
2494 case VMEXIT_CR4_WRITE:
2495 svm_cr_access(v, 4, TYPE_MOV_TO_CR, regs);
2496 break;
2498 case VMEXIT_CR8_WRITE:
2499 svm_cr_access(v, 8, TYPE_MOV_TO_CR, regs);
2500 break;
2502 case VMEXIT_DR0_WRITE ... VMEXIT_DR7_WRITE:
2503 svm_dr_access(v, regs);
2504 break;
2506 case VMEXIT_IOIO:
2507 svm_io_instruction(v);
2508 break;
2510 case VMEXIT_MSR:
2511 svm_do_msr_access(v, regs);
2512 break;
2514 case VMEXIT_SHUTDOWN:
2515 hvm_triple_fault();
2516 break;
2518 case VMEXIT_VMRUN:
2519 case VMEXIT_VMLOAD:
2520 case VMEXIT_VMSAVE:
2521 case VMEXIT_STGI:
2522 case VMEXIT_CLGI:
2523 case VMEXIT_SKINIT:
2524 /* Report "Invalid opcode" on any VM-operation except VMMCALL */
2525 svm_inject_exception(v, TRAP_invalid_op, 0, 0);
2526 break;
2528 case VMEXIT_NPF:
2529 regs->error_code = vmcb->exitinfo1;
2530 if ( !svm_do_nested_pgfault(vmcb->exitinfo2, regs) )
2531 domain_crash(v->domain);
2532 break;
2534 default:
2535 exit_and_crash:
2536 gdprintk(XENLOG_ERR, "unexpected VMEXIT: exit reason = 0x%x, "
2537 "exitinfo1 = %"PRIx64", exitinfo2 = %"PRIx64"\n",
2538 exit_reason,
2539 (u64)vmcb->exitinfo1, (u64)vmcb->exitinfo2);
2540 domain_crash(v->domain);
2541 break;
2545 asmlinkage void svm_trace_vmentry(void)
2547 struct vcpu *v = current;
2549 /* This is the last C code before the VMRUN instruction. */
2550 HVMTRACE_0D(VMENTRY, v);
2553 /*
2554 * Local variables:
2555 * mode: C
2556 * c-set-style: "BSD"
2557 * c-basic-offset: 4
2558 * tab-width: 4
2559 * indent-tabs-mode: nil
2560 * End:
2561 */