direct-io.hg

view xen/arch/powerpc/powerpc64/ppc970.c @ 11379:215d5eae720c

[XEN][POWERPC] restructure RMA code to allow dom0 tools to allocate in the future
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
author Hollis Blanchard <hollisb@us.ibm.com>
date Fri Aug 25 14:48:07 2006 -0500 (2006-08-25)
parents 43ec7afa5734
children bc349d862a5d
line source
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
15 *
16 * Copyright (C) IBM Corp. 2005, 2006
17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 * Jimi Xenidis <jimix@watson.ibm.com>
20 */
22 #include <xen/config.h>
23 #include <xen/types.h>
24 #include <xen/mm.h>
25 #include <xen/sched.h>
26 #include <xen/lib.h>
27 #include <asm/time.h>
28 #include <asm/current.h>
29 #include <asm/powerpc64/procarea.h>
30 #include <asm/powerpc64/processor.h>
31 #include <asm/powerpc64/ppc970-hid.h>
33 #undef SERIALIZE
35 extern volatile struct processor_area * volatile global_cpu_table[];
37 struct rma_settings {
38 int order;
39 int rmlr0;
40 int rmlr12;
41 };
43 static struct rma_settings rma_orders[] = {
44 { .order = 26, .rmlr0 = 0, .rmlr12 = 3, }, /* 64 MB */
45 { .order = 27, .rmlr0 = 1, .rmlr12 = 3, }, /* 128 MB */
46 { .order = 28, .rmlr0 = 1, .rmlr12 = 0, }, /* 256 MB */
47 { .order = 30, .rmlr0 = 0, .rmlr12 = 2, }, /* 1 GB */
48 { .order = 34, .rmlr0 = 0, .rmlr12 = 1, }, /* 16 GB */
49 { .order = 38, .rmlr0 = 0, .rmlr12 = 0, }, /* 256 GB */
50 };
52 static struct rma_settings *cpu_find_rma(unsigned int order)
53 {
54 int i;
55 for (i = 0; i < ARRAY_SIZE(rma_orders); i++) {
56 if (rma_orders[i].order == order)
57 return &rma_orders[i];
58 }
59 return NULL;
60 }
62 unsigned int cpu_default_rma_order_pages(void)
63 {
64 return rma_orders[0].order - PAGE_SHIFT;
65 }
67 unsigned int cpu_large_page_orders(uint *sizes, uint max)
68 {
69 uint lp_log_size = 4 + 20; /* (1 << 4) == 16M */
70 if (max < 1)
71 return 0;
73 sizes[0] = lp_log_size - PAGE_SHIFT;
75 return 1;
76 }
78 void cpu_initialize(int cpuid)
79 {
80 ulong r1, r2;
81 __asm__ __volatile__ ("mr %0, 1" : "=r" (r1));
82 __asm__ __volatile__ ("mr %0, 2" : "=r" (r2));
84 /* This is SMP safe because the compiler must use r13 for it. */
85 parea = global_cpu_table[cpuid];
86 ASSERT(parea != NULL);
88 mthsprg0((ulong)parea); /* now ready for exceptions */
90 /* Set decrementers for 1 second to keep them out of the way during
91 * intialization. */
92 /* XXX make tickless */
93 mtdec(timebase_freq);
94 mthdec(timebase_freq);
96 union hid0 hid0;
98 hid0.word = mfhid0();
99 hid0.bits.nap = 1;
100 hid0.bits.dpm = 1;
101 hid0.bits.nhr = 1;
102 hid0.bits.hdice = 1; /* enable HDEC */
103 hid0.bits.eb_therm = 1;
104 hid0.bits.en_attn = 1;
105 #ifdef SERIALIZE
106 ulong s = 0;
108 s |= 1UL << (63-0); /* one_ppc */
109 s |= 1UL << (63-2); /* isync_sc */
110 s |= 1UL << (63-16); /* inorder */
111 /* may not want these */
112 s |= 1UL << (63-1); /* do_single */
113 s |= 1UL << (63-3); /* ser-gp */
114 hid0.word |= s;
115 #endif
117 printk("CPU #%d: Hello World! SP = %lx TOC = %lx HID0 = %lx\n",
118 smp_processor_id(), r1, r2, hid0.word);
120 mthid0(hid0.word);
122 union hid1 hid1;
124 hid1.word = mfhid1();
125 hid1.bits.bht_pm = 7;
126 hid1.bits.en_ls = 1;
128 hid1.bits.en_cc = 1;
129 hid1.bits.en_ic = 1;
131 hid1.bits.pf_mode = 2;
133 hid1.bits.en_if_cach = 1;
134 hid1.bits.en_ic_rec = 1;
135 hid1.bits.en_id_rec = 1;
136 hid1.bits.en_er_rec = 1;
138 hid1.bits.en_sp_itw = 1;
139 mthid1(hid1.word);
141 union hid5 hid5;
143 hid5.word = mfhid5();
144 hid5.bits.DCBZ_size = 0;
145 hid5.bits.DCBZ32_ill = 0;
146 mthid5(hid5.word);
148 __asm__ __volatile__("isync; slbia; isync" : : : "memory");
149 }
151 void cpu_init_vcpu(struct vcpu *v)
152 {
153 struct domain *d = v->domain;
154 union hid4 hid4;
155 struct rma_settings *rma_settings;
157 hid4.word = mfhid4();
159 hid4.bits.lpes0 = 0; /* exceptions set MSR_HV=1 */
160 hid4.bits.lpes1 = 1; /* RMA applies */
162 hid4.bits.rmor = page_to_maddr(d->arch.rma_page) >> 26;
164 hid4.bits.lpid01 = d->domain_id & 3;
165 hid4.bits.lpid25 = (d->domain_id >> 2) & 0xf;
167 rma_settings = cpu_find_rma(d->arch.rma_order + PAGE_SHIFT);
168 ASSERT(rma_settings != NULL);
169 hid4.bits.rmlr0 = rma_settings->rmlr0;
170 hid4.bits.rmlr12 = rma_settings->rmlr12;
172 v->arch.cpu.hid4.word = hid4.word;
173 }
175 void save_cpu_sprs(struct vcpu *v)
176 {
177 /* HID4 is initialized with a per-domain value at domain creation time, and
178 * does not change after that. */
179 }
181 void load_cpu_sprs(struct vcpu *v)
182 {
183 mthid4(v->arch.cpu.hid4.word);
184 }